1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 #include "gt/intel_engine_types.h" 13 14 #include "abi/guc_actions_abi.h" 15 #include "abi/guc_actions_slpc_abi.h" 16 #include "abi/guc_errors_abi.h" 17 #include "abi/guc_communication_mmio_abi.h" 18 #include "abi/guc_communication_ctb_abi.h" 19 #include "abi/guc_messages_abi.h" 20 21 /* Payload length only i.e. don't include G2H header length */ 22 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2 23 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1 24 25 #define GUC_CONTEXT_DISABLE 0 26 #define GUC_CONTEXT_ENABLE 1 27 28 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 29 #define GUC_CLIENT_PRIORITY_HIGH 1 30 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 31 #define GUC_CLIENT_PRIORITY_NORMAL 3 32 #define GUC_CLIENT_PRIORITY_NUM 4 33 34 #define GUC_MAX_LRC_DESCRIPTORS 65535 35 #define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS 36 37 #define GUC_RENDER_ENGINE 0 38 #define GUC_VIDEO_ENGINE 1 39 #define GUC_BLITTER_ENGINE 2 40 #define GUC_VIDEOENHANCE_ENGINE 3 41 #define GUC_VIDEO_ENGINE2 4 42 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 43 44 #define GUC_RENDER_CLASS 0 45 #define GUC_VIDEO_CLASS 1 46 #define GUC_VIDEOENHANCE_CLASS 2 47 #define GUC_BLITTER_CLASS 3 48 #define GUC_RESERVED_CLASS 4 49 #define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS 50 #define GUC_MAX_ENGINE_CLASSES 16 51 #define GUC_MAX_INSTANCES_PER_CLASS 32 52 53 #define GUC_DOORBELL_INVALID 256 54 55 /* 56 * Work queue item header definitions 57 * 58 * Work queue is circular buffer used to submit complex (multi-lrc) submissions 59 * to the GuC. A work queue item is an entry in the circular buffer. 60 */ 61 #define WQ_STATUS_ACTIVE 1 62 #define WQ_STATUS_SUSPENDED 2 63 #define WQ_STATUS_CMD_ERROR 3 64 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 65 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 66 #define WQ_TYPE_BATCH_BUF 0x1 67 #define WQ_TYPE_PSEUDO 0x2 68 #define WQ_TYPE_INORDER 0x3 69 #define WQ_TYPE_NOOP 0x4 70 #define WQ_TYPE_MULTI_LRC 0x5 71 #define WQ_TYPE_MASK GENMASK(7, 0) 72 #define WQ_LEN_MASK GENMASK(26, 16) 73 74 #define WQ_GUC_ID_MASK GENMASK(15, 0) 75 #define WQ_RING_TAIL_MASK GENMASK(28, 18) 76 77 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 78 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 79 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 80 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 81 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 82 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 83 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 84 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 85 86 #define GUC_CTL_LOG_PARAMS 0 87 #define GUC_LOG_VALID (1 << 0) 88 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 89 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 90 #define GUC_LOG_CRASH_SHIFT 4 91 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 92 #define GUC_LOG_DEBUG_SHIFT 6 93 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT) 94 #define GUC_LOG_BUF_ADDR_SHIFT 12 95 96 #define GUC_CTL_WA 1 97 #define GUC_CTL_FEATURE 2 98 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 99 #define GUC_CTL_ENABLE_SLPC BIT(2) 100 101 #define GUC_CTL_DEBUG 3 102 #define GUC_LOG_VERBOSITY_SHIFT 0 103 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 104 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 105 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 106 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 107 /* Verbosity range-check limits, without the shift */ 108 #define GUC_LOG_VERBOSITY_MIN 0 109 #define GUC_LOG_VERBOSITY_MAX 3 110 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 111 #define GUC_LOG_DESTINATION_MASK (3 << 4) 112 #define GUC_LOG_DISABLED (1 << 6) 113 #define GUC_PROFILE_ENABLED (1 << 7) 114 115 #define GUC_CTL_ADS 4 116 #define GUC_ADS_ADDR_SHIFT 1 117 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 118 119 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 120 121 /* Generic GT SysInfo data types */ 122 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0 123 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1 124 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2 125 #define GUC_GENERIC_GT_SYSINFO_MAX 16 126 127 /* 128 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. 129 * Bit 7 can be used for operations that apply to all engine classes&instances. 130 */ 131 #define GUC_ENGINE_CLASS_SHIFT 0 132 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) 133 #define GUC_ENGINE_INSTANCE_SHIFT 3 134 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) 135 #define GUC_ENGINE_ALL_INSTANCES BIT(7) 136 137 #define MAKE_GUC_ID(class, instance) \ 138 (((class) << GUC_ENGINE_CLASS_SHIFT) | \ 139 ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) 140 141 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \ 142 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) 143 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ 144 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) 145 146 #define SLPC_EVENT(id, c) (\ 147 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 148 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \ 149 ) 150 151 static inline u8 engine_class_to_guc_class(u8 class) 152 { 153 BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS); 154 BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS); 155 BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS); 156 BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS); 157 GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS); 158 159 return class; 160 } 161 162 static inline u8 guc_class_to_engine_class(u8 guc_class) 163 { 164 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS); 165 GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS); 166 167 return guc_class; 168 } 169 170 /* Work item for submitting workloads into work queue of GuC. */ 171 struct guc_wq_item { 172 u32 header; 173 u32 context_desc; 174 u32 submit_element_info; 175 u32 fence_id; 176 } __packed; 177 178 struct guc_process_desc { 179 u32 stage_id; 180 u64 db_base_addr; 181 u32 head; 182 u32 tail; 183 u32 error_offset; 184 u64 wq_base_addr; 185 u32 wq_size_bytes; 186 u32 wq_status; 187 u32 engine_presence; 188 u32 priority; 189 u32 reserved[36]; 190 } __packed; 191 192 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) 193 194 #define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 195 #define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 500000 196 197 /* Preempt to idle on quantum expiry */ 198 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0) 199 200 /* 201 * GuC Context registration descriptor. 202 * FIXME: This is only required to exist during context registration. 203 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC 204 * is not required. 205 */ 206 struct guc_lrc_desc { 207 u32 hw_context_desc; 208 u32 slpm_perf_mode_hint; /* SPLC v1 only */ 209 u32 slpm_freq_hint; 210 u32 engine_submit_mask; /* In logical space */ 211 u8 engine_class; 212 u8 reserved0[3]; 213 u32 priority; 214 u32 process_desc; 215 u32 wq_addr; 216 u32 wq_size; 217 u32 context_flags; /* CONTEXT_REGISTRATION_* */ 218 /* Time for one workload to execute. (in micro seconds) */ 219 u32 execution_quantum; 220 /* Time to wait for a preemption request to complete before issuing a 221 * reset. (in micro seconds). 222 */ 223 u32 preemption_timeout; 224 u32 policy_flags; /* CONTEXT_POLICY_* */ 225 u32 reserved1[19]; 226 } __packed; 227 228 #define GUC_POWER_UNSPECIFIED 0 229 #define GUC_POWER_D0 1 230 #define GUC_POWER_D1 2 231 #define GUC_POWER_D2 3 232 #define GUC_POWER_D3 4 233 234 /* Scheduling policy settings */ 235 236 #define GLOBAL_POLICY_MAX_NUM_WI 15 237 238 /* Don't reset an engine upon preemption failure */ 239 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0) 240 241 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 242 243 struct guc_policies { 244 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 245 /* In micro seconds. How much time to allow before DPC processing is 246 * called back via interrupt (to prevent DPC queue drain starving). 247 * Typically 1000s of micro seconds (example only, not granularity). */ 248 u32 dpc_promote_time; 249 250 /* Must be set to take these new values. */ 251 u32 is_valid; 252 253 /* Max number of WIs to process per call. A large value may keep CS 254 * idle. */ 255 u32 max_num_work_items; 256 257 u32 global_flags; 258 u32 reserved[4]; 259 } __packed; 260 261 /* GuC MMIO reg state struct */ 262 struct guc_mmio_reg { 263 u32 offset; 264 u32 value; 265 u32 flags; 266 #define GUC_REGSET_MASKED (1 << 0) 267 } __packed; 268 269 /* GuC register sets */ 270 struct guc_mmio_reg_set { 271 u32 address; 272 u16 count; 273 u16 reserved; 274 } __packed; 275 276 /* HW info */ 277 struct guc_gt_system_info { 278 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 279 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES]; 280 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX]; 281 } __packed; 282 283 /* GuC Additional Data Struct */ 284 struct guc_ads { 285 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 286 u32 reserved0; 287 u32 scheduler_policies; 288 u32 gt_system_info; 289 u32 reserved1; 290 u32 control_data; 291 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 292 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 293 u32 private_data; 294 u32 reserved[15]; 295 } __packed; 296 297 /* GuC logging structures */ 298 299 enum guc_log_buffer_type { 300 GUC_DEBUG_LOG_BUFFER, 301 GUC_CRASH_DUMP_LOG_BUFFER, 302 GUC_MAX_LOG_BUFFER 303 }; 304 305 /** 306 * struct guc_log_buffer_state - GuC log buffer state 307 * 308 * Below state structure is used for coordination of retrieval of GuC firmware 309 * logs. Separate state is maintained for each log buffer type. 310 * read_ptr points to the location where i915 read last in log buffer and 311 * is read only for GuC firmware. write_ptr is incremented by GuC with number 312 * of bytes written for each log entry and is read only for i915. 313 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 314 * GuC firmware expects that while it is writing to 2nd half of the buffer, 315 * first half would get consumed by Host and then get a flush completed 316 * acknowledgment from Host, so that it does not end up doing any overwrite 317 * causing loss of logs. So when buffer gets half filled & i915 has requested 318 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 319 * to the value of write_ptr and raise the interrupt. 320 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 321 * field and also update read_ptr with the value of sample_write_ptr, before 322 * sending an acknowledgment to GuC. marker & version fields are for internal 323 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 324 * time GuC detects the log buffer overflow. 325 */ 326 struct guc_log_buffer_state { 327 u32 marker[2]; 328 u32 read_ptr; 329 u32 write_ptr; 330 u32 size; 331 u32 sampled_write_ptr; 332 union { 333 struct { 334 u32 flush_to_file:1; 335 u32 buffer_full_cnt:4; 336 u32 reserved:27; 337 }; 338 u32 flags; 339 }; 340 u32 version; 341 } __packed; 342 343 struct guc_ctx_report { 344 u32 report_return_status; 345 u32 reserved1[64]; 346 u32 affected_count; 347 u32 reserved2[2]; 348 } __packed; 349 350 /* GuC Shared Context Data Struct */ 351 struct guc_shared_ctx_data { 352 u32 addr_of_last_preempted_data_low; 353 u32 addr_of_last_preempted_data_high; 354 u32 addr_of_last_preempted_data_high_tmp; 355 u32 padding; 356 u32 is_mapped_to_proxy; 357 u32 proxy_ctx_id; 358 u32 engine_reset_ctx_id; 359 u32 media_reset_count; 360 u32 reserved1[8]; 361 u32 uk_last_ctx_switch_reason; 362 u32 was_reset; 363 u32 lrca_gpu_addr; 364 u64 execlist_ctx; 365 u32 reserved2[66]; 366 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 367 } __packed; 368 369 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 370 enum intel_guc_recv_message { 371 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 372 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 373 }; 374 375 #endif 376