1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 #include "gt/intel_engine_types.h" 13 14 #include "abi/guc_actions_abi.h" 15 #include "abi/guc_actions_slpc_abi.h" 16 #include "abi/guc_errors_abi.h" 17 #include "abi/guc_communication_mmio_abi.h" 18 #include "abi/guc_communication_ctb_abi.h" 19 #include "abi/guc_klvs_abi.h" 20 #include "abi/guc_messages_abi.h" 21 22 /* Payload length only i.e. don't include G2H header length */ 23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2 24 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1 25 26 #define GUC_CONTEXT_DISABLE 0 27 #define GUC_CONTEXT_ENABLE 1 28 29 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 30 #define GUC_CLIENT_PRIORITY_HIGH 1 31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 32 #define GUC_CLIENT_PRIORITY_NORMAL 3 33 #define GUC_CLIENT_PRIORITY_NUM 4 34 35 #define GUC_MAX_CONTEXT_ID 65535 36 #define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID 37 38 #define GUC_RENDER_ENGINE 0 39 #define GUC_VIDEO_ENGINE 1 40 #define GUC_BLITTER_ENGINE 2 41 #define GUC_VIDEOENHANCE_ENGINE 3 42 #define GUC_VIDEO_ENGINE2 4 43 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 44 45 #define GUC_RENDER_CLASS 0 46 #define GUC_VIDEO_CLASS 1 47 #define GUC_VIDEOENHANCE_CLASS 2 48 #define GUC_BLITTER_CLASS 3 49 #define GUC_COMPUTE_CLASS 4 50 #define GUC_GSC_OTHER_CLASS 5 51 #define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS 52 #define GUC_MAX_ENGINE_CLASSES 16 53 #define GUC_MAX_INSTANCES_PER_CLASS 32 54 55 #define GUC_DOORBELL_INVALID 256 56 57 /* 58 * Work queue item header definitions 59 * 60 * Work queue is circular buffer used to submit complex (multi-lrc) submissions 61 * to the GuC. A work queue item is an entry in the circular buffer. 62 */ 63 #define WQ_STATUS_ACTIVE 1 64 #define WQ_STATUS_SUSPENDED 2 65 #define WQ_STATUS_CMD_ERROR 3 66 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 67 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 68 #define WQ_TYPE_BATCH_BUF 0x1 69 #define WQ_TYPE_PSEUDO 0x2 70 #define WQ_TYPE_INORDER 0x3 71 #define WQ_TYPE_NOOP 0x4 72 #define WQ_TYPE_MULTI_LRC 0x5 73 #define WQ_TYPE_MASK GENMASK(7, 0) 74 #define WQ_LEN_MASK GENMASK(26, 16) 75 76 #define WQ_GUC_ID_MASK GENMASK(15, 0) 77 #define WQ_RING_TAIL_MASK GENMASK(28, 18) 78 79 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 80 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 81 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 82 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 83 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 84 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 85 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 86 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 87 88 #define GUC_CTL_LOG_PARAMS 0 89 #define GUC_LOG_VALID BIT(0) 90 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1) 91 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2) 92 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3) 93 #define GUC_LOG_CRASH_SHIFT 4 94 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 95 #define GUC_LOG_DEBUG_SHIFT 6 96 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT) 97 #define GUC_LOG_CAPTURE_SHIFT 10 98 #define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT) 99 #define GUC_LOG_BUF_ADDR_SHIFT 12 100 101 #define GUC_CTL_WA 1 102 #define GUC_WA_GAM_CREDITS BIT(10) 103 #define GUC_WA_DUAL_QUEUE BIT(11) 104 #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) 105 #define GUC_WA_CONTEXT_ISOLATION BIT(15) 106 #define GUC_WA_PRE_PARSER BIT(14) 107 #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) 108 #define GUC_WA_POLLCS BIT(18) 109 #define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21) 110 111 #define GUC_CTL_FEATURE 2 112 #define GUC_CTL_ENABLE_SLPC BIT(2) 113 #define GUC_CTL_DISABLE_SCHEDULER BIT(14) 114 115 #define GUC_CTL_DEBUG 3 116 #define GUC_LOG_VERBOSITY_SHIFT 0 117 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 118 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 119 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 120 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 121 /* Verbosity range-check limits, without the shift */ 122 #define GUC_LOG_VERBOSITY_MIN 0 123 #define GUC_LOG_VERBOSITY_MAX 3 124 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 125 #define GUC_LOG_DESTINATION_MASK (3 << 4) 126 #define GUC_LOG_DISABLED (1 << 6) 127 #define GUC_PROFILE_ENABLED (1 << 7) 128 129 #define GUC_CTL_ADS 4 130 #define GUC_ADS_ADDR_SHIFT 1 131 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 132 133 #define GUC_CTL_DEVID 5 134 135 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 136 137 /* Generic GT SysInfo data types */ 138 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0 139 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1 140 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2 141 #define GUC_GENERIC_GT_SYSINFO_MAX 16 142 143 /* 144 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. 145 * Bit 7 can be used for operations that apply to all engine classes&instances. 146 */ 147 #define GUC_ENGINE_CLASS_SHIFT 0 148 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) 149 #define GUC_ENGINE_INSTANCE_SHIFT 3 150 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) 151 #define GUC_ENGINE_ALL_INSTANCES BIT(7) 152 153 #define MAKE_GUC_ID(class, instance) \ 154 (((class) << GUC_ENGINE_CLASS_SHIFT) | \ 155 ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) 156 157 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \ 158 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) 159 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ 160 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) 161 162 #define SLPC_EVENT(id, c) (\ 163 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 164 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \ 165 ) 166 167 /* the GuC arrays don't include OTHER_CLASS */ 168 static u8 engine_class_guc_class_map[] = { 169 [RENDER_CLASS] = GUC_RENDER_CLASS, 170 [COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS, 171 [VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS, 172 [VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS, 173 [OTHER_CLASS] = GUC_GSC_OTHER_CLASS, 174 [COMPUTE_CLASS] = GUC_COMPUTE_CLASS, 175 }; 176 177 static u8 guc_class_engine_class_map[] = { 178 [GUC_RENDER_CLASS] = RENDER_CLASS, 179 [GUC_BLITTER_CLASS] = COPY_ENGINE_CLASS, 180 [GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS, 181 [GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS, 182 [GUC_COMPUTE_CLASS] = COMPUTE_CLASS, 183 [GUC_GSC_OTHER_CLASS] = OTHER_CLASS, 184 }; 185 186 static inline u8 engine_class_to_guc_class(u8 class) 187 { 188 BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1); 189 GEM_BUG_ON(class > MAX_ENGINE_CLASS); 190 191 return engine_class_guc_class_map[class]; 192 } 193 194 static inline u8 guc_class_to_engine_class(u8 guc_class) 195 { 196 BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1); 197 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS); 198 199 return guc_class_engine_class_map[guc_class]; 200 } 201 202 /* Work item for submitting workloads into work queue of GuC. */ 203 struct guc_wq_item { 204 u32 header; 205 u32 context_desc; 206 u32 submit_element_info; 207 u32 fence_id; 208 } __packed; 209 210 struct guc_process_desc_v69 { 211 u32 stage_id; 212 u64 db_base_addr; 213 u32 head; 214 u32 tail; 215 u32 error_offset; 216 u64 wq_base_addr; 217 u32 wq_size_bytes; 218 u32 wq_status; 219 u32 engine_presence; 220 u32 priority; 221 u32 reserved[36]; 222 } __packed; 223 224 struct guc_sched_wq_desc { 225 u32 head; 226 u32 tail; 227 u32 error_offset; 228 u32 wq_status; 229 u32 reserved[28]; 230 } __packed; 231 232 /* Helper for context registration H2G */ 233 struct guc_ctxt_registration_info { 234 u32 flags; 235 u32 context_idx; 236 u32 engine_class; 237 u32 engine_submit_mask; 238 u32 wq_desc_lo; 239 u32 wq_desc_hi; 240 u32 wq_base_lo; 241 u32 wq_base_hi; 242 u32 wq_size; 243 u32 hwlrca_lo; 244 u32 hwlrca_hi; 245 }; 246 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) 247 248 /* Preempt to idle on quantum expiry */ 249 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0) 250 251 /* 252 * GuC Context registration descriptor. 253 * FIXME: This is only required to exist during context registration. 254 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC 255 * is not required. 256 */ 257 struct guc_lrc_desc_v69 { 258 u32 hw_context_desc; 259 u32 slpm_perf_mode_hint; /* SPLC v1 only */ 260 u32 slpm_freq_hint; 261 u32 engine_submit_mask; /* In logical space */ 262 u8 engine_class; 263 u8 reserved0[3]; 264 u32 priority; 265 u32 process_desc; 266 u32 wq_addr; 267 u32 wq_size; 268 u32 context_flags; /* CONTEXT_REGISTRATION_* */ 269 /* Time for one workload to execute. (in micro seconds) */ 270 u32 execution_quantum; 271 /* Time to wait for a preemption request to complete before issuing a 272 * reset. (in micro seconds). 273 */ 274 u32 preemption_timeout; 275 u32 policy_flags; /* CONTEXT_POLICY_* */ 276 u32 reserved1[19]; 277 } __packed; 278 279 /* 32-bit KLV structure as used by policy updates and others */ 280 struct guc_klv_generic_dw_t { 281 u32 kl; 282 u32 value; 283 } __packed; 284 285 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */ 286 struct guc_update_context_policy_header { 287 u32 action; 288 u32 ctx_id; 289 } __packed; 290 291 struct guc_update_context_policy { 292 struct guc_update_context_policy_header header; 293 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS]; 294 } __packed; 295 296 /* Format of the UPDATE_SCHEDULING_POLICIES H2G data packet */ 297 struct guc_update_scheduling_policy_header { 298 u32 action; 299 } __packed; 300 301 /* 302 * Can't dynmically allocate memory for the scheduling policy KLV because 303 * it will be sent from within the reset path. Need a fixed size lump on 304 * the stack instead :(. 305 * 306 * Currently, there is only one KLV defined, which has 1 word of KL + 2 words of V. 307 */ 308 #define MAX_SCHEDULING_POLICY_SIZE 3 309 310 struct guc_update_scheduling_policy { 311 struct guc_update_scheduling_policy_header header; 312 u32 data[MAX_SCHEDULING_POLICY_SIZE]; 313 } __packed; 314 315 #define GUC_POWER_UNSPECIFIED 0 316 #define GUC_POWER_D0 1 317 #define GUC_POWER_D1 2 318 #define GUC_POWER_D2 3 319 #define GUC_POWER_D3 4 320 321 /* Scheduling policy settings */ 322 323 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION 100 /* in ms */ 324 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO 50 /* in percent */ 325 326 #define GLOBAL_POLICY_MAX_NUM_WI 15 327 328 /* Don't reset an engine upon preemption failure */ 329 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0) 330 331 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 332 333 /* 334 * GuC converts the timeout to clock ticks internally. Different platforms have 335 * different GuC clocks. Thus, the maximum value before overflow is platform 336 * dependent. Current worst case scenario is about 110s. So, the spec says to 337 * limit to 100s to be safe. 338 */ 339 #define GUC_POLICY_MAX_EXEC_QUANTUM_US (100 * 1000 * 1000UL) 340 #define GUC_POLICY_MAX_PREEMPT_TIMEOUT_US (100 * 1000 * 1000UL) 341 342 static inline u32 guc_policy_max_exec_quantum_ms(void) 343 { 344 BUILD_BUG_ON(GUC_POLICY_MAX_EXEC_QUANTUM_US >= UINT_MAX); 345 return GUC_POLICY_MAX_EXEC_QUANTUM_US / 1000; 346 } 347 348 static inline u32 guc_policy_max_preempt_timeout_ms(void) 349 { 350 BUILD_BUG_ON(GUC_POLICY_MAX_PREEMPT_TIMEOUT_US >= UINT_MAX); 351 return GUC_POLICY_MAX_PREEMPT_TIMEOUT_US / 1000; 352 } 353 354 struct guc_policies { 355 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 356 /* In micro seconds. How much time to allow before DPC processing is 357 * called back via interrupt (to prevent DPC queue drain starving). 358 * Typically 1000s of micro seconds (example only, not granularity). */ 359 u32 dpc_promote_time; 360 361 /* Must be set to take these new values. */ 362 u32 is_valid; 363 364 /* Max number of WIs to process per call. A large value may keep CS 365 * idle. */ 366 u32 max_num_work_items; 367 368 u32 global_flags; 369 u32 reserved[4]; 370 } __packed; 371 372 /* GuC MMIO reg state struct */ 373 struct guc_mmio_reg { 374 u32 offset; 375 u32 value; 376 u32 flags; 377 #define GUC_REGSET_MASKED BIT(0) 378 #define GUC_REGSET_NEEDS_STEERING BIT(1) 379 #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) 380 #define GUC_REGSET_RESTORE_ONLY BIT(3) 381 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12) 382 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20) 383 u32 mask; 384 } __packed; 385 386 /* GuC register sets */ 387 struct guc_mmio_reg_set { 388 u32 address; 389 u16 count; 390 u16 reserved; 391 } __packed; 392 393 /* HW info */ 394 struct guc_gt_system_info { 395 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 396 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES]; 397 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX]; 398 } __packed; 399 400 enum { 401 GUC_CAPTURE_LIST_INDEX_PF = 0, 402 GUC_CAPTURE_LIST_INDEX_VF = 1, 403 GUC_CAPTURE_LIST_INDEX_MAX = 2, 404 }; 405 406 /*Register-types of GuC capture register lists */ 407 enum guc_capture_type { 408 GUC_CAPTURE_LIST_TYPE_GLOBAL = 0, 409 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 410 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 411 GUC_CAPTURE_LIST_TYPE_MAX, 412 }; 413 414 /* GuC Additional Data Struct */ 415 struct guc_ads { 416 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 417 u32 reserved0; 418 u32 scheduler_policies; 419 u32 gt_system_info; 420 u32 reserved1; 421 u32 control_data; 422 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 423 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 424 u32 private_data; 425 u32 reserved2; 426 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 427 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 428 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX]; 429 u32 reserved[14]; 430 } __packed; 431 432 /* Engine usage stats */ 433 struct guc_engine_usage_record { 434 u32 current_context_index; 435 u32 last_switch_in_stamp; 436 u32 reserved0; 437 u32 total_runtime; 438 u32 reserved1[4]; 439 } __packed; 440 441 struct guc_engine_usage { 442 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 443 } __packed; 444 445 /* GuC logging structures */ 446 447 enum guc_log_buffer_type { 448 GUC_DEBUG_LOG_BUFFER, 449 GUC_CRASH_DUMP_LOG_BUFFER, 450 GUC_CAPTURE_LOG_BUFFER, 451 GUC_MAX_LOG_BUFFER 452 }; 453 454 /** 455 * struct guc_log_buffer_state - GuC log buffer state 456 * 457 * Below state structure is used for coordination of retrieval of GuC firmware 458 * logs. Separate state is maintained for each log buffer type. 459 * read_ptr points to the location where i915 read last in log buffer and 460 * is read only for GuC firmware. write_ptr is incremented by GuC with number 461 * of bytes written for each log entry and is read only for i915. 462 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 463 * GuC firmware expects that while it is writing to 2nd half of the buffer, 464 * first half would get consumed by Host and then get a flush completed 465 * acknowledgment from Host, so that it does not end up doing any overwrite 466 * causing loss of logs. So when buffer gets half filled & i915 has requested 467 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 468 * to the value of write_ptr and raise the interrupt. 469 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 470 * field and also update read_ptr with the value of sample_write_ptr, before 471 * sending an acknowledgment to GuC. marker & version fields are for internal 472 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 473 * time GuC detects the log buffer overflow. 474 */ 475 struct guc_log_buffer_state { 476 u32 marker[2]; 477 u32 read_ptr; 478 u32 write_ptr; 479 u32 size; 480 u32 sampled_write_ptr; 481 u32 wrap_offset; 482 union { 483 struct { 484 u32 flush_to_file:1; 485 u32 buffer_full_cnt:4; 486 u32 reserved:27; 487 }; 488 u32 flags; 489 }; 490 u32 version; 491 } __packed; 492 493 struct guc_ctx_report { 494 u32 report_return_status; 495 u32 reserved1[64]; 496 u32 affected_count; 497 u32 reserved2[2]; 498 } __packed; 499 500 /* GuC Shared Context Data Struct */ 501 struct guc_shared_ctx_data { 502 u32 addr_of_last_preempted_data_low; 503 u32 addr_of_last_preempted_data_high; 504 u32 addr_of_last_preempted_data_high_tmp; 505 u32 padding; 506 u32 is_mapped_to_proxy; 507 u32 proxy_ctx_id; 508 u32 engine_reset_ctx_id; 509 u32 media_reset_count; 510 u32 reserved1[8]; 511 u32 uk_last_ctx_switch_reason; 512 u32 was_reset; 513 u32 lrca_gpu_addr; 514 u64 execlist_ctx; 515 u32 reserved2[66]; 516 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 517 } __packed; 518 519 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 520 enum intel_guc_recv_message { 521 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 522 INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30), 523 }; 524 525 #endif 526