1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  *
5  * Authors:
6  *    Vinit Azad <vinit.azad@intel.com>
7  *    Ben Widawsky <ben@bwidawsk.net>
8  *    Dave Gordon <david.s.gordon@intel.com>
9  *    Alex Dai <yu.dai@intel.com>
10  */
11 
12 #include "gt/intel_gt.h"
13 #include "intel_guc_fw.h"
14 #include "i915_drv.h"
15 
16 static void guc_prepare_xfer(struct intel_uncore *uncore)
17 {
18 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
19 			 GUC_ENABLE_READ_CACHE_LOGIC |
20 			 GUC_ENABLE_MIA_CACHING |
21 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
22 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
23 			 GUC_ENABLE_MIA_CLOCK_GATING;
24 
25 	/* Must program this register before loading the ucode with DMA */
26 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
27 
28 	if (IS_GEN9_LP(uncore->i915))
29 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
30 	else
31 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
32 
33 	if (GRAPHICS_VER(uncore->i915) == 9) {
34 		/* DOP Clock Gating Enable for GuC clocks */
35 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
36 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
37 
38 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
39 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
40 	}
41 }
42 
43 /* Copy RSA signature from the fw image to HW for verification */
44 static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
45 			struct intel_uncore *uncore)
46 {
47 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
48 	size_t copied;
49 	int i;
50 
51 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
52 	if (copied < sizeof(rsa))
53 		return -ENOMEM;
54 
55 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
56 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
57 
58 	return 0;
59 }
60 
61 /*
62  * Read the GuC status register (GUC_STATUS) and store it in the
63  * specified location; then return a boolean indicating whether
64  * the value matches either of two values representing completion
65  * of the GuC boot process.
66  *
67  * This is used for polling the GuC status in a wait_for()
68  * loop below.
69  */
70 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
71 {
72 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
73 	u32 uk_val = val & GS_UKERNEL_MASK;
74 
75 	*status = val;
76 	return (uk_val == GS_UKERNEL_READY) ||
77 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
78 }
79 
80 static int guc_wait_ucode(struct intel_uncore *uncore)
81 {
82 	u32 status;
83 	int ret;
84 
85 	/*
86 	 * Wait for the GuC to start up.
87 	 * NB: Docs recommend not using the interrupt for completion.
88 	 * Measurements indicate this should take no more than 20ms, so a
89 	 * timeout here indicates that the GuC has failed and is unusable.
90 	 * (Higher levels of the driver may decide to reset the GuC and
91 	 * attempt the ucode load again if this happens.)
92 	 */
93 	ret = wait_for(guc_ready(uncore, &status), 100);
94 	if (ret) {
95 		struct drm_device *drm = &uncore->i915->drm;
96 
97 		drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status);
98 		drm_dbg(drm, "GuC load failed: status: Reset = %d, "
99 			"BootROM = 0x%02X, UKernel = 0x%02X, "
100 			"MIA = 0x%02X, Auth = 0x%02X\n",
101 			REG_FIELD_GET(GS_MIA_IN_RESET, status),
102 			REG_FIELD_GET(GS_BOOTROM_MASK, status),
103 			REG_FIELD_GET(GS_UKERNEL_MASK, status),
104 			REG_FIELD_GET(GS_MIA_MASK, status),
105 			REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
106 
107 		if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
108 			drm_dbg(drm, "GuC firmware signature verification failed\n");
109 			ret = -ENOEXEC;
110 		}
111 
112 		if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
113 			drm_dbg(drm, "GuC firmware exception. EIP: %#x\n",
114 				intel_uncore_read(uncore, SOFT_SCRATCH(13)));
115 			ret = -ENXIO;
116 		}
117 	}
118 
119 	return ret;
120 }
121 
122 /**
123  * intel_guc_fw_upload() - load GuC uCode to device
124  * @guc: intel_guc structure
125  *
126  * Called from intel_uc_init_hw() during driver load, resume from sleep and
127  * after a GPU reset.
128  *
129  * The firmware image should have already been fetched into memory, so only
130  * check that fetch succeeded, and then transfer the image to the h/w.
131  *
132  * Return:	non-zero code on error
133  */
134 int intel_guc_fw_upload(struct intel_guc *guc)
135 {
136 	struct intel_gt *gt = guc_to_gt(guc);
137 	struct intel_uncore *uncore = gt->uncore;
138 	int ret;
139 
140 	guc_prepare_xfer(uncore);
141 
142 	/*
143 	 * Note that GuC needs the CSS header plus uKernel code to be copied
144 	 * by the DMA engine in one operation, whereas the RSA signature is
145 	 * loaded via MMIO.
146 	 */
147 	ret = guc_xfer_rsa(&guc->fw, uncore);
148 	if (ret)
149 		goto out;
150 
151 	/*
152 	 * Current uCode expects the code to be loaded at 8k; locations below
153 	 * this are used for the stack.
154 	 */
155 	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
156 	if (ret)
157 		goto out;
158 
159 	ret = guc_wait_ucode(uncore);
160 	if (ret)
161 		goto out;
162 
163 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
164 	return 0;
165 
166 out:
167 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL);
168 	return ret;
169 }
170