1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Vinit Azad <vinit.azad@intel.com>
25  *    Ben Widawsky <ben@bwidawsk.net>
26  *    Dave Gordon <david.s.gordon@intel.com>
27  *    Alex Dai <yu.dai@intel.com>
28  */
29 
30 #include "gt/intel_gt.h"
31 #include "intel_guc_fw.h"
32 #include "i915_drv.h"
33 
34 /**
35  * intel_guc_fw_init_early() - initializes GuC firmware struct
36  * @guc: intel_guc struct
37  *
38  * On platforms with GuC selects firmware for uploading
39  */
40 void intel_guc_fw_init_early(struct intel_guc *guc)
41 {
42 	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, guc_to_gt(guc)->i915);
43 }
44 
45 static void guc_prepare_xfer(struct intel_uncore *uncore)
46 {
47 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
48 			 GUC_ENABLE_READ_CACHE_LOGIC |
49 			 GUC_ENABLE_MIA_CACHING |
50 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
51 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
52 			 GUC_ENABLE_MIA_CLOCK_GATING;
53 
54 	/* Must program this register before loading the ucode with DMA */
55 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
56 
57 	if (IS_GEN9_LP(uncore->i915))
58 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
59 	else
60 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
61 
62 	if (IS_GEN(uncore->i915, 9)) {
63 		/* DOP Clock Gating Enable for GuC clocks */
64 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
65 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
66 
67 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
68 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
69 	}
70 }
71 
72 /* Copy RSA signature from the fw image to HW for verification */
73 static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
74 			 struct intel_uncore *uncore)
75 {
76 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
77 	size_t copied;
78 	int i;
79 
80 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
81 	GEM_BUG_ON(copied < sizeof(rsa));
82 
83 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
84 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
85 }
86 
87 /*
88  * Read the GuC status register (GUC_STATUS) and store it in the
89  * specified location; then return a boolean indicating whether
90  * the value matches either of two values representing completion
91  * of the GuC boot process.
92  *
93  * This is used for polling the GuC status in a wait_for()
94  * loop below.
95  */
96 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
97 {
98 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
99 	u32 uk_val = val & GS_UKERNEL_MASK;
100 
101 	*status = val;
102 	return (uk_val == GS_UKERNEL_READY) ||
103 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
104 }
105 
106 static int guc_wait_ucode(struct intel_uncore *uncore)
107 {
108 	u32 status;
109 	int ret;
110 
111 	/*
112 	 * Wait for the GuC to start up.
113 	 * NB: Docs recommend not using the interrupt for completion.
114 	 * Measurements indicate this should take no more than 20ms, so a
115 	 * timeout here indicates that the GuC has failed and is unusable.
116 	 * (Higher levels of the driver may decide to reset the GuC and
117 	 * attempt the ucode load again if this happens.)
118 	 */
119 	ret = wait_for(guc_ready(uncore, &status), 100);
120 	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
121 
122 	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
123 		DRM_ERROR("GuC firmware signature verification failed\n");
124 		ret = -ENOEXEC;
125 	}
126 
127 	if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
128 		DRM_ERROR("GuC firmware exception. EIP: %#x\n",
129 			  intel_uncore_read(uncore, SOFT_SCRATCH(13)));
130 		ret = -ENXIO;
131 	}
132 
133 	return ret;
134 }
135 
136 /**
137  * intel_guc_fw_upload() - load GuC uCode to device
138  * @guc: intel_guc structure
139  *
140  * Called from intel_uc_init_hw() during driver load, resume from sleep and
141  * after a GPU reset.
142  *
143  * The firmware image should have already been fetched into memory, so only
144  * check that fetch succeeded, and then transfer the image to the h/w.
145  *
146  * Return:	non-zero code on error
147  */
148 int intel_guc_fw_upload(struct intel_guc *guc)
149 {
150 	struct intel_gt *gt = guc_to_gt(guc);
151 	struct intel_uncore *uncore = gt->uncore;
152 	int ret;
153 
154 	guc_prepare_xfer(uncore);
155 
156 	/*
157 	 * Note that GuC needs the CSS header plus uKernel code to be copied
158 	 * by the DMA engine in one operation, whereas the RSA signature is
159 	 * loaded via MMIO.
160 	 */
161 	guc_xfer_rsa(&guc->fw, uncore);
162 
163 	/*
164 	 * Current uCode expects the code to be loaded at 8k; locations below
165 	 * this are used for the stack.
166 	 */
167 	ret = intel_uc_fw_upload(&guc->fw, gt, 0x2000, UOS_MOVE);
168 	if (ret)
169 		goto out;
170 
171 	ret = guc_wait_ucode(uncore);
172 	if (ret)
173 		goto out;
174 
175 	guc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
176 	return 0;
177 
178 out:
179 	guc->fw.status = INTEL_UC_FIRMWARE_FAIL;
180 	return ret;
181 }
182