1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  *
5  * Authors:
6  *    Vinit Azad <vinit.azad@intel.com>
7  *    Ben Widawsky <ben@bwidawsk.net>
8  *    Dave Gordon <david.s.gordon@intel.com>
9  *    Alex Dai <yu.dai@intel.com>
10  */
11 
12 #include "gt/intel_gt.h"
13 #include "intel_guc_fw.h"
14 #include "i915_drv.h"
15 
16 /**
17  * intel_guc_fw_init_early() - initializes GuC firmware struct
18  * @guc: intel_guc struct
19  *
20  * On platforms with GuC selects firmware for uploading
21  */
22 void intel_guc_fw_init_early(struct intel_guc *guc)
23 {
24 	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
25 
26 	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915),
27 			       INTEL_INFO(i915)->platform, INTEL_REVID(i915));
28 }
29 
30 static void guc_prepare_xfer(struct intel_uncore *uncore)
31 {
32 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
33 			 GUC_ENABLE_READ_CACHE_LOGIC |
34 			 GUC_ENABLE_MIA_CACHING |
35 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
36 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
37 			 GUC_ENABLE_MIA_CLOCK_GATING;
38 
39 	/* Must program this register before loading the ucode with DMA */
40 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
41 
42 	if (IS_GEN9_LP(uncore->i915))
43 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
44 	else
45 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
46 
47 	if (IS_GEN(uncore->i915, 9)) {
48 		/* DOP Clock Gating Enable for GuC clocks */
49 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
50 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
51 
52 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
53 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
54 	}
55 }
56 
57 /* Copy RSA signature from the fw image to HW for verification */
58 static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
59 			 struct intel_uncore *uncore)
60 {
61 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
62 	size_t copied;
63 	int i;
64 
65 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
66 	GEM_BUG_ON(copied < sizeof(rsa));
67 
68 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
69 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
70 }
71 
72 /*
73  * Read the GuC status register (GUC_STATUS) and store it in the
74  * specified location; then return a boolean indicating whether
75  * the value matches either of two values representing completion
76  * of the GuC boot process.
77  *
78  * This is used for polling the GuC status in a wait_for()
79  * loop below.
80  */
81 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
82 {
83 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
84 	u32 uk_val = val & GS_UKERNEL_MASK;
85 
86 	*status = val;
87 	return (uk_val == GS_UKERNEL_READY) ||
88 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
89 }
90 
91 static int guc_wait_ucode(struct intel_uncore *uncore)
92 {
93 	u32 status;
94 	int ret;
95 
96 	/*
97 	 * Wait for the GuC to start up.
98 	 * NB: Docs recommend not using the interrupt for completion.
99 	 * Measurements indicate this should take no more than 20ms, so a
100 	 * timeout here indicates that the GuC has failed and is unusable.
101 	 * (Higher levels of the driver may decide to reset the GuC and
102 	 * attempt the ucode load again if this happens.)
103 	 */
104 	ret = wait_for(guc_ready(uncore, &status), 100);
105 	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
106 
107 	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
108 		DRM_ERROR("GuC firmware signature verification failed\n");
109 		ret = -ENOEXEC;
110 	}
111 
112 	if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
113 		DRM_ERROR("GuC firmware exception. EIP: %#x\n",
114 			  intel_uncore_read(uncore, SOFT_SCRATCH(13)));
115 		ret = -ENXIO;
116 	}
117 
118 	return ret;
119 }
120 
121 /**
122  * intel_guc_fw_upload() - load GuC uCode to device
123  * @guc: intel_guc structure
124  *
125  * Called from intel_uc_init_hw() during driver load, resume from sleep and
126  * after a GPU reset.
127  *
128  * The firmware image should have already been fetched into memory, so only
129  * check that fetch succeeded, and then transfer the image to the h/w.
130  *
131  * Return:	non-zero code on error
132  */
133 int intel_guc_fw_upload(struct intel_guc *guc)
134 {
135 	struct intel_gt *gt = guc_to_gt(guc);
136 	struct intel_uncore *uncore = gt->uncore;
137 	int ret;
138 
139 	guc_prepare_xfer(uncore);
140 
141 	/*
142 	 * Note that GuC needs the CSS header plus uKernel code to be copied
143 	 * by the DMA engine in one operation, whereas the RSA signature is
144 	 * loaded via MMIO.
145 	 */
146 	guc_xfer_rsa(&guc->fw, uncore);
147 
148 	/*
149 	 * Current uCode expects the code to be loaded at 8k; locations below
150 	 * this are used for the stack.
151 	 */
152 	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
153 	if (ret)
154 		goto out;
155 
156 	ret = guc_wait_ucode(uncore);
157 	if (ret)
158 		goto out;
159 
160 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
161 	return 0;
162 
163 out:
164 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL);
165 	return ret;
166 }
167