1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  *
5  * Authors:
6  *    Vinit Azad <vinit.azad@intel.com>
7  *    Ben Widawsky <ben@bwidawsk.net>
8  *    Dave Gordon <david.s.gordon@intel.com>
9  *    Alex Dai <yu.dai@intel.com>
10  */
11 
12 #include "gt/intel_gt.h"
13 #include "intel_guc_fw.h"
14 #include "i915_drv.h"
15 
16 static void guc_prepare_xfer(struct intel_uncore *uncore)
17 {
18 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
19 			 GUC_ENABLE_READ_CACHE_LOGIC |
20 			 GUC_ENABLE_MIA_CACHING |
21 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
22 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
23 			 GUC_ENABLE_MIA_CLOCK_GATING;
24 
25 	/* Must program this register before loading the ucode with DMA */
26 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
27 
28 	if (IS_GEN9_LP(uncore->i915))
29 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
30 	else
31 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
32 
33 	if (IS_GEN(uncore->i915, 9)) {
34 		/* DOP Clock Gating Enable for GuC clocks */
35 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
36 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
37 
38 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
39 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
40 	}
41 }
42 
43 /* Copy RSA signature from the fw image to HW for verification */
44 static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
45 			 struct intel_uncore *uncore)
46 {
47 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
48 	size_t copied;
49 	int i;
50 
51 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
52 	GEM_BUG_ON(copied < sizeof(rsa));
53 
54 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
55 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
56 }
57 
58 /*
59  * Read the GuC status register (GUC_STATUS) and store it in the
60  * specified location; then return a boolean indicating whether
61  * the value matches either of two values representing completion
62  * of the GuC boot process.
63  *
64  * This is used for polling the GuC status in a wait_for()
65  * loop below.
66  */
67 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
68 {
69 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
70 	u32 uk_val = val & GS_UKERNEL_MASK;
71 
72 	*status = val;
73 	return (uk_val == GS_UKERNEL_READY) ||
74 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
75 }
76 
77 static int guc_wait_ucode(struct intel_uncore *uncore)
78 {
79 	struct drm_device *drm = &uncore->i915->drm;
80 	u32 status;
81 	int ret;
82 
83 	/*
84 	 * Wait for the GuC to start up.
85 	 * NB: Docs recommend not using the interrupt for completion.
86 	 * Measurements indicate this should take no more than 20ms, so a
87 	 * timeout here indicates that the GuC has failed and is unusable.
88 	 * (Higher levels of the driver may decide to reset the GuC and
89 	 * attempt the ucode load again if this happens.)
90 	 */
91 	ret = wait_for(guc_ready(uncore, &status), 100);
92 	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
93 
94 	if (ret) {
95 		drm_err(drm, "GuC load failed: status = 0x%08X\n", status);
96 		drm_err(drm, "GuC load failed: status: Reset = %d, "
97 			"BootROM = 0x%02X, UKernel = 0x%02X, "
98 			"MIA = 0x%02X, Auth = 0x%02X\n",
99 			REG_FIELD_GET(GS_MIA_IN_RESET, status),
100 			REG_FIELD_GET(GS_BOOTROM_MASK, status),
101 			REG_FIELD_GET(GS_UKERNEL_MASK, status),
102 			REG_FIELD_GET(GS_MIA_MASK, status),
103 			REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
104 
105 		if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
106 			drm_err(drm, "GuC firmware signature verification failed\n");
107 			ret = -ENOEXEC;
108 		}
109 
110 		if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
111 			drm_err(drm, "GuC firmware exception. EIP: %#x\n",
112 				intel_uncore_read(uncore, SOFT_SCRATCH(13)));
113 			ret = -ENXIO;
114 		}
115 	}
116 
117 	return ret;
118 }
119 
120 /**
121  * intel_guc_fw_upload() - load GuC uCode to device
122  * @guc: intel_guc structure
123  *
124  * Called from intel_uc_init_hw() during driver load, resume from sleep and
125  * after a GPU reset.
126  *
127  * The firmware image should have already been fetched into memory, so only
128  * check that fetch succeeded, and then transfer the image to the h/w.
129  *
130  * Return:	non-zero code on error
131  */
132 int intel_guc_fw_upload(struct intel_guc *guc)
133 {
134 	struct intel_gt *gt = guc_to_gt(guc);
135 	struct intel_uncore *uncore = gt->uncore;
136 	int ret;
137 
138 	guc_prepare_xfer(uncore);
139 
140 	/*
141 	 * Note that GuC needs the CSS header plus uKernel code to be copied
142 	 * by the DMA engine in one operation, whereas the RSA signature is
143 	 * loaded via MMIO.
144 	 */
145 	guc_xfer_rsa(&guc->fw, uncore);
146 
147 	/*
148 	 * Current uCode expects the code to be loaded at 8k; locations below
149 	 * this are used for the stack.
150 	 */
151 	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
152 	if (ret)
153 		goto out;
154 
155 	ret = guc_wait_ucode(uncore);
156 	if (ret)
157 		goto out;
158 
159 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
160 	return 0;
161 
162 out:
163 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL);
164 	return ret;
165 }
166