1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2019 Intel Corporation
4  *
5  * Authors:
6  *    Vinit Azad <vinit.azad@intel.com>
7  *    Ben Widawsky <ben@bwidawsk.net>
8  *    Dave Gordon <david.s.gordon@intel.com>
9  *    Alex Dai <yu.dai@intel.com>
10  */
11 
12 #include "gt/intel_gt.h"
13 #include "gt/intel_gt_regs.h"
14 #include "intel_guc_fw.h"
15 #include "i915_drv.h"
16 
17 static void guc_prepare_xfer(struct intel_uncore *uncore)
18 {
19 	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
20 			 GUC_ENABLE_READ_CACHE_LOGIC |
21 			 GUC_ENABLE_MIA_CACHING |
22 			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
23 			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
24 			 GUC_ENABLE_MIA_CLOCK_GATING;
25 
26 	/* Must program this register before loading the ucode with DMA */
27 	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
28 
29 	if (IS_GEN9_LP(uncore->i915))
30 		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
31 	else
32 		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
33 
34 	if (GRAPHICS_VER(uncore->i915) == 9) {
35 		/* DOP Clock Gating Enable for GuC clocks */
36 		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
37 				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
38 
39 		/* allows for 5us (in 10ns units) before GT can go to RC6 */
40 		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
41 	}
42 }
43 
44 static int guc_xfer_rsa_mmio(struct intel_uc_fw *guc_fw,
45 			     struct intel_uncore *uncore)
46 {
47 	u32 rsa[UOS_RSA_SCRATCH_COUNT];
48 	size_t copied;
49 	int i;
50 
51 	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
52 	if (copied < sizeof(rsa))
53 		return -ENOMEM;
54 
55 	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
56 		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
57 
58 	return 0;
59 }
60 
61 static int guc_xfer_rsa_vma(struct intel_uc_fw *guc_fw,
62 			    struct intel_uncore *uncore)
63 {
64 	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
65 
66 	intel_uncore_write(uncore, UOS_RSA_SCRATCH(0),
67 			   intel_guc_ggtt_offset(guc, guc_fw->rsa_data));
68 
69 	return 0;
70 }
71 
72 /* Copy RSA signature from the fw image to HW for verification */
73 static int guc_xfer_rsa(struct intel_uc_fw *guc_fw,
74 			struct intel_uncore *uncore)
75 {
76 	if (guc_fw->rsa_data)
77 		return guc_xfer_rsa_vma(guc_fw, uncore);
78 	else
79 		return guc_xfer_rsa_mmio(guc_fw, uncore);
80 }
81 
82 /*
83  * Read the GuC status register (GUC_STATUS) and store it in the
84  * specified location; then return a boolean indicating whether
85  * the value matches either of two values representing completion
86  * of the GuC boot process.
87  *
88  * This is used for polling the GuC status in a wait_for()
89  * loop below.
90  */
91 static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
92 {
93 	u32 val = intel_uncore_read(uncore, GUC_STATUS);
94 	u32 uk_val = val & GS_UKERNEL_MASK;
95 
96 	*status = val;
97 	return (uk_val == GS_UKERNEL_READY) ||
98 		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
99 }
100 
101 static int guc_wait_ucode(struct intel_uncore *uncore)
102 {
103 	u32 status;
104 	int ret;
105 
106 	/*
107 	 * Wait for the GuC to start up.
108 	 * NB: Docs recommend not using the interrupt for completion.
109 	 * Measurements indicate this should take no more than 20ms, so a
110 	 * timeout here indicates that the GuC has failed and is unusable.
111 	 * (Higher levels of the driver may decide to reset the GuC and
112 	 * attempt the ucode load again if this happens.)
113 	 */
114 	ret = wait_for(guc_ready(uncore, &status), 100);
115 	if (ret) {
116 		struct drm_device *drm = &uncore->i915->drm;
117 
118 		drm_dbg(drm, "GuC load failed: status = 0x%08X\n", status);
119 		drm_dbg(drm, "GuC load failed: status: Reset = %d, "
120 			"BootROM = 0x%02X, UKernel = 0x%02X, "
121 			"MIA = 0x%02X, Auth = 0x%02X\n",
122 			REG_FIELD_GET(GS_MIA_IN_RESET, status),
123 			REG_FIELD_GET(GS_BOOTROM_MASK, status),
124 			REG_FIELD_GET(GS_UKERNEL_MASK, status),
125 			REG_FIELD_GET(GS_MIA_MASK, status),
126 			REG_FIELD_GET(GS_AUTH_STATUS_MASK, status));
127 
128 		if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
129 			drm_dbg(drm, "GuC firmware signature verification failed\n");
130 			ret = -ENOEXEC;
131 		}
132 
133 		if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
134 			drm_dbg(drm, "GuC firmware exception. EIP: %#x\n",
135 				intel_uncore_read(uncore, SOFT_SCRATCH(13)));
136 			ret = -ENXIO;
137 		}
138 	}
139 
140 	return ret;
141 }
142 
143 /**
144  * intel_guc_fw_upload() - load GuC uCode to device
145  * @guc: intel_guc structure
146  *
147  * Called from intel_uc_init_hw() during driver load, resume from sleep and
148  * after a GPU reset.
149  *
150  * The firmware image should have already been fetched into memory, so only
151  * check that fetch succeeded, and then transfer the image to the h/w.
152  *
153  * Return:	non-zero code on error
154  */
155 int intel_guc_fw_upload(struct intel_guc *guc)
156 {
157 	struct intel_gt *gt = guc_to_gt(guc);
158 	struct intel_uncore *uncore = gt->uncore;
159 	int ret;
160 
161 	guc_prepare_xfer(uncore);
162 
163 	/*
164 	 * Note that GuC needs the CSS header plus uKernel code to be copied
165 	 * by the DMA engine in one operation, whereas the RSA signature is
166 	 * loaded separately, either by copying it to the UOS_RSA_SCRATCH
167 	 * register (if key size <= 256) or through a ggtt-pinned vma (if key
168 	 * size > 256). The RSA size and therefore the way we provide it to the
169 	 * HW is fixed for each platform and hard-coded in the bootrom.
170 	 */
171 	ret = guc_xfer_rsa(&guc->fw, uncore);
172 	if (ret)
173 		goto out;
174 
175 	/*
176 	 * Current uCode expects the code to be loaded at 8k; locations below
177 	 * this are used for the stack.
178 	 */
179 	ret = intel_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE);
180 	if (ret)
181 		goto out;
182 
183 	ret = guc_wait_ucode(uncore);
184 	if (ret)
185 		goto out;
186 
187 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING);
188 	return 0;
189 
190 out:
191 	intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
192 	return ret;
193 }
194