1 /*
2  * Copyright © 2016-2017 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #ifndef _INTEL_GUC_CT_H_
25 #define _INTEL_GUC_CT_H_
26 
27 #include <linux/spinlock.h>
28 #include <linux/workqueue.h>
29 
30 #include "intel_guc_fwif.h"
31 
32 struct i915_vma;
33 struct intel_guc;
34 
35 /**
36  * DOC: Command Transport (CT).
37  *
38  * Buffer based command transport is a replacement for MMIO based mechanism.
39  * It can be used to perform both host-2-guc and guc-to-host communication.
40  */
41 
42 /** Represents single command transport buffer.
43  *
44  * A single command transport buffer consists of two parts, the header
45  * record (command transport buffer descriptor) and the actual buffer which
46  * holds the commands.
47  *
48  * @desc: pointer to the buffer descriptor
49  * @cmds: pointer to the commands buffer
50  */
51 struct intel_guc_ct_buffer {
52 	struct guc_ct_buffer_desc *desc;
53 	u32 *cmds;
54 };
55 
56 /** Represents pair of command transport buffers.
57  *
58  * Buffers go in pairs to allow bi-directional communication.
59  * To simplify the code we place both of them in the same vma.
60  * Buffers from the same pair must share unique owner id.
61  *
62  * @vma: pointer to the vma with pair of CT buffers
63  * @ctbs: buffers for sending(0) and receiving(1) commands
64  * @owner: unique identifier
65  * @next_fence: fence to be used with next send command
66  */
67 struct intel_guc_ct_channel {
68 	struct i915_vma *vma;
69 	struct intel_guc_ct_buffer ctbs[2];
70 	u32 owner;
71 	u32 next_fence;
72 	bool enabled;
73 };
74 
75 /** Holds all command transport channels.
76  *
77  * @host_channel: main channel used by the host
78  */
79 struct intel_guc_ct {
80 	struct intel_guc_ct_channel host_channel;
81 	/* other channels are tbd */
82 
83 	/** @lock: protects pending requests list */
84 	spinlock_t lock;
85 
86 	/** @pending_requests: list of requests waiting for response */
87 	struct list_head pending_requests;
88 
89 	/** @incoming_requests: list of incoming requests */
90 	struct list_head incoming_requests;
91 
92 	/** @worker: worker for handling incoming requests */
93 	struct work_struct worker;
94 };
95 
96 void intel_guc_ct_init_early(struct intel_guc_ct *ct);
97 int intel_guc_ct_init(struct intel_guc_ct *ct);
98 void intel_guc_ct_fini(struct intel_guc_ct *ct);
99 int intel_guc_ct_enable(struct intel_guc_ct *ct);
100 void intel_guc_ct_disable(struct intel_guc_ct *ct);
101 
102 static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
103 {
104 	ct->host_channel.enabled = false;
105 }
106 
107 int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
108 		      u32 *response_buf, u32 response_buf_size);
109 void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
110 
111 #endif /* _INTEL_GUC_CT_H_ */
112