1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2022 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include <drm/drm_print.h> 9 10 #include "gt/intel_engine_regs.h" 11 #include "gt/intel_gt.h" 12 #include "gt/intel_gt_mcr.h" 13 #include "gt/intel_gt_regs.h" 14 #include "gt/intel_lrc.h" 15 #include "guc_capture_fwif.h" 16 #include "intel_guc_capture.h" 17 #include "intel_guc_fwif.h" 18 #include "intel_guc_print.h" 19 #include "i915_drv.h" 20 #include "i915_gpu_error.h" 21 #include "i915_irq.h" 22 #include "i915_memcpy.h" 23 #include "i915_reg.h" 24 25 /* 26 * Define all device tables of GuC error capture register lists 27 * NOTE: For engine-registers, GuC only needs the register offsets 28 * from the engine-mmio-base 29 */ 30 #define COMMON_BASE_GLOBAL \ 31 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } 32 33 #define COMMON_GEN9BASE_GLOBAL \ 34 { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 35 { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ 36 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ 37 { DONE_REG, 0, 0, "DONE_REG" }, \ 38 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } 39 40 #define COMMON_GEN12BASE_GLOBAL \ 41 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ 42 { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ 43 { GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG" }, \ 44 { GEN12_GAM_DONE, 0, 0, "GAM_DONE" }, \ 45 { GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG" } 46 47 #define COMMON_BASE_ENGINE_INSTANCE \ 48 { RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \ 49 { RING_ESR(0), 0, 0, "ESR" }, \ 50 { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW" }, \ 51 { RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW" }, \ 52 { RING_IPEIR(0), 0, 0, "IPEIR" }, \ 53 { RING_IPEHR(0), 0, 0, "IPEHR" }, \ 54 { RING_INSTPS(0), 0, 0, "INSTPS" }, \ 55 { RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32" }, \ 56 { RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32" }, \ 57 { RING_BBSTATE(0), 0, 0, "BB_STATE" }, \ 58 { CCID(0), 0, 0, "CCID" }, \ 59 { RING_ACTHD(0), 0, 0, "ACTHD_LDW" }, \ 60 { RING_ACTHD_UDW(0), 0, 0, "ACTHD_UDW" }, \ 61 { RING_INSTPM(0), 0, 0, "INSTPM" }, \ 62 { RING_INSTDONE(0), 0, 0, "INSTDONE" }, \ 63 { RING_NOPID(0), 0, 0, "RING_NOPID" }, \ 64 { RING_START(0), 0, 0, "START" }, \ 65 { RING_HEAD(0), 0, 0, "HEAD" }, \ 66 { RING_TAIL(0), 0, 0, "TAIL" }, \ 67 { RING_CTL(0), 0, 0, "CTL" }, \ 68 { RING_MI_MODE(0), 0, 0, "MODE" }, \ 69 { RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL" }, \ 70 { RING_HWS_PGA(0), 0, 0, "HWS" }, \ 71 { RING_MODE_GEN7(0), 0, 0, "GFX_MODE" }, \ 72 { GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW" }, \ 73 { GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW" }, \ 74 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \ 75 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \ 76 { GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW" }, \ 77 { GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW" }, \ 78 { GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW" }, \ 79 { GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW" } 80 81 #define COMMON_BASE_HAS_EU \ 82 { EIR, 0, 0, "EIR" } 83 84 #define COMMON_BASE_RENDER \ 85 { GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE" } 86 87 #define COMMON_GEN12BASE_RENDER \ 88 { GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA" }, \ 89 { GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2" } 90 91 #define COMMON_GEN12BASE_VEC \ 92 { GEN12_SFC_DONE(0), 0, 0, "SFC_DONE[0]" }, \ 93 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \ 94 { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \ 95 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" } 96 97 /* XE_LPD - Global */ 98 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = { 99 COMMON_BASE_GLOBAL, 100 COMMON_GEN9BASE_GLOBAL, 101 COMMON_GEN12BASE_GLOBAL, 102 }; 103 104 /* XE_LPD - Render / Compute Per-Class */ 105 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = { 106 COMMON_BASE_HAS_EU, 107 COMMON_BASE_RENDER, 108 COMMON_GEN12BASE_RENDER, 109 }; 110 111 /* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */ 112 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = { 113 COMMON_BASE_ENGINE_INSTANCE, 114 }; 115 116 /* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */ 117 static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = { 118 COMMON_BASE_ENGINE_INSTANCE, 119 }; 120 121 /* XE_LPD - Video Enhancement Per-Class */ 122 static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = { 123 COMMON_GEN12BASE_VEC, 124 }; 125 126 /* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */ 127 static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = { 128 COMMON_BASE_ENGINE_INSTANCE, 129 }; 130 131 /* GEN9/XE_LPD - Blitter Per-Engine-Instance */ 132 static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = { 133 COMMON_BASE_ENGINE_INSTANCE, 134 }; 135 136 /* XE_LPD - GSC Per-Engine-Instance */ 137 static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { 138 COMMON_BASE_ENGINE_INSTANCE, 139 }; 140 141 /* GEN9 - Global */ 142 static const struct __guc_mmio_reg_descr default_global_regs[] = { 143 COMMON_BASE_GLOBAL, 144 COMMON_GEN9BASE_GLOBAL, 145 }; 146 147 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { 148 COMMON_BASE_HAS_EU, 149 COMMON_BASE_RENDER, 150 }; 151 152 /* 153 * Empty lists: 154 * GEN9/XE_LPD - Blitter Per-Class 155 * GEN9/XE_LPD - Media Decode/Encode Per-Class 156 * GEN9 - VEC Class 157 */ 158 static const struct __guc_mmio_reg_descr empty_regs_list[] = { 159 }; 160 161 #define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) 162 #define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) 163 #define MAKE_REGLIST(regslist, regsowner, regstype, class) \ 164 { \ 165 regslist, \ 166 ARRAY_SIZE(regslist), \ 167 TO_GCAP_DEF_OWNER(regsowner), \ 168 TO_GCAP_DEF_TYPE(regstype), \ 169 class, \ 170 NULL, \ 171 } 172 173 /* List of lists */ 174 static const struct __guc_mmio_reg_descr_group default_lists[] = { 175 MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0), 176 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 177 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 178 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), 179 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), 180 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 181 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 182 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 183 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 184 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 185 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 186 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), 187 MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), 188 {} 189 }; 190 191 static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = { 192 MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0), 193 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 194 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 195 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), 196 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), 197 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 198 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 199 MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 200 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 201 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 202 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 203 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), 204 MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), 205 {} 206 }; 207 208 static const struct __guc_mmio_reg_descr_group * 209 guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, 210 u32 owner, u32 type, u32 id) 211 { 212 int i; 213 214 if (!reglists) 215 return NULL; 216 217 for (i = 0; reglists[i].list; ++i) { 218 if (reglists[i].owner == owner && reglists[i].type == type && 219 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 220 return ®lists[i]; 221 } 222 223 return NULL; 224 } 225 226 static struct __guc_mmio_reg_descr_group * 227 guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, 228 u32 owner, u32 type, u32 id) 229 { 230 int i; 231 232 if (!reglists) 233 return NULL; 234 235 for (i = 0; reglists[i].extlist; ++i) { 236 if (reglists[i].owner == owner && reglists[i].type == type && 237 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 238 return ®lists[i]; 239 } 240 241 return NULL; 242 } 243 244 static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglists) 245 { 246 int i = 0; 247 248 if (!reglists) 249 return; 250 251 while (reglists[i].extlist) 252 kfree(reglists[i++].extlist); 253 } 254 255 struct __ext_steer_reg { 256 const char *name; 257 i915_mcr_reg_t reg; 258 }; 259 260 static const struct __ext_steer_reg xe_extregs[] = { 261 {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE}, 262 {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE} 263 }; 264 265 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, 266 const struct __ext_steer_reg *extlist, 267 int slice_id, int subslice_id) 268 { 269 ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg)); 270 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 271 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); 272 ext->regname = extlist->name; 273 } 274 275 static int 276 __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, 277 const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) 278 { 279 struct __guc_mmio_reg_descr *list; 280 281 list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); 282 if (!list) 283 return -ENOMEM; 284 285 newlist->extlist = list; 286 newlist->num_regs = num_regs; 287 newlist->owner = rootlist->owner; 288 newlist->engine = rootlist->engine; 289 newlist->type = rootlist->type; 290 291 return 0; 292 } 293 294 static void 295 guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, 296 const struct __guc_mmio_reg_descr_group *lists) 297 { 298 struct intel_gt *gt = guc_to_gt(guc); 299 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; 300 const struct __guc_mmio_reg_descr_group *list; 301 struct __guc_mmio_reg_descr_group *extlists; 302 struct __guc_mmio_reg_descr *extarray; 303 struct sseu_dev_info *sseu; 304 305 /* In XE_LPD we only have steered registers for the render-class */ 306 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 307 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 308 /* skip if extlists was previously allocated */ 309 if (!list || guc->capture->extlists) 310 return; 311 312 num_steer_regs = ARRAY_SIZE(xe_extregs); 313 314 sseu = >->info.sseu; 315 for_each_ss_steering(iter, gt, slice, subslice) 316 num_tot_regs += num_steer_regs; 317 318 if (!num_tot_regs) 319 return; 320 321 /* allocate an extra for an end marker */ 322 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 323 if (!extlists) 324 return; 325 326 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 327 kfree(extlists); 328 return; 329 } 330 331 extarray = extlists[0].extlist; 332 for_each_ss_steering(iter, gt, slice, subslice) { 333 for (i = 0; i < num_steer_regs; ++i) { 334 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 335 ++extarray; 336 } 337 } 338 339 guc->capture->extlists = extlists; 340 } 341 342 static const struct __ext_steer_reg xehpg_extregs[] = { 343 {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} 344 }; 345 346 static bool __has_xehpg_extregs(u32 ipver) 347 { 348 return (ipver >= IP_VER(12, 55)); 349 } 350 351 static void 352 guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, 353 const struct __guc_mmio_reg_descr_group *lists, 354 u32 ipver) 355 { 356 struct intel_gt *gt = guc_to_gt(guc); 357 struct sseu_dev_info *sseu; 358 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; 359 const struct __guc_mmio_reg_descr_group *list; 360 struct __guc_mmio_reg_descr_group *extlists; 361 struct __guc_mmio_reg_descr *extarray; 362 363 /* In XE_LP / HPG we only have render-class steering registers during error-capture */ 364 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 365 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 366 /* skip if extlists was previously allocated */ 367 if (!list || guc->capture->extlists) 368 return; 369 370 num_steer_regs = ARRAY_SIZE(xe_extregs); 371 if (__has_xehpg_extregs(ipver)) 372 num_steer_regs += ARRAY_SIZE(xehpg_extregs); 373 374 sseu = >->info.sseu; 375 for_each_ss_steering(iter, gt, slice, subslice) 376 num_tot_regs += num_steer_regs; 377 378 if (!num_tot_regs) 379 return; 380 381 /* allocate an extra for an end marker */ 382 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 383 if (!extlists) 384 return; 385 386 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 387 kfree(extlists); 388 return; 389 } 390 391 extarray = extlists[0].extlist; 392 for_each_ss_steering(iter, gt, slice, subslice) { 393 for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { 394 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 395 ++extarray; 396 } 397 if (__has_xehpg_extregs(ipver)) { 398 for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { 399 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); 400 ++extarray; 401 } 402 } 403 } 404 405 guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs); 406 guc->capture->extlists = extlists; 407 } 408 409 static const struct __guc_mmio_reg_descr_group * 410 guc_capture_get_device_reglist(struct intel_guc *guc) 411 { 412 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 413 414 if (GRAPHICS_VER(i915) > 11) { 415 /* 416 * For certain engine classes, there are slice and subslice 417 * level registers requiring steering. We allocate and populate 418 * these at init time based on hw config add it as an extension 419 * list at the end of the pre-populated render list. 420 */ 421 if (IS_DG2(i915)) 422 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)); 423 else if (IS_XEHPSDV(i915)) 424 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)); 425 else 426 guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists); 427 428 return xe_lpd_lists; 429 } 430 431 /* if GuC submission is enabled on a non-POR platform, just use a common baseline */ 432 return default_lists; 433 } 434 435 static const char * 436 __stringify_type(u32 type) 437 { 438 switch (type) { 439 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 440 return "Global"; 441 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 442 return "Class"; 443 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 444 return "Instance"; 445 default: 446 break; 447 } 448 449 return "unknown"; 450 } 451 452 static const char * 453 __stringify_engclass(u32 class) 454 { 455 switch (class) { 456 case GUC_RENDER_CLASS: 457 return "Render"; 458 case GUC_VIDEO_CLASS: 459 return "Video"; 460 case GUC_VIDEOENHANCE_CLASS: 461 return "VideoEnhance"; 462 case GUC_BLITTER_CLASS: 463 return "Blitter"; 464 case GUC_COMPUTE_CLASS: 465 return "Compute"; 466 case GUC_GSC_OTHER_CLASS: 467 return "GSC-Other"; 468 default: 469 break; 470 } 471 472 return "unknown"; 473 } 474 475 static int 476 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 477 struct guc_mmio_reg *ptr, u16 num_entries) 478 { 479 u32 i = 0, j = 0; 480 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 481 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 482 const struct __guc_mmio_reg_descr_group *match; 483 struct __guc_mmio_reg_descr_group *matchext; 484 485 if (!reglists) 486 return -ENODEV; 487 488 match = guc_capture_get_one_list(reglists, owner, type, classid); 489 if (!match) 490 return -ENODATA; 491 492 for (i = 0; i < num_entries && i < match->num_regs; ++i) { 493 ptr[i].offset = match->list[i].reg.reg; 494 ptr[i].value = 0xDEADF00D; 495 ptr[i].flags = match->list[i].flags; 496 ptr[i].mask = match->list[i].mask; 497 } 498 499 matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid); 500 if (matchext) { 501 for (i = match->num_regs, j = 0; i < num_entries && 502 i < (match->num_regs + matchext->num_regs) && 503 j < matchext->num_regs; ++i, ++j) { 504 ptr[i].offset = matchext->extlist[j].reg.reg; 505 ptr[i].value = 0xDEADF00D; 506 ptr[i].flags = matchext->extlist[j].flags; 507 ptr[i].mask = matchext->extlist[j].mask; 508 } 509 } 510 if (i < num_entries) 511 guc_dbg(guc, "Got short capture reglist init: %d out %d.\n", i, num_entries); 512 513 return 0; 514 } 515 516 static int 517 guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid) 518 { 519 const struct __guc_mmio_reg_descr_group *match; 520 struct __guc_mmio_reg_descr_group *matchext; 521 int num_regs; 522 523 match = guc_capture_get_one_list(gc->reglists, owner, type, classid); 524 if (!match) 525 return 0; 526 527 num_regs = match->num_regs; 528 529 matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid); 530 if (matchext) 531 num_regs += matchext->num_regs; 532 533 return num_regs; 534 } 535 536 static int 537 guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 538 size_t *size, bool is_purpose_est) 539 { 540 struct intel_guc_state_capture *gc = guc->capture; 541 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 542 int num_regs; 543 544 if (!gc->reglists) { 545 guc_warn(guc, "No capture reglist for this device\n"); 546 return -ENODEV; 547 } 548 549 if (cache->is_valid) { 550 *size = cache->size; 551 return cache->status; 552 } 553 554 if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF && 555 !guc_capture_get_one_list(gc->reglists, owner, type, classid)) { 556 if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL) 557 guc_warn(guc, "Missing capture reglist: global!\n"); 558 else 559 guc_warn(guc, "Missing capture reglist: %s(%u):%s(%u)!\n", 560 __stringify_type(type), type, 561 __stringify_engclass(classid), classid); 562 return -ENODATA; 563 } 564 565 num_regs = guc_cap_list_num_regs(gc, owner, type, classid); 566 /* intentional empty lists can exist depending on hw config */ 567 if (!num_regs) 568 return -ENODATA; 569 570 if (size) 571 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + 572 (num_regs * sizeof(struct guc_mmio_reg))); 573 574 return 0; 575 } 576 577 int 578 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 579 size_t *size) 580 { 581 return guc_capture_getlistsize(guc, owner, type, classid, size, false); 582 } 583 584 static void guc_capture_create_prealloc_nodes(struct intel_guc *guc); 585 586 int 587 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 588 void **outptr) 589 { 590 struct intel_guc_state_capture *gc = guc->capture; 591 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 592 struct guc_debug_capture_list *listnode; 593 int ret, num_regs; 594 u8 *caplist, *tmp; 595 size_t size = 0; 596 597 if (!gc->reglists) 598 return -ENODEV; 599 600 if (cache->is_valid) { 601 *outptr = cache->ptr; 602 return cache->status; 603 } 604 605 /* 606 * ADS population of input registers is a good 607 * time to pre-allocate cachelist output nodes 608 */ 609 guc_capture_create_prealloc_nodes(guc); 610 611 ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size); 612 if (ret) { 613 cache->is_valid = true; 614 cache->ptr = NULL; 615 cache->size = 0; 616 cache->status = ret; 617 return ret; 618 } 619 620 caplist = kzalloc(size, GFP_KERNEL); 621 if (!caplist) { 622 guc_dbg(guc, "Failed to alloc cached register capture list"); 623 return -ENOMEM; 624 } 625 626 /* populate capture list header */ 627 tmp = caplist; 628 num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); 629 listnode = (struct guc_debug_capture_list *)tmp; 630 listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); 631 632 /* populate list of register descriptor */ 633 tmp += sizeof(struct guc_debug_capture_list); 634 guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); 635 636 /* cache this list */ 637 cache->is_valid = true; 638 cache->ptr = caplist; 639 cache->size = size; 640 cache->status = 0; 641 642 *outptr = caplist; 643 644 return 0; 645 } 646 647 int 648 intel_guc_capture_getnullheader(struct intel_guc *guc, 649 void **outptr, size_t *size) 650 { 651 struct intel_guc_state_capture *gc = guc->capture; 652 int tmp = sizeof(u32) * 4; 653 void *null_header; 654 655 if (gc->ads_null_cache) { 656 *outptr = gc->ads_null_cache; 657 *size = tmp; 658 return 0; 659 } 660 661 null_header = kzalloc(tmp, GFP_KERNEL); 662 if (!null_header) { 663 guc_dbg(guc, "Failed to alloc cached register capture null list"); 664 return -ENOMEM; 665 } 666 667 gc->ads_null_cache = null_header; 668 *outptr = null_header; 669 *size = tmp; 670 671 return 0; 672 } 673 674 static int 675 guc_capture_output_min_size_est(struct intel_guc *guc) 676 { 677 struct intel_gt *gt = guc_to_gt(guc); 678 struct intel_engine_cs *engine; 679 enum intel_engine_id id; 680 int worst_min_size = 0; 681 size_t tmp = 0; 682 683 if (!guc->capture) 684 return -ENODEV; 685 686 /* 687 * If every single engine-instance suffered a failure in quick succession but 688 * were all unrelated, then a burst of multiple error-capture events would dump 689 * registers for every one engine instance, one at a time. In this case, GuC 690 * would even dump the global-registers repeatedly. 691 * 692 * For each engine instance, there would be 1 x guc_state_capture_group_t output 693 * followed by 3 x guc_state_capture_t lists. The latter is how the register 694 * dumps are split across different register types (where the '3' are global vs class 695 * vs instance). 696 */ 697 for_each_engine(engine, gt, id) { 698 worst_min_size += sizeof(struct guc_state_capture_group_header_t) + 699 (3 * sizeof(struct guc_state_capture_header_t)); 700 701 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) 702 worst_min_size += tmp; 703 704 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 705 engine->class, &tmp, true)) { 706 worst_min_size += tmp; 707 } 708 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 709 engine->class, &tmp, true)) { 710 worst_min_size += tmp; 711 } 712 } 713 714 return worst_min_size; 715 } 716 717 /* 718 * Add on a 3x multiplier to allow for multiple back-to-back captures occurring 719 * before the i915 can read the data out and process it 720 */ 721 #define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 722 723 static void check_guc_capture_size(struct intel_guc *guc) 724 { 725 int min_size = guc_capture_output_min_size_est(guc); 726 int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; 727 u32 buffer_size = intel_guc_log_section_size_capture(&guc->log); 728 729 /* 730 * NOTE: min_size is much smaller than the capture region allocation (DG2: <80K vs 1MB) 731 * Additionally, its based on space needed to fit all engines getting reset at once 732 * within the same G2H handler task slot. This is very unlikely. However, if GuC really 733 * does run out of space for whatever reason, we will see an separate warning message 734 * when processing the G2H event capture-notification, search for: 735 * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE. 736 */ 737 if (min_size < 0) 738 guc_warn(guc, "Failed to calculate error state capture buffer minimum size: %d!\n", 739 min_size); 740 else if (min_size > buffer_size) 741 guc_warn(guc, "Error state capture buffer maybe small: %d < %d\n", 742 buffer_size, min_size); 743 else if (spare_size > buffer_size) 744 guc_dbg(guc, "Error state capture buffer lacks spare size: %d < %d (min = %d)\n", 745 buffer_size, spare_size, min_size); 746 } 747 748 /* 749 * KMD Init time flows: 750 * -------------------- 751 * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). 752 * intel_guc_ads acquires the register lists by calling 753 * intel_guc_capture_list_size and intel_guc_capture_list_get 'n' times, 754 * where n = 1 for global-reg-list + 755 * num_engine_classes for class-reg-list + 756 * num_engine_classes for instance-reg-list 757 * (since all instances of the same engine-class type 758 * have an identical engine-instance register-list). 759 * ADS module also calls separately for PF vs VF. 760 * 761 * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) 762 * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) 763 * Note2: 'x 3' to hold multiple capture groups 764 * 765 * GUC Runtime notify capture: 766 * -------------------------- 767 * --> G2H STATE_CAPTURE_NOTIFICATION 768 * L--> intel_guc_capture_process 769 * L--> Loop through B (head..tail) and for each engine instance's 770 * err-state-captured register-list we find, we alloc 'C': 771 * --> alloc C: A capture-output-node structure that includes misc capture info along 772 * with 3 register list dumps (global, engine-class and engine-instance) 773 * This node is created from a pre-allocated list of blank nodes in 774 * guc->capture->cachelist and populated with the error-capture 775 * data from GuC and then it's added into guc->capture->outlist linked 776 * list. This list is used for matchup and printout by i915_gpu_coredump 777 * and err_print_gt, (when user invokes the error capture sysfs). 778 * 779 * GUC --> notify context reset: 780 * ----------------------------- 781 * --> G2H CONTEXT RESET 782 * L--> guc_handle_context_reset --> i915_capture_error_state 783 * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> gt_record_engines 784 * --> capture_engine(..IS_GUC_CAPTURE) 785 * L--> intel_guc_capture_get_matching_node is where 786 * detach C from internal linked list and add it into 787 * intel_engine_coredump struct (if the context and 788 * engine of the event notification matches a node 789 * in the link list). 790 * 791 * User Sysfs / Debugfs 792 * -------------------- 793 * --> i915_gpu_coredump_copy_to_buffer-> 794 * L--> err_print_to_sgl --> err_print_gt 795 * L--> error_print_guc_captures 796 * L--> intel_guc_capture_print_node prints the 797 * register lists values of the attached node 798 * on the error-engine-dump being reported. 799 * L--> i915_reset_error_state ... -->__i915_gpu_coredump_free 800 * L--> ... cleanup_gt --> 801 * L--> intel_guc_capture_free_node returns the 802 * capture-output-node back to the internal 803 * cachelist for reuse. 804 * 805 */ 806 807 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) 808 { 809 if (buf->wr >= buf->rd) 810 return (buf->wr - buf->rd); 811 return (buf->size - buf->rd) + buf->wr; 812 } 813 814 static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) 815 { 816 if (buf->rd > buf->wr) 817 return (buf->size - buf->rd); 818 return (buf->wr - buf->rd); 819 } 820 821 /* 822 * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: 823 * 824 * The GuC Log buffer region for error-capture is managed like a ring buffer. 825 * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. 826 * Additionally, as per the current and foreseeable future, all packed error- 827 * capture output structures are dword aligned. 828 * 829 * That said, if the GuC firmware is in the midst of writing a structure that is larger 830 * than one dword but the tail end of the err-capture buffer-region has lesser space left, 831 * we would need to extract that structure one dword at a time straddled across the end, 832 * onto the start of the ring. 833 * 834 * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this 835 * function would typically do a straight-up memcpy from the ring contents and will only 836 * call this helper if their structure-extraction is straddling across the end of the 837 * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease 838 * scalability for future expansion of output data types without requiring a redesign 839 * of the flow controls. 840 */ 841 static int 842 guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 843 u32 *dw) 844 { 845 int tries = 2; 846 int avail = 0; 847 u32 *src_data; 848 849 if (!guc_capture_buf_cnt(buf)) 850 return 0; 851 852 while (tries--) { 853 avail = guc_capture_buf_cnt_to_end(buf); 854 if (avail >= sizeof(u32)) { 855 src_data = (u32 *)(buf->data + buf->rd); 856 *dw = *src_data; 857 buf->rd += 4; 858 return 4; 859 } 860 if (avail) 861 guc_dbg(guc, "Register capture log not dword aligned, skipping.\n"); 862 buf->rd = 0; 863 } 864 865 return 0; 866 } 867 868 static bool 869 guc_capture_data_extracted(struct __guc_capture_bufstate *b, 870 int size, void *dest) 871 { 872 if (guc_capture_buf_cnt_to_end(b) >= size) { 873 memcpy(dest, (b->data + b->rd), size); 874 b->rd += size; 875 return true; 876 } 877 return false; 878 } 879 880 static int 881 guc_capture_log_get_group_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 882 struct guc_state_capture_group_header_t *ghdr) 883 { 884 int read = 0; 885 int fullsize = sizeof(struct guc_state_capture_group_header_t); 886 887 if (fullsize > guc_capture_buf_cnt(buf)) 888 return -1; 889 890 if (guc_capture_data_extracted(buf, fullsize, (void *)ghdr)) 891 return 0; 892 893 read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); 894 read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); 895 if (read != fullsize) 896 return -1; 897 898 return 0; 899 } 900 901 static int 902 guc_capture_log_get_data_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 903 struct guc_state_capture_header_t *hdr) 904 { 905 int read = 0; 906 int fullsize = sizeof(struct guc_state_capture_header_t); 907 908 if (fullsize > guc_capture_buf_cnt(buf)) 909 return -1; 910 911 if (guc_capture_data_extracted(buf, fullsize, (void *)hdr)) 912 return 0; 913 914 read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); 915 read += guc_capture_log_remove_dw(guc, buf, &hdr->info); 916 read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); 917 read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); 918 read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); 919 if (read != fullsize) 920 return -1; 921 922 return 0; 923 } 924 925 static int 926 guc_capture_log_get_register(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 927 struct guc_mmio_reg *reg) 928 { 929 int read = 0; 930 int fullsize = sizeof(struct guc_mmio_reg); 931 932 if (fullsize > guc_capture_buf_cnt(buf)) 933 return -1; 934 935 if (guc_capture_data_extracted(buf, fullsize, (void *)reg)) 936 return 0; 937 938 read += guc_capture_log_remove_dw(guc, buf, ®->offset); 939 read += guc_capture_log_remove_dw(guc, buf, ®->value); 940 read += guc_capture_log_remove_dw(guc, buf, ®->flags); 941 read += guc_capture_log_remove_dw(guc, buf, ®->mask); 942 if (read != fullsize) 943 return -1; 944 945 return 0; 946 } 947 948 static void 949 guc_capture_delete_one_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 950 { 951 int i; 952 953 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 954 kfree(node->reginfo[i].regs); 955 list_del(&node->link); 956 kfree(node); 957 } 958 959 static void 960 guc_capture_delete_prealloc_nodes(struct intel_guc *guc) 961 { 962 struct __guc_capture_parsed_output *n, *ntmp; 963 964 /* 965 * NOTE: At the end of driver operation, we must assume that we 966 * have prealloc nodes in both the cachelist as well as outlist 967 * if unclaimed error capture events occurred prior to shutdown. 968 */ 969 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) 970 guc_capture_delete_one_node(guc, n); 971 972 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) 973 guc_capture_delete_one_node(guc, n); 974 } 975 976 static void 977 guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, 978 struct list_head *list) 979 { 980 list_add_tail(&node->link, list); 981 } 982 983 static void 984 guc_capture_add_node_to_outlist(struct intel_guc_state_capture *gc, 985 struct __guc_capture_parsed_output *node) 986 { 987 guc_capture_add_node_to_list(node, &gc->outlist); 988 } 989 990 static void 991 guc_capture_add_node_to_cachelist(struct intel_guc_state_capture *gc, 992 struct __guc_capture_parsed_output *node) 993 { 994 guc_capture_add_node_to_list(node, &gc->cachelist); 995 } 996 997 static void 998 guc_capture_init_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 999 { 1000 struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; 1001 int i; 1002 1003 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1004 tmp[i] = node->reginfo[i].regs; 1005 memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * 1006 guc->capture->max_mmio_per_node); 1007 } 1008 memset(node, 0, sizeof(*node)); 1009 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 1010 node->reginfo[i].regs = tmp[i]; 1011 1012 INIT_LIST_HEAD(&node->link); 1013 } 1014 1015 static struct __guc_capture_parsed_output * 1016 guc_capture_get_prealloc_node(struct intel_guc *guc) 1017 { 1018 struct __guc_capture_parsed_output *found = NULL; 1019 1020 if (!list_empty(&guc->capture->cachelist)) { 1021 struct __guc_capture_parsed_output *n, *ntmp; 1022 1023 /* get first avail node from the cache list */ 1024 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { 1025 found = n; 1026 list_del(&n->link); 1027 break; 1028 } 1029 } else { 1030 struct __guc_capture_parsed_output *n, *ntmp; 1031 1032 /* traverse down and steal back the oldest node already allocated */ 1033 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1034 found = n; 1035 } 1036 if (found) 1037 list_del(&found->link); 1038 } 1039 if (found) 1040 guc_capture_init_node(guc, found); 1041 1042 return found; 1043 } 1044 1045 static struct __guc_capture_parsed_output * 1046 guc_capture_alloc_one_node(struct intel_guc *guc) 1047 { 1048 struct __guc_capture_parsed_output *new; 1049 int i; 1050 1051 new = kzalloc(sizeof(*new), GFP_KERNEL); 1052 if (!new) 1053 return NULL; 1054 1055 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1056 new->reginfo[i].regs = kcalloc(guc->capture->max_mmio_per_node, 1057 sizeof(struct guc_mmio_reg), GFP_KERNEL); 1058 if (!new->reginfo[i].regs) { 1059 while (i) 1060 kfree(new->reginfo[--i].regs); 1061 kfree(new); 1062 return NULL; 1063 } 1064 } 1065 guc_capture_init_node(guc, new); 1066 1067 return new; 1068 } 1069 1070 static struct __guc_capture_parsed_output * 1071 guc_capture_clone_node(struct intel_guc *guc, struct __guc_capture_parsed_output *original, 1072 u32 keep_reglist_mask) 1073 { 1074 struct __guc_capture_parsed_output *new; 1075 int i; 1076 1077 new = guc_capture_get_prealloc_node(guc); 1078 if (!new) 1079 return NULL; 1080 if (!original) 1081 return new; 1082 1083 new->is_partial = original->is_partial; 1084 1085 /* copy reg-lists that we want to clone */ 1086 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1087 if (keep_reglist_mask & BIT(i)) { 1088 GEM_BUG_ON(original->reginfo[i].num_regs > 1089 guc->capture->max_mmio_per_node); 1090 1091 memcpy(new->reginfo[i].regs, original->reginfo[i].regs, 1092 original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); 1093 1094 new->reginfo[i].num_regs = original->reginfo[i].num_regs; 1095 new->reginfo[i].vfid = original->reginfo[i].vfid; 1096 1097 if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { 1098 new->eng_class = original->eng_class; 1099 } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1100 new->eng_inst = original->eng_inst; 1101 new->guc_id = original->guc_id; 1102 new->lrca = original->lrca; 1103 } 1104 } 1105 } 1106 1107 return new; 1108 } 1109 1110 static void 1111 __guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1112 { 1113 struct __guc_capture_parsed_output *node = NULL; 1114 int i; 1115 1116 for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { 1117 node = guc_capture_alloc_one_node(guc); 1118 if (!node) { 1119 guc_warn(guc, "Register capture pre-alloc-cache failure\n"); 1120 /* dont free the priors, use what we got and cleanup at shutdown */ 1121 return; 1122 } 1123 guc_capture_add_node_to_cachelist(guc->capture, node); 1124 } 1125 } 1126 1127 static int 1128 guc_get_max_reglist_count(struct intel_guc *guc) 1129 { 1130 int i, j, k, tmp, maxregcount = 0; 1131 1132 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1133 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1134 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1135 if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) 1136 continue; 1137 1138 tmp = guc_cap_list_num_regs(guc->capture, i, j, k); 1139 if (tmp > maxregcount) 1140 maxregcount = tmp; 1141 } 1142 } 1143 } 1144 if (!maxregcount) 1145 maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; 1146 1147 return maxregcount; 1148 } 1149 1150 static void 1151 guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1152 { 1153 /* skip if we've already done the pre-alloc */ 1154 if (guc->capture->max_mmio_per_node) 1155 return; 1156 1157 guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); 1158 __guc_capture_create_prealloc_nodes(guc); 1159 } 1160 1161 static int 1162 guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf) 1163 { 1164 struct guc_state_capture_group_header_t ghdr = {0}; 1165 struct guc_state_capture_header_t hdr = {0}; 1166 struct __guc_capture_parsed_output *node = NULL; 1167 struct guc_mmio_reg *regs = NULL; 1168 int i, numlists, numregs, ret = 0; 1169 enum guc_capture_type datatype; 1170 struct guc_mmio_reg tmp; 1171 bool is_partial = false; 1172 1173 i = guc_capture_buf_cnt(buf); 1174 if (!i) 1175 return -ENODATA; 1176 if (i % sizeof(u32)) { 1177 guc_warn(guc, "Got mis-aligned register capture entries\n"); 1178 ret = -EIO; 1179 goto bailout; 1180 } 1181 1182 /* first get the capture group header */ 1183 if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { 1184 ret = -EIO; 1185 goto bailout; 1186 } 1187 /* 1188 * we would typically expect a layout as below where n would be expected to be 1189 * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine 1190 * instances being reset together. 1191 * ____________________________________________ 1192 * | Capture Group | 1193 * | ________________________________________ | 1194 * | | Capture Group Header: | | 1195 * | | - num_captures = 5 | | 1196 * | |______________________________________| | 1197 * | ________________________________________ | 1198 * | | Capture1: | | 1199 * | | Hdr: GLOBAL, numregs=a | | 1200 * | | ____________________________________ | | 1201 * | | | Reglist | | | 1202 * | | | - reg1, reg2, ... rega | | | 1203 * | | |__________________________________| | | 1204 * | |______________________________________| | 1205 * | ________________________________________ | 1206 * | | Capture2: | | 1207 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | 1208 * | | ____________________________________ | | 1209 * | | | Reglist | | | 1210 * | | | - reg1, reg2, ... regb | | | 1211 * | | |__________________________________| | | 1212 * | |______________________________________| | 1213 * | ________________________________________ | 1214 * | | Capture3: | | 1215 * | | Hdr: INSTANCE=RCS, numregs=c | | 1216 * | | ____________________________________ | | 1217 * | | | Reglist | | | 1218 * | | | - reg1, reg2, ... regc | | | 1219 * | | |__________________________________| | | 1220 * | |______________________________________| | 1221 * | ________________________________________ | 1222 * | | Capture4: | | 1223 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | 1224 * | | ____________________________________ | | 1225 * | | | Reglist | | | 1226 * | | | - reg1, reg2, ... regd | | | 1227 * | | |__________________________________| | | 1228 * | |______________________________________| | 1229 * | ________________________________________ | 1230 * | | Capture5: | | 1231 * | | Hdr: INSTANCE=CCS0, numregs=e | | 1232 * | | ____________________________________ | | 1233 * | | | Reglist | | | 1234 * | | | - reg1, reg2, ... rege | | | 1235 * | | |__________________________________| | | 1236 * | |______________________________________| | 1237 * |__________________________________________| 1238 */ 1239 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); 1240 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); 1241 1242 while (numlists--) { 1243 if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { 1244 ret = -EIO; 1245 break; 1246 } 1247 1248 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); 1249 if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1250 /* unknown capture type - skip over to next capture set */ 1251 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1252 while (numregs--) { 1253 if (guc_capture_log_get_register(guc, buf, &tmp)) { 1254 ret = -EIO; 1255 break; 1256 } 1257 } 1258 continue; 1259 } else if (node) { 1260 /* 1261 * Based on the current capture type and what we have so far, 1262 * decide if we should add the current node into the internal 1263 * linked list for match-up when i915_gpu_coredump calls later 1264 * (and alloc a blank node for the next set of reglists) 1265 * or continue with the same node or clone the current node 1266 * but only retain the global or class registers (such as the 1267 * case of dependent engine resets). 1268 */ 1269 if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { 1270 guc_capture_add_node_to_outlist(guc->capture, node); 1271 node = NULL; 1272 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && 1273 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { 1274 /* Add to list, clone node and duplicate global list */ 1275 guc_capture_add_node_to_outlist(guc->capture, node); 1276 node = guc_capture_clone_node(guc, node, 1277 GCAP_PARSED_REGLIST_INDEX_GLOBAL); 1278 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && 1279 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { 1280 /* Add to list, clone node and duplicate global + class lists */ 1281 guc_capture_add_node_to_outlist(guc->capture, node); 1282 node = guc_capture_clone_node(guc, node, 1283 (GCAP_PARSED_REGLIST_INDEX_GLOBAL | 1284 GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); 1285 } 1286 } 1287 1288 if (!node) { 1289 node = guc_capture_get_prealloc_node(guc); 1290 if (!node) { 1291 ret = -ENOMEM; 1292 break; 1293 } 1294 if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) 1295 guc_dbg(guc, "Register capture missing global dump: %08x!\n", 1296 datatype); 1297 } 1298 node->is_partial = is_partial; 1299 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); 1300 switch (datatype) { 1301 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1302 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1303 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); 1304 node->lrca = hdr.lrca; 1305 node->guc_id = hdr.guc_id; 1306 break; 1307 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1308 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1309 break; 1310 default: 1311 break; 1312 } 1313 1314 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1315 if (numregs > guc->capture->max_mmio_per_node) { 1316 guc_dbg(guc, "Register capture list extraction clipped by prealloc!\n"); 1317 numregs = guc->capture->max_mmio_per_node; 1318 } 1319 node->reginfo[datatype].num_regs = numregs; 1320 regs = node->reginfo[datatype].regs; 1321 i = 0; 1322 while (numregs--) { 1323 if (guc_capture_log_get_register(guc, buf, ®s[i++])) { 1324 ret = -EIO; 1325 break; 1326 } 1327 } 1328 } 1329 1330 bailout: 1331 if (node) { 1332 /* If we have data, add to linked list for match-up when i915_gpu_coredump calls */ 1333 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1334 if (node->reginfo[i].regs) { 1335 guc_capture_add_node_to_outlist(guc->capture, node); 1336 node = NULL; 1337 break; 1338 } 1339 } 1340 if (node) /* else return it back to cache list */ 1341 guc_capture_add_node_to_cachelist(guc->capture, node); 1342 } 1343 return ret; 1344 } 1345 1346 static int __guc_capture_flushlog_complete(struct intel_guc *guc) 1347 { 1348 u32 action[] = { 1349 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, 1350 GUC_CAPTURE_LOG_BUFFER 1351 }; 1352 1353 return intel_guc_send_nb(guc, action, ARRAY_SIZE(action), 0); 1354 1355 } 1356 1357 static void __guc_capture_process_output(struct intel_guc *guc) 1358 { 1359 unsigned int buffer_size, read_offset, write_offset, full_count; 1360 struct intel_uc *uc = container_of(guc, typeof(*uc), guc); 1361 struct guc_log_buffer_state log_buf_state_local; 1362 struct guc_log_buffer_state *log_buf_state; 1363 struct __guc_capture_bufstate buf; 1364 void *src_data = NULL; 1365 bool new_overflow; 1366 int ret; 1367 1368 log_buf_state = guc->log.buf_addr + 1369 (sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER); 1370 src_data = guc->log.buf_addr + 1371 intel_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1372 1373 /* 1374 * Make a copy of the state structure, inside GuC log buffer 1375 * (which is uncached mapped), on the stack to avoid reading 1376 * from it multiple times. 1377 */ 1378 memcpy(&log_buf_state_local, log_buf_state, sizeof(struct guc_log_buffer_state)); 1379 buffer_size = intel_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1380 read_offset = log_buf_state_local.read_ptr; 1381 write_offset = log_buf_state_local.sampled_write_ptr; 1382 full_count = log_buf_state_local.buffer_full_cnt; 1383 1384 /* Bookkeeping stuff */ 1385 guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; 1386 new_overflow = intel_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, 1387 full_count); 1388 1389 /* Now copy the actual logs. */ 1390 if (unlikely(new_overflow)) { 1391 /* copy the whole buffer in case of overflow */ 1392 read_offset = 0; 1393 write_offset = buffer_size; 1394 } else if (unlikely((read_offset > buffer_size) || 1395 (write_offset > buffer_size))) { 1396 guc_err(guc, "Register capture buffer in invalid state: read = 0x%X, size = 0x%X!\n", 1397 read_offset, buffer_size); 1398 /* copy whole buffer as offsets are unreliable */ 1399 read_offset = 0; 1400 write_offset = buffer_size; 1401 } 1402 1403 buf.size = buffer_size; 1404 buf.rd = read_offset; 1405 buf.wr = write_offset; 1406 buf.data = src_data; 1407 1408 if (!uc->reset_in_progress) { 1409 do { 1410 ret = guc_capture_extract_reglists(guc, &buf); 1411 } while (ret >= 0); 1412 } 1413 1414 /* Update the state of log buffer err-cap state */ 1415 log_buf_state->read_ptr = write_offset; 1416 log_buf_state->flush_to_file = 0; 1417 __guc_capture_flushlog_complete(guc); 1418 } 1419 1420 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1421 1422 static const char * 1423 guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type, 1424 u32 class, u32 id, u32 offset, u32 *is_ext) 1425 { 1426 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 1427 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 1428 const struct __guc_mmio_reg_descr_group *match; 1429 struct __guc_mmio_reg_descr_group *matchext; 1430 int j; 1431 1432 *is_ext = 0; 1433 if (!reglists) 1434 return NULL; 1435 1436 match = guc_capture_get_one_list(reglists, owner, type, id); 1437 if (!match) 1438 return NULL; 1439 1440 for (j = 0; j < match->num_regs; ++j) { 1441 if (offset == match->list[j].reg.reg) 1442 return match->list[j].regname; 1443 } 1444 if (extlists) { 1445 matchext = guc_capture_get_one_ext_list(extlists, owner, type, id); 1446 if (!matchext) 1447 return NULL; 1448 for (j = 0; j < matchext->num_regs; ++j) { 1449 if (offset == matchext->extlist[j].reg.reg) { 1450 *is_ext = 1; 1451 return matchext->extlist[j].regname; 1452 } 1453 } 1454 } 1455 1456 return NULL; 1457 } 1458 1459 #define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng) \ 1460 do { \ 1461 i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n", \ 1462 (eng)->name); \ 1463 i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n", (eng)->class); \ 1464 i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance); \ 1465 i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n", \ 1466 (eng)->logical_mask); \ 1467 } while (0) 1468 1469 #define GCAP_PRINT_GUC_INST_INFO(ebuf, node) \ 1470 do { \ 1471 i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n", \ 1472 (node)->eng_inst); \ 1473 i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n", (node)->guc_id); \ 1474 i915_error_printf(ebuf, " LRCA: 0x%08x\n", (node)->lrca); \ 1475 } while (0) 1476 1477 int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf, 1478 const struct intel_engine_coredump *ee) 1479 { 1480 const char *grptype[GUC_STATE_CAPTURE_GROUP_TYPE_MAX] = { 1481 "full-capture", 1482 "partial-capture" 1483 }; 1484 const char *datatype[GUC_CAPTURE_LIST_TYPE_MAX] = { 1485 "Global", 1486 "Engine-Class", 1487 "Engine-Instance" 1488 }; 1489 struct intel_guc_state_capture *cap; 1490 struct __guc_capture_parsed_output *node; 1491 struct intel_engine_cs *eng; 1492 struct guc_mmio_reg *regs; 1493 struct intel_guc *guc; 1494 const char *str; 1495 int numregs, i, j; 1496 u32 is_ext; 1497 1498 if (!ebuf || !ee) 1499 return -EINVAL; 1500 cap = ee->guc_capture; 1501 if (!cap || !ee->engine) 1502 return -ENODEV; 1503 1504 guc = &ee->engine->gt->uc.guc; 1505 1506 i915_error_printf(ebuf, "global --- GuC Error Capture on %s command stream:\n", 1507 ee->engine->name); 1508 1509 node = ee->guc_capture_node; 1510 if (!node) { 1511 i915_error_printf(ebuf, " No matching ee-node\n"); 1512 return 0; 1513 } 1514 1515 i915_error_printf(ebuf, "Coverage: %s\n", grptype[node->is_partial]); 1516 1517 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1518 i915_error_printf(ebuf, " RegListType: %s\n", 1519 datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]); 1520 i915_error_printf(ebuf, " Owner-Id: %d\n", node->reginfo[i].vfid); 1521 1522 switch (i) { 1523 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 1524 default: 1525 break; 1526 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1527 i915_error_printf(ebuf, " GuC-Eng-Class: %d\n", node->eng_class); 1528 i915_error_printf(ebuf, " i915-Eng-Class: %d\n", 1529 guc_class_to_engine_class(node->eng_class)); 1530 break; 1531 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1532 eng = intel_guc_lookup_engine(guc, node->eng_class, node->eng_inst); 1533 if (eng) 1534 GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng); 1535 else 1536 i915_error_printf(ebuf, " i915-Eng-Lookup Fail!\n"); 1537 GCAP_PRINT_GUC_INST_INFO(ebuf, node); 1538 break; 1539 } 1540 1541 numregs = node->reginfo[i].num_regs; 1542 i915_error_printf(ebuf, " NumRegs: %d\n", numregs); 1543 j = 0; 1544 while (numregs--) { 1545 regs = node->reginfo[i].regs; 1546 str = guc_capture_reg_to_str(guc, GUC_CAPTURE_LIST_INDEX_PF, i, 1547 node->eng_class, 0, regs[j].offset, &is_ext); 1548 if (!str) 1549 i915_error_printf(ebuf, " REG-0x%08x", regs[j].offset); 1550 else 1551 i915_error_printf(ebuf, " %s", str); 1552 if (is_ext) 1553 i915_error_printf(ebuf, "[%ld][%ld]", 1554 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), 1555 FIELD_GET(GUC_REGSET_STEERING_INSTANCE, regs[j].flags)); 1556 i915_error_printf(ebuf, ": 0x%08x\n", regs[j].value); 1557 ++j; 1558 } 1559 } 1560 return 0; 1561 } 1562 1563 #endif //CONFIG_DRM_I915_CAPTURE_ERROR 1564 1565 static void guc_capture_find_ecode(struct intel_engine_coredump *ee) 1566 { 1567 struct gcap_reg_list_info *reginfo; 1568 struct guc_mmio_reg *regs; 1569 i915_reg_t reg_ipehr = RING_IPEHR(0); 1570 i915_reg_t reg_instdone = RING_INSTDONE(0); 1571 int i; 1572 1573 if (!ee->guc_capture_node) 1574 return; 1575 1576 reginfo = ee->guc_capture_node->reginfo + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE; 1577 regs = reginfo->regs; 1578 for (i = 0; i < reginfo->num_regs; i++) { 1579 if (regs[i].offset == reg_ipehr.reg) 1580 ee->ipehr = regs[i].value; 1581 else if (regs[i].offset == reg_instdone.reg) 1582 ee->instdone.instdone = regs[i].value; 1583 } 1584 } 1585 1586 void intel_guc_capture_free_node(struct intel_engine_coredump *ee) 1587 { 1588 if (!ee || !ee->guc_capture_node) 1589 return; 1590 1591 guc_capture_add_node_to_cachelist(ee->guc_capture, ee->guc_capture_node); 1592 ee->guc_capture = NULL; 1593 ee->guc_capture_node = NULL; 1594 } 1595 1596 void intel_guc_capture_get_matching_node(struct intel_gt *gt, 1597 struct intel_engine_coredump *ee, 1598 struct intel_context *ce) 1599 { 1600 struct __guc_capture_parsed_output *n, *ntmp; 1601 struct intel_guc *guc; 1602 1603 if (!gt || !ee || !ce) 1604 return; 1605 1606 guc = >->uc.guc; 1607 if (!guc->capture) 1608 return; 1609 1610 GEM_BUG_ON(ee->guc_capture_node); 1611 /* 1612 * Look for a matching GuC reported error capture node from 1613 * the internal output link-list based on lrca, guc-id and engine 1614 * identification. 1615 */ 1616 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1617 if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) && 1618 n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) && 1619 n->guc_id == ce->guc_id.id && 1620 (n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) { 1621 list_del(&n->link); 1622 ee->guc_capture_node = n; 1623 ee->guc_capture = guc->capture; 1624 guc_capture_find_ecode(ee); 1625 return; 1626 } 1627 } 1628 1629 guc_warn(guc, "No register capture node found for 0x%04X / 0x%08X\n", 1630 ce->guc_id.id, ce->lrc.lrca); 1631 } 1632 1633 void intel_guc_capture_process(struct intel_guc *guc) 1634 { 1635 if (guc->capture) 1636 __guc_capture_process_output(guc); 1637 } 1638 1639 static void 1640 guc_capture_free_ads_cache(struct intel_guc_state_capture *gc) 1641 { 1642 int i, j, k; 1643 struct __guc_capture_ads_cache *cache; 1644 1645 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1646 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1647 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1648 cache = &gc->ads_cache[i][j][k]; 1649 if (cache->is_valid) 1650 kfree(cache->ptr); 1651 } 1652 } 1653 } 1654 kfree(gc->ads_null_cache); 1655 } 1656 1657 void intel_guc_capture_destroy(struct intel_guc *guc) 1658 { 1659 if (!guc->capture) 1660 return; 1661 1662 guc_capture_free_ads_cache(guc->capture); 1663 1664 guc_capture_delete_prealloc_nodes(guc); 1665 1666 guc_capture_free_extlists(guc->capture->extlists); 1667 kfree(guc->capture->extlists); 1668 1669 kfree(guc->capture); 1670 guc->capture = NULL; 1671 } 1672 1673 int intel_guc_capture_init(struct intel_guc *guc) 1674 { 1675 guc->capture = kzalloc(sizeof(*guc->capture), GFP_KERNEL); 1676 if (!guc->capture) 1677 return -ENOMEM; 1678 1679 guc->capture->reglists = guc_capture_get_device_reglist(guc); 1680 1681 INIT_LIST_HEAD(&guc->capture->outlist); 1682 INIT_LIST_HEAD(&guc->capture->cachelist); 1683 1684 check_guc_capture_size(guc); 1685 1686 return 0; 1687 } 1688