1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2022 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include <drm/drm_print.h> 9 10 #include "gt/intel_engine_regs.h" 11 #include "gt/intel_gt.h" 12 #include "gt/intel_gt_mcr.h" 13 #include "gt/intel_gt_regs.h" 14 #include "gt/intel_lrc.h" 15 #include "guc_capture_fwif.h" 16 #include "intel_guc_capture.h" 17 #include "intel_guc_fwif.h" 18 #include "intel_guc_print.h" 19 #include "i915_drv.h" 20 #include "i915_gpu_error.h" 21 #include "i915_irq.h" 22 #include "i915_memcpy.h" 23 #include "i915_reg.h" 24 25 /* 26 * Define all device tables of GuC error capture register lists 27 * NOTE: For engine-registers, GuC only needs the register offsets 28 * from the engine-mmio-base 29 */ 30 #define COMMON_BASE_GLOBAL \ 31 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } 32 33 #define COMMON_GEN9BASE_GLOBAL \ 34 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ 35 { DONE_REG, 0, 0, "DONE_REG" }, \ 36 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } 37 38 #define GEN9_GLOBAL \ 39 { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 40 { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" } 41 42 #define COMMON_GEN12BASE_GLOBAL \ 43 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ 44 { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ 45 { GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG" }, \ 46 { GEN12_GAM_DONE, 0, 0, "GAM_DONE" }, \ 47 { GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG" } 48 49 #define COMMON_BASE_ENGINE_INSTANCE \ 50 { RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \ 51 { RING_ESR(0), 0, 0, "ESR" }, \ 52 { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW" }, \ 53 { RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW" }, \ 54 { RING_IPEIR(0), 0, 0, "IPEIR" }, \ 55 { RING_IPEHR(0), 0, 0, "IPEHR" }, \ 56 { RING_INSTPS(0), 0, 0, "INSTPS" }, \ 57 { RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32" }, \ 58 { RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32" }, \ 59 { RING_BBSTATE(0), 0, 0, "BB_STATE" }, \ 60 { CCID(0), 0, 0, "CCID" }, \ 61 { RING_ACTHD(0), 0, 0, "ACTHD_LDW" }, \ 62 { RING_ACTHD_UDW(0), 0, 0, "ACTHD_UDW" }, \ 63 { RING_INSTPM(0), 0, 0, "INSTPM" }, \ 64 { RING_INSTDONE(0), 0, 0, "INSTDONE" }, \ 65 { RING_NOPID(0), 0, 0, "RING_NOPID" }, \ 66 { RING_START(0), 0, 0, "START" }, \ 67 { RING_HEAD(0), 0, 0, "HEAD" }, \ 68 { RING_TAIL(0), 0, 0, "TAIL" }, \ 69 { RING_CTL(0), 0, 0, "CTL" }, \ 70 { RING_MI_MODE(0), 0, 0, "MODE" }, \ 71 { RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL" }, \ 72 { RING_HWS_PGA(0), 0, 0, "HWS" }, \ 73 { RING_MODE_GEN7(0), 0, 0, "GFX_MODE" }, \ 74 { GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW" }, \ 75 { GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW" }, \ 76 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \ 77 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \ 78 { GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW" }, \ 79 { GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW" }, \ 80 { GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW" }, \ 81 { GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW" } 82 83 #define COMMON_BASE_HAS_EU \ 84 { EIR, 0, 0, "EIR" } 85 86 #define COMMON_BASE_RENDER \ 87 { GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE" } 88 89 #define COMMON_GEN12BASE_RENDER \ 90 { GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA" }, \ 91 { GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2" } 92 93 #define COMMON_GEN12BASE_VEC \ 94 { GEN12_SFC_DONE(0), 0, 0, "SFC_DONE[0]" }, \ 95 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \ 96 { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \ 97 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" } 98 99 /* XE_LPD - Global */ 100 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = { 101 COMMON_BASE_GLOBAL, 102 COMMON_GEN9BASE_GLOBAL, 103 COMMON_GEN12BASE_GLOBAL, 104 }; 105 106 /* XE_LPD - Render / Compute Per-Class */ 107 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = { 108 COMMON_BASE_HAS_EU, 109 COMMON_BASE_RENDER, 110 COMMON_GEN12BASE_RENDER, 111 }; 112 113 /* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */ 114 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = { 115 COMMON_BASE_ENGINE_INSTANCE, 116 }; 117 118 /* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */ 119 static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = { 120 COMMON_BASE_ENGINE_INSTANCE, 121 }; 122 123 /* XE_LPD - Video Enhancement Per-Class */ 124 static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = { 125 COMMON_GEN12BASE_VEC, 126 }; 127 128 /* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */ 129 static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = { 130 COMMON_BASE_ENGINE_INSTANCE, 131 }; 132 133 /* GEN9/XE_LPD - Blitter Per-Engine-Instance */ 134 static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = { 135 COMMON_BASE_ENGINE_INSTANCE, 136 }; 137 138 /* XE_LPD - GSC Per-Engine-Instance */ 139 static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = { 140 COMMON_BASE_ENGINE_INSTANCE, 141 }; 142 143 /* GEN9 - Global */ 144 static const struct __guc_mmio_reg_descr default_global_regs[] = { 145 COMMON_BASE_GLOBAL, 146 COMMON_GEN9BASE_GLOBAL, 147 GEN9_GLOBAL, 148 }; 149 150 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { 151 COMMON_BASE_HAS_EU, 152 COMMON_BASE_RENDER, 153 }; 154 155 /* 156 * Empty lists: 157 * GEN9/XE_LPD - Blitter Per-Class 158 * GEN9/XE_LPD - Media Decode/Encode Per-Class 159 * GEN9 - VEC Class 160 */ 161 static const struct __guc_mmio_reg_descr empty_regs_list[] = { 162 }; 163 164 #define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) 165 #define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) 166 #define MAKE_REGLIST(regslist, regsowner, regstype, class) \ 167 { \ 168 regslist, \ 169 ARRAY_SIZE(regslist), \ 170 TO_GCAP_DEF_OWNER(regsowner), \ 171 TO_GCAP_DEF_TYPE(regstype), \ 172 class, \ 173 NULL, \ 174 } 175 176 /* List of lists */ 177 static const struct __guc_mmio_reg_descr_group default_lists[] = { 178 MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0), 179 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 180 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 181 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), 182 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), 183 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 184 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 185 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 186 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 187 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 188 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 189 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), 190 MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), 191 {} 192 }; 193 194 static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = { 195 MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0), 196 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 197 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 198 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS), 199 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS), 200 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 201 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 202 MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 203 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 204 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 205 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 206 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS), 207 MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS), 208 {} 209 }; 210 211 static const struct __guc_mmio_reg_descr_group * 212 guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, 213 u32 owner, u32 type, u32 id) 214 { 215 int i; 216 217 if (!reglists) 218 return NULL; 219 220 for (i = 0; reglists[i].list; ++i) { 221 if (reglists[i].owner == owner && reglists[i].type == type && 222 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 223 return ®lists[i]; 224 } 225 226 return NULL; 227 } 228 229 static struct __guc_mmio_reg_descr_group * 230 guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, 231 u32 owner, u32 type, u32 id) 232 { 233 int i; 234 235 if (!reglists) 236 return NULL; 237 238 for (i = 0; reglists[i].extlist; ++i) { 239 if (reglists[i].owner == owner && reglists[i].type == type && 240 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 241 return ®lists[i]; 242 } 243 244 return NULL; 245 } 246 247 static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglists) 248 { 249 int i = 0; 250 251 if (!reglists) 252 return; 253 254 while (reglists[i].extlist) 255 kfree(reglists[i++].extlist); 256 } 257 258 struct __ext_steer_reg { 259 const char *name; 260 i915_mcr_reg_t reg; 261 }; 262 263 static const struct __ext_steer_reg xe_extregs[] = { 264 {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE}, 265 {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE} 266 }; 267 268 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, 269 const struct __ext_steer_reg *extlist, 270 int slice_id, int subslice_id) 271 { 272 ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg)); 273 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 274 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); 275 ext->regname = extlist->name; 276 } 277 278 static int 279 __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, 280 const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) 281 { 282 struct __guc_mmio_reg_descr *list; 283 284 list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); 285 if (!list) 286 return -ENOMEM; 287 288 newlist->extlist = list; 289 newlist->num_regs = num_regs; 290 newlist->owner = rootlist->owner; 291 newlist->engine = rootlist->engine; 292 newlist->type = rootlist->type; 293 294 return 0; 295 } 296 297 static void 298 guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, 299 const struct __guc_mmio_reg_descr_group *lists) 300 { 301 struct intel_gt *gt = guc_to_gt(guc); 302 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; 303 const struct __guc_mmio_reg_descr_group *list; 304 struct __guc_mmio_reg_descr_group *extlists; 305 struct __guc_mmio_reg_descr *extarray; 306 struct sseu_dev_info *sseu; 307 308 /* In XE_LPD we only have steered registers for the render-class */ 309 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 310 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 311 /* skip if extlists was previously allocated */ 312 if (!list || guc->capture->extlists) 313 return; 314 315 num_steer_regs = ARRAY_SIZE(xe_extregs); 316 317 sseu = >->info.sseu; 318 for_each_ss_steering(iter, gt, slice, subslice) 319 num_tot_regs += num_steer_regs; 320 321 if (!num_tot_regs) 322 return; 323 324 /* allocate an extra for an end marker */ 325 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 326 if (!extlists) 327 return; 328 329 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 330 kfree(extlists); 331 return; 332 } 333 334 extarray = extlists[0].extlist; 335 for_each_ss_steering(iter, gt, slice, subslice) { 336 for (i = 0; i < num_steer_regs; ++i) { 337 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 338 ++extarray; 339 } 340 } 341 342 guc->capture->extlists = extlists; 343 } 344 345 static const struct __ext_steer_reg xehpg_extregs[] = { 346 {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} 347 }; 348 349 static bool __has_xehpg_extregs(u32 ipver) 350 { 351 return (ipver >= IP_VER(12, 55)); 352 } 353 354 static void 355 guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, 356 const struct __guc_mmio_reg_descr_group *lists, 357 u32 ipver) 358 { 359 struct intel_gt *gt = guc_to_gt(guc); 360 struct sseu_dev_info *sseu; 361 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; 362 const struct __guc_mmio_reg_descr_group *list; 363 struct __guc_mmio_reg_descr_group *extlists; 364 struct __guc_mmio_reg_descr *extarray; 365 366 /* In XE_LP / HPG we only have render-class steering registers during error-capture */ 367 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 368 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 369 /* skip if extlists was previously allocated */ 370 if (!list || guc->capture->extlists) 371 return; 372 373 num_steer_regs = ARRAY_SIZE(xe_extregs); 374 if (__has_xehpg_extregs(ipver)) 375 num_steer_regs += ARRAY_SIZE(xehpg_extregs); 376 377 sseu = >->info.sseu; 378 for_each_ss_steering(iter, gt, slice, subslice) 379 num_tot_regs += num_steer_regs; 380 381 if (!num_tot_regs) 382 return; 383 384 /* allocate an extra for an end marker */ 385 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 386 if (!extlists) 387 return; 388 389 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 390 kfree(extlists); 391 return; 392 } 393 394 extarray = extlists[0].extlist; 395 for_each_ss_steering(iter, gt, slice, subslice) { 396 for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { 397 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 398 ++extarray; 399 } 400 if (__has_xehpg_extregs(ipver)) { 401 for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { 402 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); 403 ++extarray; 404 } 405 } 406 } 407 408 guc_dbg(guc, "capture found %d ext-regs.\n", num_tot_regs); 409 guc->capture->extlists = extlists; 410 } 411 412 static const struct __guc_mmio_reg_descr_group * 413 guc_capture_get_device_reglist(struct intel_guc *guc) 414 { 415 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 416 417 if (GRAPHICS_VER(i915) > 11) { 418 /* 419 * For certain engine classes, there are slice and subslice 420 * level registers requiring steering. We allocate and populate 421 * these at init time based on hw config add it as an extension 422 * list at the end of the pre-populated render list. 423 */ 424 if (IS_DG2(i915)) 425 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)); 426 else if (IS_XEHPSDV(i915)) 427 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)); 428 else 429 guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists); 430 431 return xe_lpd_lists; 432 } 433 434 /* if GuC submission is enabled on a non-POR platform, just use a common baseline */ 435 return default_lists; 436 } 437 438 static const char * 439 __stringify_type(u32 type) 440 { 441 switch (type) { 442 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 443 return "Global"; 444 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 445 return "Class"; 446 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 447 return "Instance"; 448 default: 449 break; 450 } 451 452 return "unknown"; 453 } 454 455 static const char * 456 __stringify_engclass(u32 class) 457 { 458 switch (class) { 459 case GUC_RENDER_CLASS: 460 return "Render"; 461 case GUC_VIDEO_CLASS: 462 return "Video"; 463 case GUC_VIDEOENHANCE_CLASS: 464 return "VideoEnhance"; 465 case GUC_BLITTER_CLASS: 466 return "Blitter"; 467 case GUC_COMPUTE_CLASS: 468 return "Compute"; 469 case GUC_GSC_OTHER_CLASS: 470 return "GSC-Other"; 471 default: 472 break; 473 } 474 475 return "unknown"; 476 } 477 478 static int 479 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 480 struct guc_mmio_reg *ptr, u16 num_entries) 481 { 482 u32 i = 0, j = 0; 483 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 484 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 485 const struct __guc_mmio_reg_descr_group *match; 486 struct __guc_mmio_reg_descr_group *matchext; 487 488 if (!reglists) 489 return -ENODEV; 490 491 match = guc_capture_get_one_list(reglists, owner, type, classid); 492 if (!match) 493 return -ENODATA; 494 495 for (i = 0; i < num_entries && i < match->num_regs; ++i) { 496 ptr[i].offset = match->list[i].reg.reg; 497 ptr[i].value = 0xDEADF00D; 498 ptr[i].flags = match->list[i].flags; 499 ptr[i].mask = match->list[i].mask; 500 } 501 502 matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid); 503 if (matchext) { 504 for (i = match->num_regs, j = 0; i < num_entries && 505 i < (match->num_regs + matchext->num_regs) && 506 j < matchext->num_regs; ++i, ++j) { 507 ptr[i].offset = matchext->extlist[j].reg.reg; 508 ptr[i].value = 0xDEADF00D; 509 ptr[i].flags = matchext->extlist[j].flags; 510 ptr[i].mask = matchext->extlist[j].mask; 511 } 512 } 513 if (i < num_entries) 514 guc_dbg(guc, "Got short capture reglist init: %d out %d.\n", i, num_entries); 515 516 return 0; 517 } 518 519 static int 520 guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid) 521 { 522 const struct __guc_mmio_reg_descr_group *match; 523 struct __guc_mmio_reg_descr_group *matchext; 524 int num_regs; 525 526 match = guc_capture_get_one_list(gc->reglists, owner, type, classid); 527 if (!match) 528 return 0; 529 530 num_regs = match->num_regs; 531 532 matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid); 533 if (matchext) 534 num_regs += matchext->num_regs; 535 536 return num_regs; 537 } 538 539 static int 540 guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 541 size_t *size, bool is_purpose_est) 542 { 543 struct intel_guc_state_capture *gc = guc->capture; 544 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 545 int num_regs; 546 547 if (!gc->reglists) { 548 guc_warn(guc, "No capture reglist for this device\n"); 549 return -ENODEV; 550 } 551 552 if (cache->is_valid) { 553 *size = cache->size; 554 return cache->status; 555 } 556 557 if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF && 558 !guc_capture_get_one_list(gc->reglists, owner, type, classid)) { 559 if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL) 560 guc_warn(guc, "Missing capture reglist: global!\n"); 561 else 562 guc_warn(guc, "Missing capture reglist: %s(%u):%s(%u)!\n", 563 __stringify_type(type), type, 564 __stringify_engclass(classid), classid); 565 return -ENODATA; 566 } 567 568 num_regs = guc_cap_list_num_regs(gc, owner, type, classid); 569 /* intentional empty lists can exist depending on hw config */ 570 if (!num_regs) 571 return -ENODATA; 572 573 if (size) 574 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + 575 (num_regs * sizeof(struct guc_mmio_reg))); 576 577 return 0; 578 } 579 580 int 581 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 582 size_t *size) 583 { 584 return guc_capture_getlistsize(guc, owner, type, classid, size, false); 585 } 586 587 static void guc_capture_create_prealloc_nodes(struct intel_guc *guc); 588 589 int 590 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 591 void **outptr) 592 { 593 struct intel_guc_state_capture *gc = guc->capture; 594 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 595 struct guc_debug_capture_list *listnode; 596 int ret, num_regs; 597 u8 *caplist, *tmp; 598 size_t size = 0; 599 600 if (!gc->reglists) 601 return -ENODEV; 602 603 if (cache->is_valid) { 604 *outptr = cache->ptr; 605 return cache->status; 606 } 607 608 /* 609 * ADS population of input registers is a good 610 * time to pre-allocate cachelist output nodes 611 */ 612 guc_capture_create_prealloc_nodes(guc); 613 614 ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size); 615 if (ret) { 616 cache->is_valid = true; 617 cache->ptr = NULL; 618 cache->size = 0; 619 cache->status = ret; 620 return ret; 621 } 622 623 caplist = kzalloc(size, GFP_KERNEL); 624 if (!caplist) { 625 guc_dbg(guc, "Failed to alloc cached register capture list"); 626 return -ENOMEM; 627 } 628 629 /* populate capture list header */ 630 tmp = caplist; 631 num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); 632 listnode = (struct guc_debug_capture_list *)tmp; 633 listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); 634 635 /* populate list of register descriptor */ 636 tmp += sizeof(struct guc_debug_capture_list); 637 guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); 638 639 /* cache this list */ 640 cache->is_valid = true; 641 cache->ptr = caplist; 642 cache->size = size; 643 cache->status = 0; 644 645 *outptr = caplist; 646 647 return 0; 648 } 649 650 int 651 intel_guc_capture_getnullheader(struct intel_guc *guc, 652 void **outptr, size_t *size) 653 { 654 struct intel_guc_state_capture *gc = guc->capture; 655 int tmp = sizeof(u32) * 4; 656 void *null_header; 657 658 if (gc->ads_null_cache) { 659 *outptr = gc->ads_null_cache; 660 *size = tmp; 661 return 0; 662 } 663 664 null_header = kzalloc(tmp, GFP_KERNEL); 665 if (!null_header) { 666 guc_dbg(guc, "Failed to alloc cached register capture null list"); 667 return -ENOMEM; 668 } 669 670 gc->ads_null_cache = null_header; 671 *outptr = null_header; 672 *size = tmp; 673 674 return 0; 675 } 676 677 static int 678 guc_capture_output_min_size_est(struct intel_guc *guc) 679 { 680 struct intel_gt *gt = guc_to_gt(guc); 681 struct intel_engine_cs *engine; 682 enum intel_engine_id id; 683 int worst_min_size = 0; 684 size_t tmp = 0; 685 686 if (!guc->capture) 687 return -ENODEV; 688 689 /* 690 * If every single engine-instance suffered a failure in quick succession but 691 * were all unrelated, then a burst of multiple error-capture events would dump 692 * registers for every one engine instance, one at a time. In this case, GuC 693 * would even dump the global-registers repeatedly. 694 * 695 * For each engine instance, there would be 1 x guc_state_capture_group_t output 696 * followed by 3 x guc_state_capture_t lists. The latter is how the register 697 * dumps are split across different register types (where the '3' are global vs class 698 * vs instance). 699 */ 700 for_each_engine(engine, gt, id) { 701 worst_min_size += sizeof(struct guc_state_capture_group_header_t) + 702 (3 * sizeof(struct guc_state_capture_header_t)); 703 704 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true)) 705 worst_min_size += tmp; 706 707 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 708 engine->class, &tmp, true)) { 709 worst_min_size += tmp; 710 } 711 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 712 engine->class, &tmp, true)) { 713 worst_min_size += tmp; 714 } 715 } 716 717 return worst_min_size; 718 } 719 720 /* 721 * Add on a 3x multiplier to allow for multiple back-to-back captures occurring 722 * before the i915 can read the data out and process it 723 */ 724 #define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 725 726 static void check_guc_capture_size(struct intel_guc *guc) 727 { 728 int min_size = guc_capture_output_min_size_est(guc); 729 int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER; 730 u32 buffer_size = intel_guc_log_section_size_capture(&guc->log); 731 732 /* 733 * NOTE: min_size is much smaller than the capture region allocation (DG2: <80K vs 1MB) 734 * Additionally, its based on space needed to fit all engines getting reset at once 735 * within the same G2H handler task slot. This is very unlikely. However, if GuC really 736 * does run out of space for whatever reason, we will see an separate warning message 737 * when processing the G2H event capture-notification, search for: 738 * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE. 739 */ 740 if (min_size < 0) 741 guc_warn(guc, "Failed to calculate error state capture buffer minimum size: %d!\n", 742 min_size); 743 else if (min_size > buffer_size) 744 guc_warn(guc, "Error state capture buffer maybe small: %d < %d\n", 745 buffer_size, min_size); 746 else if (spare_size > buffer_size) 747 guc_dbg(guc, "Error state capture buffer lacks spare size: %d < %d (min = %d)\n", 748 buffer_size, spare_size, min_size); 749 } 750 751 /* 752 * KMD Init time flows: 753 * -------------------- 754 * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). 755 * intel_guc_ads acquires the register lists by calling 756 * intel_guc_capture_list_size and intel_guc_capture_list_get 'n' times, 757 * where n = 1 for global-reg-list + 758 * num_engine_classes for class-reg-list + 759 * num_engine_classes for instance-reg-list 760 * (since all instances of the same engine-class type 761 * have an identical engine-instance register-list). 762 * ADS module also calls separately for PF vs VF. 763 * 764 * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) 765 * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) 766 * Note2: 'x 3' to hold multiple capture groups 767 * 768 * GUC Runtime notify capture: 769 * -------------------------- 770 * --> G2H STATE_CAPTURE_NOTIFICATION 771 * L--> intel_guc_capture_process 772 * L--> Loop through B (head..tail) and for each engine instance's 773 * err-state-captured register-list we find, we alloc 'C': 774 * --> alloc C: A capture-output-node structure that includes misc capture info along 775 * with 3 register list dumps (global, engine-class and engine-instance) 776 * This node is created from a pre-allocated list of blank nodes in 777 * guc->capture->cachelist and populated with the error-capture 778 * data from GuC and then it's added into guc->capture->outlist linked 779 * list. This list is used for matchup and printout by i915_gpu_coredump 780 * and err_print_gt, (when user invokes the error capture sysfs). 781 * 782 * GUC --> notify context reset: 783 * ----------------------------- 784 * --> G2H CONTEXT RESET 785 * L--> guc_handle_context_reset --> i915_capture_error_state 786 * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> gt_record_engines 787 * --> capture_engine(..IS_GUC_CAPTURE) 788 * L--> intel_guc_capture_get_matching_node is where 789 * detach C from internal linked list and add it into 790 * intel_engine_coredump struct (if the context and 791 * engine of the event notification matches a node 792 * in the link list). 793 * 794 * User Sysfs / Debugfs 795 * -------------------- 796 * --> i915_gpu_coredump_copy_to_buffer-> 797 * L--> err_print_to_sgl --> err_print_gt 798 * L--> error_print_guc_captures 799 * L--> intel_guc_capture_print_node prints the 800 * register lists values of the attached node 801 * on the error-engine-dump being reported. 802 * L--> i915_reset_error_state ... -->__i915_gpu_coredump_free 803 * L--> ... cleanup_gt --> 804 * L--> intel_guc_capture_free_node returns the 805 * capture-output-node back to the internal 806 * cachelist for reuse. 807 * 808 */ 809 810 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) 811 { 812 if (buf->wr >= buf->rd) 813 return (buf->wr - buf->rd); 814 return (buf->size - buf->rd) + buf->wr; 815 } 816 817 static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) 818 { 819 if (buf->rd > buf->wr) 820 return (buf->size - buf->rd); 821 return (buf->wr - buf->rd); 822 } 823 824 /* 825 * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: 826 * 827 * The GuC Log buffer region for error-capture is managed like a ring buffer. 828 * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. 829 * Additionally, as per the current and foreseeable future, all packed error- 830 * capture output structures are dword aligned. 831 * 832 * That said, if the GuC firmware is in the midst of writing a structure that is larger 833 * than one dword but the tail end of the err-capture buffer-region has lesser space left, 834 * we would need to extract that structure one dword at a time straddled across the end, 835 * onto the start of the ring. 836 * 837 * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this 838 * function would typically do a straight-up memcpy from the ring contents and will only 839 * call this helper if their structure-extraction is straddling across the end of the 840 * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease 841 * scalability for future expansion of output data types without requiring a redesign 842 * of the flow controls. 843 */ 844 static int 845 guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 846 u32 *dw) 847 { 848 int tries = 2; 849 int avail = 0; 850 u32 *src_data; 851 852 if (!guc_capture_buf_cnt(buf)) 853 return 0; 854 855 while (tries--) { 856 avail = guc_capture_buf_cnt_to_end(buf); 857 if (avail >= sizeof(u32)) { 858 src_data = (u32 *)(buf->data + buf->rd); 859 *dw = *src_data; 860 buf->rd += 4; 861 return 4; 862 } 863 if (avail) 864 guc_dbg(guc, "Register capture log not dword aligned, skipping.\n"); 865 buf->rd = 0; 866 } 867 868 return 0; 869 } 870 871 static bool 872 guc_capture_data_extracted(struct __guc_capture_bufstate *b, 873 int size, void *dest) 874 { 875 if (guc_capture_buf_cnt_to_end(b) >= size) { 876 memcpy(dest, (b->data + b->rd), size); 877 b->rd += size; 878 return true; 879 } 880 return false; 881 } 882 883 static int 884 guc_capture_log_get_group_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 885 struct guc_state_capture_group_header_t *ghdr) 886 { 887 int read = 0; 888 int fullsize = sizeof(struct guc_state_capture_group_header_t); 889 890 if (fullsize > guc_capture_buf_cnt(buf)) 891 return -1; 892 893 if (guc_capture_data_extracted(buf, fullsize, (void *)ghdr)) 894 return 0; 895 896 read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); 897 read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); 898 if (read != fullsize) 899 return -1; 900 901 return 0; 902 } 903 904 static int 905 guc_capture_log_get_data_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 906 struct guc_state_capture_header_t *hdr) 907 { 908 int read = 0; 909 int fullsize = sizeof(struct guc_state_capture_header_t); 910 911 if (fullsize > guc_capture_buf_cnt(buf)) 912 return -1; 913 914 if (guc_capture_data_extracted(buf, fullsize, (void *)hdr)) 915 return 0; 916 917 read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); 918 read += guc_capture_log_remove_dw(guc, buf, &hdr->info); 919 read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); 920 read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); 921 read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); 922 if (read != fullsize) 923 return -1; 924 925 return 0; 926 } 927 928 static int 929 guc_capture_log_get_register(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 930 struct guc_mmio_reg *reg) 931 { 932 int read = 0; 933 int fullsize = sizeof(struct guc_mmio_reg); 934 935 if (fullsize > guc_capture_buf_cnt(buf)) 936 return -1; 937 938 if (guc_capture_data_extracted(buf, fullsize, (void *)reg)) 939 return 0; 940 941 read += guc_capture_log_remove_dw(guc, buf, ®->offset); 942 read += guc_capture_log_remove_dw(guc, buf, ®->value); 943 read += guc_capture_log_remove_dw(guc, buf, ®->flags); 944 read += guc_capture_log_remove_dw(guc, buf, ®->mask); 945 if (read != fullsize) 946 return -1; 947 948 return 0; 949 } 950 951 static void 952 guc_capture_delete_one_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 953 { 954 int i; 955 956 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 957 kfree(node->reginfo[i].regs); 958 list_del(&node->link); 959 kfree(node); 960 } 961 962 static void 963 guc_capture_delete_prealloc_nodes(struct intel_guc *guc) 964 { 965 struct __guc_capture_parsed_output *n, *ntmp; 966 967 /* 968 * NOTE: At the end of driver operation, we must assume that we 969 * have prealloc nodes in both the cachelist as well as outlist 970 * if unclaimed error capture events occurred prior to shutdown. 971 */ 972 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) 973 guc_capture_delete_one_node(guc, n); 974 975 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) 976 guc_capture_delete_one_node(guc, n); 977 } 978 979 static void 980 guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, 981 struct list_head *list) 982 { 983 list_add_tail(&node->link, list); 984 } 985 986 static void 987 guc_capture_add_node_to_outlist(struct intel_guc_state_capture *gc, 988 struct __guc_capture_parsed_output *node) 989 { 990 guc_capture_add_node_to_list(node, &gc->outlist); 991 } 992 993 static void 994 guc_capture_add_node_to_cachelist(struct intel_guc_state_capture *gc, 995 struct __guc_capture_parsed_output *node) 996 { 997 guc_capture_add_node_to_list(node, &gc->cachelist); 998 } 999 1000 static void 1001 guc_capture_init_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 1002 { 1003 struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; 1004 int i; 1005 1006 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1007 tmp[i] = node->reginfo[i].regs; 1008 memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * 1009 guc->capture->max_mmio_per_node); 1010 } 1011 memset(node, 0, sizeof(*node)); 1012 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 1013 node->reginfo[i].regs = tmp[i]; 1014 1015 INIT_LIST_HEAD(&node->link); 1016 } 1017 1018 static struct __guc_capture_parsed_output * 1019 guc_capture_get_prealloc_node(struct intel_guc *guc) 1020 { 1021 struct __guc_capture_parsed_output *found = NULL; 1022 1023 if (!list_empty(&guc->capture->cachelist)) { 1024 struct __guc_capture_parsed_output *n, *ntmp; 1025 1026 /* get first avail node from the cache list */ 1027 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { 1028 found = n; 1029 list_del(&n->link); 1030 break; 1031 } 1032 } else { 1033 struct __guc_capture_parsed_output *n, *ntmp; 1034 1035 /* traverse down and steal back the oldest node already allocated */ 1036 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1037 found = n; 1038 } 1039 if (found) 1040 list_del(&found->link); 1041 } 1042 if (found) 1043 guc_capture_init_node(guc, found); 1044 1045 return found; 1046 } 1047 1048 static struct __guc_capture_parsed_output * 1049 guc_capture_alloc_one_node(struct intel_guc *guc) 1050 { 1051 struct __guc_capture_parsed_output *new; 1052 int i; 1053 1054 new = kzalloc(sizeof(*new), GFP_KERNEL); 1055 if (!new) 1056 return NULL; 1057 1058 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1059 new->reginfo[i].regs = kcalloc(guc->capture->max_mmio_per_node, 1060 sizeof(struct guc_mmio_reg), GFP_KERNEL); 1061 if (!new->reginfo[i].regs) { 1062 while (i) 1063 kfree(new->reginfo[--i].regs); 1064 kfree(new); 1065 return NULL; 1066 } 1067 } 1068 guc_capture_init_node(guc, new); 1069 1070 return new; 1071 } 1072 1073 static struct __guc_capture_parsed_output * 1074 guc_capture_clone_node(struct intel_guc *guc, struct __guc_capture_parsed_output *original, 1075 u32 keep_reglist_mask) 1076 { 1077 struct __guc_capture_parsed_output *new; 1078 int i; 1079 1080 new = guc_capture_get_prealloc_node(guc); 1081 if (!new) 1082 return NULL; 1083 if (!original) 1084 return new; 1085 1086 new->is_partial = original->is_partial; 1087 1088 /* copy reg-lists that we want to clone */ 1089 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1090 if (keep_reglist_mask & BIT(i)) { 1091 GEM_BUG_ON(original->reginfo[i].num_regs > 1092 guc->capture->max_mmio_per_node); 1093 1094 memcpy(new->reginfo[i].regs, original->reginfo[i].regs, 1095 original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); 1096 1097 new->reginfo[i].num_regs = original->reginfo[i].num_regs; 1098 new->reginfo[i].vfid = original->reginfo[i].vfid; 1099 1100 if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { 1101 new->eng_class = original->eng_class; 1102 } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1103 new->eng_inst = original->eng_inst; 1104 new->guc_id = original->guc_id; 1105 new->lrca = original->lrca; 1106 } 1107 } 1108 } 1109 1110 return new; 1111 } 1112 1113 static void 1114 __guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1115 { 1116 struct __guc_capture_parsed_output *node = NULL; 1117 int i; 1118 1119 for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { 1120 node = guc_capture_alloc_one_node(guc); 1121 if (!node) { 1122 guc_warn(guc, "Register capture pre-alloc-cache failure\n"); 1123 /* dont free the priors, use what we got and cleanup at shutdown */ 1124 return; 1125 } 1126 guc_capture_add_node_to_cachelist(guc->capture, node); 1127 } 1128 } 1129 1130 static int 1131 guc_get_max_reglist_count(struct intel_guc *guc) 1132 { 1133 int i, j, k, tmp, maxregcount = 0; 1134 1135 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1136 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1137 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1138 if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) 1139 continue; 1140 1141 tmp = guc_cap_list_num_regs(guc->capture, i, j, k); 1142 if (tmp > maxregcount) 1143 maxregcount = tmp; 1144 } 1145 } 1146 } 1147 if (!maxregcount) 1148 maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; 1149 1150 return maxregcount; 1151 } 1152 1153 static void 1154 guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1155 { 1156 /* skip if we've already done the pre-alloc */ 1157 if (guc->capture->max_mmio_per_node) 1158 return; 1159 1160 guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); 1161 __guc_capture_create_prealloc_nodes(guc); 1162 } 1163 1164 static int 1165 guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf) 1166 { 1167 struct guc_state_capture_group_header_t ghdr = {0}; 1168 struct guc_state_capture_header_t hdr = {0}; 1169 struct __guc_capture_parsed_output *node = NULL; 1170 struct guc_mmio_reg *regs = NULL; 1171 int i, numlists, numregs, ret = 0; 1172 enum guc_capture_type datatype; 1173 struct guc_mmio_reg tmp; 1174 bool is_partial = false; 1175 1176 i = guc_capture_buf_cnt(buf); 1177 if (!i) 1178 return -ENODATA; 1179 if (i % sizeof(u32)) { 1180 guc_warn(guc, "Got mis-aligned register capture entries\n"); 1181 ret = -EIO; 1182 goto bailout; 1183 } 1184 1185 /* first get the capture group header */ 1186 if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { 1187 ret = -EIO; 1188 goto bailout; 1189 } 1190 /* 1191 * we would typically expect a layout as below where n would be expected to be 1192 * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine 1193 * instances being reset together. 1194 * ____________________________________________ 1195 * | Capture Group | 1196 * | ________________________________________ | 1197 * | | Capture Group Header: | | 1198 * | | - num_captures = 5 | | 1199 * | |______________________________________| | 1200 * | ________________________________________ | 1201 * | | Capture1: | | 1202 * | | Hdr: GLOBAL, numregs=a | | 1203 * | | ____________________________________ | | 1204 * | | | Reglist | | | 1205 * | | | - reg1, reg2, ... rega | | | 1206 * | | |__________________________________| | | 1207 * | |______________________________________| | 1208 * | ________________________________________ | 1209 * | | Capture2: | | 1210 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | 1211 * | | ____________________________________ | | 1212 * | | | Reglist | | | 1213 * | | | - reg1, reg2, ... regb | | | 1214 * | | |__________________________________| | | 1215 * | |______________________________________| | 1216 * | ________________________________________ | 1217 * | | Capture3: | | 1218 * | | Hdr: INSTANCE=RCS, numregs=c | | 1219 * | | ____________________________________ | | 1220 * | | | Reglist | | | 1221 * | | | - reg1, reg2, ... regc | | | 1222 * | | |__________________________________| | | 1223 * | |______________________________________| | 1224 * | ________________________________________ | 1225 * | | Capture4: | | 1226 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | 1227 * | | ____________________________________ | | 1228 * | | | Reglist | | | 1229 * | | | - reg1, reg2, ... regd | | | 1230 * | | |__________________________________| | | 1231 * | |______________________________________| | 1232 * | ________________________________________ | 1233 * | | Capture5: | | 1234 * | | Hdr: INSTANCE=CCS0, numregs=e | | 1235 * | | ____________________________________ | | 1236 * | | | Reglist | | | 1237 * | | | - reg1, reg2, ... rege | | | 1238 * | | |__________________________________| | | 1239 * | |______________________________________| | 1240 * |__________________________________________| 1241 */ 1242 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); 1243 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); 1244 1245 while (numlists--) { 1246 if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { 1247 ret = -EIO; 1248 break; 1249 } 1250 1251 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); 1252 if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1253 /* unknown capture type - skip over to next capture set */ 1254 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1255 while (numregs--) { 1256 if (guc_capture_log_get_register(guc, buf, &tmp)) { 1257 ret = -EIO; 1258 break; 1259 } 1260 } 1261 continue; 1262 } else if (node) { 1263 /* 1264 * Based on the current capture type and what we have so far, 1265 * decide if we should add the current node into the internal 1266 * linked list for match-up when i915_gpu_coredump calls later 1267 * (and alloc a blank node for the next set of reglists) 1268 * or continue with the same node or clone the current node 1269 * but only retain the global or class registers (such as the 1270 * case of dependent engine resets). 1271 */ 1272 if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { 1273 guc_capture_add_node_to_outlist(guc->capture, node); 1274 node = NULL; 1275 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && 1276 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { 1277 /* Add to list, clone node and duplicate global list */ 1278 guc_capture_add_node_to_outlist(guc->capture, node); 1279 node = guc_capture_clone_node(guc, node, 1280 GCAP_PARSED_REGLIST_INDEX_GLOBAL); 1281 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && 1282 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { 1283 /* Add to list, clone node and duplicate global + class lists */ 1284 guc_capture_add_node_to_outlist(guc->capture, node); 1285 node = guc_capture_clone_node(guc, node, 1286 (GCAP_PARSED_REGLIST_INDEX_GLOBAL | 1287 GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); 1288 } 1289 } 1290 1291 if (!node) { 1292 node = guc_capture_get_prealloc_node(guc); 1293 if (!node) { 1294 ret = -ENOMEM; 1295 break; 1296 } 1297 if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) 1298 guc_dbg(guc, "Register capture missing global dump: %08x!\n", 1299 datatype); 1300 } 1301 node->is_partial = is_partial; 1302 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); 1303 switch (datatype) { 1304 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1305 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1306 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); 1307 node->lrca = hdr.lrca; 1308 node->guc_id = hdr.guc_id; 1309 break; 1310 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1311 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1312 break; 1313 default: 1314 break; 1315 } 1316 1317 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1318 if (numregs > guc->capture->max_mmio_per_node) { 1319 guc_dbg(guc, "Register capture list extraction clipped by prealloc!\n"); 1320 numregs = guc->capture->max_mmio_per_node; 1321 } 1322 node->reginfo[datatype].num_regs = numregs; 1323 regs = node->reginfo[datatype].regs; 1324 i = 0; 1325 while (numregs--) { 1326 if (guc_capture_log_get_register(guc, buf, ®s[i++])) { 1327 ret = -EIO; 1328 break; 1329 } 1330 } 1331 } 1332 1333 bailout: 1334 if (node) { 1335 /* If we have data, add to linked list for match-up when i915_gpu_coredump calls */ 1336 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1337 if (node->reginfo[i].regs) { 1338 guc_capture_add_node_to_outlist(guc->capture, node); 1339 node = NULL; 1340 break; 1341 } 1342 } 1343 if (node) /* else return it back to cache list */ 1344 guc_capture_add_node_to_cachelist(guc->capture, node); 1345 } 1346 return ret; 1347 } 1348 1349 static int __guc_capture_flushlog_complete(struct intel_guc *guc) 1350 { 1351 u32 action[] = { 1352 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, 1353 GUC_CAPTURE_LOG_BUFFER 1354 }; 1355 1356 return intel_guc_send_nb(guc, action, ARRAY_SIZE(action), 0); 1357 1358 } 1359 1360 static void __guc_capture_process_output(struct intel_guc *guc) 1361 { 1362 unsigned int buffer_size, read_offset, write_offset, full_count; 1363 struct intel_uc *uc = container_of(guc, typeof(*uc), guc); 1364 struct guc_log_buffer_state log_buf_state_local; 1365 struct guc_log_buffer_state *log_buf_state; 1366 struct __guc_capture_bufstate buf; 1367 void *src_data = NULL; 1368 bool new_overflow; 1369 int ret; 1370 1371 log_buf_state = guc->log.buf_addr + 1372 (sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER); 1373 src_data = guc->log.buf_addr + 1374 intel_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1375 1376 /* 1377 * Make a copy of the state structure, inside GuC log buffer 1378 * (which is uncached mapped), on the stack to avoid reading 1379 * from it multiple times. 1380 */ 1381 memcpy(&log_buf_state_local, log_buf_state, sizeof(struct guc_log_buffer_state)); 1382 buffer_size = intel_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER); 1383 read_offset = log_buf_state_local.read_ptr; 1384 write_offset = log_buf_state_local.sampled_write_ptr; 1385 full_count = log_buf_state_local.buffer_full_cnt; 1386 1387 /* Bookkeeping stuff */ 1388 guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; 1389 new_overflow = intel_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, 1390 full_count); 1391 1392 /* Now copy the actual logs. */ 1393 if (unlikely(new_overflow)) { 1394 /* copy the whole buffer in case of overflow */ 1395 read_offset = 0; 1396 write_offset = buffer_size; 1397 } else if (unlikely((read_offset > buffer_size) || 1398 (write_offset > buffer_size))) { 1399 guc_err(guc, "Register capture buffer in invalid state: read = 0x%X, size = 0x%X!\n", 1400 read_offset, buffer_size); 1401 /* copy whole buffer as offsets are unreliable */ 1402 read_offset = 0; 1403 write_offset = buffer_size; 1404 } 1405 1406 buf.size = buffer_size; 1407 buf.rd = read_offset; 1408 buf.wr = write_offset; 1409 buf.data = src_data; 1410 1411 if (!uc->reset_in_progress) { 1412 do { 1413 ret = guc_capture_extract_reglists(guc, &buf); 1414 } while (ret >= 0); 1415 } 1416 1417 /* Update the state of log buffer err-cap state */ 1418 log_buf_state->read_ptr = write_offset; 1419 log_buf_state->flush_to_file = 0; 1420 __guc_capture_flushlog_complete(guc); 1421 } 1422 1423 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1424 1425 static const char * 1426 guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type, 1427 u32 class, u32 id, u32 offset, u32 *is_ext) 1428 { 1429 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 1430 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 1431 const struct __guc_mmio_reg_descr_group *match; 1432 struct __guc_mmio_reg_descr_group *matchext; 1433 int j; 1434 1435 *is_ext = 0; 1436 if (!reglists) 1437 return NULL; 1438 1439 match = guc_capture_get_one_list(reglists, owner, type, id); 1440 if (!match) 1441 return NULL; 1442 1443 for (j = 0; j < match->num_regs; ++j) { 1444 if (offset == match->list[j].reg.reg) 1445 return match->list[j].regname; 1446 } 1447 if (extlists) { 1448 matchext = guc_capture_get_one_ext_list(extlists, owner, type, id); 1449 if (!matchext) 1450 return NULL; 1451 for (j = 0; j < matchext->num_regs; ++j) { 1452 if (offset == matchext->extlist[j].reg.reg) { 1453 *is_ext = 1; 1454 return matchext->extlist[j].regname; 1455 } 1456 } 1457 } 1458 1459 return NULL; 1460 } 1461 1462 #define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng) \ 1463 do { \ 1464 i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n", \ 1465 (eng)->name); \ 1466 i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n", (eng)->class); \ 1467 i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance); \ 1468 i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n", \ 1469 (eng)->logical_mask); \ 1470 } while (0) 1471 1472 #define GCAP_PRINT_GUC_INST_INFO(ebuf, node) \ 1473 do { \ 1474 i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n", \ 1475 (node)->eng_inst); \ 1476 i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n", (node)->guc_id); \ 1477 i915_error_printf(ebuf, " LRCA: 0x%08x\n", (node)->lrca); \ 1478 } while (0) 1479 1480 int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf, 1481 const struct intel_engine_coredump *ee) 1482 { 1483 const char *grptype[GUC_STATE_CAPTURE_GROUP_TYPE_MAX] = { 1484 "full-capture", 1485 "partial-capture" 1486 }; 1487 const char *datatype[GUC_CAPTURE_LIST_TYPE_MAX] = { 1488 "Global", 1489 "Engine-Class", 1490 "Engine-Instance" 1491 }; 1492 struct intel_guc_state_capture *cap; 1493 struct __guc_capture_parsed_output *node; 1494 struct intel_engine_cs *eng; 1495 struct guc_mmio_reg *regs; 1496 struct intel_guc *guc; 1497 const char *str; 1498 int numregs, i, j; 1499 u32 is_ext; 1500 1501 if (!ebuf || !ee) 1502 return -EINVAL; 1503 cap = ee->guc_capture; 1504 if (!cap || !ee->engine) 1505 return -ENODEV; 1506 1507 guc = &ee->engine->gt->uc.guc; 1508 1509 i915_error_printf(ebuf, "global --- GuC Error Capture on %s command stream:\n", 1510 ee->engine->name); 1511 1512 node = ee->guc_capture_node; 1513 if (!node) { 1514 i915_error_printf(ebuf, " No matching ee-node\n"); 1515 return 0; 1516 } 1517 1518 i915_error_printf(ebuf, "Coverage: %s\n", grptype[node->is_partial]); 1519 1520 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1521 i915_error_printf(ebuf, " RegListType: %s\n", 1522 datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]); 1523 i915_error_printf(ebuf, " Owner-Id: %d\n", node->reginfo[i].vfid); 1524 1525 switch (i) { 1526 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 1527 default: 1528 break; 1529 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1530 i915_error_printf(ebuf, " GuC-Eng-Class: %d\n", node->eng_class); 1531 i915_error_printf(ebuf, " i915-Eng-Class: %d\n", 1532 guc_class_to_engine_class(node->eng_class)); 1533 break; 1534 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1535 eng = intel_guc_lookup_engine(guc, node->eng_class, node->eng_inst); 1536 if (eng) 1537 GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng); 1538 else 1539 i915_error_printf(ebuf, " i915-Eng-Lookup Fail!\n"); 1540 GCAP_PRINT_GUC_INST_INFO(ebuf, node); 1541 break; 1542 } 1543 1544 numregs = node->reginfo[i].num_regs; 1545 i915_error_printf(ebuf, " NumRegs: %d\n", numregs); 1546 j = 0; 1547 while (numregs--) { 1548 regs = node->reginfo[i].regs; 1549 str = guc_capture_reg_to_str(guc, GUC_CAPTURE_LIST_INDEX_PF, i, 1550 node->eng_class, 0, regs[j].offset, &is_ext); 1551 if (!str) 1552 i915_error_printf(ebuf, " REG-0x%08x", regs[j].offset); 1553 else 1554 i915_error_printf(ebuf, " %s", str); 1555 if (is_ext) 1556 i915_error_printf(ebuf, "[%ld][%ld]", 1557 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), 1558 FIELD_GET(GUC_REGSET_STEERING_INSTANCE, regs[j].flags)); 1559 i915_error_printf(ebuf, ": 0x%08x\n", regs[j].value); 1560 ++j; 1561 } 1562 } 1563 return 0; 1564 } 1565 1566 #endif //CONFIG_DRM_I915_CAPTURE_ERROR 1567 1568 static void guc_capture_find_ecode(struct intel_engine_coredump *ee) 1569 { 1570 struct gcap_reg_list_info *reginfo; 1571 struct guc_mmio_reg *regs; 1572 i915_reg_t reg_ipehr = RING_IPEHR(0); 1573 i915_reg_t reg_instdone = RING_INSTDONE(0); 1574 int i; 1575 1576 if (!ee->guc_capture_node) 1577 return; 1578 1579 reginfo = ee->guc_capture_node->reginfo + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE; 1580 regs = reginfo->regs; 1581 for (i = 0; i < reginfo->num_regs; i++) { 1582 if (regs[i].offset == reg_ipehr.reg) 1583 ee->ipehr = regs[i].value; 1584 else if (regs[i].offset == reg_instdone.reg) 1585 ee->instdone.instdone = regs[i].value; 1586 } 1587 } 1588 1589 void intel_guc_capture_free_node(struct intel_engine_coredump *ee) 1590 { 1591 if (!ee || !ee->guc_capture_node) 1592 return; 1593 1594 guc_capture_add_node_to_cachelist(ee->guc_capture, ee->guc_capture_node); 1595 ee->guc_capture = NULL; 1596 ee->guc_capture_node = NULL; 1597 } 1598 1599 void intel_guc_capture_get_matching_node(struct intel_gt *gt, 1600 struct intel_engine_coredump *ee, 1601 struct intel_context *ce) 1602 { 1603 struct __guc_capture_parsed_output *n, *ntmp; 1604 struct intel_guc *guc; 1605 1606 if (!gt || !ee || !ce) 1607 return; 1608 1609 guc = >->uc.guc; 1610 if (!guc->capture) 1611 return; 1612 1613 GEM_BUG_ON(ee->guc_capture_node); 1614 /* 1615 * Look for a matching GuC reported error capture node from 1616 * the internal output link-list based on lrca, guc-id and engine 1617 * identification. 1618 */ 1619 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1620 if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) && 1621 n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) && 1622 n->guc_id == ce->guc_id.id && 1623 (n->lrca & CTX_GTT_ADDRESS_MASK) == (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) { 1624 list_del(&n->link); 1625 ee->guc_capture_node = n; 1626 ee->guc_capture = guc->capture; 1627 guc_capture_find_ecode(ee); 1628 return; 1629 } 1630 } 1631 1632 guc_warn(guc, "No register capture node found for 0x%04X / 0x%08X\n", 1633 ce->guc_id.id, ce->lrc.lrca); 1634 } 1635 1636 void intel_guc_capture_process(struct intel_guc *guc) 1637 { 1638 if (guc->capture) 1639 __guc_capture_process_output(guc); 1640 } 1641 1642 static void 1643 guc_capture_free_ads_cache(struct intel_guc_state_capture *gc) 1644 { 1645 int i, j, k; 1646 struct __guc_capture_ads_cache *cache; 1647 1648 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1649 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1650 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1651 cache = &gc->ads_cache[i][j][k]; 1652 if (cache->is_valid) 1653 kfree(cache->ptr); 1654 } 1655 } 1656 } 1657 kfree(gc->ads_null_cache); 1658 } 1659 1660 void intel_guc_capture_destroy(struct intel_guc *guc) 1661 { 1662 if (!guc->capture) 1663 return; 1664 1665 guc_capture_free_ads_cache(guc->capture); 1666 1667 guc_capture_delete_prealloc_nodes(guc); 1668 1669 guc_capture_free_extlists(guc->capture->extlists); 1670 kfree(guc->capture->extlists); 1671 1672 kfree(guc->capture); 1673 guc->capture = NULL; 1674 } 1675 1676 int intel_guc_capture_init(struct intel_guc *guc) 1677 { 1678 guc->capture = kzalloc(sizeof(*guc->capture), GFP_KERNEL); 1679 if (!guc->capture) 1680 return -ENOMEM; 1681 1682 guc->capture->reglists = guc_capture_get_device_reglist(guc); 1683 1684 INIT_LIST_HEAD(&guc->capture->outlist); 1685 INIT_LIST_HEAD(&guc->capture->cachelist); 1686 1687 check_guc_capture_size(guc); 1688 1689 return 0; 1690 } 1691