1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021-2022 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include <drm/drm_print.h> 9 10 #include "gt/intel_engine_regs.h" 11 #include "gt/intel_gt.h" 12 #include "gt/intel_gt_regs.h" 13 #include "gt/intel_lrc.h" 14 #include "guc_capture_fwif.h" 15 #include "intel_guc_capture.h" 16 #include "intel_guc_fwif.h" 17 #include "i915_drv.h" 18 #include "i915_gpu_error.h" 19 #include "i915_irq.h" 20 #include "i915_memcpy.h" 21 #include "i915_reg.h" 22 23 /* 24 * Define all device tables of GuC error capture register lists 25 * NOTE: For engine-registers, GuC only needs the register offsets 26 * from the engine-mmio-base 27 */ 28 #define COMMON_BASE_GLOBAL \ 29 { FORCEWAKE_MT, 0, 0, "FORCEWAKE" } 30 31 #define COMMON_GEN9BASE_GLOBAL \ 32 { GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0" }, \ 33 { GEN8_FAULT_TLB_DATA1, 0, 0, "GEN8_FAULT_TLB_DATA1" }, \ 34 { ERROR_GEN6, 0, 0, "ERROR_GEN6" }, \ 35 { DONE_REG, 0, 0, "DONE_REG" }, \ 36 { HSW_GTT_CACHE_EN, 0, 0, "HSW_GTT_CACHE_EN" } 37 38 #define COMMON_GEN12BASE_GLOBAL \ 39 { GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0" }, \ 40 { GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1" }, \ 41 { GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG" }, \ 42 { GEN12_GAM_DONE, 0, 0, "GAM_DONE" }, \ 43 { GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG" } 44 45 #define COMMON_BASE_ENGINE_INSTANCE \ 46 { RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \ 47 { RING_ESR(0), 0, 0, "ESR" }, \ 48 { RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW" }, \ 49 { RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW" }, \ 50 { RING_IPEIR(0), 0, 0, "IPEIR" }, \ 51 { RING_IPEHR(0), 0, 0, "IPEHR" }, \ 52 { RING_INSTPS(0), 0, 0, "INSTPS" }, \ 53 { RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32" }, \ 54 { RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32" }, \ 55 { RING_BBSTATE(0), 0, 0, "BB_STATE" }, \ 56 { CCID(0), 0, 0, "CCID" }, \ 57 { RING_ACTHD(0), 0, 0, "ACTHD_LDW" }, \ 58 { RING_ACTHD_UDW(0), 0, 0, "ACTHD_UDW" }, \ 59 { RING_INSTPM(0), 0, 0, "INSTPM" }, \ 60 { RING_INSTDONE(0), 0, 0, "INSTDONE" }, \ 61 { RING_NOPID(0), 0, 0, "RING_NOPID" }, \ 62 { RING_START(0), 0, 0, "START" }, \ 63 { RING_HEAD(0), 0, 0, "HEAD" }, \ 64 { RING_TAIL(0), 0, 0, "TAIL" }, \ 65 { RING_CTL(0), 0, 0, "CTL" }, \ 66 { RING_MI_MODE(0), 0, 0, "MODE" }, \ 67 { RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL" }, \ 68 { RING_HWS_PGA(0), 0, 0, "HWS" }, \ 69 { RING_MODE_GEN7(0), 0, 0, "GFX_MODE" }, \ 70 { GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW" }, \ 71 { GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW" }, \ 72 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \ 73 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \ 74 { GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW" }, \ 75 { GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW" }, \ 76 { GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW" }, \ 77 { GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW" } 78 79 #define COMMON_BASE_HAS_EU \ 80 { EIR, 0, 0, "EIR" } 81 82 #define COMMON_BASE_RENDER \ 83 { GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE" } 84 85 #define COMMON_GEN12BASE_RENDER \ 86 { GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA" }, \ 87 { GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2" } 88 89 #define COMMON_GEN12BASE_VEC \ 90 { GEN12_SFC_DONE(0), 0, 0, "SFC_DONE[0]" }, \ 91 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \ 92 { GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]" }, \ 93 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" } 94 95 /* XE_LPD - Global */ 96 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = { 97 COMMON_BASE_GLOBAL, 98 COMMON_GEN9BASE_GLOBAL, 99 COMMON_GEN12BASE_GLOBAL, 100 }; 101 102 /* XE_LPD - Render / Compute Per-Class */ 103 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = { 104 COMMON_BASE_HAS_EU, 105 COMMON_BASE_RENDER, 106 COMMON_GEN12BASE_RENDER, 107 }; 108 109 /* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */ 110 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = { 111 COMMON_BASE_ENGINE_INSTANCE, 112 }; 113 114 /* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */ 115 static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = { 116 COMMON_BASE_ENGINE_INSTANCE, 117 }; 118 119 /* XE_LPD - Video Enhancement Per-Class */ 120 static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = { 121 COMMON_GEN12BASE_VEC, 122 }; 123 124 /* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */ 125 static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = { 126 COMMON_BASE_ENGINE_INSTANCE, 127 }; 128 129 /* GEN9/XE_LPD - Blitter Per-Engine-Instance */ 130 static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = { 131 COMMON_BASE_ENGINE_INSTANCE, 132 }; 133 134 /* GEN9 - Global */ 135 static const struct __guc_mmio_reg_descr default_global_regs[] = { 136 COMMON_BASE_GLOBAL, 137 COMMON_GEN9BASE_GLOBAL, 138 }; 139 140 static const struct __guc_mmio_reg_descr default_rc_class_regs[] = { 141 COMMON_BASE_HAS_EU, 142 COMMON_BASE_RENDER, 143 }; 144 145 /* 146 * Empty lists: 147 * GEN9/XE_LPD - Blitter Per-Class 148 * GEN9/XE_LPD - Media Decode/Encode Per-Class 149 * GEN9 - VEC Class 150 */ 151 static const struct __guc_mmio_reg_descr empty_regs_list[] = { 152 }; 153 154 #define TO_GCAP_DEF_OWNER(x) (GUC_CAPTURE_LIST_INDEX_##x) 155 #define TO_GCAP_DEF_TYPE(x) (GUC_CAPTURE_LIST_TYPE_##x) 156 #define MAKE_REGLIST(regslist, regsowner, regstype, class) \ 157 { \ 158 regslist, \ 159 ARRAY_SIZE(regslist), \ 160 TO_GCAP_DEF_OWNER(regsowner), \ 161 TO_GCAP_DEF_TYPE(regstype), \ 162 class, \ 163 NULL, \ 164 } 165 166 /* List of lists */ 167 static struct __guc_mmio_reg_descr_group default_lists[] = { 168 MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0), 169 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 170 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 171 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 172 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 173 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 174 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 175 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 176 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 177 {} 178 }; 179 180 static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = { 181 MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0), 182 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS), 183 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS), 184 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS), 185 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS), 186 MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS), 187 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS), 188 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS), 189 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS), 190 {} 191 }; 192 193 static const struct __guc_mmio_reg_descr_group * 194 guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, 195 u32 owner, u32 type, u32 id) 196 { 197 int i; 198 199 if (!reglists) 200 return NULL; 201 202 for (i = 0; reglists[i].list; ++i) { 203 if (reglists[i].owner == owner && reglists[i].type == type && 204 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 205 return ®lists[i]; 206 } 207 208 return NULL; 209 } 210 211 static struct __guc_mmio_reg_descr_group * 212 guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, 213 u32 owner, u32 type, u32 id) 214 { 215 int i; 216 217 if (!reglists) 218 return NULL; 219 220 for (i = 0; reglists[i].extlist; ++i) { 221 if (reglists[i].owner == owner && reglists[i].type == type && 222 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL)) 223 return ®lists[i]; 224 } 225 226 return NULL; 227 } 228 229 static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglists) 230 { 231 int i = 0; 232 233 if (!reglists) 234 return; 235 236 while (reglists[i].extlist) 237 kfree(reglists[i++].extlist); 238 } 239 240 struct __ext_steer_reg { 241 const char *name; 242 i915_reg_t reg; 243 }; 244 245 static const struct __ext_steer_reg xe_extregs[] = { 246 {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE}, 247 {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE} 248 }; 249 250 static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, 251 const struct __ext_steer_reg *extlist, 252 int slice_id, int subslice_id) 253 { 254 ext->reg = extlist->reg; 255 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 256 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); 257 ext->regname = extlist->name; 258 } 259 260 static int 261 __alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist, 262 const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) 263 { 264 struct __guc_mmio_reg_descr *list; 265 266 list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); 267 if (!list) 268 return -ENOMEM; 269 270 newlist->extlist = list; 271 newlist->num_regs = num_regs; 272 newlist->owner = rootlist->owner; 273 newlist->engine = rootlist->engine; 274 newlist->type = rootlist->type; 275 276 return 0; 277 } 278 279 static void 280 guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc, 281 const struct __guc_mmio_reg_descr_group *lists) 282 { 283 struct intel_gt *gt = guc_to_gt(guc); 284 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 285 int slice, subslice, i, num_steer_regs, num_tot_regs = 0; 286 const struct __guc_mmio_reg_descr_group *list; 287 struct __guc_mmio_reg_descr_group *extlists; 288 struct __guc_mmio_reg_descr *extarray; 289 struct sseu_dev_info *sseu; 290 291 /* In XE_LPD we only have steered registers for the render-class */ 292 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 293 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 294 /* skip if extlists was previously allocated */ 295 if (!list || guc->capture->extlists) 296 return; 297 298 num_steer_regs = ARRAY_SIZE(xe_extregs); 299 300 sseu = >->info.sseu; 301 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) 302 num_tot_regs += num_steer_regs; 303 304 if (!num_tot_regs) 305 return; 306 307 /* allocate an extra for an end marker */ 308 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 309 if (!extlists) 310 return; 311 312 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 313 kfree(extlists); 314 return; 315 } 316 317 extarray = extlists[0].extlist; 318 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { 319 for (i = 0; i < num_steer_regs; ++i) { 320 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 321 ++extarray; 322 } 323 } 324 325 guc->capture->extlists = extlists; 326 } 327 328 static const struct __ext_steer_reg xehpg_extregs[] = { 329 {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG} 330 }; 331 332 static bool __has_xehpg_extregs(u32 ipver) 333 { 334 return (ipver >= IP_VER(12, 55)); 335 } 336 337 static void 338 guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc, 339 const struct __guc_mmio_reg_descr_group *lists, 340 u32 ipver) 341 { 342 struct intel_gt *gt = guc_to_gt(guc); 343 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 344 struct sseu_dev_info *sseu; 345 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; 346 const struct __guc_mmio_reg_descr_group *list; 347 struct __guc_mmio_reg_descr_group *extlists; 348 struct __guc_mmio_reg_descr *extarray; 349 350 /* In XE_LP / HPG we only have render-class steering registers during error-capture */ 351 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, 352 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS); 353 /* skip if extlists was previously allocated */ 354 if (!list || guc->capture->extlists) 355 return; 356 357 num_steer_regs = ARRAY_SIZE(xe_extregs); 358 if (__has_xehpg_extregs(ipver)) 359 num_steer_regs += ARRAY_SIZE(xehpg_extregs); 360 361 sseu = >->info.sseu; 362 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { 363 num_tot_regs += num_steer_regs; 364 } 365 366 if (!num_tot_regs) 367 return; 368 369 /* allocate an extra for an end marker */ 370 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); 371 if (!extlists) 372 return; 373 374 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) { 375 kfree(extlists); 376 return; 377 } 378 379 extarray = extlists[0].extlist; 380 for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { 381 for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { 382 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); 383 ++extarray; 384 } 385 if (__has_xehpg_extregs(ipver)) { 386 for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { 387 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); 388 ++extarray; 389 } 390 } 391 } 392 393 drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs); 394 guc->capture->extlists = extlists; 395 } 396 397 static const struct __guc_mmio_reg_descr_group * 398 guc_capture_get_device_reglist(struct intel_guc *guc) 399 { 400 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 401 402 if (GRAPHICS_VER(i915) > 11) { 403 /* 404 * For certain engine classes, there are slice and subslice 405 * level registers requiring steering. We allocate and populate 406 * these at init time based on hw config add it as an extension 407 * list at the end of the pre-populated render list. 408 */ 409 if (IS_DG2(i915)) 410 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)); 411 else if (IS_XEHPSDV(i915)) 412 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)); 413 else 414 guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists); 415 416 return xe_lpd_lists; 417 } 418 419 /* if GuC submission is enabled on a non-POR platform, just use a common baseline */ 420 return default_lists; 421 } 422 423 static int 424 guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 425 struct guc_mmio_reg *ptr, u16 num_entries) 426 { 427 u32 i = 0, j = 0; 428 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 429 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 430 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 431 const struct __guc_mmio_reg_descr_group *match; 432 struct __guc_mmio_reg_descr_group *matchext; 433 434 if (!reglists) 435 return -ENODEV; 436 437 match = guc_capture_get_one_list(reglists, owner, type, classid); 438 if (!match) 439 return -ENODATA; 440 441 for (i = 0; i < num_entries && i < match->num_regs; ++i) { 442 ptr[i].offset = match->list[i].reg.reg; 443 ptr[i].value = 0xDEADF00D; 444 ptr[i].flags = match->list[i].flags; 445 ptr[i].mask = match->list[i].mask; 446 } 447 448 matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid); 449 if (matchext) { 450 for (i = match->num_regs, j = 0; i < num_entries && 451 i < (match->num_regs + matchext->num_regs) && 452 j < matchext->num_regs; ++i, ++j) { 453 ptr[i].offset = matchext->extlist[j].reg.reg; 454 ptr[i].value = 0xDEADF00D; 455 ptr[i].flags = matchext->extlist[j].flags; 456 ptr[i].mask = matchext->extlist[j].mask; 457 } 458 } 459 if (i < num_entries) 460 drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n", 461 (int)i, (int)num_entries); 462 463 return 0; 464 } 465 466 static int 467 guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid) 468 { 469 const struct __guc_mmio_reg_descr_group *match; 470 struct __guc_mmio_reg_descr_group *matchext; 471 int num_regs; 472 473 match = guc_capture_get_one_list(gc->reglists, owner, type, classid); 474 if (!match) 475 return 0; 476 477 num_regs = match->num_regs; 478 479 matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid); 480 if (matchext) 481 num_regs += matchext->num_regs; 482 483 return num_regs; 484 } 485 486 int 487 intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 488 size_t *size) 489 { 490 struct intel_guc_state_capture *gc = guc->capture; 491 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 492 int num_regs; 493 494 if (!gc->reglists) 495 return -ENODEV; 496 497 if (cache->is_valid) { 498 *size = cache->size; 499 return cache->status; 500 } 501 502 num_regs = guc_cap_list_num_regs(gc, owner, type, classid); 503 if (!num_regs) 504 return -ENODATA; 505 506 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) + 507 (num_regs * sizeof(struct guc_mmio_reg))); 508 509 return 0; 510 } 511 512 static void guc_capture_create_prealloc_nodes(struct intel_guc *guc); 513 514 int 515 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid, 516 void **outptr) 517 { 518 struct intel_guc_state_capture *gc = guc->capture; 519 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid]; 520 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 521 struct guc_debug_capture_list *listnode; 522 int ret, num_regs; 523 u8 *caplist, *tmp; 524 size_t size = 0; 525 526 if (!gc->reglists) 527 return -ENODEV; 528 529 if (cache->is_valid) { 530 *outptr = cache->ptr; 531 return cache->status; 532 } 533 534 /* 535 * ADS population of input registers is a good 536 * time to pre-allocate cachelist output nodes 537 */ 538 guc_capture_create_prealloc_nodes(guc); 539 540 ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size); 541 if (ret) { 542 cache->is_valid = true; 543 cache->ptr = NULL; 544 cache->size = 0; 545 cache->status = ret; 546 return ret; 547 } 548 549 caplist = kzalloc(size, GFP_KERNEL); 550 if (!caplist) { 551 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist"); 552 return -ENOMEM; 553 } 554 555 /* populate capture list header */ 556 tmp = caplist; 557 num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid); 558 listnode = (struct guc_debug_capture_list *)tmp; 559 listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs); 560 561 /* populate list of register descriptor */ 562 tmp += sizeof(struct guc_debug_capture_list); 563 guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs); 564 565 /* cache this list */ 566 cache->is_valid = true; 567 cache->ptr = caplist; 568 cache->size = size; 569 cache->status = 0; 570 571 *outptr = caplist; 572 573 return 0; 574 } 575 576 int 577 intel_guc_capture_getnullheader(struct intel_guc *guc, 578 void **outptr, size_t *size) 579 { 580 struct intel_guc_state_capture *gc = guc->capture; 581 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 582 int tmp = sizeof(u32) * 4; 583 void *null_header; 584 585 if (gc->ads_null_cache) { 586 *outptr = gc->ads_null_cache; 587 *size = tmp; 588 return 0; 589 } 590 591 null_header = kzalloc(tmp, GFP_KERNEL); 592 if (!null_header) { 593 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist"); 594 return -ENOMEM; 595 } 596 597 gc->ads_null_cache = null_header; 598 *outptr = null_header; 599 *size = tmp; 600 601 return 0; 602 } 603 604 #define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3 605 606 int 607 intel_guc_capture_output_min_size_est(struct intel_guc *guc) 608 { 609 struct intel_gt *gt = guc_to_gt(guc); 610 struct intel_engine_cs *engine; 611 enum intel_engine_id id; 612 int worst_min_size = 0, num_regs = 0; 613 size_t tmp = 0; 614 615 if (!guc->capture) 616 return -ENODEV; 617 618 /* 619 * If every single engine-instance suffered a failure in quick succession but 620 * were all unrelated, then a burst of multiple error-capture events would dump 621 * registers for every one engine instance, one at a time. In this case, GuC 622 * would even dump the global-registers repeatedly. 623 * 624 * For each engine instance, there would be 1 x guc_state_capture_group_t output 625 * followed by 3 x guc_state_capture_t lists. The latter is how the register 626 * dumps are split across different register types (where the '3' are global vs class 627 * vs instance). Finally, let's multiply the whole thing by 3x (just so we are 628 * not limited to just 1 round of data in a worst case full register dump log) 629 * 630 * NOTE: intel_guc_log that allocates the log buffer would round this size up to 631 * a power of two. 632 */ 633 634 for_each_engine(engine, gt, id) { 635 worst_min_size += sizeof(struct guc_state_capture_group_header_t) + 636 (3 * sizeof(struct guc_state_capture_header_t)); 637 638 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp)) 639 num_regs += tmp; 640 641 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 642 engine->class, &tmp)) { 643 num_regs += tmp; 644 } 645 if (!intel_guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 646 engine->class, &tmp)) { 647 num_regs += tmp; 648 } 649 } 650 651 worst_min_size += (num_regs * sizeof(struct guc_mmio_reg)); 652 653 return (worst_min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER); 654 } 655 656 /* 657 * KMD Init time flows: 658 * -------------------- 659 * --> alloc A: GuC input capture regs lists (registered to GuC via ADS). 660 * intel_guc_ads acquires the register lists by calling 661 * intel_guc_capture_list_size and intel_guc_capture_list_get 'n' times, 662 * where n = 1 for global-reg-list + 663 * num_engine_classes for class-reg-list + 664 * num_engine_classes for instance-reg-list 665 * (since all instances of the same engine-class type 666 * have an identical engine-instance register-list). 667 * ADS module also calls separately for PF vs VF. 668 * 669 * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param)) 670 * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small) 671 * Note2: 'x 3' to hold multiple capture groups 672 * 673 * GUC Runtime notify capture: 674 * -------------------------- 675 * --> G2H STATE_CAPTURE_NOTIFICATION 676 * L--> intel_guc_capture_process 677 * L--> Loop through B (head..tail) and for each engine instance's 678 * err-state-captured register-list we find, we alloc 'C': 679 * --> alloc C: A capture-output-node structure that includes misc capture info along 680 * with 3 register list dumps (global, engine-class and engine-instance) 681 * This node is created from a pre-allocated list of blank nodes in 682 * guc->capture->cachelist and populated with the error-capture 683 * data from GuC and then it's added into guc->capture->outlist linked 684 * list. This list is used for matchup and printout by i915_gpu_coredump 685 * and err_print_gt, (when user invokes the error capture sysfs). 686 * 687 * GUC --> notify context reset: 688 * ----------------------------- 689 * --> G2H CONTEXT RESET 690 * L--> guc_handle_context_reset --> i915_capture_error_state 691 * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> gt_record_engines 692 * --> capture_engine(..IS_GUC_CAPTURE) 693 * L--> intel_guc_capture_get_matching_node is where 694 * detach C from internal linked list and add it into 695 * intel_engine_coredump struct (if the context and 696 * engine of the event notification matches a node 697 * in the link list). 698 * 699 * User Sysfs / Debugfs 700 * -------------------- 701 * --> i915_gpu_coredump_copy_to_buffer-> 702 * L--> err_print_to_sgl --> err_print_gt 703 * L--> error_print_guc_captures 704 * L--> intel_guc_capture_print_node prints the 705 * register lists values of the attached node 706 * on the error-engine-dump being reported. 707 * L--> i915_reset_error_state ... -->__i915_gpu_coredump_free 708 * L--> ... cleanup_gt --> 709 * L--> intel_guc_capture_free_node returns the 710 * capture-output-node back to the internal 711 * cachelist for reuse. 712 * 713 */ 714 715 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf) 716 { 717 if (buf->wr >= buf->rd) 718 return (buf->wr - buf->rd); 719 return (buf->size - buf->rd) + buf->wr; 720 } 721 722 static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf) 723 { 724 if (buf->rd > buf->wr) 725 return (buf->size - buf->rd); 726 return (buf->wr - buf->rd); 727 } 728 729 /* 730 * GuC's error-capture output is a ring buffer populated in a byte-stream fashion: 731 * 732 * The GuC Log buffer region for error-capture is managed like a ring buffer. 733 * The GuC firmware dumps error capture logs into this ring in a byte-stream flow. 734 * Additionally, as per the current and foreseeable future, all packed error- 735 * capture output structures are dword aligned. 736 * 737 * That said, if the GuC firmware is in the midst of writing a structure that is larger 738 * than one dword but the tail end of the err-capture buffer-region has lesser space left, 739 * we would need to extract that structure one dword at a time straddled across the end, 740 * onto the start of the ring. 741 * 742 * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this 743 * function would typically do a straight-up memcpy from the ring contents and will only 744 * call this helper if their structure-extraction is straddling across the end of the 745 * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease 746 * scalability for future expansion of output data types without requiring a redesign 747 * of the flow controls. 748 */ 749 static int 750 guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 751 u32 *dw) 752 { 753 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 754 int tries = 2; 755 int avail = 0; 756 u32 *src_data; 757 758 if (!guc_capture_buf_cnt(buf)) 759 return 0; 760 761 while (tries--) { 762 avail = guc_capture_buf_cnt_to_end(buf); 763 if (avail >= sizeof(u32)) { 764 src_data = (u32 *)(buf->data + buf->rd); 765 *dw = *src_data; 766 buf->rd += 4; 767 return 4; 768 } 769 if (avail) 770 drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n"); 771 buf->rd = 0; 772 } 773 774 return 0; 775 } 776 777 static bool 778 guc_capture_data_extracted(struct __guc_capture_bufstate *b, 779 int size, void *dest) 780 { 781 if (guc_capture_buf_cnt_to_end(b) >= size) { 782 memcpy(dest, (b->data + b->rd), size); 783 b->rd += size; 784 return true; 785 } 786 return false; 787 } 788 789 static int 790 guc_capture_log_get_group_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 791 struct guc_state_capture_group_header_t *ghdr) 792 { 793 int read = 0; 794 int fullsize = sizeof(struct guc_state_capture_group_header_t); 795 796 if (fullsize > guc_capture_buf_cnt(buf)) 797 return -1; 798 799 if (guc_capture_data_extracted(buf, fullsize, (void *)ghdr)) 800 return 0; 801 802 read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner); 803 read += guc_capture_log_remove_dw(guc, buf, &ghdr->info); 804 if (read != fullsize) 805 return -1; 806 807 return 0; 808 } 809 810 static int 811 guc_capture_log_get_data_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 812 struct guc_state_capture_header_t *hdr) 813 { 814 int read = 0; 815 int fullsize = sizeof(struct guc_state_capture_header_t); 816 817 if (fullsize > guc_capture_buf_cnt(buf)) 818 return -1; 819 820 if (guc_capture_data_extracted(buf, fullsize, (void *)hdr)) 821 return 0; 822 823 read += guc_capture_log_remove_dw(guc, buf, &hdr->owner); 824 read += guc_capture_log_remove_dw(guc, buf, &hdr->info); 825 read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca); 826 read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id); 827 read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios); 828 if (read != fullsize) 829 return -1; 830 831 return 0; 832 } 833 834 static int 835 guc_capture_log_get_register(struct intel_guc *guc, struct __guc_capture_bufstate *buf, 836 struct guc_mmio_reg *reg) 837 { 838 int read = 0; 839 int fullsize = sizeof(struct guc_mmio_reg); 840 841 if (fullsize > guc_capture_buf_cnt(buf)) 842 return -1; 843 844 if (guc_capture_data_extracted(buf, fullsize, (void *)reg)) 845 return 0; 846 847 read += guc_capture_log_remove_dw(guc, buf, ®->offset); 848 read += guc_capture_log_remove_dw(guc, buf, ®->value); 849 read += guc_capture_log_remove_dw(guc, buf, ®->flags); 850 read += guc_capture_log_remove_dw(guc, buf, ®->mask); 851 if (read != fullsize) 852 return -1; 853 854 return 0; 855 } 856 857 static void 858 guc_capture_delete_one_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 859 { 860 int i; 861 862 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 863 kfree(node->reginfo[i].regs); 864 list_del(&node->link); 865 kfree(node); 866 } 867 868 static void 869 guc_capture_delete_prealloc_nodes(struct intel_guc *guc) 870 { 871 struct __guc_capture_parsed_output *n, *ntmp; 872 873 /* 874 * NOTE: At the end of driver operation, we must assume that we 875 * have prealloc nodes in both the cachelist as well as outlist 876 * if unclaimed error capture events occurred prior to shutdown. 877 */ 878 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) 879 guc_capture_delete_one_node(guc, n); 880 881 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) 882 guc_capture_delete_one_node(guc, n); 883 } 884 885 static void 886 guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node, 887 struct list_head *list) 888 { 889 list_add_tail(&node->link, list); 890 } 891 892 static void 893 guc_capture_add_node_to_outlist(struct intel_guc_state_capture *gc, 894 struct __guc_capture_parsed_output *node) 895 { 896 guc_capture_add_node_to_list(node, &gc->outlist); 897 } 898 899 static void 900 guc_capture_add_node_to_cachelist(struct intel_guc_state_capture *gc, 901 struct __guc_capture_parsed_output *node) 902 { 903 guc_capture_add_node_to_list(node, &gc->cachelist); 904 } 905 906 static void 907 guc_capture_init_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node) 908 { 909 struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX]; 910 int i; 911 912 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 913 tmp[i] = node->reginfo[i].regs; 914 memset(tmp[i], 0, sizeof(struct guc_mmio_reg) * 915 guc->capture->max_mmio_per_node); 916 } 917 memset(node, 0, sizeof(*node)); 918 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) 919 node->reginfo[i].regs = tmp[i]; 920 921 INIT_LIST_HEAD(&node->link); 922 } 923 924 static struct __guc_capture_parsed_output * 925 guc_capture_get_prealloc_node(struct intel_guc *guc) 926 { 927 struct __guc_capture_parsed_output *found = NULL; 928 929 if (!list_empty(&guc->capture->cachelist)) { 930 struct __guc_capture_parsed_output *n, *ntmp; 931 932 /* get first avail node from the cache list */ 933 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link) { 934 found = n; 935 list_del(&n->link); 936 break; 937 } 938 } else { 939 struct __guc_capture_parsed_output *n, *ntmp; 940 941 /* traverse down and steal back the oldest node already allocated */ 942 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 943 found = n; 944 } 945 if (found) 946 list_del(&found->link); 947 } 948 if (found) 949 guc_capture_init_node(guc, found); 950 951 return found; 952 } 953 954 static struct __guc_capture_parsed_output * 955 guc_capture_alloc_one_node(struct intel_guc *guc) 956 { 957 struct __guc_capture_parsed_output *new; 958 int i; 959 960 new = kzalloc(sizeof(*new), GFP_KERNEL); 961 if (!new) 962 return NULL; 963 964 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 965 new->reginfo[i].regs = kcalloc(guc->capture->max_mmio_per_node, 966 sizeof(struct guc_mmio_reg), GFP_KERNEL); 967 if (!new->reginfo[i].regs) { 968 while (i) 969 kfree(new->reginfo[--i].regs); 970 kfree(new); 971 return NULL; 972 } 973 } 974 guc_capture_init_node(guc, new); 975 976 return new; 977 } 978 979 static struct __guc_capture_parsed_output * 980 guc_capture_clone_node(struct intel_guc *guc, struct __guc_capture_parsed_output *original, 981 u32 keep_reglist_mask) 982 { 983 struct __guc_capture_parsed_output *new; 984 int i; 985 986 new = guc_capture_get_prealloc_node(guc); 987 if (!new) 988 return NULL; 989 if (!original) 990 return new; 991 992 new->is_partial = original->is_partial; 993 994 /* copy reg-lists that we want to clone */ 995 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 996 if (keep_reglist_mask & BIT(i)) { 997 GEM_BUG_ON(original->reginfo[i].num_regs > 998 guc->capture->max_mmio_per_node); 999 1000 memcpy(new->reginfo[i].regs, original->reginfo[i].regs, 1001 original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg)); 1002 1003 new->reginfo[i].num_regs = original->reginfo[i].num_regs; 1004 new->reginfo[i].vfid = original->reginfo[i].vfid; 1005 1006 if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) { 1007 new->eng_class = original->eng_class; 1008 } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1009 new->eng_inst = original->eng_inst; 1010 new->guc_id = original->guc_id; 1011 new->lrca = original->lrca; 1012 } 1013 } 1014 } 1015 1016 return new; 1017 } 1018 1019 static void 1020 __guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1021 { 1022 struct __guc_capture_parsed_output *node = NULL; 1023 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1024 int i; 1025 1026 for (i = 0; i < PREALLOC_NODES_MAX_COUNT; ++i) { 1027 node = guc_capture_alloc_one_node(guc); 1028 if (!node) { 1029 drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n"); 1030 /* dont free the priors, use what we got and cleanup at shutdown */ 1031 return; 1032 } 1033 guc_capture_add_node_to_cachelist(guc->capture, node); 1034 } 1035 } 1036 1037 static int 1038 guc_get_max_reglist_count(struct intel_guc *guc) 1039 { 1040 int i, j, k, tmp, maxregcount = 0; 1041 1042 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1043 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1044 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1045 if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0) 1046 continue; 1047 1048 tmp = guc_cap_list_num_regs(guc->capture, i, j, k); 1049 if (tmp > maxregcount) 1050 maxregcount = tmp; 1051 } 1052 } 1053 } 1054 if (!maxregcount) 1055 maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS; 1056 1057 return maxregcount; 1058 } 1059 1060 static void 1061 guc_capture_create_prealloc_nodes(struct intel_guc *guc) 1062 { 1063 /* skip if we've already done the pre-alloc */ 1064 if (guc->capture->max_mmio_per_node) 1065 return; 1066 1067 guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc); 1068 __guc_capture_create_prealloc_nodes(guc); 1069 } 1070 1071 static int 1072 guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf) 1073 { 1074 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1075 struct guc_state_capture_group_header_t ghdr = {0}; 1076 struct guc_state_capture_header_t hdr = {0}; 1077 struct __guc_capture_parsed_output *node = NULL; 1078 struct guc_mmio_reg *regs = NULL; 1079 int i, numlists, numregs, ret = 0; 1080 enum guc_capture_type datatype; 1081 struct guc_mmio_reg tmp; 1082 bool is_partial = false; 1083 1084 i = guc_capture_buf_cnt(buf); 1085 if (!i) 1086 return -ENODATA; 1087 if (i % sizeof(u32)) { 1088 drm_warn(&i915->drm, "GuC Capture new entries unaligned\n"); 1089 ret = -EIO; 1090 goto bailout; 1091 } 1092 1093 /* first get the capture group header */ 1094 if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) { 1095 ret = -EIO; 1096 goto bailout; 1097 } 1098 /* 1099 * we would typically expect a layout as below where n would be expected to be 1100 * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine 1101 * instances being reset together. 1102 * ____________________________________________ 1103 * | Capture Group | 1104 * | ________________________________________ | 1105 * | | Capture Group Header: | | 1106 * | | - num_captures = 5 | | 1107 * | |______________________________________| | 1108 * | ________________________________________ | 1109 * | | Capture1: | | 1110 * | | Hdr: GLOBAL, numregs=a | | 1111 * | | ____________________________________ | | 1112 * | | | Reglist | | | 1113 * | | | - reg1, reg2, ... rega | | | 1114 * | | |__________________________________| | | 1115 * | |______________________________________| | 1116 * | ________________________________________ | 1117 * | | Capture2: | | 1118 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| | 1119 * | | ____________________________________ | | 1120 * | | | Reglist | | | 1121 * | | | - reg1, reg2, ... regb | | | 1122 * | | |__________________________________| | | 1123 * | |______________________________________| | 1124 * | ________________________________________ | 1125 * | | Capture3: | | 1126 * | | Hdr: INSTANCE=RCS, numregs=c | | 1127 * | | ____________________________________ | | 1128 * | | | Reglist | | | 1129 * | | | - reg1, reg2, ... regc | | | 1130 * | | |__________________________________| | | 1131 * | |______________________________________| | 1132 * | ________________________________________ | 1133 * | | Capture4: | | 1134 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| | 1135 * | | ____________________________________ | | 1136 * | | | Reglist | | | 1137 * | | | - reg1, reg2, ... regd | | | 1138 * | | |__________________________________| | | 1139 * | |______________________________________| | 1140 * | ________________________________________ | 1141 * | | Capture5: | | 1142 * | | Hdr: INSTANCE=CCS0, numregs=e | | 1143 * | | ____________________________________ | | 1144 * | | | Reglist | | | 1145 * | | | - reg1, reg2, ... rege | | | 1146 * | | |__________________________________| | | 1147 * | |______________________________________| | 1148 * |__________________________________________| 1149 */ 1150 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info); 1151 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info); 1152 1153 while (numlists--) { 1154 if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) { 1155 ret = -EIO; 1156 break; 1157 } 1158 1159 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info); 1160 if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) { 1161 /* unknown capture type - skip over to next capture set */ 1162 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1163 while (numregs--) { 1164 if (guc_capture_log_get_register(guc, buf, &tmp)) { 1165 ret = -EIO; 1166 break; 1167 } 1168 } 1169 continue; 1170 } else if (node) { 1171 /* 1172 * Based on the current capture type and what we have so far, 1173 * decide if we should add the current node into the internal 1174 * linked list for match-up when i915_gpu_coredump calls later 1175 * (and alloc a blank node for the next set of reglists) 1176 * or continue with the same node or clone the current node 1177 * but only retain the global or class registers (such as the 1178 * case of dependent engine resets). 1179 */ 1180 if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) { 1181 guc_capture_add_node_to_outlist(guc->capture, node); 1182 node = NULL; 1183 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS && 1184 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) { 1185 /* Add to list, clone node and duplicate global list */ 1186 guc_capture_add_node_to_outlist(guc->capture, node); 1187 node = guc_capture_clone_node(guc, node, 1188 GCAP_PARSED_REGLIST_INDEX_GLOBAL); 1189 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE && 1190 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) { 1191 /* Add to list, clone node and duplicate global + class lists */ 1192 guc_capture_add_node_to_outlist(guc->capture, node); 1193 node = guc_capture_clone_node(guc, node, 1194 (GCAP_PARSED_REGLIST_INDEX_GLOBAL | 1195 GCAP_PARSED_REGLIST_INDEX_ENGCLASS)); 1196 } 1197 } 1198 1199 if (!node) { 1200 node = guc_capture_get_prealloc_node(guc); 1201 if (!node) { 1202 ret = -ENOMEM; 1203 break; 1204 } 1205 if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL) 1206 drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n", 1207 datatype); 1208 } 1209 node->is_partial = is_partial; 1210 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner); 1211 switch (datatype) { 1212 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1213 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1214 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info); 1215 node->lrca = hdr.lrca; 1216 node->guc_id = hdr.guc_id; 1217 break; 1218 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1219 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info); 1220 break; 1221 default: 1222 break; 1223 } 1224 1225 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios); 1226 if (numregs > guc->capture->max_mmio_per_node) { 1227 drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n"); 1228 numregs = guc->capture->max_mmio_per_node; 1229 } 1230 node->reginfo[datatype].num_regs = numregs; 1231 regs = node->reginfo[datatype].regs; 1232 i = 0; 1233 while (numregs--) { 1234 if (guc_capture_log_get_register(guc, buf, ®s[i++])) { 1235 ret = -EIO; 1236 break; 1237 } 1238 } 1239 } 1240 1241 bailout: 1242 if (node) { 1243 /* If we have data, add to linked list for match-up when i915_gpu_coredump calls */ 1244 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1245 if (node->reginfo[i].regs) { 1246 guc_capture_add_node_to_outlist(guc->capture, node); 1247 node = NULL; 1248 break; 1249 } 1250 } 1251 if (node) /* else return it back to cache list */ 1252 guc_capture_add_node_to_cachelist(guc->capture, node); 1253 } 1254 return ret; 1255 } 1256 1257 static int __guc_capture_flushlog_complete(struct intel_guc *guc) 1258 { 1259 u32 action[] = { 1260 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE, 1261 GUC_CAPTURE_LOG_BUFFER 1262 }; 1263 1264 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 1265 } 1266 1267 static void __guc_capture_process_output(struct intel_guc *guc) 1268 { 1269 unsigned int buffer_size, read_offset, write_offset, full_count; 1270 struct intel_uc *uc = container_of(guc, typeof(*uc), guc); 1271 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 1272 struct guc_log_buffer_state log_buf_state_local; 1273 struct guc_log_buffer_state *log_buf_state; 1274 struct __guc_capture_bufstate buf; 1275 void *src_data = NULL; 1276 bool new_overflow; 1277 int ret; 1278 1279 log_buf_state = guc->log.buf_addr + 1280 (sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER); 1281 src_data = guc->log.buf_addr + intel_guc_get_log_buffer_offset(GUC_CAPTURE_LOG_BUFFER); 1282 1283 /* 1284 * Make a copy of the state structure, inside GuC log buffer 1285 * (which is uncached mapped), on the stack to avoid reading 1286 * from it multiple times. 1287 */ 1288 memcpy(&log_buf_state_local, log_buf_state, sizeof(struct guc_log_buffer_state)); 1289 buffer_size = intel_guc_get_log_buffer_size(GUC_CAPTURE_LOG_BUFFER); 1290 read_offset = log_buf_state_local.read_ptr; 1291 write_offset = log_buf_state_local.sampled_write_ptr; 1292 full_count = log_buf_state_local.buffer_full_cnt; 1293 1294 /* Bookkeeping stuff */ 1295 guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file; 1296 new_overflow = intel_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER, 1297 full_count); 1298 1299 /* Now copy the actual logs. */ 1300 if (unlikely(new_overflow)) { 1301 /* copy the whole buffer in case of overflow */ 1302 read_offset = 0; 1303 write_offset = buffer_size; 1304 } else if (unlikely((read_offset > buffer_size) || 1305 (write_offset > buffer_size))) { 1306 drm_err(&i915->drm, "invalid GuC log capture buffer state!\n"); 1307 /* copy whole buffer as offsets are unreliable */ 1308 read_offset = 0; 1309 write_offset = buffer_size; 1310 } 1311 1312 buf.size = buffer_size; 1313 buf.rd = read_offset; 1314 buf.wr = write_offset; 1315 buf.data = src_data; 1316 1317 if (!uc->reset_in_progress) { 1318 do { 1319 ret = guc_capture_extract_reglists(guc, &buf); 1320 } while (ret >= 0); 1321 } 1322 1323 /* Update the state of log buffer err-cap state */ 1324 log_buf_state->read_ptr = write_offset; 1325 log_buf_state->flush_to_file = 0; 1326 __guc_capture_flushlog_complete(guc); 1327 } 1328 1329 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1330 1331 static const char * 1332 guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type, 1333 u32 class, u32 id, u32 offset, u32 *is_ext) 1334 { 1335 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; 1336 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; 1337 const struct __guc_mmio_reg_descr_group *match; 1338 struct __guc_mmio_reg_descr_group *matchext; 1339 int j; 1340 1341 *is_ext = 0; 1342 if (!reglists) 1343 return NULL; 1344 1345 match = guc_capture_get_one_list(reglists, owner, type, id); 1346 if (!match) 1347 return NULL; 1348 1349 for (j = 0; j < match->num_regs; ++j) { 1350 if (offset == match->list[j].reg.reg) 1351 return match->list[j].regname; 1352 } 1353 if (extlists) { 1354 matchext = guc_capture_get_one_ext_list(extlists, owner, type, id); 1355 if (!matchext) 1356 return NULL; 1357 for (j = 0; j < matchext->num_regs; ++j) { 1358 if (offset == matchext->extlist[j].reg.reg) { 1359 *is_ext = 1; 1360 return matchext->extlist[j].regname; 1361 } 1362 } 1363 } 1364 1365 return NULL; 1366 } 1367 1368 #ifdef CONFIG_DRM_I915_DEBUG_GUC 1369 #define __out(a, ...) \ 1370 do { \ 1371 drm_warn((&(a)->i915->drm), __VA_ARGS__); \ 1372 i915_error_printf((a), __VA_ARGS__); \ 1373 } while (0) 1374 #else 1375 #define __out(a, ...) \ 1376 i915_error_printf(a, __VA_ARGS__) 1377 #endif 1378 1379 #define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng) \ 1380 do { \ 1381 __out(ebuf, " i915-Eng-Name: %s command stream\n", \ 1382 (eng)->name); \ 1383 __out(ebuf, " i915-Eng-Inst-Class: 0x%02x\n", (eng)->class); \ 1384 __out(ebuf, " i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance); \ 1385 __out(ebuf, " i915-Eng-LogicalMask: 0x%08x\n", \ 1386 (eng)->logical_mask); \ 1387 } while (0) 1388 1389 #define GCAP_PRINT_GUC_INST_INFO(ebuf, node) \ 1390 do { \ 1391 __out(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n", \ 1392 (node)->eng_inst); \ 1393 __out(ebuf, " GuC-Context-Id: 0x%08x\n", (node)->guc_id); \ 1394 __out(ebuf, " LRCA: 0x%08x\n", (node)->lrca); \ 1395 } while (0) 1396 1397 int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf, 1398 const struct intel_engine_coredump *ee) 1399 { 1400 const char *grptype[GUC_STATE_CAPTURE_GROUP_TYPE_MAX] = { 1401 "full-capture", 1402 "partial-capture" 1403 }; 1404 const char *datatype[GUC_CAPTURE_LIST_TYPE_MAX] = { 1405 "Global", 1406 "Engine-Class", 1407 "Engine-Instance" 1408 }; 1409 struct intel_guc_state_capture *cap; 1410 struct __guc_capture_parsed_output *node; 1411 struct intel_engine_cs *eng; 1412 struct guc_mmio_reg *regs; 1413 struct intel_guc *guc; 1414 const char *str; 1415 int numregs, i, j; 1416 u32 is_ext; 1417 1418 if (!ebuf || !ee) 1419 return -EINVAL; 1420 cap = ee->capture; 1421 if (!cap || !ee->engine) 1422 return -ENODEV; 1423 1424 guc = &ee->engine->gt->uc.guc; 1425 1426 __out(ebuf, "global --- GuC Error Capture on %s command stream:\n", 1427 ee->engine->name); 1428 1429 node = ee->guc_capture_node; 1430 if (!node) { 1431 __out(ebuf, " No matching ee-node\n"); 1432 return 0; 1433 } 1434 1435 __out(ebuf, "Coverage: %s\n", grptype[node->is_partial]); 1436 1437 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) { 1438 __out(ebuf, " RegListType: %s\n", 1439 datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]); 1440 __out(ebuf, " Owner-Id: %d\n", node->reginfo[i].vfid); 1441 1442 switch (i) { 1443 case GUC_CAPTURE_LIST_TYPE_GLOBAL: 1444 default: 1445 break; 1446 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS: 1447 __out(ebuf, " GuC-Eng-Class: %d\n", node->eng_class); 1448 __out(ebuf, " i915-Eng-Class: %d\n", 1449 guc_class_to_engine_class(node->eng_class)); 1450 break; 1451 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE: 1452 eng = intel_guc_lookup_engine(guc, node->eng_class, node->eng_inst); 1453 if (eng) 1454 GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng); 1455 else 1456 __out(ebuf, " i915-Eng-Lookup Fail!\n"); 1457 GCAP_PRINT_GUC_INST_INFO(ebuf, node); 1458 break; 1459 } 1460 1461 numregs = node->reginfo[i].num_regs; 1462 __out(ebuf, " NumRegs: %d\n", numregs); 1463 j = 0; 1464 while (numregs--) { 1465 regs = node->reginfo[i].regs; 1466 str = guc_capture_reg_to_str(guc, GUC_CAPTURE_LIST_INDEX_PF, i, 1467 node->eng_class, 0, regs[j].offset, &is_ext); 1468 if (!str) 1469 __out(ebuf, " REG-0x%08x", regs[j].offset); 1470 else 1471 __out(ebuf, " %s", str); 1472 if (is_ext) 1473 __out(ebuf, "[%ld][%ld]", 1474 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags), 1475 FIELD_GET(GUC_REGSET_STEERING_INSTANCE, regs[j].flags)); 1476 __out(ebuf, ": 0x%08x\n", regs[j].value); 1477 ++j; 1478 } 1479 } 1480 return 0; 1481 } 1482 1483 #endif //CONFIG_DRM_I915_CAPTURE_ERROR 1484 1485 void intel_guc_capture_free_node(struct intel_engine_coredump *ee) 1486 { 1487 if (!ee || !ee->guc_capture_node) 1488 return; 1489 1490 guc_capture_add_node_to_cachelist(ee->capture, ee->guc_capture_node); 1491 ee->capture = NULL; 1492 ee->guc_capture_node = NULL; 1493 } 1494 1495 void intel_guc_capture_get_matching_node(struct intel_gt *gt, 1496 struct intel_engine_coredump *ee, 1497 struct intel_context *ce) 1498 { 1499 struct __guc_capture_parsed_output *n, *ntmp; 1500 struct drm_i915_private *i915; 1501 struct intel_guc *guc; 1502 1503 if (!gt || !ee || !ce) 1504 return; 1505 1506 i915 = gt->i915; 1507 guc = >->uc.guc; 1508 if (!guc->capture) 1509 return; 1510 1511 GEM_BUG_ON(ee->guc_capture_node); 1512 /* 1513 * Look for a matching GuC reported error capture node from 1514 * the internal output link-list based on lrca, guc-id and engine 1515 * identification. 1516 */ 1517 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link) { 1518 if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id) && 1519 n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id) && 1520 n->guc_id && n->guc_id == ce->guc_id.id && 1521 (n->lrca & CTX_GTT_ADDRESS_MASK) && (n->lrca & CTX_GTT_ADDRESS_MASK) == 1522 (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK)) { 1523 list_del(&n->link); 1524 ee->guc_capture_node = n; 1525 ee->capture = guc->capture; 1526 return; 1527 } 1528 } 1529 drm_dbg(&i915->drm, "GuC capture can't match ee to node\n"); 1530 } 1531 1532 void intel_guc_capture_process(struct intel_guc *guc) 1533 { 1534 if (guc->capture) 1535 __guc_capture_process_output(guc); 1536 } 1537 1538 static void 1539 guc_capture_free_ads_cache(struct intel_guc_state_capture *gc) 1540 { 1541 int i, j, k; 1542 struct __guc_capture_ads_cache *cache; 1543 1544 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) { 1545 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) { 1546 for (k = 0; k < GUC_MAX_ENGINE_CLASSES; ++k) { 1547 cache = &gc->ads_cache[i][j][k]; 1548 if (cache->is_valid) 1549 kfree(cache->ptr); 1550 } 1551 } 1552 } 1553 kfree(gc->ads_null_cache); 1554 } 1555 1556 void intel_guc_capture_destroy(struct intel_guc *guc) 1557 { 1558 if (!guc->capture) 1559 return; 1560 1561 guc_capture_free_ads_cache(guc->capture); 1562 1563 guc_capture_delete_prealloc_nodes(guc); 1564 1565 guc_capture_free_extlists(guc->capture->extlists); 1566 kfree(guc->capture->extlists); 1567 1568 kfree(guc->capture); 1569 guc->capture = NULL; 1570 } 1571 1572 int intel_guc_capture_init(struct intel_guc *guc) 1573 { 1574 guc->capture = kzalloc(sizeof(*guc->capture), GFP_KERNEL); 1575 if (!guc->capture) 1576 return -ENOMEM; 1577 1578 guc->capture->reglists = guc_capture_get_device_reglist(guc); 1579 1580 INIT_LIST_HEAD(&guc->capture->outlist); 1581 INIT_LIST_HEAD(&guc->capture->cachelist); 1582 1583 return 0; 1584 } 1585