1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #include <linux/bsearch.h> 7 8 #include "gt/intel_engine_regs.h" 9 #include "gt/intel_gt.h" 10 #include "gt/intel_gt_regs.h" 11 #include "gt/intel_lrc.h" 12 #include "gt/shmem_utils.h" 13 #include "intel_guc_ads.h" 14 #include "intel_guc_fwif.h" 15 #include "intel_uc.h" 16 #include "i915_drv.h" 17 18 /* 19 * The Additional Data Struct (ADS) has pointers for different buffers used by 20 * the GuC. One single gem object contains the ADS struct itself (guc_ads) and 21 * all the extra buffers indirectly linked via the ADS struct's entries. 22 * 23 * Layout of the ADS blob allocated for the GuC: 24 * 25 * +---------------------------------------+ <== base 26 * | guc_ads | 27 * +---------------------------------------+ 28 * | guc_policies | 29 * +---------------------------------------+ 30 * | guc_gt_system_info | 31 * +---------------------------------------+ 32 * | guc_engine_usage | 33 * +---------------------------------------+ <== static 34 * | guc_mmio_reg[countA] (engine 0.0) | 35 * | guc_mmio_reg[countB] (engine 0.1) | 36 * | guc_mmio_reg[countC] (engine 1.0) | 37 * | ... | 38 * +---------------------------------------+ <== dynamic 39 * | padding | 40 * +---------------------------------------+ <== 4K aligned 41 * | golden contexts | 42 * +---------------------------------------+ 43 * | padding | 44 * +---------------------------------------+ <== 4K aligned 45 * | capture lists | 46 * +---------------------------------------+ 47 * | padding | 48 * +---------------------------------------+ <== 4K aligned 49 * | private data | 50 * +---------------------------------------+ 51 * | padding | 52 * +---------------------------------------+ <== 4K aligned 53 */ 54 struct __guc_ads_blob { 55 struct guc_ads ads; 56 struct guc_policies policies; 57 struct guc_gt_system_info system_info; 58 struct guc_engine_usage engine_usage; 59 /* From here on, location is dynamic! Refer to above diagram. */ 60 struct guc_mmio_reg regset[]; 61 } __packed; 62 63 #define ads_blob_read(guc_, field_) \ 64 iosys_map_rd_field(&(guc_)->ads_map, 0, struct __guc_ads_blob, field_) 65 66 #define ads_blob_write(guc_, field_, val_) \ 67 iosys_map_wr_field(&(guc_)->ads_map, 0, struct __guc_ads_blob, \ 68 field_, val_) 69 70 #define info_map_write(map_, field_, val_) \ 71 iosys_map_wr_field(map_, 0, struct guc_gt_system_info, field_, val_) 72 73 #define info_map_read(map_, field_) \ 74 iosys_map_rd_field(map_, 0, struct guc_gt_system_info, field_) 75 76 static u32 guc_ads_regset_size(struct intel_guc *guc) 77 { 78 GEM_BUG_ON(!guc->ads_regset_size); 79 return guc->ads_regset_size; 80 } 81 82 static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc) 83 { 84 return PAGE_ALIGN(guc->ads_golden_ctxt_size); 85 } 86 87 static u32 guc_ads_capture_size(struct intel_guc *guc) 88 { 89 /* FIXME: Allocate a proper capture list */ 90 return PAGE_ALIGN(PAGE_SIZE); 91 } 92 93 static u32 guc_ads_private_data_size(struct intel_guc *guc) 94 { 95 return PAGE_ALIGN(guc->fw.private_data_size); 96 } 97 98 static u32 guc_ads_regset_offset(struct intel_guc *guc) 99 { 100 return offsetof(struct __guc_ads_blob, regset); 101 } 102 103 static u32 guc_ads_golden_ctxt_offset(struct intel_guc *guc) 104 { 105 u32 offset; 106 107 offset = guc_ads_regset_offset(guc) + 108 guc_ads_regset_size(guc); 109 110 return PAGE_ALIGN(offset); 111 } 112 113 static u32 guc_ads_capture_offset(struct intel_guc *guc) 114 { 115 u32 offset; 116 117 offset = guc_ads_golden_ctxt_offset(guc) + 118 guc_ads_golden_ctxt_size(guc); 119 120 return PAGE_ALIGN(offset); 121 } 122 123 static u32 guc_ads_private_data_offset(struct intel_guc *guc) 124 { 125 u32 offset; 126 127 offset = guc_ads_capture_offset(guc) + 128 guc_ads_capture_size(guc); 129 130 return PAGE_ALIGN(offset); 131 } 132 133 static u32 guc_ads_blob_size(struct intel_guc *guc) 134 { 135 return guc_ads_private_data_offset(guc) + 136 guc_ads_private_data_size(guc); 137 } 138 139 static void guc_policies_init(struct intel_guc *guc) 140 { 141 struct intel_gt *gt = guc_to_gt(guc); 142 struct drm_i915_private *i915 = gt->i915; 143 u32 global_flags = 0; 144 145 ads_blob_write(guc, policies.dpc_promote_time, 146 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); 147 ads_blob_write(guc, policies.max_num_work_items, 148 GLOBAL_POLICY_MAX_NUM_WI); 149 150 if (i915->params.reset < 2) 151 global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 152 153 ads_blob_write(guc, policies.global_flags, global_flags); 154 ads_blob_write(guc, policies.is_valid, 1); 155 } 156 157 void intel_guc_ads_print_policy_info(struct intel_guc *guc, 158 struct drm_printer *dp) 159 { 160 if (unlikely(iosys_map_is_null(&guc->ads_map))) 161 return; 162 163 drm_printf(dp, "Global scheduling policies:\n"); 164 drm_printf(dp, " DPC promote time = %u\n", 165 ads_blob_read(guc, policies.dpc_promote_time)); 166 drm_printf(dp, " Max num work items = %u\n", 167 ads_blob_read(guc, policies.max_num_work_items)); 168 drm_printf(dp, " Flags = %u\n", 169 ads_blob_read(guc, policies.global_flags)); 170 } 171 172 static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset) 173 { 174 u32 action[] = { 175 INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE, 176 policy_offset 177 }; 178 179 return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true); 180 } 181 182 int intel_guc_global_policies_update(struct intel_guc *guc) 183 { 184 struct intel_gt *gt = guc_to_gt(guc); 185 u32 scheduler_policies; 186 intel_wakeref_t wakeref; 187 int ret; 188 189 if (iosys_map_is_null(&guc->ads_map)) 190 return -EOPNOTSUPP; 191 192 scheduler_policies = ads_blob_read(guc, ads.scheduler_policies); 193 GEM_BUG_ON(!scheduler_policies); 194 195 guc_policies_init(guc); 196 197 if (!intel_guc_is_ready(guc)) 198 return 0; 199 200 with_intel_runtime_pm(>->i915->runtime_pm, wakeref) 201 ret = guc_action_policies_update(guc, scheduler_policies); 202 203 return ret; 204 } 205 206 static void guc_mapping_table_init(struct intel_gt *gt, 207 struct iosys_map *info_map) 208 { 209 unsigned int i, j; 210 struct intel_engine_cs *engine; 211 enum intel_engine_id id; 212 213 /* Table must be set to invalid values for entries not used */ 214 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) 215 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) 216 info_map_write(info_map, mapping_table[i][j], 217 GUC_MAX_INSTANCES_PER_CLASS); 218 219 for_each_engine(engine, gt, id) { 220 u8 guc_class = engine_class_to_guc_class(engine->class); 221 222 info_map_write(info_map, mapping_table[guc_class][ilog2(engine->logical_mask)], 223 engine->instance); 224 } 225 } 226 227 /* 228 * The save/restore register list must be pre-calculated to a temporary 229 * buffer before it can be copied inside the ADS. 230 */ 231 struct temp_regset { 232 /* 233 * ptr to the section of the storage for the engine currently being 234 * worked on 235 */ 236 struct guc_mmio_reg *registers; 237 /* ptr to the base of the allocated storage for all engines */ 238 struct guc_mmio_reg *storage; 239 u32 storage_used; 240 u32 storage_max; 241 }; 242 243 static int guc_mmio_reg_cmp(const void *a, const void *b) 244 { 245 const struct guc_mmio_reg *ra = a; 246 const struct guc_mmio_reg *rb = b; 247 248 return (int)ra->offset - (int)rb->offset; 249 } 250 251 static struct guc_mmio_reg * __must_check 252 __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg) 253 { 254 u32 pos = regset->storage_used; 255 struct guc_mmio_reg *slot; 256 257 if (pos >= regset->storage_max) { 258 size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE); 259 struct guc_mmio_reg *r = krealloc(regset->storage, 260 size, GFP_KERNEL); 261 if (!r) { 262 WARN_ONCE(1, "Incomplete regset list: can't add register (%d)\n", 263 -ENOMEM); 264 return ERR_PTR(-ENOMEM); 265 } 266 267 regset->registers = r + (regset->registers - regset->storage); 268 regset->storage = r; 269 regset->storage_max = size / sizeof(*slot); 270 } 271 272 slot = ®set->storage[pos]; 273 regset->storage_used++; 274 *slot = *reg; 275 276 return slot; 277 } 278 279 static long __must_check guc_mmio_reg_add(struct temp_regset *regset, 280 u32 offset, u32 flags) 281 { 282 u32 count = regset->storage_used - (regset->registers - regset->storage); 283 struct guc_mmio_reg reg = { 284 .offset = offset, 285 .flags = flags, 286 }; 287 struct guc_mmio_reg *slot; 288 289 /* 290 * The mmio list is built using separate lists within the driver. 291 * It's possible that at some point we may attempt to add the same 292 * register more than once. Do not consider this an error; silently 293 * move on if the register is already in the list. 294 */ 295 if (bsearch(®, regset->registers, count, 296 sizeof(reg), guc_mmio_reg_cmp)) 297 return 0; 298 299 slot = __mmio_reg_add(regset, ®); 300 if (IS_ERR(slot)) 301 return PTR_ERR(slot); 302 303 while (slot-- > regset->registers) { 304 GEM_BUG_ON(slot[0].offset == slot[1].offset); 305 if (slot[1].offset > slot[0].offset) 306 break; 307 308 swap(slot[1], slot[0]); 309 } 310 311 return 0; 312 } 313 314 #define GUC_MMIO_REG_ADD(regset, reg, masked) \ 315 guc_mmio_reg_add(regset, \ 316 i915_mmio_reg_offset((reg)), \ 317 (masked) ? GUC_REGSET_MASKED : 0) 318 319 static int guc_mmio_regset_init(struct temp_regset *regset, 320 struct intel_engine_cs *engine) 321 { 322 const u32 base = engine->mmio_base; 323 struct i915_wa_list *wal = &engine->wa_list; 324 struct i915_wa *wa; 325 unsigned int i; 326 int ret = 0; 327 328 /* 329 * Each engine's registers point to a new start relative to 330 * storage 331 */ 332 regset->registers = regset->storage + regset->storage_used; 333 334 ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true); 335 ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false); 336 ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false); 337 338 if (engine->class == RENDER_CLASS && 339 CCS_MASK(engine->gt)) 340 ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true); 341 342 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 343 ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg); 344 345 /* Be extra paranoid and include all whitelist registers. */ 346 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) 347 ret |= GUC_MMIO_REG_ADD(regset, 348 RING_FORCE_TO_NONPRIV(base, i), 349 false); 350 351 /* add in local MOCS registers */ 352 for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++) 353 ret |= GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false); 354 355 return ret ? -1 : 0; 356 } 357 358 static long guc_mmio_reg_state_create(struct intel_guc *guc) 359 { 360 struct intel_gt *gt = guc_to_gt(guc); 361 struct intel_engine_cs *engine; 362 enum intel_engine_id id; 363 struct temp_regset temp_set = {}; 364 long total = 0; 365 long ret; 366 367 for_each_engine(engine, gt, id) { 368 u32 used = temp_set.storage_used; 369 370 ret = guc_mmio_regset_init(&temp_set, engine); 371 if (ret < 0) 372 goto fail_regset_init; 373 374 guc->ads_regset_count[id] = temp_set.storage_used - used; 375 total += guc->ads_regset_count[id]; 376 } 377 378 guc->ads_regset = temp_set.storage; 379 380 drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n", 381 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10); 382 383 return total * sizeof(struct guc_mmio_reg); 384 385 fail_regset_init: 386 kfree(temp_set.storage); 387 return ret; 388 } 389 390 static void guc_mmio_reg_state_init(struct intel_guc *guc) 391 { 392 struct intel_gt *gt = guc_to_gt(guc); 393 struct intel_engine_cs *engine; 394 enum intel_engine_id id; 395 u32 addr_ggtt, offset; 396 397 offset = guc_ads_regset_offset(guc); 398 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 399 400 iosys_map_memcpy_to(&guc->ads_map, offset, guc->ads_regset, 401 guc->ads_regset_size); 402 403 for_each_engine(engine, gt, id) { 404 u32 count = guc->ads_regset_count[id]; 405 u8 guc_class; 406 407 /* Class index is checked in class converter */ 408 GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS); 409 410 guc_class = engine_class_to_guc_class(engine->class); 411 412 if (!count) { 413 ads_blob_write(guc, 414 ads.reg_state_list[guc_class][engine->instance].address, 415 0); 416 ads_blob_write(guc, 417 ads.reg_state_list[guc_class][engine->instance].count, 418 0); 419 continue; 420 } 421 422 ads_blob_write(guc, 423 ads.reg_state_list[guc_class][engine->instance].address, 424 addr_ggtt); 425 ads_blob_write(guc, 426 ads.reg_state_list[guc_class][engine->instance].count, 427 count); 428 429 addr_ggtt += count * sizeof(struct guc_mmio_reg); 430 } 431 } 432 433 static void fill_engine_enable_masks(struct intel_gt *gt, 434 struct iosys_map *info_map) 435 { 436 info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1); 437 info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); 438 info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1); 439 info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); 440 info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt)); 441 } 442 443 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) 444 #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE) 445 static int guc_prep_golden_context(struct intel_guc *guc) 446 { 447 struct intel_gt *gt = guc_to_gt(guc); 448 u32 addr_ggtt, offset; 449 u32 total_size = 0, alloc_size, real_size; 450 u8 engine_class, guc_class; 451 struct guc_gt_system_info local_info; 452 struct iosys_map info_map; 453 454 /* 455 * Reserve the memory for the golden contexts and point GuC at it but 456 * leave it empty for now. The context data will be filled in later 457 * once there is something available to put there. 458 * 459 * Note that the HWSP and ring context are not included. 460 * 461 * Note also that the storage must be pinned in the GGTT, so that the 462 * address won't change after GuC has been told where to find it. The 463 * GuC will also validate that the LRC base + size fall within the 464 * allowed GGTT range. 465 */ 466 if (!iosys_map_is_null(&guc->ads_map)) { 467 offset = guc_ads_golden_ctxt_offset(guc); 468 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 469 info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map, 470 offsetof(struct __guc_ads_blob, system_info)); 471 } else { 472 memset(&local_info, 0, sizeof(local_info)); 473 iosys_map_set_vaddr(&info_map, &local_info); 474 fill_engine_enable_masks(gt, &info_map); 475 } 476 477 for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { 478 if (engine_class == OTHER_CLASS) 479 continue; 480 481 guc_class = engine_class_to_guc_class(engine_class); 482 483 if (!info_map_read(&info_map, engine_enabled_masks[guc_class])) 484 continue; 485 486 real_size = intel_engine_context_size(gt, engine_class); 487 alloc_size = PAGE_ALIGN(real_size); 488 total_size += alloc_size; 489 490 if (iosys_map_is_null(&guc->ads_map)) 491 continue; 492 493 /* 494 * This interface is slightly confusing. We need to pass the 495 * base address of the full golden context and the size of just 496 * the engine state, which is the section of the context image 497 * that starts after the execlists context. This is required to 498 * allow the GuC to restore just the engine state when a 499 * watchdog reset occurs. 500 * We calculate the engine state size by removing the size of 501 * what comes before it in the context image (which is identical 502 * on all engines). 503 */ 504 ads_blob_write(guc, ads.eng_state_size[guc_class], 505 real_size - LRC_SKIP_SIZE); 506 ads_blob_write(guc, ads.golden_context_lrca[guc_class], 507 addr_ggtt); 508 509 addr_ggtt += alloc_size; 510 } 511 512 /* Make sure current size matches what we calculated previously */ 513 if (guc->ads_golden_ctxt_size) 514 GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); 515 516 return total_size; 517 } 518 519 static struct intel_engine_cs *find_engine_state(struct intel_gt *gt, u8 engine_class) 520 { 521 struct intel_engine_cs *engine; 522 enum intel_engine_id id; 523 524 for_each_engine(engine, gt, id) { 525 if (engine->class != engine_class) 526 continue; 527 528 if (!engine->default_state) 529 continue; 530 531 return engine; 532 } 533 534 return NULL; 535 } 536 537 static void guc_init_golden_context(struct intel_guc *guc) 538 { 539 struct intel_engine_cs *engine; 540 struct intel_gt *gt = guc_to_gt(guc); 541 unsigned long offset; 542 u32 addr_ggtt, total_size = 0, alloc_size, real_size; 543 u8 engine_class, guc_class; 544 545 if (!intel_uc_uses_guc_submission(>->uc)) 546 return; 547 548 GEM_BUG_ON(iosys_map_is_null(&guc->ads_map)); 549 550 /* 551 * Go back and fill in the golden context data now that it is 552 * available. 553 */ 554 offset = guc_ads_golden_ctxt_offset(guc); 555 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 556 557 for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { 558 if (engine_class == OTHER_CLASS) 559 continue; 560 561 guc_class = engine_class_to_guc_class(engine_class); 562 if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class])) 563 continue; 564 565 real_size = intel_engine_context_size(gt, engine_class); 566 alloc_size = PAGE_ALIGN(real_size); 567 total_size += alloc_size; 568 569 engine = find_engine_state(gt, engine_class); 570 if (!engine) { 571 drm_err(>->i915->drm, "No engine state recorded for class %d!\n", 572 engine_class); 573 ads_blob_write(guc, ads.eng_state_size[guc_class], 0); 574 ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0); 575 continue; 576 } 577 578 GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) != 579 real_size - LRC_SKIP_SIZE); 580 GEM_BUG_ON(ads_blob_read(guc, ads.golden_context_lrca[guc_class]) != addr_ggtt); 581 582 addr_ggtt += alloc_size; 583 584 shmem_read_to_iosys_map(engine->default_state, 0, &guc->ads_map, 585 offset, real_size); 586 offset += alloc_size; 587 } 588 589 GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); 590 } 591 592 static void guc_capture_list_init(struct intel_guc *guc) 593 { 594 int i, j; 595 u32 addr_ggtt, offset; 596 597 offset = guc_ads_capture_offset(guc); 598 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 599 600 /* FIXME: Populate a proper capture list */ 601 602 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { 603 for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { 604 ads_blob_write(guc, ads.capture_instance[i][j], addr_ggtt); 605 ads_blob_write(guc, ads.capture_class[i][j], addr_ggtt); 606 } 607 608 ads_blob_write(guc, ads.capture_global[i], addr_ggtt); 609 } 610 } 611 612 static void __guc_ads_init(struct intel_guc *guc) 613 { 614 struct intel_gt *gt = guc_to_gt(guc); 615 struct drm_i915_private *i915 = gt->i915; 616 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map, 617 offsetof(struct __guc_ads_blob, system_info)); 618 u32 base; 619 620 /* GuC scheduling policies */ 621 guc_policies_init(guc); 622 623 /* System info */ 624 fill_engine_enable_masks(gt, &info_map); 625 626 ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED], 627 hweight8(gt->info.sseu.slice_mask)); 628 ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK], 629 gt->info.vdbox_sfc_access); 630 631 if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) { 632 u32 distdbreg = intel_uncore_read(gt->uncore, 633 GEN12_DIST_DBS_POPULATED); 634 ads_blob_write(guc, 635 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], 636 ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) 637 & GEN12_DOORBELLS_PER_SQIDI) + 1); 638 } 639 640 /* Golden contexts for re-initialising after a watchdog reset */ 641 guc_prep_golden_context(guc); 642 643 guc_mapping_table_init(guc_to_gt(guc), &info_map); 644 645 base = intel_guc_ggtt_offset(guc, guc->ads_vma); 646 647 /* Capture list for hang debug */ 648 guc_capture_list_init(guc); 649 650 /* ADS */ 651 ads_blob_write(guc, ads.scheduler_policies, base + 652 offsetof(struct __guc_ads_blob, policies)); 653 ads_blob_write(guc, ads.gt_system_info, base + 654 offsetof(struct __guc_ads_blob, system_info)); 655 656 /* MMIO save/restore list */ 657 guc_mmio_reg_state_init(guc); 658 659 /* Private Data */ 660 ads_blob_write(guc, ads.private_data, base + 661 guc_ads_private_data_offset(guc)); 662 663 i915_gem_object_flush_map(guc->ads_vma->obj); 664 } 665 666 /** 667 * intel_guc_ads_create() - allocates and initializes GuC ADS. 668 * @guc: intel_guc struct 669 * 670 * GuC needs memory block (Additional Data Struct), where it will store 671 * some data. Allocate and initialize such memory block for GuC use. 672 */ 673 int intel_guc_ads_create(struct intel_guc *guc) 674 { 675 void *ads_blob; 676 u32 size; 677 int ret; 678 679 GEM_BUG_ON(guc->ads_vma); 680 681 /* 682 * Create reg state size dynamically on system memory to be copied to 683 * the final ads blob on gt init/reset 684 */ 685 ret = guc_mmio_reg_state_create(guc); 686 if (ret < 0) 687 return ret; 688 guc->ads_regset_size = ret; 689 690 /* Likewise the golden contexts: */ 691 ret = guc_prep_golden_context(guc); 692 if (ret < 0) 693 return ret; 694 guc->ads_golden_ctxt_size = ret; 695 696 /* Now the total size can be determined: */ 697 size = guc_ads_blob_size(guc); 698 699 ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma, 700 &ads_blob); 701 if (ret) 702 return ret; 703 704 if (i915_gem_object_is_lmem(guc->ads_vma->obj)) 705 iosys_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)ads_blob); 706 else 707 iosys_map_set_vaddr(&guc->ads_map, ads_blob); 708 709 __guc_ads_init(guc); 710 711 return 0; 712 } 713 714 void intel_guc_ads_init_late(struct intel_guc *guc) 715 { 716 /* 717 * The golden context setup requires the saved engine state from 718 * __engines_record_defaults(). However, that requires engines to be 719 * operational which means the ADS must already have been configured. 720 * Fortunately, the golden context state is not needed until a hang 721 * occurs, so it can be filled in during this late init phase. 722 */ 723 guc_init_golden_context(guc); 724 } 725 726 void intel_guc_ads_destroy(struct intel_guc *guc) 727 { 728 i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); 729 iosys_map_clear(&guc->ads_map); 730 kfree(guc->ads_regset); 731 } 732 733 static void guc_ads_private_data_reset(struct intel_guc *guc) 734 { 735 u32 size; 736 737 size = guc_ads_private_data_size(guc); 738 if (!size) 739 return; 740 741 iosys_map_memset(&guc->ads_map, guc_ads_private_data_offset(guc), 742 0, size); 743 } 744 745 /** 746 * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse 747 * @guc: intel_guc struct 748 * 749 * GuC stores some data in ADS, which might be stale after a reset. 750 * Reinitialize whole ADS in case any part of it was corrupted during 751 * previous GuC run. 752 */ 753 void intel_guc_ads_reset(struct intel_guc *guc) 754 { 755 if (!guc->ads_vma) 756 return; 757 758 __guc_ads_init(guc); 759 760 guc_ads_private_data_reset(guc); 761 } 762 763 u32 intel_guc_engine_usage_offset(struct intel_guc *guc) 764 { 765 return intel_guc_ggtt_offset(guc, guc->ads_vma) + 766 offsetof(struct __guc_ads_blob, engine_usage); 767 } 768 769 struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine) 770 { 771 struct intel_guc *guc = &engine->gt->uc.guc; 772 u8 guc_class = engine_class_to_guc_class(engine->class); 773 size_t offset = offsetof(struct __guc_ads_blob, 774 engine_usage.engines[guc_class][ilog2(engine->logical_mask)]); 775 776 return IOSYS_MAP_INIT_OFFSET(&guc->ads_map, offset); 777 } 778