1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #include <linux/bsearch.h> 7 8 #include "gt/intel_engine_regs.h" 9 #include "gt/intel_gt.h" 10 #include "gt/intel_gt_mcr.h" 11 #include "gt/intel_gt_regs.h" 12 #include "gt/intel_lrc.h" 13 #include "gt/shmem_utils.h" 14 #include "intel_guc_ads.h" 15 #include "intel_guc_capture.h" 16 #include "intel_guc_fwif.h" 17 #include "intel_uc.h" 18 #include "i915_drv.h" 19 20 /* 21 * The Additional Data Struct (ADS) has pointers for different buffers used by 22 * the GuC. One single gem object contains the ADS struct itself (guc_ads) and 23 * all the extra buffers indirectly linked via the ADS struct's entries. 24 * 25 * Layout of the ADS blob allocated for the GuC: 26 * 27 * +---------------------------------------+ <== base 28 * | guc_ads | 29 * +---------------------------------------+ 30 * | guc_policies | 31 * +---------------------------------------+ 32 * | guc_gt_system_info | 33 * +---------------------------------------+ 34 * | guc_engine_usage | 35 * +---------------------------------------+ <== static 36 * | guc_mmio_reg[countA] (engine 0.0) | 37 * | guc_mmio_reg[countB] (engine 0.1) | 38 * | guc_mmio_reg[countC] (engine 1.0) | 39 * | ... | 40 * +---------------------------------------+ <== dynamic 41 * | padding | 42 * +---------------------------------------+ <== 4K aligned 43 * | golden contexts | 44 * +---------------------------------------+ 45 * | padding | 46 * +---------------------------------------+ <== 4K aligned 47 * | capture lists | 48 * +---------------------------------------+ 49 * | padding | 50 * +---------------------------------------+ <== 4K aligned 51 * | private data | 52 * +---------------------------------------+ 53 * | padding | 54 * +---------------------------------------+ <== 4K aligned 55 */ 56 struct __guc_ads_blob { 57 struct guc_ads ads; 58 struct guc_policies policies; 59 struct guc_gt_system_info system_info; 60 struct guc_engine_usage engine_usage; 61 /* From here on, location is dynamic! Refer to above diagram. */ 62 struct guc_mmio_reg regset[]; 63 } __packed; 64 65 #define ads_blob_read(guc_, field_) \ 66 iosys_map_rd_field(&(guc_)->ads_map, 0, struct __guc_ads_blob, field_) 67 68 #define ads_blob_write(guc_, field_, val_) \ 69 iosys_map_wr_field(&(guc_)->ads_map, 0, struct __guc_ads_blob, \ 70 field_, val_) 71 72 #define info_map_write(map_, field_, val_) \ 73 iosys_map_wr_field(map_, 0, struct guc_gt_system_info, field_, val_) 74 75 #define info_map_read(map_, field_) \ 76 iosys_map_rd_field(map_, 0, struct guc_gt_system_info, field_) 77 78 static u32 guc_ads_regset_size(struct intel_guc *guc) 79 { 80 GEM_BUG_ON(!guc->ads_regset_size); 81 return guc->ads_regset_size; 82 } 83 84 static u32 guc_ads_golden_ctxt_size(struct intel_guc *guc) 85 { 86 return PAGE_ALIGN(guc->ads_golden_ctxt_size); 87 } 88 89 static u32 guc_ads_capture_size(struct intel_guc *guc) 90 { 91 return PAGE_ALIGN(guc->ads_capture_size); 92 } 93 94 static u32 guc_ads_private_data_size(struct intel_guc *guc) 95 { 96 return PAGE_ALIGN(guc->fw.private_data_size); 97 } 98 99 static u32 guc_ads_regset_offset(struct intel_guc *guc) 100 { 101 return offsetof(struct __guc_ads_blob, regset); 102 } 103 104 static u32 guc_ads_golden_ctxt_offset(struct intel_guc *guc) 105 { 106 u32 offset; 107 108 offset = guc_ads_regset_offset(guc) + 109 guc_ads_regset_size(guc); 110 111 return PAGE_ALIGN(offset); 112 } 113 114 static u32 guc_ads_capture_offset(struct intel_guc *guc) 115 { 116 u32 offset; 117 118 offset = guc_ads_golden_ctxt_offset(guc) + 119 guc_ads_golden_ctxt_size(guc); 120 121 return PAGE_ALIGN(offset); 122 } 123 124 static u32 guc_ads_private_data_offset(struct intel_guc *guc) 125 { 126 u32 offset; 127 128 offset = guc_ads_capture_offset(guc) + 129 guc_ads_capture_size(guc); 130 131 return PAGE_ALIGN(offset); 132 } 133 134 static u32 guc_ads_blob_size(struct intel_guc *guc) 135 { 136 return guc_ads_private_data_offset(guc) + 137 guc_ads_private_data_size(guc); 138 } 139 140 static void guc_policies_init(struct intel_guc *guc) 141 { 142 struct intel_gt *gt = guc_to_gt(guc); 143 struct drm_i915_private *i915 = gt->i915; 144 u32 global_flags = 0; 145 146 ads_blob_write(guc, policies.dpc_promote_time, 147 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); 148 ads_blob_write(guc, policies.max_num_work_items, 149 GLOBAL_POLICY_MAX_NUM_WI); 150 151 if (i915->params.reset < 2) 152 global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 153 154 ads_blob_write(guc, policies.global_flags, global_flags); 155 ads_blob_write(guc, policies.is_valid, 1); 156 } 157 158 void intel_guc_ads_print_policy_info(struct intel_guc *guc, 159 struct drm_printer *dp) 160 { 161 if (unlikely(iosys_map_is_null(&guc->ads_map))) 162 return; 163 164 drm_printf(dp, "Global scheduling policies:\n"); 165 drm_printf(dp, " DPC promote time = %u\n", 166 ads_blob_read(guc, policies.dpc_promote_time)); 167 drm_printf(dp, " Max num work items = %u\n", 168 ads_blob_read(guc, policies.max_num_work_items)); 169 drm_printf(dp, " Flags = %u\n", 170 ads_blob_read(guc, policies.global_flags)); 171 } 172 173 static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset) 174 { 175 u32 action[] = { 176 INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE, 177 policy_offset 178 }; 179 180 return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true); 181 } 182 183 int intel_guc_global_policies_update(struct intel_guc *guc) 184 { 185 struct intel_gt *gt = guc_to_gt(guc); 186 u32 scheduler_policies; 187 intel_wakeref_t wakeref; 188 int ret; 189 190 if (iosys_map_is_null(&guc->ads_map)) 191 return -EOPNOTSUPP; 192 193 scheduler_policies = ads_blob_read(guc, ads.scheduler_policies); 194 GEM_BUG_ON(!scheduler_policies); 195 196 guc_policies_init(guc); 197 198 if (!intel_guc_is_ready(guc)) 199 return 0; 200 201 with_intel_runtime_pm(>->i915->runtime_pm, wakeref) 202 ret = guc_action_policies_update(guc, scheduler_policies); 203 204 return ret; 205 } 206 207 static void guc_mapping_table_init(struct intel_gt *gt, 208 struct iosys_map *info_map) 209 { 210 unsigned int i, j; 211 struct intel_engine_cs *engine; 212 enum intel_engine_id id; 213 214 /* Table must be set to invalid values for entries not used */ 215 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) 216 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) 217 info_map_write(info_map, mapping_table[i][j], 218 GUC_MAX_INSTANCES_PER_CLASS); 219 220 for_each_engine(engine, gt, id) { 221 u8 guc_class = engine_class_to_guc_class(engine->class); 222 223 info_map_write(info_map, mapping_table[guc_class][ilog2(engine->logical_mask)], 224 engine->instance); 225 } 226 } 227 228 /* 229 * The save/restore register list must be pre-calculated to a temporary 230 * buffer before it can be copied inside the ADS. 231 */ 232 struct temp_regset { 233 /* 234 * ptr to the section of the storage for the engine currently being 235 * worked on 236 */ 237 struct guc_mmio_reg *registers; 238 /* ptr to the base of the allocated storage for all engines */ 239 struct guc_mmio_reg *storage; 240 u32 storage_used; 241 u32 storage_max; 242 }; 243 244 static int guc_mmio_reg_cmp(const void *a, const void *b) 245 { 246 const struct guc_mmio_reg *ra = a; 247 const struct guc_mmio_reg *rb = b; 248 249 return (int)ra->offset - (int)rb->offset; 250 } 251 252 static struct guc_mmio_reg * __must_check 253 __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg) 254 { 255 u32 pos = regset->storage_used; 256 struct guc_mmio_reg *slot; 257 258 if (pos >= regset->storage_max) { 259 size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE); 260 struct guc_mmio_reg *r = krealloc(regset->storage, 261 size, GFP_KERNEL); 262 if (!r) { 263 WARN_ONCE(1, "Incomplete regset list: can't add register (%d)\n", 264 -ENOMEM); 265 return ERR_PTR(-ENOMEM); 266 } 267 268 regset->registers = r + (regset->registers - regset->storage); 269 regset->storage = r; 270 regset->storage_max = size / sizeof(*slot); 271 } 272 273 slot = ®set->storage[pos]; 274 regset->storage_used++; 275 *slot = *reg; 276 277 return slot; 278 } 279 280 #define GUC_REGSET_STEERING(group, instance) ( \ 281 FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \ 282 FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \ 283 GUC_REGSET_NEEDS_STEERING \ 284 ) 285 286 static long __must_check guc_mmio_reg_add(struct intel_gt *gt, 287 struct temp_regset *regset, 288 i915_reg_t reg, u32 flags) 289 { 290 u32 count = regset->storage_used - (regset->registers - regset->storage); 291 u32 offset = i915_mmio_reg_offset(reg); 292 struct guc_mmio_reg entry = { 293 .offset = offset, 294 .flags = flags, 295 }; 296 struct guc_mmio_reg *slot; 297 u8 group, inst; 298 299 /* 300 * The mmio list is built using separate lists within the driver. 301 * It's possible that at some point we may attempt to add the same 302 * register more than once. Do not consider this an error; silently 303 * move on if the register is already in the list. 304 */ 305 if (bsearch(&entry, regset->registers, count, 306 sizeof(entry), guc_mmio_reg_cmp)) 307 return 0; 308 309 /* 310 * The GuC doesn't have a default steering, so we need to explicitly 311 * steer all registers that need steering. However, we do not keep track 312 * of all the steering ranges, only of those that have a chance of using 313 * a non-default steering from the i915 pov. Instead of adding such 314 * tracking, it is easier to just program the default steering for all 315 * regs that don't need a non-default one. 316 */ 317 intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst); 318 entry.flags |= GUC_REGSET_STEERING(group, inst); 319 320 slot = __mmio_reg_add(regset, &entry); 321 if (IS_ERR(slot)) 322 return PTR_ERR(slot); 323 324 while (slot-- > regset->registers) { 325 GEM_BUG_ON(slot[0].offset == slot[1].offset); 326 if (slot[1].offset > slot[0].offset) 327 break; 328 329 swap(slot[1], slot[0]); 330 } 331 332 return 0; 333 } 334 335 #define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \ 336 guc_mmio_reg_add(gt, \ 337 regset, \ 338 (reg), \ 339 (masked) ? GUC_REGSET_MASKED : 0) 340 341 static int guc_mmio_regset_init(struct temp_regset *regset, 342 struct intel_engine_cs *engine) 343 { 344 struct intel_gt *gt = engine->gt; 345 const u32 base = engine->mmio_base; 346 struct i915_wa_list *wal = &engine->wa_list; 347 struct i915_wa *wa; 348 unsigned int i; 349 int ret = 0; 350 351 /* 352 * Each engine's registers point to a new start relative to 353 * storage 354 */ 355 regset->registers = regset->storage + regset->storage_used; 356 357 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_MODE_GEN7(base), true); 358 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false); 359 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false); 360 361 if ((engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) && 362 CCS_MASK(engine->gt)) 363 ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true); 364 365 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 366 ret |= GUC_MMIO_REG_ADD(gt, regset, wa->reg, wa->masked_reg); 367 368 /* Be extra paranoid and include all whitelist registers. */ 369 for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) 370 ret |= GUC_MMIO_REG_ADD(gt, regset, 371 RING_FORCE_TO_NONPRIV(base, i), 372 false); 373 374 /* add in local MOCS registers */ 375 for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++) 376 ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false); 377 378 return ret ? -1 : 0; 379 } 380 381 static long guc_mmio_reg_state_create(struct intel_guc *guc) 382 { 383 struct intel_gt *gt = guc_to_gt(guc); 384 struct intel_engine_cs *engine; 385 enum intel_engine_id id; 386 struct temp_regset temp_set = {}; 387 long total = 0; 388 long ret; 389 390 for_each_engine(engine, gt, id) { 391 u32 used = temp_set.storage_used; 392 393 ret = guc_mmio_regset_init(&temp_set, engine); 394 if (ret < 0) 395 goto fail_regset_init; 396 397 guc->ads_regset_count[id] = temp_set.storage_used - used; 398 total += guc->ads_regset_count[id]; 399 } 400 401 guc->ads_regset = temp_set.storage; 402 403 drm_dbg(&guc_to_gt(guc)->i915->drm, "Used %zu KB for temporary ADS regset\n", 404 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10); 405 406 return total * sizeof(struct guc_mmio_reg); 407 408 fail_regset_init: 409 kfree(temp_set.storage); 410 return ret; 411 } 412 413 static void guc_mmio_reg_state_init(struct intel_guc *guc) 414 { 415 struct intel_gt *gt = guc_to_gt(guc); 416 struct intel_engine_cs *engine; 417 enum intel_engine_id id; 418 u32 addr_ggtt, offset; 419 420 offset = guc_ads_regset_offset(guc); 421 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 422 423 iosys_map_memcpy_to(&guc->ads_map, offset, guc->ads_regset, 424 guc->ads_regset_size); 425 426 for_each_engine(engine, gt, id) { 427 u32 count = guc->ads_regset_count[id]; 428 u8 guc_class; 429 430 /* Class index is checked in class converter */ 431 GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS); 432 433 guc_class = engine_class_to_guc_class(engine->class); 434 435 if (!count) { 436 ads_blob_write(guc, 437 ads.reg_state_list[guc_class][engine->instance].address, 438 0); 439 ads_blob_write(guc, 440 ads.reg_state_list[guc_class][engine->instance].count, 441 0); 442 continue; 443 } 444 445 ads_blob_write(guc, 446 ads.reg_state_list[guc_class][engine->instance].address, 447 addr_ggtt); 448 ads_blob_write(guc, 449 ads.reg_state_list[guc_class][engine->instance].count, 450 count); 451 452 addr_ggtt += count * sizeof(struct guc_mmio_reg); 453 } 454 } 455 456 static void fill_engine_enable_masks(struct intel_gt *gt, 457 struct iosys_map *info_map) 458 { 459 info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], RCS_MASK(gt)); 460 info_map_write(info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], CCS_MASK(gt)); 461 info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], BCS_MASK(gt)); 462 info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS], VDBOX_MASK(gt)); 463 info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], VEBOX_MASK(gt)); 464 } 465 466 #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) 467 #define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE) 468 static int guc_prep_golden_context(struct intel_guc *guc) 469 { 470 struct intel_gt *gt = guc_to_gt(guc); 471 u32 addr_ggtt, offset; 472 u32 total_size = 0, alloc_size, real_size; 473 u8 engine_class, guc_class; 474 struct guc_gt_system_info local_info; 475 struct iosys_map info_map; 476 477 /* 478 * Reserve the memory for the golden contexts and point GuC at it but 479 * leave it empty for now. The context data will be filled in later 480 * once there is something available to put there. 481 * 482 * Note that the HWSP and ring context are not included. 483 * 484 * Note also that the storage must be pinned in the GGTT, so that the 485 * address won't change after GuC has been told where to find it. The 486 * GuC will also validate that the LRC base + size fall within the 487 * allowed GGTT range. 488 */ 489 if (!iosys_map_is_null(&guc->ads_map)) { 490 offset = guc_ads_golden_ctxt_offset(guc); 491 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 492 info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map, 493 offsetof(struct __guc_ads_blob, system_info)); 494 } else { 495 memset(&local_info, 0, sizeof(local_info)); 496 iosys_map_set_vaddr(&info_map, &local_info); 497 fill_engine_enable_masks(gt, &info_map); 498 } 499 500 for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { 501 if (engine_class == OTHER_CLASS) 502 continue; 503 504 guc_class = engine_class_to_guc_class(engine_class); 505 506 if (!info_map_read(&info_map, engine_enabled_masks[guc_class])) 507 continue; 508 509 real_size = intel_engine_context_size(gt, engine_class); 510 alloc_size = PAGE_ALIGN(real_size); 511 total_size += alloc_size; 512 513 if (iosys_map_is_null(&guc->ads_map)) 514 continue; 515 516 /* 517 * This interface is slightly confusing. We need to pass the 518 * base address of the full golden context and the size of just 519 * the engine state, which is the section of the context image 520 * that starts after the execlists context. This is required to 521 * allow the GuC to restore just the engine state when a 522 * watchdog reset occurs. 523 * We calculate the engine state size by removing the size of 524 * what comes before it in the context image (which is identical 525 * on all engines). 526 */ 527 ads_blob_write(guc, ads.eng_state_size[guc_class], 528 real_size - LRC_SKIP_SIZE); 529 ads_blob_write(guc, ads.golden_context_lrca[guc_class], 530 addr_ggtt); 531 532 addr_ggtt += alloc_size; 533 } 534 535 /* Make sure current size matches what we calculated previously */ 536 if (guc->ads_golden_ctxt_size) 537 GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); 538 539 return total_size; 540 } 541 542 static struct intel_engine_cs *find_engine_state(struct intel_gt *gt, u8 engine_class) 543 { 544 struct intel_engine_cs *engine; 545 enum intel_engine_id id; 546 547 for_each_engine(engine, gt, id) { 548 if (engine->class != engine_class) 549 continue; 550 551 if (!engine->default_state) 552 continue; 553 554 return engine; 555 } 556 557 return NULL; 558 } 559 560 static void guc_init_golden_context(struct intel_guc *guc) 561 { 562 struct intel_engine_cs *engine; 563 struct intel_gt *gt = guc_to_gt(guc); 564 unsigned long offset; 565 u32 addr_ggtt, total_size = 0, alloc_size, real_size; 566 u8 engine_class, guc_class; 567 568 if (!intel_uc_uses_guc_submission(>->uc)) 569 return; 570 571 GEM_BUG_ON(iosys_map_is_null(&guc->ads_map)); 572 573 /* 574 * Go back and fill in the golden context data now that it is 575 * available. 576 */ 577 offset = guc_ads_golden_ctxt_offset(guc); 578 addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset; 579 580 for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { 581 if (engine_class == OTHER_CLASS) 582 continue; 583 584 guc_class = engine_class_to_guc_class(engine_class); 585 if (!ads_blob_read(guc, system_info.engine_enabled_masks[guc_class])) 586 continue; 587 588 real_size = intel_engine_context_size(gt, engine_class); 589 alloc_size = PAGE_ALIGN(real_size); 590 total_size += alloc_size; 591 592 engine = find_engine_state(gt, engine_class); 593 if (!engine) { 594 drm_err(>->i915->drm, "No engine state recorded for class %d!\n", 595 engine_class); 596 ads_blob_write(guc, ads.eng_state_size[guc_class], 0); 597 ads_blob_write(guc, ads.golden_context_lrca[guc_class], 0); 598 continue; 599 } 600 601 GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) != 602 real_size - LRC_SKIP_SIZE); 603 GEM_BUG_ON(ads_blob_read(guc, ads.golden_context_lrca[guc_class]) != addr_ggtt); 604 605 addr_ggtt += alloc_size; 606 607 shmem_read_to_iosys_map(engine->default_state, 0, &guc->ads_map, 608 offset, real_size); 609 offset += alloc_size; 610 } 611 612 GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); 613 } 614 615 static int 616 guc_capture_prep_lists(struct intel_guc *guc) 617 { 618 struct intel_gt *gt = guc_to_gt(guc); 619 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 620 u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; 621 struct guc_gt_system_info local_info; 622 struct iosys_map info_map; 623 bool ads_is_mapped; 624 size_t size = 0; 625 void *ptr; 626 int i, j; 627 628 ads_is_mapped = !iosys_map_is_null(&guc->ads_map); 629 if (ads_is_mapped) { 630 capture_offset = guc_ads_capture_offset(guc); 631 ads_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma); 632 info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map, 633 offsetof(struct __guc_ads_blob, system_info)); 634 } else { 635 memset(&local_info, 0, sizeof(local_info)); 636 iosys_map_set_vaddr(&info_map, &local_info); 637 fill_engine_enable_masks(gt, &info_map); 638 } 639 640 /* first, set aside the first page for a capture_list with zero descriptors */ 641 total_size = PAGE_SIZE; 642 if (ads_is_mapped) { 643 if (!intel_guc_capture_getnullheader(guc, &ptr, &size)) 644 iosys_map_memcpy_to(&guc->ads_map, capture_offset, ptr, size); 645 null_ggtt = ads_ggtt + capture_offset; 646 capture_offset += PAGE_SIZE; 647 } 648 649 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { 650 for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { 651 652 /* null list if we dont have said engine or list */ 653 if (!info_map_read(&info_map, engine_enabled_masks[j])) { 654 if (ads_is_mapped) { 655 ads_blob_write(guc, ads.capture_class[i][j], null_ggtt); 656 ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt); 657 } 658 continue; 659 } 660 if (intel_guc_capture_getlistsize(guc, i, 661 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 662 j, &size)) { 663 if (ads_is_mapped) 664 ads_blob_write(guc, ads.capture_class[i][j], null_ggtt); 665 goto engine_instance_list; 666 } 667 total_size += size; 668 if (ads_is_mapped) { 669 if (total_size > guc->ads_capture_size || 670 intel_guc_capture_getlist(guc, i, 671 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 672 j, &ptr)) { 673 ads_blob_write(guc, ads.capture_class[i][j], null_ggtt); 674 continue; 675 } 676 ads_blob_write(guc, ads.capture_class[i][j], ads_ggtt + 677 capture_offset); 678 iosys_map_memcpy_to(&guc->ads_map, capture_offset, ptr, size); 679 capture_offset += size; 680 } 681 engine_instance_list: 682 if (intel_guc_capture_getlistsize(guc, i, 683 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 684 j, &size)) { 685 if (ads_is_mapped) 686 ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt); 687 continue; 688 } 689 total_size += size; 690 if (ads_is_mapped) { 691 if (total_size > guc->ads_capture_size || 692 intel_guc_capture_getlist(guc, i, 693 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 694 j, &ptr)) { 695 ads_blob_write(guc, ads.capture_instance[i][j], null_ggtt); 696 continue; 697 } 698 ads_blob_write(guc, ads.capture_instance[i][j], ads_ggtt + 699 capture_offset); 700 iosys_map_memcpy_to(&guc->ads_map, capture_offset, ptr, size); 701 capture_offset += size; 702 } 703 } 704 if (intel_guc_capture_getlistsize(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &size)) { 705 if (ads_is_mapped) 706 ads_blob_write(guc, ads.capture_global[i], null_ggtt); 707 continue; 708 } 709 total_size += size; 710 if (ads_is_mapped) { 711 if (total_size > guc->ads_capture_size || 712 intel_guc_capture_getlist(guc, i, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, 713 &ptr)) { 714 ads_blob_write(guc, ads.capture_global[i], null_ggtt); 715 continue; 716 } 717 ads_blob_write(guc, ads.capture_global[i], ads_ggtt + capture_offset); 718 iosys_map_memcpy_to(&guc->ads_map, capture_offset, ptr, size); 719 capture_offset += size; 720 } 721 } 722 723 if (guc->ads_capture_size && guc->ads_capture_size != PAGE_ALIGN(total_size)) 724 drm_warn(&i915->drm, "GuC->ADS->Capture alloc size changed from %d to %d\n", 725 guc->ads_capture_size, PAGE_ALIGN(total_size)); 726 727 return PAGE_ALIGN(total_size); 728 } 729 730 static void __guc_ads_init(struct intel_guc *guc) 731 { 732 struct intel_gt *gt = guc_to_gt(guc); 733 struct drm_i915_private *i915 = gt->i915; 734 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(&guc->ads_map, 735 offsetof(struct __guc_ads_blob, system_info)); 736 u32 base; 737 738 /* GuC scheduling policies */ 739 guc_policies_init(guc); 740 741 /* System info */ 742 fill_engine_enable_masks(gt, &info_map); 743 744 ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED], 745 hweight8(gt->info.sseu.slice_mask)); 746 ads_blob_write(guc, system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK], 747 gt->info.vdbox_sfc_access); 748 749 if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) { 750 u32 distdbreg = intel_uncore_read(gt->uncore, 751 GEN12_DIST_DBS_POPULATED); 752 ads_blob_write(guc, 753 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], 754 ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) 755 & GEN12_DOORBELLS_PER_SQIDI) + 1); 756 } 757 758 /* Golden contexts for re-initialising after a watchdog reset */ 759 guc_prep_golden_context(guc); 760 761 guc_mapping_table_init(guc_to_gt(guc), &info_map); 762 763 base = intel_guc_ggtt_offset(guc, guc->ads_vma); 764 765 /* Lists for error capture debug */ 766 guc_capture_prep_lists(guc); 767 768 /* ADS */ 769 ads_blob_write(guc, ads.scheduler_policies, base + 770 offsetof(struct __guc_ads_blob, policies)); 771 ads_blob_write(guc, ads.gt_system_info, base + 772 offsetof(struct __guc_ads_blob, system_info)); 773 774 /* MMIO save/restore list */ 775 guc_mmio_reg_state_init(guc); 776 777 /* Private Data */ 778 ads_blob_write(guc, ads.private_data, base + 779 guc_ads_private_data_offset(guc)); 780 781 i915_gem_object_flush_map(guc->ads_vma->obj); 782 } 783 784 /** 785 * intel_guc_ads_create() - allocates and initializes GuC ADS. 786 * @guc: intel_guc struct 787 * 788 * GuC needs memory block (Additional Data Struct), where it will store 789 * some data. Allocate and initialize such memory block for GuC use. 790 */ 791 int intel_guc_ads_create(struct intel_guc *guc) 792 { 793 void *ads_blob; 794 u32 size; 795 int ret; 796 797 GEM_BUG_ON(guc->ads_vma); 798 799 /* 800 * Create reg state size dynamically on system memory to be copied to 801 * the final ads blob on gt init/reset 802 */ 803 ret = guc_mmio_reg_state_create(guc); 804 if (ret < 0) 805 return ret; 806 guc->ads_regset_size = ret; 807 808 /* Likewise the golden contexts: */ 809 ret = guc_prep_golden_context(guc); 810 if (ret < 0) 811 return ret; 812 guc->ads_golden_ctxt_size = ret; 813 814 /* Likewise the capture lists: */ 815 ret = guc_capture_prep_lists(guc); 816 if (ret < 0) 817 return ret; 818 guc->ads_capture_size = ret; 819 820 /* Now the total size can be determined: */ 821 size = guc_ads_blob_size(guc); 822 823 ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma, 824 &ads_blob); 825 if (ret) 826 return ret; 827 828 if (i915_gem_object_is_lmem(guc->ads_vma->obj)) 829 iosys_map_set_vaddr_iomem(&guc->ads_map, (void __iomem *)ads_blob); 830 else 831 iosys_map_set_vaddr(&guc->ads_map, ads_blob); 832 833 __guc_ads_init(guc); 834 835 return 0; 836 } 837 838 void intel_guc_ads_init_late(struct intel_guc *guc) 839 { 840 /* 841 * The golden context setup requires the saved engine state from 842 * __engines_record_defaults(). However, that requires engines to be 843 * operational which means the ADS must already have been configured. 844 * Fortunately, the golden context state is not needed until a hang 845 * occurs, so it can be filled in during this late init phase. 846 */ 847 guc_init_golden_context(guc); 848 } 849 850 void intel_guc_ads_destroy(struct intel_guc *guc) 851 { 852 i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); 853 iosys_map_clear(&guc->ads_map); 854 kfree(guc->ads_regset); 855 } 856 857 static void guc_ads_private_data_reset(struct intel_guc *guc) 858 { 859 u32 size; 860 861 size = guc_ads_private_data_size(guc); 862 if (!size) 863 return; 864 865 iosys_map_memset(&guc->ads_map, guc_ads_private_data_offset(guc), 866 0, size); 867 } 868 869 /** 870 * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse 871 * @guc: intel_guc struct 872 * 873 * GuC stores some data in ADS, which might be stale after a reset. 874 * Reinitialize whole ADS in case any part of it was corrupted during 875 * previous GuC run. 876 */ 877 void intel_guc_ads_reset(struct intel_guc *guc) 878 { 879 if (!guc->ads_vma) 880 return; 881 882 __guc_ads_init(guc); 883 884 guc_ads_private_data_reset(guc); 885 } 886 887 u32 intel_guc_engine_usage_offset(struct intel_guc *guc) 888 { 889 return intel_guc_ggtt_offset(guc, guc->ads_vma) + 890 offsetof(struct __guc_ads_blob, engine_usage); 891 } 892 893 struct iosys_map intel_guc_engine_usage_record_map(struct intel_engine_cs *engine) 894 { 895 struct intel_guc *guc = &engine->gt->uc.guc; 896 u8 guc_class = engine_class_to_guc_class(engine->class); 897 size_t offset = offsetof(struct __guc_ads_blob, 898 engine_usage.engines[guc_class][ilog2(engine->logical_mask)]); 899 900 return IOSYS_MAP_INIT_OFFSET(&guc->ads_map, offset); 901 } 902