1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_H_ 7 #define _INTEL_GUC_H_ 8 9 #include "intel_uncore.h" 10 #include "intel_guc_fw.h" 11 #include "intel_guc_fwif.h" 12 #include "intel_guc_ct.h" 13 #include "intel_guc_log.h" 14 #include "intel_guc_reg.h" 15 #include "intel_uc_fw.h" 16 #include "i915_utils.h" 17 #include "i915_vma.h" 18 19 struct __guc_ads_blob; 20 21 /* 22 * Top level structure of GuC. It handles firmware loading and manages client 23 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy 24 * ExecList submission. 25 */ 26 struct intel_guc { 27 struct intel_uc_fw fw; 28 struct intel_guc_log log; 29 struct intel_guc_ct ct; 30 31 /* intel_guc_recv interrupt related state */ 32 spinlock_t irq_lock; 33 unsigned int msg_enabled_mask; 34 35 struct { 36 bool enabled; 37 void (*reset)(struct intel_guc *guc); 38 void (*enable)(struct intel_guc *guc); 39 void (*disable)(struct intel_guc *guc); 40 } interrupts; 41 42 bool submission_supported; 43 44 struct i915_vma *ads_vma; 45 struct __guc_ads_blob *ads_blob; 46 47 struct i915_vma *stage_desc_pool; 48 void *stage_desc_pool_vaddr; 49 struct ida stage_ids; 50 51 struct intel_guc_client *execbuf_client; 52 53 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); 54 /* Cyclic counter mod pagesize */ 55 u32 db_cacheline; 56 57 /* Control params for fw initialization */ 58 u32 params[GUC_CTL_MAX_DWORDS]; 59 60 /* GuC's FW specific registers used in MMIO send */ 61 struct { 62 u32 base; 63 unsigned int count; 64 enum forcewake_domains fw_domains; 65 } send_regs; 66 67 /* Store msg (e.g. log flush) that we see while CTBs are disabled */ 68 u32 mmio_msg; 69 70 /* To serialize the intel_guc_send actions */ 71 struct mutex send_mutex; 72 73 /* GuC's FW specific send function */ 74 int (*send)(struct intel_guc *guc, const u32 *data, u32 len, 75 u32 *response_buf, u32 response_buf_size); 76 77 /* GuC's FW specific event handler function */ 78 void (*handler)(struct intel_guc *guc); 79 80 /* GuC's FW specific notify function */ 81 void (*notify)(struct intel_guc *guc); 82 }; 83 84 static 85 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 86 { 87 return guc->send(guc, action, len, NULL, 0); 88 } 89 90 static inline int 91 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, 92 u32 *response_buf, u32 response_buf_size) 93 { 94 return guc->send(guc, action, len, response_buf, response_buf_size); 95 } 96 97 static inline void intel_guc_notify(struct intel_guc *guc) 98 { 99 guc->notify(guc); 100 } 101 102 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) 103 { 104 guc->handler(guc); 105 } 106 107 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 108 #define GUC_GGTT_TOP 0xFEE00000 109 110 /** 111 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma 112 * @guc: intel_guc structure. 113 * @vma: i915 graphics virtual memory area. 114 * 115 * GuC does not allow any gfx GGTT address that falls into range 116 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. 117 * Currently, in order to exclude [0, ggtt.pin_bias) address space from 118 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() 119 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. 120 * 121 * Return: GGTT offset of the @vma. 122 */ 123 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, 124 struct i915_vma *vma) 125 { 126 u32 offset = i915_ggtt_offset(vma); 127 128 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); 129 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 130 131 return offset; 132 } 133 134 void intel_guc_init_early(struct intel_guc *guc); 135 void intel_guc_init_send_regs(struct intel_guc *guc); 136 void intel_guc_write_params(struct intel_guc *guc); 137 int intel_guc_init(struct intel_guc *guc); 138 void intel_guc_fini(struct intel_guc *guc); 139 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, 140 u32 *response_buf, u32 response_buf_size); 141 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 142 u32 *response_buf, u32 response_buf_size); 143 void intel_guc_to_host_event_handler(struct intel_guc *guc); 144 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); 145 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 146 const u32 *payload, u32 len); 147 int intel_guc_sample_forcewake(struct intel_guc *guc); 148 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 149 int intel_guc_suspend(struct intel_guc *guc); 150 int intel_guc_resume(struct intel_guc *guc); 151 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 152 153 static inline bool intel_guc_is_supported(struct intel_guc *guc) 154 { 155 return intel_uc_fw_is_supported(&guc->fw); 156 } 157 158 static inline bool intel_guc_is_enabled(struct intel_guc *guc) 159 { 160 return intel_uc_fw_is_enabled(&guc->fw); 161 } 162 163 static inline bool intel_guc_is_running(struct intel_guc *guc) 164 { 165 return intel_uc_fw_is_running(&guc->fw); 166 } 167 168 static inline int intel_guc_sanitize(struct intel_guc *guc) 169 { 170 intel_uc_fw_sanitize(&guc->fw); 171 guc->mmio_msg = 0; 172 173 return 0; 174 } 175 176 static inline bool intel_guc_is_submission_supported(struct intel_guc *guc) 177 { 178 return guc->submission_supported; 179 } 180 181 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) 182 { 183 spin_lock_irq(&guc->irq_lock); 184 guc->msg_enabled_mask |= mask; 185 spin_unlock_irq(&guc->irq_lock); 186 } 187 188 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) 189 { 190 spin_lock_irq(&guc->irq_lock); 191 guc->msg_enabled_mask &= ~mask; 192 spin_unlock_irq(&guc->irq_lock); 193 } 194 195 int intel_guc_reset_engine(struct intel_guc *guc, 196 struct intel_engine_cs *engine); 197 198 #endif 199