1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_GUC_H_ 26 #define _INTEL_GUC_H_ 27 28 #include "intel_uncore.h" 29 #include "intel_guc_fw.h" 30 #include "intel_guc_fwif.h" 31 #include "intel_guc_ct.h" 32 #include "intel_guc_log.h" 33 #include "intel_guc_reg.h" 34 #include "intel_uc_fw.h" 35 #include "i915_utils.h" 36 #include "i915_vma.h" 37 38 struct __guc_ads_blob; 39 40 /* 41 * Top level structure of GuC. It handles firmware loading and manages client 42 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy 43 * ExecList submission. 44 */ 45 struct intel_guc { 46 struct intel_uc_fw fw; 47 struct intel_guc_log log; 48 struct intel_guc_ct ct; 49 50 /* Log snapshot if GuC errors during load */ 51 struct drm_i915_gem_object *load_err_log; 52 53 /* intel_guc_recv interrupt related state */ 54 spinlock_t irq_lock; 55 unsigned int msg_enabled_mask; 56 57 struct { 58 bool enabled; 59 void (*reset)(struct intel_guc *guc); 60 void (*enable)(struct intel_guc *guc); 61 void (*disable)(struct intel_guc *guc); 62 } interrupts; 63 64 struct i915_vma *ads_vma; 65 struct __guc_ads_blob *ads_blob; 66 67 struct i915_vma *stage_desc_pool; 68 void *stage_desc_pool_vaddr; 69 struct ida stage_ids; 70 struct i915_vma *shared_data; 71 void *shared_data_vaddr; 72 73 struct intel_guc_client *execbuf_client; 74 75 DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS); 76 /* Cyclic counter mod pagesize */ 77 u32 db_cacheline; 78 79 /* Control params for fw initialization */ 80 u32 params[GUC_CTL_MAX_DWORDS]; 81 82 /* GuC's FW specific registers used in MMIO send */ 83 struct { 84 u32 base; 85 unsigned int count; 86 enum forcewake_domains fw_domains; 87 } send_regs; 88 89 /* Store msg (e.g. log flush) that we see while CTBs are disabled */ 90 u32 mmio_msg; 91 92 /* To serialize the intel_guc_send actions */ 93 struct mutex send_mutex; 94 95 /* GuC's FW specific send function */ 96 int (*send)(struct intel_guc *guc, const u32 *data, u32 len, 97 u32 *response_buf, u32 response_buf_size); 98 99 /* GuC's FW specific event handler function */ 100 void (*handler)(struct intel_guc *guc); 101 102 /* GuC's FW specific notify function */ 103 void (*notify)(struct intel_guc *guc); 104 }; 105 106 static 107 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 108 { 109 return guc->send(guc, action, len, NULL, 0); 110 } 111 112 static inline int 113 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, 114 u32 *response_buf, u32 response_buf_size) 115 { 116 return guc->send(guc, action, len, response_buf, response_buf_size); 117 } 118 119 static inline void intel_guc_notify(struct intel_guc *guc) 120 { 121 guc->notify(guc); 122 } 123 124 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) 125 { 126 guc->handler(guc); 127 } 128 129 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 130 #define GUC_GGTT_TOP 0xFEE00000 131 132 /** 133 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma 134 * @guc: intel_guc structure. 135 * @vma: i915 graphics virtual memory area. 136 * 137 * GuC does not allow any gfx GGTT address that falls into range 138 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. 139 * Currently, in order to exclude [0, ggtt.pin_bias) address space from 140 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() 141 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. 142 * 143 * Return: GGTT offset of the @vma. 144 */ 145 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, 146 struct i915_vma *vma) 147 { 148 u32 offset = i915_ggtt_offset(vma); 149 150 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); 151 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 152 153 return offset; 154 } 155 156 void intel_guc_init_early(struct intel_guc *guc); 157 void intel_guc_init_send_regs(struct intel_guc *guc); 158 void intel_guc_write_params(struct intel_guc *guc); 159 int intel_guc_init(struct intel_guc *guc); 160 void intel_guc_fini(struct intel_guc *guc); 161 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, 162 u32 *response_buf, u32 response_buf_size); 163 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 164 u32 *response_buf, u32 response_buf_size); 165 void intel_guc_to_host_event_handler(struct intel_guc *guc); 166 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); 167 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 168 const u32 *payload, u32 len); 169 int intel_guc_sample_forcewake(struct intel_guc *guc); 170 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 171 int intel_guc_suspend(struct intel_guc *guc); 172 int intel_guc_resume(struct intel_guc *guc); 173 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 174 175 static inline bool intel_guc_is_running(struct intel_guc *guc) 176 { 177 return intel_uc_fw_is_running(&guc->fw); 178 } 179 180 static inline int intel_guc_sanitize(struct intel_guc *guc) 181 { 182 intel_uc_fw_sanitize(&guc->fw); 183 guc->mmio_msg = 0; 184 185 return 0; 186 } 187 188 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) 189 { 190 spin_lock_irq(&guc->irq_lock); 191 guc->msg_enabled_mask |= mask; 192 spin_unlock_irq(&guc->irq_lock); 193 } 194 195 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) 196 { 197 spin_lock_irq(&guc->irq_lock); 198 guc->msg_enabled_mask &= ~mask; 199 spin_unlock_irq(&guc->irq_lock); 200 } 201 202 int intel_guc_reset_engine(struct intel_guc *guc, 203 struct intel_engine_cs *engine); 204 205 #endif 206