1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_H_ 7 #define _INTEL_GUC_H_ 8 9 #include <linux/xarray.h> 10 #include <linux/delay.h> 11 12 #include "intel_uncore.h" 13 #include "intel_guc_fw.h" 14 #include "intel_guc_fwif.h" 15 #include "intel_guc_ct.h" 16 #include "intel_guc_log.h" 17 #include "intel_guc_reg.h" 18 #include "intel_guc_slpc_types.h" 19 #include "intel_uc_fw.h" 20 #include "i915_utils.h" 21 #include "i915_vma.h" 22 23 struct __guc_ads_blob; 24 25 /** 26 * struct intel_guc - Top level structure of GuC. 27 * 28 * It handles firmware loading and manages client pool. intel_guc owns an 29 * i915_sched_engine for submission. 30 */ 31 struct intel_guc { 32 /** @fw: the GuC firmware */ 33 struct intel_uc_fw fw; 34 /** @log: sub-structure containing GuC log related data and objects */ 35 struct intel_guc_log log; 36 /** @ct: the command transport communication channel */ 37 struct intel_guc_ct ct; 38 /** @slpc: sub-structure containing SLPC related data and objects */ 39 struct intel_guc_slpc slpc; 40 41 /** @sched_engine: Global engine used to submit requests to GuC */ 42 struct i915_sched_engine *sched_engine; 43 /** 44 * @stalled_request: if GuC can't process a request for any reason, we 45 * save it until GuC restarts processing. No other request can be 46 * submitted until the stalled request is processed. 47 */ 48 struct i915_request *stalled_request; 49 /** 50 * @submission_stall_reason: reason why submission is stalled 51 */ 52 enum { 53 STALL_NONE, 54 STALL_REGISTER_CONTEXT, 55 STALL_MOVE_LRC_TAIL, 56 STALL_ADD_REQUEST, 57 } submission_stall_reason; 58 59 /* intel_guc_recv interrupt related state */ 60 /** @irq_lock: protects GuC irq state */ 61 spinlock_t irq_lock; 62 /** 63 * @msg_enabled_mask: mask of events that are processed when receiving 64 * an INTEL_GUC_ACTION_DEFAULT G2H message. 65 */ 66 unsigned int msg_enabled_mask; 67 68 /** 69 * @outstanding_submission_g2h: number of outstanding GuC to Host 70 * responses related to GuC submission, used to determine if the GT is 71 * idle 72 */ 73 atomic_t outstanding_submission_g2h; 74 75 /** @interrupts: pointers to GuC interrupt-managing functions. */ 76 struct { 77 void (*reset)(struct intel_guc *guc); 78 void (*enable)(struct intel_guc *guc); 79 void (*disable)(struct intel_guc *guc); 80 } interrupts; 81 82 /** 83 * @submission_state: sub-structure for submission state protected by 84 * single lock 85 */ 86 struct { 87 /** 88 * @lock: protects everything in submission_state, 89 * ce->guc_id.id, and ce->guc_id.ref when transitioning in and 90 * out of zero 91 */ 92 spinlock_t lock; 93 /** 94 * @guc_ids: used to allocate new guc_ids, single-lrc 95 */ 96 struct ida guc_ids; 97 /** 98 * @num_guc_ids: Number of guc_ids, selftest feature to be able 99 * to reduce this number while testing. 100 */ 101 int num_guc_ids; 102 /** 103 * @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc 104 */ 105 unsigned long *guc_ids_bitmap; 106 /** 107 * @guc_id_list: list of intel_context with valid guc_ids but no 108 * refs 109 */ 110 struct list_head guc_id_list; 111 /** 112 * @destroyed_contexts: list of contexts waiting to be destroyed 113 * (deregistered with the GuC) 114 */ 115 struct list_head destroyed_contexts; 116 /** 117 * @destroyed_worker: worker to deregister contexts, need as we 118 * need to take a GT PM reference and can't from destroy 119 * function as it might be in an atomic context (no sleeping) 120 */ 121 struct work_struct destroyed_worker; 122 /** 123 * @reset_fail_worker: worker to trigger a GT reset after an 124 * engine reset fails 125 */ 126 struct work_struct reset_fail_worker; 127 /** 128 * @reset_fail_mask: mask of engines that failed to reset 129 */ 130 intel_engine_mask_t reset_fail_mask; 131 } submission_state; 132 133 /** 134 * @submission_supported: tracks whether we support GuC submission on 135 * the current platform 136 */ 137 bool submission_supported; 138 /** @submission_selected: tracks whether the user enabled GuC submission */ 139 bool submission_selected; 140 /** 141 * @rc_supported: tracks whether we support GuC rc on the current platform 142 */ 143 bool rc_supported; 144 /** @rc_selected: tracks whether the user enabled GuC rc */ 145 bool rc_selected; 146 147 /** @ads_vma: object allocated to hold the GuC ADS */ 148 struct i915_vma *ads_vma; 149 /** @ads_blob: contents of the GuC ADS */ 150 struct __guc_ads_blob *ads_blob; 151 /** @ads_regset_size: size of the save/restore regsets in the ADS */ 152 u32 ads_regset_size; 153 /** 154 * @ads_regset_count: number of save/restore registers in the ADS for 155 * each engine 156 */ 157 u32 ads_regset_count[I915_NUM_ENGINES]; 158 /** @ads_regset: save/restore regsets in the ADS */ 159 struct guc_mmio_reg *ads_regset; 160 /** @ads_golden_ctxt_size: size of the golden contexts in the ADS */ 161 u32 ads_golden_ctxt_size; 162 /** @ads_engine_usage_size: size of engine usage in the ADS */ 163 u32 ads_engine_usage_size; 164 165 /** @lrc_desc_pool: object allocated to hold the GuC LRC descriptor pool */ 166 struct i915_vma *lrc_desc_pool; 167 /** @lrc_desc_pool_vaddr: contents of the GuC LRC descriptor pool */ 168 void *lrc_desc_pool_vaddr; 169 170 /** 171 * @context_lookup: used to resolve intel_context from guc_id, if a 172 * context is present in this structure it is registered with the GuC 173 */ 174 struct xarray context_lookup; 175 176 /** @params: Control params for fw initialization */ 177 u32 params[GUC_CTL_MAX_DWORDS]; 178 179 /** @send_regs: GuC's FW specific registers used for sending MMIO H2G */ 180 struct { 181 u32 base; 182 unsigned int count; 183 enum forcewake_domains fw_domains; 184 } send_regs; 185 186 /** @notify_reg: register used to send interrupts to the GuC FW */ 187 i915_reg_t notify_reg; 188 189 /** 190 * @mmio_msg: notification bitmask that the GuC writes in one of its 191 * registers when the CT channel is disabled, to be processed when the 192 * channel is back up. 193 */ 194 u32 mmio_msg; 195 196 /** @send_mutex: used to serialize the intel_guc_send actions */ 197 struct mutex send_mutex; 198 199 /** 200 * @timestamp: GT timestamp object that stores a copy of the timestamp 201 * and adjusts it for overflow using a worker. 202 */ 203 struct { 204 /** 205 * @lock: Lock protecting the below fields and the engine stats. 206 */ 207 spinlock_t lock; 208 209 /** 210 * @gt_stamp: 64 bit extended value of the GT timestamp. 211 */ 212 u64 gt_stamp; 213 214 /** 215 * @ping_delay: Period for polling the GT timestamp for 216 * overflow. 217 */ 218 unsigned long ping_delay; 219 220 /** 221 * @work: Periodic work to adjust GT timestamp, engine and 222 * context usage for overflows. 223 */ 224 struct delayed_work work; 225 226 /** 227 * @shift: Right shift value for the gpm timestamp 228 */ 229 u32 shift; 230 } timestamp; 231 232 #ifdef CONFIG_DRM_I915_SELFTEST 233 /** 234 * @number_guc_id_stolen: The number of guc_ids that have been stolen 235 */ 236 int number_guc_id_stolen; 237 #endif 238 }; 239 240 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log) 241 { 242 return container_of(log, struct intel_guc, log); 243 } 244 245 static 246 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 247 { 248 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 0); 249 } 250 251 static 252 inline int intel_guc_send_nb(struct intel_guc *guc, const u32 *action, u32 len, 253 u32 g2h_len_dw) 254 { 255 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0, 256 MAKE_SEND_FLAGS(g2h_len_dw)); 257 } 258 259 static inline int 260 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, 261 u32 *response_buf, u32 response_buf_size) 262 { 263 return intel_guc_ct_send(&guc->ct, action, len, 264 response_buf, response_buf_size, 0); 265 } 266 267 static inline int intel_guc_send_busy_loop(struct intel_guc *guc, 268 const u32 *action, 269 u32 len, 270 u32 g2h_len_dw, 271 bool loop) 272 { 273 int err; 274 unsigned int sleep_period_ms = 1; 275 bool not_atomic = !in_atomic() && !irqs_disabled(); 276 277 /* 278 * FIXME: Have caller pass in if we are in an atomic context to avoid 279 * using in_atomic(). It is likely safe here as we check for irqs 280 * disabled which basically all the spin locks in the i915 do but 281 * regardless this should be cleaned up. 282 */ 283 284 /* No sleeping with spin locks, just busy loop */ 285 might_sleep_if(loop && not_atomic); 286 287 retry: 288 err = intel_guc_send_nb(guc, action, len, g2h_len_dw); 289 if (unlikely(err == -EBUSY && loop)) { 290 if (likely(not_atomic)) { 291 if (msleep_interruptible(sleep_period_ms)) 292 return -EINTR; 293 sleep_period_ms = sleep_period_ms << 1; 294 } else { 295 cpu_relax(); 296 } 297 goto retry; 298 } 299 300 return err; 301 } 302 303 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) 304 { 305 intel_guc_ct_event_handler(&guc->ct); 306 } 307 308 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 309 #define GUC_GGTT_TOP 0xFEE00000 310 311 /** 312 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma 313 * @guc: intel_guc structure. 314 * @vma: i915 graphics virtual memory area. 315 * 316 * GuC does not allow any gfx GGTT address that falls into range 317 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. 318 * Currently, in order to exclude [0, ggtt.pin_bias) address space from 319 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() 320 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. 321 * 322 * Return: GGTT offset of the @vma. 323 */ 324 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, 325 struct i915_vma *vma) 326 { 327 u32 offset = i915_ggtt_offset(vma); 328 329 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); 330 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 331 332 return offset; 333 } 334 335 void intel_guc_init_early(struct intel_guc *guc); 336 void intel_guc_init_late(struct intel_guc *guc); 337 void intel_guc_init_send_regs(struct intel_guc *guc); 338 void intel_guc_write_params(struct intel_guc *guc); 339 int intel_guc_init(struct intel_guc *guc); 340 void intel_guc_fini(struct intel_guc *guc); 341 void intel_guc_notify(struct intel_guc *guc); 342 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 343 u32 *response_buf, u32 response_buf_size); 344 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 345 const u32 *payload, u32 len); 346 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 347 int intel_guc_suspend(struct intel_guc *guc); 348 int intel_guc_resume(struct intel_guc *guc); 349 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 350 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 351 struct i915_vma **out_vma, void **out_vaddr); 352 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value); 353 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value); 354 355 static inline bool intel_guc_is_supported(struct intel_guc *guc) 356 { 357 return intel_uc_fw_is_supported(&guc->fw); 358 } 359 360 static inline bool intel_guc_is_wanted(struct intel_guc *guc) 361 { 362 return intel_uc_fw_is_enabled(&guc->fw); 363 } 364 365 static inline bool intel_guc_is_used(struct intel_guc *guc) 366 { 367 GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED); 368 return intel_uc_fw_is_available(&guc->fw); 369 } 370 371 static inline bool intel_guc_is_fw_running(struct intel_guc *guc) 372 { 373 return intel_uc_fw_is_running(&guc->fw); 374 } 375 376 static inline bool intel_guc_is_ready(struct intel_guc *guc) 377 { 378 return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct); 379 } 380 381 static inline void intel_guc_reset_interrupts(struct intel_guc *guc) 382 { 383 guc->interrupts.reset(guc); 384 } 385 386 static inline void intel_guc_enable_interrupts(struct intel_guc *guc) 387 { 388 guc->interrupts.enable(guc); 389 } 390 391 static inline void intel_guc_disable_interrupts(struct intel_guc *guc) 392 { 393 guc->interrupts.disable(guc); 394 } 395 396 static inline int intel_guc_sanitize(struct intel_guc *guc) 397 { 398 intel_uc_fw_sanitize(&guc->fw); 399 intel_guc_disable_interrupts(guc); 400 intel_guc_ct_sanitize(&guc->ct); 401 guc->mmio_msg = 0; 402 403 return 0; 404 } 405 406 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) 407 { 408 spin_lock_irq(&guc->irq_lock); 409 guc->msg_enabled_mask |= mask; 410 spin_unlock_irq(&guc->irq_lock); 411 } 412 413 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) 414 { 415 spin_lock_irq(&guc->irq_lock); 416 guc->msg_enabled_mask &= ~mask; 417 spin_unlock_irq(&guc->irq_lock); 418 } 419 420 int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout); 421 422 int intel_guc_deregister_done_process_msg(struct intel_guc *guc, 423 const u32 *msg, u32 len); 424 int intel_guc_sched_done_process_msg(struct intel_guc *guc, 425 const u32 *msg, u32 len); 426 int intel_guc_context_reset_process_msg(struct intel_guc *guc, 427 const u32 *msg, u32 len); 428 int intel_guc_engine_failure_process_msg(struct intel_guc *guc, 429 const u32 *msg, u32 len); 430 int intel_guc_error_capture_process_msg(struct intel_guc *guc, 431 const u32 *msg, u32 len); 432 433 void intel_guc_find_hung_context(struct intel_engine_cs *engine); 434 435 int intel_guc_global_policies_update(struct intel_guc *guc); 436 437 void intel_guc_context_ban(struct intel_context *ce, struct i915_request *rq); 438 439 void intel_guc_submission_reset_prepare(struct intel_guc *guc); 440 void intel_guc_submission_reset(struct intel_guc *guc, bool stalled); 441 void intel_guc_submission_reset_finish(struct intel_guc *guc); 442 void intel_guc_submission_cancel_requests(struct intel_guc *guc); 443 444 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p); 445 446 void intel_guc_write_barrier(struct intel_guc *guc); 447 448 #endif 449