1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_H_ 7 #define _INTEL_GUC_H_ 8 9 #include "intel_uncore.h" 10 #include "intel_guc_fw.h" 11 #include "intel_guc_fwif.h" 12 #include "intel_guc_ct.h" 13 #include "intel_guc_log.h" 14 #include "intel_guc_reg.h" 15 #include "intel_uc_fw.h" 16 #include "i915_utils.h" 17 #include "i915_vma.h" 18 19 struct __guc_ads_blob; 20 21 /* 22 * Top level structure of GuC. It handles firmware loading and manages client 23 * pool. intel_guc owns a intel_guc_client to replace the legacy ExecList 24 * submission. 25 */ 26 struct intel_guc { 27 struct intel_uc_fw fw; 28 struct intel_guc_log log; 29 struct intel_guc_ct ct; 30 31 /* intel_guc_recv interrupt related state */ 32 spinlock_t irq_lock; 33 unsigned int msg_enabled_mask; 34 35 struct { 36 bool enabled; 37 void (*reset)(struct intel_guc *guc); 38 void (*enable)(struct intel_guc *guc); 39 void (*disable)(struct intel_guc *guc); 40 } interrupts; 41 42 bool submission_selected; 43 44 struct i915_vma *ads_vma; 45 struct __guc_ads_blob *ads_blob; 46 47 struct i915_vma *stage_desc_pool; 48 void *stage_desc_pool_vaddr; 49 50 /* Control params for fw initialization */ 51 u32 params[GUC_CTL_MAX_DWORDS]; 52 53 /* GuC's FW specific registers used in MMIO send */ 54 struct { 55 u32 base; 56 unsigned int count; 57 enum forcewake_domains fw_domains; 58 } send_regs; 59 60 /* register used to send interrupts to the GuC FW */ 61 i915_reg_t notify_reg; 62 63 /* Store msg (e.g. log flush) that we see while CTBs are disabled */ 64 u32 mmio_msg; 65 66 /* To serialize the intel_guc_send actions */ 67 struct mutex send_mutex; 68 }; 69 70 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log) 71 { 72 return container_of(log, struct intel_guc, log); 73 } 74 75 static 76 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) 77 { 78 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0); 79 } 80 81 static inline int 82 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, 83 u32 *response_buf, u32 response_buf_size) 84 { 85 return intel_guc_ct_send(&guc->ct, action, len, 86 response_buf, response_buf_size); 87 } 88 89 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) 90 { 91 intel_guc_ct_event_handler(&guc->ct); 92 } 93 94 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ 95 #define GUC_GGTT_TOP 0xFEE00000 96 97 /** 98 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma 99 * @guc: intel_guc structure. 100 * @vma: i915 graphics virtual memory area. 101 * 102 * GuC does not allow any gfx GGTT address that falls into range 103 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM. 104 * Currently, in order to exclude [0, ggtt.pin_bias) address space from 105 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma() 106 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias. 107 * 108 * Return: GGTT offset of the @vma. 109 */ 110 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, 111 struct i915_vma *vma) 112 { 113 u32 offset = i915_ggtt_offset(vma); 114 115 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma)); 116 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP)); 117 118 return offset; 119 } 120 121 void intel_guc_init_early(struct intel_guc *guc); 122 void intel_guc_init_send_regs(struct intel_guc *guc); 123 void intel_guc_write_params(struct intel_guc *guc); 124 int intel_guc_init(struct intel_guc *guc); 125 void intel_guc_fini(struct intel_guc *guc); 126 void intel_guc_notify(struct intel_guc *guc); 127 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, 128 u32 *response_buf, u32 response_buf_size); 129 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 130 const u32 *payload, u32 len); 131 int intel_guc_sample_forcewake(struct intel_guc *guc); 132 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); 133 int intel_guc_suspend(struct intel_guc *guc); 134 int intel_guc_resume(struct intel_guc *guc); 135 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); 136 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 137 struct i915_vma **out_vma, void **out_vaddr); 138 139 static inline bool intel_guc_is_supported(struct intel_guc *guc) 140 { 141 return intel_uc_fw_is_supported(&guc->fw); 142 } 143 144 static inline bool intel_guc_is_wanted(struct intel_guc *guc) 145 { 146 return intel_uc_fw_is_enabled(&guc->fw); 147 } 148 149 static inline bool intel_guc_is_used(struct intel_guc *guc) 150 { 151 GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED); 152 return intel_uc_fw_is_available(&guc->fw); 153 } 154 155 static inline bool intel_guc_is_fw_running(struct intel_guc *guc) 156 { 157 return intel_uc_fw_is_running(&guc->fw); 158 } 159 160 static inline bool intel_guc_is_ready(struct intel_guc *guc) 161 { 162 return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct); 163 } 164 165 static inline int intel_guc_sanitize(struct intel_guc *guc) 166 { 167 intel_uc_fw_sanitize(&guc->fw); 168 intel_guc_ct_sanitize(&guc->ct); 169 guc->mmio_msg = 0; 170 171 return 0; 172 } 173 174 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) 175 { 176 spin_lock_irq(&guc->irq_lock); 177 guc->msg_enabled_mask |= mask; 178 spin_unlock_irq(&guc->irq_lock); 179 } 180 181 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) 182 { 183 spin_lock_irq(&guc->irq_lock); 184 guc->msg_enabled_mask &= ~mask; 185 spin_unlock_irq(&guc->irq_lock); 186 } 187 188 int intel_guc_reset_engine(struct intel_guc *guc, 189 struct intel_engine_cs *engine); 190 191 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p); 192 193 #endif 194