1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #include "gem/i915_gem_lmem.h" 7 #include "gt/intel_gt.h" 8 #include "gt/intel_gt_irq.h" 9 #include "gt/intel_gt_pm_irq.h" 10 #include "gt/intel_gt_regs.h" 11 #include "intel_guc.h" 12 #include "intel_guc_ads.h" 13 #include "intel_guc_capture.h" 14 #include "intel_guc_slpc.h" 15 #include "intel_guc_submission.h" 16 #include "i915_drv.h" 17 #include "i915_irq.h" 18 19 /** 20 * DOC: GuC 21 * 22 * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is 23 * designed to offload some of the functionality usually performed by the host 24 * driver; currently the main operations it can take care of are: 25 * 26 * - Authentication of the HuC, which is required to fully enable HuC usage. 27 * - Low latency graphics context scheduling (a.k.a. GuC submission). 28 * - GT Power management. 29 * 30 * The enable_guc module parameter can be used to select which of those 31 * operations to enable within GuC. Note that not all the operations are 32 * supported on all gen9+ platforms. 33 * 34 * Enabling the GuC is not mandatory and therefore the firmware is only loaded 35 * if at least one of the operations is selected. However, not loading the GuC 36 * might result in the loss of some features that do require the GuC (currently 37 * just the HuC, but more are expected to land in the future). 38 */ 39 40 void intel_guc_notify(struct intel_guc *guc) 41 { 42 struct intel_gt *gt = guc_to_gt(guc); 43 44 /* 45 * On Gen11+, the value written to the register is passes as a payload 46 * to the FW. However, the FW currently treats all values the same way 47 * (H2G interrupt), so we can just write the value that the HW expects 48 * on older gens. 49 */ 50 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER); 51 } 52 53 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i) 54 { 55 GEM_BUG_ON(!guc->send_regs.base); 56 GEM_BUG_ON(!guc->send_regs.count); 57 GEM_BUG_ON(i >= guc->send_regs.count); 58 59 return _MMIO(guc->send_regs.base + 4 * i); 60 } 61 62 void intel_guc_init_send_regs(struct intel_guc *guc) 63 { 64 struct intel_gt *gt = guc_to_gt(guc); 65 enum forcewake_domains fw_domains = 0; 66 unsigned int i; 67 68 GEM_BUG_ON(!guc->send_regs.base); 69 GEM_BUG_ON(!guc->send_regs.count); 70 71 for (i = 0; i < guc->send_regs.count; i++) { 72 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore, 73 guc_send_reg(guc, i), 74 FW_REG_READ | FW_REG_WRITE); 75 } 76 guc->send_regs.fw_domains = fw_domains; 77 } 78 79 static void gen9_reset_guc_interrupts(struct intel_guc *guc) 80 { 81 struct intel_gt *gt = guc_to_gt(guc); 82 83 assert_rpm_wakelock_held(>->i915->runtime_pm); 84 85 spin_lock_irq(>->irq_lock); 86 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events); 87 spin_unlock_irq(>->irq_lock); 88 } 89 90 static void gen9_enable_guc_interrupts(struct intel_guc *guc) 91 { 92 struct intel_gt *gt = guc_to_gt(guc); 93 94 assert_rpm_wakelock_held(>->i915->runtime_pm); 95 96 spin_lock_irq(>->irq_lock); 97 WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & 98 gt->pm_guc_events); 99 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); 100 spin_unlock_irq(>->irq_lock); 101 } 102 103 static void gen9_disable_guc_interrupts(struct intel_guc *guc) 104 { 105 struct intel_gt *gt = guc_to_gt(guc); 106 107 assert_rpm_wakelock_held(>->i915->runtime_pm); 108 109 spin_lock_irq(>->irq_lock); 110 111 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events); 112 113 spin_unlock_irq(>->irq_lock); 114 intel_synchronize_irq(gt->i915); 115 116 gen9_reset_guc_interrupts(guc); 117 } 118 119 static void gen11_reset_guc_interrupts(struct intel_guc *guc) 120 { 121 struct intel_gt *gt = guc_to_gt(guc); 122 123 spin_lock_irq(>->irq_lock); 124 gen11_gt_reset_one_iir(gt, 0, GEN11_GUC); 125 spin_unlock_irq(>->irq_lock); 126 } 127 128 static void gen11_enable_guc_interrupts(struct intel_guc *guc) 129 { 130 struct intel_gt *gt = guc_to_gt(guc); 131 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 132 133 spin_lock_irq(>->irq_lock); 134 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC)); 135 intel_uncore_write(gt->uncore, 136 GEN11_GUC_SG_INTR_ENABLE, events); 137 intel_uncore_write(gt->uncore, 138 GEN11_GUC_SG_INTR_MASK, ~events); 139 spin_unlock_irq(>->irq_lock); 140 } 141 142 static void gen11_disable_guc_interrupts(struct intel_guc *guc) 143 { 144 struct intel_gt *gt = guc_to_gt(guc); 145 146 spin_lock_irq(>->irq_lock); 147 148 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0); 149 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 150 151 spin_unlock_irq(>->irq_lock); 152 intel_synchronize_irq(gt->i915); 153 154 gen11_reset_guc_interrupts(guc); 155 } 156 157 void intel_guc_init_early(struct intel_guc *guc) 158 { 159 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 160 161 intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC); 162 intel_guc_ct_init_early(&guc->ct); 163 intel_guc_log_init_early(&guc->log); 164 intel_guc_submission_init_early(guc); 165 intel_guc_slpc_init_early(&guc->slpc); 166 intel_guc_rc_init_early(guc); 167 168 mutex_init(&guc->send_mutex); 169 spin_lock_init(&guc->irq_lock); 170 if (GRAPHICS_VER(i915) >= 11) { 171 guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; 172 guc->interrupts.reset = gen11_reset_guc_interrupts; 173 guc->interrupts.enable = gen11_enable_guc_interrupts; 174 guc->interrupts.disable = gen11_disable_guc_interrupts; 175 guc->send_regs.base = 176 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); 177 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; 178 179 } else { 180 guc->notify_reg = GUC_SEND_INTERRUPT; 181 guc->interrupts.reset = gen9_reset_guc_interrupts; 182 guc->interrupts.enable = gen9_enable_guc_interrupts; 183 guc->interrupts.disable = gen9_disable_guc_interrupts; 184 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); 185 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN; 186 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT); 187 } 188 189 intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION | 190 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED); 191 } 192 193 void intel_guc_init_late(struct intel_guc *guc) 194 { 195 intel_guc_ads_init_late(guc); 196 } 197 198 static u32 guc_ctl_debug_flags(struct intel_guc *guc) 199 { 200 u32 level = intel_guc_log_get_level(&guc->log); 201 u32 flags = 0; 202 203 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 204 flags |= GUC_LOG_DISABLED; 205 else 206 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 207 GUC_LOG_VERBOSITY_SHIFT; 208 209 return flags; 210 } 211 212 static u32 guc_ctl_feature_flags(struct intel_guc *guc) 213 { 214 u32 flags = 0; 215 216 if (!intel_guc_submission_is_used(guc)) 217 flags |= GUC_CTL_DISABLE_SCHEDULER; 218 219 if (intel_guc_slpc_is_used(guc)) 220 flags |= GUC_CTL_ENABLE_SLPC; 221 222 return flags; 223 } 224 225 static u32 guc_ctl_log_params_flags(struct intel_guc *guc) 226 { 227 u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; 228 u32 flags; 229 230 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 231 #define LOG_UNIT SZ_1M 232 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 233 #else 234 #define LOG_UNIT SZ_4K 235 #define LOG_FLAG 0 236 #endif 237 238 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 239 #define CAPTURE_UNIT SZ_1M 240 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 241 #else 242 #define CAPTURE_UNIT SZ_4K 243 #define CAPTURE_FLAG 0 244 #endif 245 246 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 247 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 248 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 249 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 250 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 251 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 252 253 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 254 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 255 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 256 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 257 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 258 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 259 260 flags = GUC_LOG_VALID | 261 GUC_LOG_NOTIFY_ON_HALF_FULL | 262 CAPTURE_FLAG | 263 LOG_FLAG | 264 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 265 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 266 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << GUC_LOG_CAPTURE_SHIFT) | 267 (offset << GUC_LOG_BUF_ADDR_SHIFT); 268 269 #undef LOG_UNIT 270 #undef LOG_FLAG 271 #undef CAPTURE_UNIT 272 #undef CAPTURE_FLAG 273 274 return flags; 275 } 276 277 static u32 guc_ctl_ads_flags(struct intel_guc *guc) 278 { 279 u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; 280 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 281 282 return flags; 283 } 284 285 static u32 guc_ctl_wa_flags(struct intel_guc *guc) 286 { 287 struct intel_gt *gt = guc_to_gt(guc); 288 u32 flags = 0; 289 290 /* Wa_22012773006:gen11,gen12 < XeHP */ 291 if (GRAPHICS_VER(gt->i915) >= 11 && 292 GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50)) 293 flags |= GUC_WA_POLLCS; 294 295 /* Wa_16011759253:dg2_g10:a0 */ 296 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 297 flags |= GUC_WA_GAM_CREDITS; 298 299 /* Wa_14014475959:dg2 */ 300 if (IS_DG2(gt->i915)) 301 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 302 303 /* 304 * Wa_14012197797:dg2_g10:a0,dg2_g11:a0 305 * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12 306 * 307 * The same WA bit is used for both and 22011391025 is applicable to 308 * all DG2. 309 */ 310 if (IS_DG2(gt->i915)) 311 flags |= GUC_WA_DUAL_QUEUE; 312 313 /* Wa_22011802037: graphics version 11/12 */ 314 if (IS_GRAPHICS_VER(gt->i915, 11, 12)) 315 flags |= GUC_WA_PRE_PARSER; 316 317 /* Wa_16011777198:dg2 */ 318 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || 319 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) 320 flags |= GUC_WA_RCS_RESET_BEFORE_RC6; 321 322 /* 323 * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..) 324 * Wa_22012727685:dg2_g11[a0..) 325 */ 326 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || 327 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER)) 328 flags |= GUC_WA_CONTEXT_ISOLATION; 329 330 /* Wa_16015675438 */ 331 if (!RCS_MASK(gt)) 332 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 333 334 return flags; 335 } 336 337 static u32 guc_ctl_devid(struct intel_guc *guc) 338 { 339 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 340 341 return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915); 342 } 343 344 /* 345 * Initialise the GuC parameter block before starting the firmware 346 * transfer. These parameters are read by the firmware on startup 347 * and cannot be changed thereafter. 348 */ 349 static void guc_init_params(struct intel_guc *guc) 350 { 351 u32 *params = guc->params; 352 int i; 353 354 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 355 356 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 357 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 358 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 359 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 360 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 361 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 362 363 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 364 DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]); 365 } 366 367 /* 368 * Initialise the GuC parameter block before starting the firmware 369 * transfer. These parameters are read by the firmware on startup 370 * and cannot be changed thereafter. 371 */ 372 void intel_guc_write_params(struct intel_guc *guc) 373 { 374 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; 375 int i; 376 377 /* 378 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and 379 * they are power context saved so it's ok to release forcewake 380 * when we are done here and take it again at xfer time. 381 */ 382 intel_uncore_forcewake_get(uncore, FORCEWAKE_GT); 383 384 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); 385 386 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 387 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); 388 389 intel_uncore_forcewake_put(uncore, FORCEWAKE_GT); 390 } 391 392 int intel_guc_init(struct intel_guc *guc) 393 { 394 struct intel_gt *gt = guc_to_gt(guc); 395 int ret; 396 397 ret = intel_uc_fw_init(&guc->fw); 398 if (ret) 399 goto out; 400 401 ret = intel_guc_log_create(&guc->log); 402 if (ret) 403 goto err_fw; 404 405 ret = intel_guc_capture_init(guc); 406 if (ret) 407 goto err_log; 408 409 ret = intel_guc_ads_create(guc); 410 if (ret) 411 goto err_capture; 412 413 GEM_BUG_ON(!guc->ads_vma); 414 415 ret = intel_guc_ct_init(&guc->ct); 416 if (ret) 417 goto err_ads; 418 419 if (intel_guc_submission_is_used(guc)) { 420 /* 421 * This is stuff we need to have available at fw load time 422 * if we are planning to enable submission later 423 */ 424 ret = intel_guc_submission_init(guc); 425 if (ret) 426 goto err_ct; 427 } 428 429 if (intel_guc_slpc_is_used(guc)) { 430 ret = intel_guc_slpc_init(&guc->slpc); 431 if (ret) 432 goto err_submission; 433 } 434 435 /* now that everything is perma-pinned, initialize the parameters */ 436 guc_init_params(guc); 437 438 /* We need to notify the guc whenever we change the GGTT */ 439 i915_ggtt_enable_guc(gt->ggtt); 440 441 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE); 442 443 return 0; 444 445 err_submission: 446 intel_guc_submission_fini(guc); 447 err_ct: 448 intel_guc_ct_fini(&guc->ct); 449 err_ads: 450 intel_guc_ads_destroy(guc); 451 err_capture: 452 intel_guc_capture_destroy(guc); 453 err_log: 454 intel_guc_log_destroy(&guc->log); 455 err_fw: 456 intel_uc_fw_fini(&guc->fw); 457 out: 458 i915_probe_error(gt->i915, "failed with %d\n", ret); 459 return ret; 460 } 461 462 void intel_guc_fini(struct intel_guc *guc) 463 { 464 struct intel_gt *gt = guc_to_gt(guc); 465 466 if (!intel_uc_fw_is_loadable(&guc->fw)) 467 return; 468 469 i915_ggtt_disable_guc(gt->ggtt); 470 471 if (intel_guc_slpc_is_used(guc)) 472 intel_guc_slpc_fini(&guc->slpc); 473 474 if (intel_guc_submission_is_used(guc)) 475 intel_guc_submission_fini(guc); 476 477 intel_guc_ct_fini(&guc->ct); 478 479 intel_guc_ads_destroy(guc); 480 intel_guc_capture_destroy(guc); 481 intel_guc_log_destroy(&guc->log); 482 intel_uc_fw_fini(&guc->fw); 483 } 484 485 /* 486 * This function implements the MMIO based host to GuC interface. 487 */ 488 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, 489 u32 *response_buf, u32 response_buf_size) 490 { 491 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 492 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; 493 u32 header; 494 int i; 495 int ret; 496 497 GEM_BUG_ON(!len); 498 GEM_BUG_ON(len > guc->send_regs.count); 499 500 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); 501 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); 502 503 mutex_lock(&guc->send_mutex); 504 intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); 505 506 retry: 507 for (i = 0; i < len; i++) 508 intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]); 509 510 intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); 511 512 intel_guc_notify(guc); 513 514 /* 515 * No GuC command should ever take longer than 10ms. 516 * Fast commands should still complete in 10us. 517 */ 518 ret = __intel_wait_for_register_fw(uncore, 519 guc_send_reg(guc, 0), 520 GUC_HXG_MSG_0_ORIGIN, 521 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, 522 GUC_HXG_ORIGIN_GUC), 523 10, 10, &header); 524 if (unlikely(ret)) { 525 timeout: 526 drm_err(&i915->drm, "mmio request %#x: no reply %x\n", 527 request[0], header); 528 goto out; 529 } 530 531 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 532 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ 533 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ 534 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) 535 536 ret = wait_for(done, 1000); 537 if (unlikely(ret)) 538 goto timeout; 539 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 540 GUC_HXG_ORIGIN_GUC)) 541 goto proto; 542 #undef done 543 } 544 545 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 546 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 547 548 drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n", 549 request[0], reason); 550 goto retry; 551 } 552 553 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { 554 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 555 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 556 557 drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n", 558 request[0], error, hint); 559 ret = -ENXIO; 560 goto out; 561 } 562 563 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { 564 proto: 565 drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n", 566 request[0], header); 567 ret = -EPROTO; 568 goto out; 569 } 570 571 if (response_buf) { 572 int count = min(response_buf_size, guc->send_regs.count); 573 574 GEM_BUG_ON(!count); 575 576 response_buf[0] = header; 577 578 for (i = 1; i < count; i++) 579 response_buf[i] = intel_uncore_read(uncore, 580 guc_send_reg(guc, i)); 581 582 /* Use number of copied dwords as our return value */ 583 ret = count; 584 } else { 585 /* Use data from the GuC response as our return value */ 586 ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 587 } 588 589 out: 590 intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); 591 mutex_unlock(&guc->send_mutex); 592 593 return ret; 594 } 595 596 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 597 const u32 *payload, u32 len) 598 { 599 u32 msg; 600 601 if (unlikely(!len)) 602 return -EPROTO; 603 604 /* Make sure to handle only enabled messages */ 605 msg = payload[0] & guc->msg_enabled_mask; 606 607 if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED) 608 drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n"); 609 if (msg & INTEL_GUC_RECV_MSG_EXCEPTION) 610 drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n"); 611 612 return 0; 613 } 614 615 /** 616 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode 617 * @guc: intel_guc structure 618 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma 619 * 620 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send 621 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by 622 * intel_huc_auth(). 623 * 624 * Return: non-zero code on error 625 */ 626 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset) 627 { 628 u32 action[] = { 629 INTEL_GUC_ACTION_AUTHENTICATE_HUC, 630 rsa_offset 631 }; 632 633 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 634 } 635 636 /** 637 * intel_guc_suspend() - notify GuC entering suspend state 638 * @guc: the guc 639 */ 640 int intel_guc_suspend(struct intel_guc *guc) 641 { 642 int ret; 643 u32 action[] = { 644 INTEL_GUC_ACTION_CLIENT_SOFT_RESET, 645 }; 646 647 if (!intel_guc_is_ready(guc)) 648 return 0; 649 650 if (intel_guc_submission_is_used(guc)) { 651 /* 652 * This H2G MMIO command tears down the GuC in two steps. First it will 653 * generate a G2H CTB for every active context indicating a reset. In 654 * practice the i915 shouldn't ever get a G2H as suspend should only be 655 * called when the GPU is idle. Next, it tears down the CTBs and this 656 * H2G MMIO command completes. 657 * 658 * Don't abort on a failure code from the GuC. Keep going and do the 659 * clean up in santize() and re-initialisation on resume and hopefully 660 * the error here won't be problematic. 661 */ 662 ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); 663 if (ret) 664 DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret); 665 } 666 667 /* Signal that the GuC isn't running. */ 668 intel_guc_sanitize(guc); 669 670 return 0; 671 } 672 673 /** 674 * intel_guc_resume() - notify GuC resuming from suspend state 675 * @guc: the guc 676 */ 677 int intel_guc_resume(struct intel_guc *guc) 678 { 679 /* 680 * NB: This function can still be called even if GuC submission is 681 * disabled, e.g. if GuC is enabled for HuC authentication only. Thus, 682 * if any code is later added here, it must be support doing nothing 683 * if submission is disabled (as per intel_guc_suspend). 684 */ 685 return 0; 686 } 687 688 /** 689 * DOC: GuC Memory Management 690 * 691 * GuC can't allocate any memory for its own usage, so all the allocations must 692 * be handled by the host driver. GuC accesses the memory via the GGTT, with the 693 * exception of the top and bottom parts of the 4GB address space, which are 694 * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) 695 * or other parts of the HW. The driver must take care not to place objects that 696 * the GuC is going to access in these reserved ranges. The layout of the GuC 697 * address space is shown below: 698 * 699 * :: 700 * 701 * +===========> +====================+ <== FFFF_FFFF 702 * ^ | Reserved | 703 * | +====================+ <== GUC_GGTT_TOP 704 * | | | 705 * | | DRAM | 706 * GuC | | 707 * Address +===> +====================+ <== GuC ggtt_pin_bias 708 * Space ^ | | 709 * | | | | 710 * | GuC | GuC | 711 * | WOPCM | WOPCM | 712 * | Size | | 713 * | | | | 714 * v v | | 715 * +=======+===> +====================+ <== 0000_0000 716 * 717 * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM 718 * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped 719 * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size. 720 */ 721 722 /** 723 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage 724 * @guc: the guc 725 * @size: size of area to allocate (both virtual space and memory) 726 * 727 * This is a wrapper to create an object for use with the GuC. In order to 728 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate 729 * both some backing storage and a range inside the Global GTT. We must pin 730 * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that 731 * range is reserved inside GuC. 732 * 733 * Return: A i915_vma if successful, otherwise an ERR_PTR. 734 */ 735 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) 736 { 737 struct intel_gt *gt = guc_to_gt(guc); 738 struct drm_i915_gem_object *obj; 739 struct i915_vma *vma; 740 u64 flags; 741 int ret; 742 743 if (HAS_LMEM(gt->i915)) 744 obj = i915_gem_object_create_lmem(gt->i915, size, 745 I915_BO_ALLOC_CPU_CLEAR | 746 I915_BO_ALLOC_CONTIGUOUS | 747 I915_BO_ALLOC_PM_EARLY); 748 else 749 obj = i915_gem_object_create_shmem(gt->i915, size); 750 751 if (IS_ERR(obj)) 752 return ERR_CAST(obj); 753 754 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 755 if (IS_ERR(vma)) 756 goto err; 757 758 flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 759 ret = i915_ggtt_pin(vma, NULL, 0, flags); 760 if (ret) { 761 vma = ERR_PTR(ret); 762 goto err; 763 } 764 765 return i915_vma_make_unshrinkable(vma); 766 767 err: 768 i915_gem_object_put(obj); 769 return vma; 770 } 771 772 /** 773 * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage 774 * @guc: the guc 775 * @size: size of area to allocate (both virtual space and memory) 776 * @out_vma: return variable for the allocated vma pointer 777 * @out_vaddr: return variable for the obj mapping 778 * 779 * This wrapper calls intel_guc_allocate_vma() and then maps the allocated 780 * object with I915_MAP_WB. 781 * 782 * Return: 0 if successful, a negative errno code otherwise. 783 */ 784 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 785 struct i915_vma **out_vma, void **out_vaddr) 786 { 787 struct i915_vma *vma; 788 void *vaddr; 789 790 vma = intel_guc_allocate_vma(guc, size); 791 if (IS_ERR(vma)) 792 return PTR_ERR(vma); 793 794 vaddr = i915_gem_object_pin_map_unlocked(vma->obj, 795 i915_coherent_map_type(guc_to_gt(guc)->i915, 796 vma->obj, true)); 797 if (IS_ERR(vaddr)) { 798 i915_vma_unpin_and_release(&vma, 0); 799 return PTR_ERR(vaddr); 800 } 801 802 *out_vma = vma; 803 *out_vaddr = vaddr; 804 805 return 0; 806 } 807 808 static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value) 809 { 810 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 811 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 812 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 813 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG), 814 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 815 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 816 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)), 817 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)), 818 }; 819 int ret; 820 821 GEM_BUG_ON(len > 2); 822 GEM_BUG_ON(len == 1 && upper_32_bits(value)); 823 824 /* Self config must go over MMIO */ 825 ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0); 826 827 if (unlikely(ret < 0)) 828 return ret; 829 if (unlikely(ret > 1)) 830 return -EPROTO; 831 if (unlikely(!ret)) 832 return -ENOKEY; 833 834 return 0; 835 } 836 837 static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value) 838 { 839 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 840 int err = __guc_action_self_cfg(guc, key, len, value); 841 842 if (unlikely(err)) 843 i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n", 844 ERR_PTR(err), key, value); 845 return err; 846 } 847 848 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value) 849 { 850 return __guc_self_cfg(guc, key, 1, value); 851 } 852 853 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value) 854 { 855 return __guc_self_cfg(guc, key, 2, value); 856 } 857 858 /** 859 * intel_guc_load_status - dump information about GuC load status 860 * @guc: the GuC 861 * @p: the &drm_printer 862 * 863 * Pretty printer for GuC load status. 864 */ 865 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p) 866 { 867 struct intel_gt *gt = guc_to_gt(guc); 868 struct intel_uncore *uncore = gt->uncore; 869 intel_wakeref_t wakeref; 870 871 if (!intel_guc_is_supported(guc)) { 872 drm_printf(p, "GuC not supported\n"); 873 return; 874 } 875 876 if (!intel_guc_is_wanted(guc)) { 877 drm_printf(p, "GuC disabled\n"); 878 return; 879 } 880 881 intel_uc_fw_dump(&guc->fw, p); 882 883 with_intel_runtime_pm(uncore->rpm, wakeref) { 884 u32 status = intel_uncore_read(uncore, GUC_STATUS); 885 u32 i; 886 887 drm_printf(p, "\nGuC status 0x%08x:\n", status); 888 drm_printf(p, "\tBootrom status = 0x%x\n", 889 (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); 890 drm_printf(p, "\tuKernel status = 0x%x\n", 891 (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); 892 drm_printf(p, "\tMIA Core status = 0x%x\n", 893 (status & GS_MIA_MASK) >> GS_MIA_SHIFT); 894 drm_puts(p, "\nScratch registers:\n"); 895 for (i = 0; i < 16; i++) { 896 drm_printf(p, "\t%2d: \t0x%x\n", 897 i, intel_uncore_read(uncore, SOFT_SCRATCH(i))); 898 } 899 } 900 } 901 902 void intel_guc_write_barrier(struct intel_guc *guc) 903 { 904 struct intel_gt *gt = guc_to_gt(guc); 905 906 if (i915_gem_object_is_lmem(guc->ct.vma->obj)) { 907 /* 908 * Ensure intel_uncore_write_fw can be used rather than 909 * intel_uncore_write. 910 */ 911 GEM_BUG_ON(guc->send_regs.fw_domains); 912 913 /* 914 * This register is used by the i915 and GuC for MMIO based 915 * communication. Once we are in this code CTBs are the only 916 * method the i915 uses to communicate with the GuC so it is 917 * safe to write to this register (a value of 0 is NOP for MMIO 918 * communication). If we ever start mixing CTBs and MMIOs a new 919 * register will have to be chosen. This function is also used 920 * to enforce ordering of a work queue item write and an update 921 * to the process descriptor. When a work queue is being used, 922 * CTBs are also the only mechanism of communication. 923 */ 924 intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0); 925 } else { 926 /* wmb() sufficient for a barrier if in smem */ 927 wmb(); 928 } 929 } 930