1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #include "gt/intel_gt.h" 7 #include "gt/intel_gt_irq.h" 8 #include "gt/intel_gt_pm_irq.h" 9 #include "intel_guc.h" 10 #include "intel_guc_slpc.h" 11 #include "intel_guc_ads.h" 12 #include "intel_guc_submission.h" 13 #include "i915_drv.h" 14 15 /** 16 * DOC: GuC 17 * 18 * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is 19 * designed to offload some of the functionality usually performed by the host 20 * driver; currently the main operations it can take care of are: 21 * 22 * - Authentication of the HuC, which is required to fully enable HuC usage. 23 * - Low latency graphics context scheduling (a.k.a. GuC submission). 24 * - GT Power management. 25 * 26 * The enable_guc module parameter can be used to select which of those 27 * operations to enable within GuC. Note that not all the operations are 28 * supported on all gen9+ platforms. 29 * 30 * Enabling the GuC is not mandatory and therefore the firmware is only loaded 31 * if at least one of the operations is selected. However, not loading the GuC 32 * might result in the loss of some features that do require the GuC (currently 33 * just the HuC, but more are expected to land in the future). 34 */ 35 36 void intel_guc_notify(struct intel_guc *guc) 37 { 38 struct intel_gt *gt = guc_to_gt(guc); 39 40 /* 41 * On Gen11+, the value written to the register is passes as a payload 42 * to the FW. However, the FW currently treats all values the same way 43 * (H2G interrupt), so we can just write the value that the HW expects 44 * on older gens. 45 */ 46 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER); 47 } 48 49 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i) 50 { 51 GEM_BUG_ON(!guc->send_regs.base); 52 GEM_BUG_ON(!guc->send_regs.count); 53 GEM_BUG_ON(i >= guc->send_regs.count); 54 55 return _MMIO(guc->send_regs.base + 4 * i); 56 } 57 58 void intel_guc_init_send_regs(struct intel_guc *guc) 59 { 60 struct intel_gt *gt = guc_to_gt(guc); 61 enum forcewake_domains fw_domains = 0; 62 unsigned int i; 63 64 GEM_BUG_ON(!guc->send_regs.base); 65 GEM_BUG_ON(!guc->send_regs.count); 66 67 for (i = 0; i < guc->send_regs.count; i++) { 68 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore, 69 guc_send_reg(guc, i), 70 FW_REG_READ | FW_REG_WRITE); 71 } 72 guc->send_regs.fw_domains = fw_domains; 73 } 74 75 static void gen9_reset_guc_interrupts(struct intel_guc *guc) 76 { 77 struct intel_gt *gt = guc_to_gt(guc); 78 79 assert_rpm_wakelock_held(>->i915->runtime_pm); 80 81 spin_lock_irq(>->irq_lock); 82 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events); 83 spin_unlock_irq(>->irq_lock); 84 } 85 86 static void gen9_enable_guc_interrupts(struct intel_guc *guc) 87 { 88 struct intel_gt *gt = guc_to_gt(guc); 89 90 assert_rpm_wakelock_held(>->i915->runtime_pm); 91 92 spin_lock_irq(>->irq_lock); 93 WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & 94 gt->pm_guc_events); 95 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); 96 spin_unlock_irq(>->irq_lock); 97 } 98 99 static void gen9_disable_guc_interrupts(struct intel_guc *guc) 100 { 101 struct intel_gt *gt = guc_to_gt(guc); 102 103 assert_rpm_wakelock_held(>->i915->runtime_pm); 104 105 spin_lock_irq(>->irq_lock); 106 107 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events); 108 109 spin_unlock_irq(>->irq_lock); 110 intel_synchronize_irq(gt->i915); 111 112 gen9_reset_guc_interrupts(guc); 113 } 114 115 static void gen11_reset_guc_interrupts(struct intel_guc *guc) 116 { 117 struct intel_gt *gt = guc_to_gt(guc); 118 119 spin_lock_irq(>->irq_lock); 120 gen11_gt_reset_one_iir(gt, 0, GEN11_GUC); 121 spin_unlock_irq(>->irq_lock); 122 } 123 124 static void gen11_enable_guc_interrupts(struct intel_guc *guc) 125 { 126 struct intel_gt *gt = guc_to_gt(guc); 127 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 128 129 spin_lock_irq(>->irq_lock); 130 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC)); 131 intel_uncore_write(gt->uncore, 132 GEN11_GUC_SG_INTR_ENABLE, events); 133 intel_uncore_write(gt->uncore, 134 GEN11_GUC_SG_INTR_MASK, ~events); 135 spin_unlock_irq(>->irq_lock); 136 } 137 138 static void gen11_disable_guc_interrupts(struct intel_guc *guc) 139 { 140 struct intel_gt *gt = guc_to_gt(guc); 141 142 spin_lock_irq(>->irq_lock); 143 144 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0); 145 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0); 146 147 spin_unlock_irq(>->irq_lock); 148 intel_synchronize_irq(gt->i915); 149 150 gen11_reset_guc_interrupts(guc); 151 } 152 153 void intel_guc_init_early(struct intel_guc *guc) 154 { 155 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 156 157 intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC); 158 intel_guc_ct_init_early(&guc->ct); 159 intel_guc_log_init_early(&guc->log); 160 intel_guc_submission_init_early(guc); 161 intel_guc_slpc_init_early(&guc->slpc); 162 intel_guc_rc_init_early(guc); 163 164 mutex_init(&guc->send_mutex); 165 spin_lock_init(&guc->irq_lock); 166 if (GRAPHICS_VER(i915) >= 11) { 167 guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; 168 guc->interrupts.reset = gen11_reset_guc_interrupts; 169 guc->interrupts.enable = gen11_enable_guc_interrupts; 170 guc->interrupts.disable = gen11_disable_guc_interrupts; 171 guc->send_regs.base = 172 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); 173 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; 174 175 } else { 176 guc->notify_reg = GUC_SEND_INTERRUPT; 177 guc->interrupts.reset = gen9_reset_guc_interrupts; 178 guc->interrupts.enable = gen9_enable_guc_interrupts; 179 guc->interrupts.disable = gen9_disable_guc_interrupts; 180 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); 181 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN; 182 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT); 183 } 184 } 185 186 void intel_guc_init_late(struct intel_guc *guc) 187 { 188 intel_guc_ads_init_late(guc); 189 } 190 191 static u32 guc_ctl_debug_flags(struct intel_guc *guc) 192 { 193 u32 level = intel_guc_log_get_level(&guc->log); 194 u32 flags = 0; 195 196 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 197 flags |= GUC_LOG_DISABLED; 198 else 199 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 200 GUC_LOG_VERBOSITY_SHIFT; 201 202 return flags; 203 } 204 205 static u32 guc_ctl_feature_flags(struct intel_guc *guc) 206 { 207 u32 flags = 0; 208 209 if (!intel_guc_submission_is_used(guc)) 210 flags |= GUC_CTL_DISABLE_SCHEDULER; 211 212 if (intel_guc_slpc_is_used(guc)) 213 flags |= GUC_CTL_ENABLE_SLPC; 214 215 return flags; 216 } 217 218 static u32 guc_ctl_log_params_flags(struct intel_guc *guc) 219 { 220 u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; 221 u32 flags; 222 223 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 224 #define UNIT SZ_1M 225 #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE 226 #else 227 #define UNIT SZ_4K 228 #define FLAG 0 229 #endif 230 231 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 232 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT)); 233 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 234 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, UNIT)); 235 236 BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) > 237 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 238 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / UNIT - 1) > 239 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 240 241 flags = GUC_LOG_VALID | 242 GUC_LOG_NOTIFY_ON_HALF_FULL | 243 FLAG | 244 ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 245 ((DEBUG_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 246 (offset << GUC_LOG_BUF_ADDR_SHIFT); 247 248 #undef UNIT 249 #undef FLAG 250 251 return flags; 252 } 253 254 static u32 guc_ctl_ads_flags(struct intel_guc *guc) 255 { 256 u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; 257 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 258 259 return flags; 260 } 261 262 /* 263 * Initialise the GuC parameter block before starting the firmware 264 * transfer. These parameters are read by the firmware on startup 265 * and cannot be changed thereafter. 266 */ 267 static void guc_init_params(struct intel_guc *guc) 268 { 269 u32 *params = guc->params; 270 int i; 271 272 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 273 274 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 275 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 276 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 277 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 278 279 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 280 DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]); 281 } 282 283 /* 284 * Initialise the GuC parameter block before starting the firmware 285 * transfer. These parameters are read by the firmware on startup 286 * and cannot be changed thereafter. 287 */ 288 void intel_guc_write_params(struct intel_guc *guc) 289 { 290 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; 291 int i; 292 293 /* 294 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and 295 * they are power context saved so it's ok to release forcewake 296 * when we are done here and take it again at xfer time. 297 */ 298 intel_uncore_forcewake_get(uncore, FORCEWAKE_GT); 299 300 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); 301 302 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 303 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); 304 305 intel_uncore_forcewake_put(uncore, FORCEWAKE_GT); 306 } 307 308 int intel_guc_init(struct intel_guc *guc) 309 { 310 struct intel_gt *gt = guc_to_gt(guc); 311 int ret; 312 313 ret = intel_uc_fw_init(&guc->fw); 314 if (ret) 315 goto out; 316 317 ret = intel_guc_log_create(&guc->log); 318 if (ret) 319 goto err_fw; 320 321 ret = intel_guc_ads_create(guc); 322 if (ret) 323 goto err_log; 324 GEM_BUG_ON(!guc->ads_vma); 325 326 ret = intel_guc_ct_init(&guc->ct); 327 if (ret) 328 goto err_ads; 329 330 if (intel_guc_submission_is_used(guc)) { 331 /* 332 * This is stuff we need to have available at fw load time 333 * if we are planning to enable submission later 334 */ 335 ret = intel_guc_submission_init(guc); 336 if (ret) 337 goto err_ct; 338 } 339 340 if (intel_guc_slpc_is_used(guc)) { 341 ret = intel_guc_slpc_init(&guc->slpc); 342 if (ret) 343 goto err_submission; 344 } 345 346 /* now that everything is perma-pinned, initialize the parameters */ 347 guc_init_params(guc); 348 349 /* We need to notify the guc whenever we change the GGTT */ 350 i915_ggtt_enable_guc(gt->ggtt); 351 352 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE); 353 354 return 0; 355 356 err_submission: 357 intel_guc_submission_fini(guc); 358 err_ct: 359 intel_guc_ct_fini(&guc->ct); 360 err_ads: 361 intel_guc_ads_destroy(guc); 362 err_log: 363 intel_guc_log_destroy(&guc->log); 364 err_fw: 365 intel_uc_fw_fini(&guc->fw); 366 out: 367 i915_probe_error(gt->i915, "failed with %d\n", ret); 368 return ret; 369 } 370 371 void intel_guc_fini(struct intel_guc *guc) 372 { 373 struct intel_gt *gt = guc_to_gt(guc); 374 375 if (!intel_uc_fw_is_loadable(&guc->fw)) 376 return; 377 378 i915_ggtt_disable_guc(gt->ggtt); 379 380 if (intel_guc_slpc_is_used(guc)) 381 intel_guc_slpc_fini(&guc->slpc); 382 383 if (intel_guc_submission_is_used(guc)) 384 intel_guc_submission_fini(guc); 385 386 intel_guc_ct_fini(&guc->ct); 387 388 intel_guc_ads_destroy(guc); 389 intel_guc_log_destroy(&guc->log); 390 intel_uc_fw_fini(&guc->fw); 391 } 392 393 /* 394 * This function implements the MMIO based host to GuC interface. 395 */ 396 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, 397 u32 *response_buf, u32 response_buf_size) 398 { 399 struct drm_i915_private *i915 = guc_to_gt(guc)->i915; 400 struct intel_uncore *uncore = guc_to_gt(guc)->uncore; 401 u32 header; 402 int i; 403 int ret; 404 405 GEM_BUG_ON(!len); 406 GEM_BUG_ON(len > guc->send_regs.count); 407 408 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); 409 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); 410 411 mutex_lock(&guc->send_mutex); 412 intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); 413 414 retry: 415 for (i = 0; i < len; i++) 416 intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]); 417 418 intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); 419 420 intel_guc_notify(guc); 421 422 /* 423 * No GuC command should ever take longer than 10ms. 424 * Fast commands should still complete in 10us. 425 */ 426 ret = __intel_wait_for_register_fw(uncore, 427 guc_send_reg(guc, 0), 428 GUC_HXG_MSG_0_ORIGIN, 429 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, 430 GUC_HXG_ORIGIN_GUC), 431 10, 10, &header); 432 if (unlikely(ret)) { 433 timeout: 434 drm_err(&i915->drm, "mmio request %#x: no reply %x\n", 435 request[0], header); 436 goto out; 437 } 438 439 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 440 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ 441 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ 442 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) 443 444 ret = wait_for(done, 1000); 445 if (unlikely(ret)) 446 goto timeout; 447 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 448 GUC_HXG_ORIGIN_GUC)) 449 goto proto; 450 #undef done 451 } 452 453 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 454 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 455 456 drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n", 457 request[0], reason); 458 goto retry; 459 } 460 461 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { 462 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 463 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 464 465 drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n", 466 request[0], error, hint); 467 ret = -ENXIO; 468 goto out; 469 } 470 471 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { 472 proto: 473 drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n", 474 request[0], header); 475 ret = -EPROTO; 476 goto out; 477 } 478 479 if (response_buf) { 480 int count = min(response_buf_size, guc->send_regs.count); 481 482 GEM_BUG_ON(!count); 483 484 response_buf[0] = header; 485 486 for (i = 1; i < count; i++) 487 response_buf[i] = intel_uncore_read(uncore, 488 guc_send_reg(guc, i)); 489 490 /* Use number of copied dwords as our return value */ 491 ret = count; 492 } else { 493 /* Use data from the GuC response as our return value */ 494 ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 495 } 496 497 out: 498 intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); 499 mutex_unlock(&guc->send_mutex); 500 501 return ret; 502 } 503 504 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, 505 const u32 *payload, u32 len) 506 { 507 u32 msg; 508 509 if (unlikely(!len)) 510 return -EPROTO; 511 512 /* Make sure to handle only enabled messages */ 513 msg = payload[0] & guc->msg_enabled_mask; 514 515 if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER | 516 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) 517 intel_guc_log_handle_flush_event(&guc->log); 518 519 return 0; 520 } 521 522 /** 523 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode 524 * @guc: intel_guc structure 525 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma 526 * 527 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send 528 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by 529 * intel_huc_auth(). 530 * 531 * Return: non-zero code on error 532 */ 533 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset) 534 { 535 u32 action[] = { 536 INTEL_GUC_ACTION_AUTHENTICATE_HUC, 537 rsa_offset 538 }; 539 540 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 541 } 542 543 /** 544 * intel_guc_suspend() - notify GuC entering suspend state 545 * @guc: the guc 546 */ 547 int intel_guc_suspend(struct intel_guc *guc) 548 { 549 int ret; 550 u32 action[] = { 551 INTEL_GUC_ACTION_RESET_CLIENT, 552 }; 553 554 if (!intel_guc_is_ready(guc)) 555 return 0; 556 557 if (intel_guc_submission_is_used(guc)) { 558 /* 559 * This H2G MMIO command tears down the GuC in two steps. First it will 560 * generate a G2H CTB for every active context indicating a reset. In 561 * practice the i915 shouldn't ever get a G2H as suspend should only be 562 * called when the GPU is idle. Next, it tears down the CTBs and this 563 * H2G MMIO command completes. 564 * 565 * Don't abort on a failure code from the GuC. Keep going and do the 566 * clean up in santize() and re-initialisation on resume and hopefully 567 * the error here won't be problematic. 568 */ 569 ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); 570 if (ret) 571 DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret); 572 } 573 574 /* Signal that the GuC isn't running. */ 575 intel_guc_sanitize(guc); 576 577 return 0; 578 } 579 580 /** 581 * intel_guc_resume() - notify GuC resuming from suspend state 582 * @guc: the guc 583 */ 584 int intel_guc_resume(struct intel_guc *guc) 585 { 586 /* 587 * NB: This function can still be called even if GuC submission is 588 * disabled, e.g. if GuC is enabled for HuC authentication only. Thus, 589 * if any code is later added here, it must be support doing nothing 590 * if submission is disabled (as per intel_guc_suspend). 591 */ 592 return 0; 593 } 594 595 /** 596 * DOC: GuC Memory Management 597 * 598 * GuC can't allocate any memory for its own usage, so all the allocations must 599 * be handled by the host driver. GuC accesses the memory via the GGTT, with the 600 * exception of the top and bottom parts of the 4GB address space, which are 601 * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM) 602 * or other parts of the HW. The driver must take care not to place objects that 603 * the GuC is going to access in these reserved ranges. The layout of the GuC 604 * address space is shown below: 605 * 606 * :: 607 * 608 * +===========> +====================+ <== FFFF_FFFF 609 * ^ | Reserved | 610 * | +====================+ <== GUC_GGTT_TOP 611 * | | | 612 * | | DRAM | 613 * GuC | | 614 * Address +===> +====================+ <== GuC ggtt_pin_bias 615 * Space ^ | | 616 * | | | | 617 * | GuC | GuC | 618 * | WOPCM | WOPCM | 619 * | Size | | 620 * | | | | 621 * v v | | 622 * +=======+===> +====================+ <== 0000_0000 623 * 624 * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM 625 * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped 626 * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size. 627 */ 628 629 /** 630 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage 631 * @guc: the guc 632 * @size: size of area to allocate (both virtual space and memory) 633 * 634 * This is a wrapper to create an object for use with the GuC. In order to 635 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate 636 * both some backing storage and a range inside the Global GTT. We must pin 637 * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that 638 * range is reserved inside GuC. 639 * 640 * Return: A i915_vma if successful, otherwise an ERR_PTR. 641 */ 642 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) 643 { 644 struct intel_gt *gt = guc_to_gt(guc); 645 struct drm_i915_gem_object *obj; 646 struct i915_vma *vma; 647 u64 flags; 648 int ret; 649 650 obj = i915_gem_object_create_shmem(gt->i915, size); 651 if (IS_ERR(obj)) 652 return ERR_CAST(obj); 653 654 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 655 if (IS_ERR(vma)) 656 goto err; 657 658 flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); 659 ret = i915_ggtt_pin(vma, NULL, 0, flags); 660 if (ret) { 661 vma = ERR_PTR(ret); 662 goto err; 663 } 664 665 return i915_vma_make_unshrinkable(vma); 666 667 err: 668 i915_gem_object_put(obj); 669 return vma; 670 } 671 672 /** 673 * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage 674 * @guc: the guc 675 * @size: size of area to allocate (both virtual space and memory) 676 * @out_vma: return variable for the allocated vma pointer 677 * @out_vaddr: return variable for the obj mapping 678 * 679 * This wrapper calls intel_guc_allocate_vma() and then maps the allocated 680 * object with I915_MAP_WB. 681 * 682 * Return: 0 if successful, a negative errno code otherwise. 683 */ 684 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size, 685 struct i915_vma **out_vma, void **out_vaddr) 686 { 687 struct i915_vma *vma; 688 void *vaddr; 689 690 vma = intel_guc_allocate_vma(guc, size); 691 if (IS_ERR(vma)) 692 return PTR_ERR(vma); 693 694 vaddr = i915_gem_object_pin_map_unlocked(vma->obj, 695 i915_coherent_map_type(guc_to_gt(guc)->i915, 696 vma->obj, true)); 697 if (IS_ERR(vaddr)) { 698 i915_vma_unpin_and_release(&vma, 0); 699 return PTR_ERR(vaddr); 700 } 701 702 *out_vma = vma; 703 *out_vaddr = vaddr; 704 705 return 0; 706 } 707 708 /** 709 * intel_guc_load_status - dump information about GuC load status 710 * @guc: the GuC 711 * @p: the &drm_printer 712 * 713 * Pretty printer for GuC load status. 714 */ 715 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p) 716 { 717 struct intel_gt *gt = guc_to_gt(guc); 718 struct intel_uncore *uncore = gt->uncore; 719 intel_wakeref_t wakeref; 720 721 if (!intel_guc_is_supported(guc)) { 722 drm_printf(p, "GuC not supported\n"); 723 return; 724 } 725 726 if (!intel_guc_is_wanted(guc)) { 727 drm_printf(p, "GuC disabled\n"); 728 return; 729 } 730 731 intel_uc_fw_dump(&guc->fw, p); 732 733 with_intel_runtime_pm(uncore->rpm, wakeref) { 734 u32 status = intel_uncore_read(uncore, GUC_STATUS); 735 u32 i; 736 737 drm_printf(p, "\nGuC status 0x%08x:\n", status); 738 drm_printf(p, "\tBootrom status = 0x%x\n", 739 (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); 740 drm_printf(p, "\tuKernel status = 0x%x\n", 741 (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); 742 drm_printf(p, "\tMIA Core status = 0x%x\n", 743 (status & GS_MIA_MASK) >> GS_MIA_SHIFT); 744 drm_puts(p, "\nScratch registers:\n"); 745 for (i = 0; i < 16; i++) { 746 drm_printf(p, "\t%2d: \t0x%x\n", 747 i, intel_uncore_read(uncore, SOFT_SCRATCH(i))); 748 } 749 } 750 } 751