1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <linux/types.h> 7 8 #include "gt/intel_gt.h" 9 #include "gt/intel_gt_print.h" 10 #include "intel_gsc_fw.h" 11 #include "intel_gsc_proxy.h" 12 #include "intel_gsc_uc.h" 13 #include "i915_drv.h" 14 #include "i915_reg.h" 15 16 static void gsc_work(struct work_struct *work) 17 { 18 struct intel_gsc_uc *gsc = container_of(work, typeof(*gsc), work); 19 struct intel_gt *gt = gsc_uc_to_gt(gsc); 20 intel_wakeref_t wakeref; 21 u32 actions; 22 int ret; 23 24 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 25 26 spin_lock_irq(gt->irq_lock); 27 actions = gsc->gsc_work_actions; 28 gsc->gsc_work_actions = 0; 29 spin_unlock_irq(gt->irq_lock); 30 31 if (actions & GSC_ACTION_FW_LOAD) { 32 ret = intel_gsc_uc_fw_upload(gsc); 33 if (!ret) 34 /* setup proxy on a new load */ 35 actions |= GSC_ACTION_SW_PROXY; 36 else if (ret != -EEXIST) 37 goto out_put; 38 39 /* 40 * The HuC auth can be done both before or after the proxy init; 41 * if done after, a proxy request will be issued and must be 42 * serviced before the authentication can complete. 43 * Since this worker also handles proxy requests, we can't 44 * perform an action that requires the proxy from within it and 45 * then stall waiting for it, because we'd be blocking the 46 * service path. Therefore, it is easier for us to load HuC 47 * first and do proxy later. The GSC will ack the HuC auth and 48 * then send the HuC proxy request as part of the proxy init 49 * flow. 50 * Note that we can only do the GSC auth if the GuC auth was 51 * successful. 52 */ 53 if (intel_uc_uses_huc(>->uc) && 54 intel_huc_is_authenticated(>->uc.huc, INTEL_HUC_AUTH_BY_GUC)) 55 intel_huc_auth(>->uc.huc, INTEL_HUC_AUTH_BY_GSC); 56 } 57 58 if (actions & GSC_ACTION_SW_PROXY) { 59 if (!intel_gsc_uc_fw_init_done(gsc)) { 60 gt_err(gt, "Proxy request received with GSC not loaded!\n"); 61 goto out_put; 62 } 63 64 ret = intel_gsc_proxy_request_handler(gsc); 65 if (ret) 66 goto out_put; 67 68 /* mark the GSC FW init as done the first time we run this */ 69 if (actions & GSC_ACTION_FW_LOAD) { 70 /* 71 * If there is a proxy establishment error, the GSC might still 72 * complete the request handling cleanly, so we need to check the 73 * status register to check if the proxy init was actually successful 74 */ 75 if (intel_gsc_uc_fw_proxy_init_done(gsc, false)) { 76 drm_dbg(>->i915->drm, "GSC Proxy initialized\n"); 77 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_RUNNING); 78 } else { 79 drm_err(>->i915->drm, 80 "GSC status reports proxy init not complete\n"); 81 } 82 } 83 } 84 85 out_put: 86 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 87 } 88 89 static bool gsc_engine_supported(struct intel_gt *gt) 90 { 91 intel_engine_mask_t mask; 92 93 /* 94 * We reach here from i915_driver_early_probe for the primary GT before 95 * its engine mask is set, so we use the device info engine mask for it. 96 * For other GTs we expect the GT-specific mask to be set before we 97 * call this function. 98 */ 99 GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask); 100 101 if (gt_is_root(gt)) 102 mask = RUNTIME_INFO(gt->i915)->platform_engine_mask; 103 else 104 mask = gt->info.engine_mask; 105 106 return __HAS_ENGINE(mask, GSC0); 107 } 108 109 void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc) 110 { 111 struct intel_gt *gt = gsc_uc_to_gt(gsc); 112 113 /* 114 * GSC FW needs to be copied to a dedicated memory allocations for 115 * loading (see gsc->local), so we don't need to GGTT map the FW image 116 * itself into GGTT. 117 */ 118 intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC, false); 119 INIT_WORK(&gsc->work, gsc_work); 120 121 /* we can arrive here from i915_driver_early_probe for primary 122 * GT with it being not fully setup hence check device info's 123 * engine mask 124 */ 125 if (!gsc_engine_supported(gt)) { 126 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED); 127 return; 128 } 129 130 gsc->wq = alloc_ordered_workqueue("i915_gsc", 0); 131 if (!gsc->wq) { 132 gt_err(gt, "failed to allocate WQ for GSC, disabling FW\n"); 133 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED); 134 } 135 } 136 137 static int gsc_allocate_and_map_vma(struct intel_gsc_uc *gsc, u32 size) 138 { 139 struct intel_gt *gt = gsc_uc_to_gt(gsc); 140 struct drm_i915_gem_object *obj; 141 struct i915_vma *vma; 142 void __iomem *vaddr; 143 int ret = 0; 144 145 /* 146 * The GSC FW doesn't immediately suspend after becoming idle, so there 147 * is a chance that it could still be awake after we successfully 148 * return from the pci suspend function, even if there are no pending 149 * operations. 150 * The FW might therefore try to access memory for its suspend operation 151 * after the kernel has completed the HW suspend flow; this can cause 152 * issues if the FW is mapped in normal RAM memory, as some of the 153 * involved HW units might've already lost power. 154 * The driver must therefore avoid this situation and the recommended 155 * way to do so is to use stolen memory for the GSC memory allocation, 156 * because stolen memory takes a different path in HW and it is 157 * guaranteed to always work as long as the GPU itself is awake (which 158 * it must be if the GSC is awake). 159 */ 160 obj = i915_gem_object_create_stolen(gt->i915, size); 161 if (IS_ERR(obj)) 162 return PTR_ERR(obj); 163 164 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); 165 if (IS_ERR(vma)) { 166 ret = PTR_ERR(vma); 167 goto err; 168 } 169 170 vaddr = i915_vma_pin_iomap(vma); 171 i915_vma_unpin(vma); 172 if (IS_ERR(vaddr)) { 173 ret = PTR_ERR(vaddr); 174 goto err; 175 } 176 177 i915_vma_make_unshrinkable(vma); 178 179 gsc->local = vma; 180 gsc->local_vaddr = vaddr; 181 182 return 0; 183 184 err: 185 i915_gem_object_put(obj); 186 return ret; 187 } 188 189 static void gsc_unmap_and_free_vma(struct intel_gsc_uc *gsc) 190 { 191 struct i915_vma *vma = fetch_and_zero(&gsc->local); 192 193 if (!vma) 194 return; 195 196 gsc->local_vaddr = NULL; 197 i915_vma_unpin_iomap(vma); 198 i915_gem_object_put(vma->obj); 199 } 200 201 int intel_gsc_uc_init(struct intel_gsc_uc *gsc) 202 { 203 static struct lock_class_key gsc_lock; 204 struct intel_gt *gt = gsc_uc_to_gt(gsc); 205 struct intel_engine_cs *engine = gt->engine[GSC0]; 206 struct intel_context *ce; 207 int err; 208 209 err = intel_uc_fw_init(&gsc->fw); 210 if (err) 211 goto out; 212 213 err = gsc_allocate_and_map_vma(gsc, SZ_4M); 214 if (err) 215 goto out_fw; 216 217 ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K, 218 I915_GEM_HWS_GSC_ADDR, 219 &gsc_lock, "gsc_context"); 220 if (IS_ERR(ce)) { 221 gt_err(gt, "failed to create GSC CS ctx for FW communication\n"); 222 err = PTR_ERR(ce); 223 goto out_vma; 224 } 225 226 gsc->ce = ce; 227 228 /* if we fail to init proxy we still want to load GSC for PM */ 229 intel_gsc_proxy_init(gsc); 230 231 intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_LOADABLE); 232 233 return 0; 234 235 out_vma: 236 gsc_unmap_and_free_vma(gsc); 237 out_fw: 238 intel_uc_fw_fini(&gsc->fw); 239 out: 240 gt_probe_error(gt, "GSC init failed %pe\n", ERR_PTR(err)); 241 return err; 242 } 243 244 void intel_gsc_uc_fini(struct intel_gsc_uc *gsc) 245 { 246 if (!intel_uc_fw_is_loadable(&gsc->fw)) 247 return; 248 249 flush_work(&gsc->work); 250 if (gsc->wq) { 251 destroy_workqueue(gsc->wq); 252 gsc->wq = NULL; 253 } 254 255 intel_gsc_proxy_fini(gsc); 256 257 if (gsc->ce) 258 intel_engine_destroy_pinned_context(fetch_and_zero(&gsc->ce)); 259 260 gsc_unmap_and_free_vma(gsc); 261 262 intel_uc_fw_fini(&gsc->fw); 263 } 264 265 void intel_gsc_uc_flush_work(struct intel_gsc_uc *gsc) 266 { 267 if (!intel_uc_fw_is_loadable(&gsc->fw)) 268 return; 269 270 flush_work(&gsc->work); 271 } 272 273 void intel_gsc_uc_resume(struct intel_gsc_uc *gsc) 274 { 275 if (!intel_uc_fw_is_loadable(&gsc->fw)) 276 return; 277 278 /* 279 * we only want to start the GSC worker from here in the actual resume 280 * flow and not during driver load. This is because GSC load is slow and 281 * therefore we want to make sure that the default state init completes 282 * first to not slow down the init thread. A separate call to 283 * intel_gsc_uc_load_start will ensure that the GSC is loaded during 284 * driver load. 285 */ 286 if (!gsc_uc_to_gt(gsc)->engine[GSC0]->default_state) 287 return; 288 289 intel_gsc_uc_load_start(gsc); 290 } 291 292 void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc) 293 { 294 struct intel_gt *gt = gsc_uc_to_gt(gsc); 295 296 if (!intel_uc_fw_is_loadable(&gsc->fw)) 297 return; 298 299 if (intel_gsc_uc_fw_init_done(gsc)) 300 return; 301 302 spin_lock_irq(gt->irq_lock); 303 gsc->gsc_work_actions |= GSC_ACTION_FW_LOAD; 304 spin_unlock_irq(gt->irq_lock); 305 306 queue_work(gsc->wq, &gsc->work); 307 } 308 309 void intel_gsc_uc_load_status(struct intel_gsc_uc *gsc, struct drm_printer *p) 310 { 311 struct intel_gt *gt = gsc_uc_to_gt(gsc); 312 struct intel_uncore *uncore = gt->uncore; 313 intel_wakeref_t wakeref; 314 315 if (!intel_gsc_uc_is_supported(gsc)) { 316 drm_printf(p, "GSC not supported\n"); 317 return; 318 } 319 320 if (!intel_gsc_uc_is_wanted(gsc)) { 321 drm_printf(p, "GSC disabled\n"); 322 return; 323 } 324 325 drm_printf(p, "GSC firmware: %s\n", gsc->fw.file_selected.path); 326 if (gsc->fw.file_selected.path != gsc->fw.file_wanted.path) 327 drm_printf(p, "GSC firmware wanted: %s\n", gsc->fw.file_wanted.path); 328 drm_printf(p, "\tstatus: %s\n", intel_uc_fw_status_repr(gsc->fw.status)); 329 330 drm_printf(p, "Release: %u.%u.%u.%u\n", 331 gsc->release.major, gsc->release.minor, 332 gsc->release.patch, gsc->release.build); 333 334 drm_printf(p, "Compatibility Version: %u.%u [min expected %u.%u]\n", 335 gsc->fw.file_selected.ver.major, gsc->fw.file_selected.ver.minor, 336 gsc->fw.file_wanted.ver.major, gsc->fw.file_wanted.ver.minor); 337 338 drm_printf(p, "SVN: %u\n", gsc->security_version); 339 340 with_intel_runtime_pm(uncore->rpm, wakeref) { 341 u32 i; 342 343 for (i = 1; i <= 6; i++) { 344 u32 status = intel_uncore_read(uncore, 345 HECI_FWSTS(MTL_GSC_HECI1_BASE, i)); 346 drm_printf(p, "HECI1 FWSTST%u = 0x%08x\n", i, status); 347 } 348 } 349 } 350