1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2014-2021 Intel Corporation
4  */
5 
6 #ifndef _ABI_GUC_ACTIONS_ABI_H
7 #define _ABI_GUC_ACTIONS_ABI_H
8 
9 /**
10  * DOC: HOST2GUC_REGISTER_CTB
11  *
12  * This message is used as part of the `CTB based communication`_ setup.
13  *
14  * This message must be sent as `MMIO HXG Message`_.
15  *
16  *  +---+-------+--------------------------------------------------------------+
17  *  |   | Bits  | Description                                                  |
18  *  +===+=======+==============================================================+
19  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
20  *  |   +-------+--------------------------------------------------------------+
21  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
22  *  |   +-------+--------------------------------------------------------------+
23  *  |   | 27:16 | DATA0 = MBZ                                                  |
24  *  |   +-------+--------------------------------------------------------------+
25  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_REGISTER_CTB` = 0x4505        |
26  *  +---+-------+--------------------------------------------------------------+
27  *  | 1 | 31:12 | RESERVED = MBZ                                               |
28  *  |   +-------+--------------------------------------------------------------+
29  *  |   |  11:8 | **TYPE** - type for the `CT Buffer`_                         |
30  *  |   |       |                                                              |
31  *  |   |       |   - _`GUC_CTB_TYPE_HOST2GUC` = 0                             |
32  *  |   |       |   - _`GUC_CTB_TYPE_GUC2HOST` = 1                             |
33  *  |   +-------+--------------------------------------------------------------+
34  *  |   |   7:0 | **SIZE** - size of the `CT Buffer`_ in 4K units minus 1      |
35  *  +---+-------+--------------------------------------------------------------+
36  *  | 2 |  31:0 | **DESC_ADDR** - GGTT address of the `CTB Descriptor`_        |
37  *  +---+-------+--------------------------------------------------------------+
38  *  | 3 |  31:0 | **BUFF_ADDF** - GGTT address of the `CT Buffer`_             |
39  *  +---+-------+--------------------------------------------------------------+
40  *
41  *  +---+-------+--------------------------------------------------------------+
42  *  |   | Bits  | Description                                                  |
43  *  +===+=======+==============================================================+
44  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
45  *  |   +-------+--------------------------------------------------------------+
46  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |
47  *  |   +-------+--------------------------------------------------------------+
48  *  |   |  27:0 | DATA0 = MBZ                                                  |
49  *  +---+-------+--------------------------------------------------------------+
50  */
51 #define GUC_ACTION_HOST2GUC_REGISTER_CTB		0x4505
52 
53 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
54 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0
55 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_MBZ		(0xfffff << 12)
56 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)
57 #define   GUC_CTB_TYPE_HOST2GUC				0u
58 #define   GUC_CTB_TYPE_GUC2HOST				1u
59 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_1_SIZE	(0xff << 0)
60 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_2_DESC_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn
61 #define HOST2GUC_REGISTER_CTB_REQUEST_MSG_3_BUFF_ADDR	GUC_HXG_REQUEST_MSG_n_DATAn
62 
63 #define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_LEN		GUC_HXG_RESPONSE_MSG_MIN_LEN
64 #define HOST2GUC_REGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0
65 
66 /**
67  * DOC: HOST2GUC_DEREGISTER_CTB
68  *
69  * This message is used as part of the `CTB based communication`_ teardown.
70  *
71  * This message must be sent as `MMIO HXG Message`_.
72  *
73  *  +---+-------+--------------------------------------------------------------+
74  *  |   | Bits  | Description                                                  |
75  *  +===+=======+==============================================================+
76  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_HOST_                                |
77  *  |   +-------+--------------------------------------------------------------+
78  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_REQUEST_                                 |
79  *  |   +-------+--------------------------------------------------------------+
80  *  |   | 27:16 | DATA0 = MBZ                                                  |
81  *  |   +-------+--------------------------------------------------------------+
82  *  |   |  15:0 | ACTION = _`GUC_ACTION_HOST2GUC_DEREGISTER_CTB` = 0x4506      |
83  *  +---+-------+--------------------------------------------------------------+
84  *  | 1 | 31:12 | RESERVED = MBZ                                               |
85  *  |   +-------+--------------------------------------------------------------+
86  *  |   |  11:8 | **TYPE** - type of the `CT Buffer`_                          |
87  *  |   |       |                                                              |
88  *  |   |       | see `GUC_ACTION_HOST2GUC_REGISTER_CTB`_                      |
89  *  |   +-------+--------------------------------------------------------------+
90  *  |   |   7:0 | RESERVED = MBZ                                               |
91  *  +---+-------+--------------------------------------------------------------+
92  *
93  *  +---+-------+--------------------------------------------------------------+
94  *  |   | Bits  | Description                                                  |
95  *  +===+=======+==============================================================+
96  *  | 0 |    31 | ORIGIN = GUC_HXG_ORIGIN_GUC_                                 |
97  *  |   +-------+--------------------------------------------------------------+
98  *  |   | 30:28 | TYPE = GUC_HXG_TYPE_RESPONSE_SUCCESS_                        |
99  *  |   +-------+--------------------------------------------------------------+
100  *  |   |  27:0 | DATA0 = MBZ                                                  |
101  *  +---+-------+--------------------------------------------------------------+
102  */
103 #define GUC_ACTION_HOST2GUC_DEREGISTER_CTB		0x4506
104 
105 #define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 1u)
106 #define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_0_MBZ	GUC_HXG_REQUEST_MSG_0_DATA0
107 #define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ	(0xfffff << 12)
108 #define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_TYPE	(0xf << 8)
109 #define HOST2GUC_DEREGISTER_CTB_REQUEST_MSG_1_MBZ2	(0xff << 0)
110 
111 #define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_LEN	GUC_HXG_RESPONSE_MSG_MIN_LEN
112 #define HOST2GUC_DEREGISTER_CTB_RESPONSE_MSG_0_MBZ	GUC_HXG_RESPONSE_MSG_0_DATA0
113 
114 /* legacy definitions */
115 
116 enum intel_guc_action {
117 	INTEL_GUC_ACTION_DEFAULT = 0x0,
118 	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
119 	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
120 	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
121 	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
122 	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
123 	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40,
124 	INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
125 	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
126 	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
127 	INTEL_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE = 0x506,
128 	INTEL_GUC_ACTION_SCHED_CONTEXT = 0x1000,
129 	INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_SET = 0x1001,
130 	INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
131 	INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
132 	INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
133 	INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
134 	INTEL_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
135 	INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
136 	INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
137 	INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
138 	INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
139 	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
140 	INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
141 	INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
142 	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
143 	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
144 	INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
145 	INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
146 	INTEL_GUC_ACTION_RESET_CLIENT = 0x5507,
147 	INTEL_GUC_ACTION_LIMIT
148 };
149 
150 enum intel_guc_rc_options {
151 	INTEL_GUCRC_HOST_CONTROL,
152 	INTEL_GUCRC_FIRMWARE_CONTROL,
153 };
154 
155 enum intel_guc_preempt_options {
156 	INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
157 	INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
158 };
159 
160 enum intel_guc_report_status {
161 	INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
162 	INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
163 	INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
164 	INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
165 };
166 
167 enum intel_guc_sleep_state_status {
168 	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
169 	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
170 	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
171 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
172 };
173 
174 #define GUC_LOG_CONTROL_LOGGING_ENABLED	(1 << 0)
175 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT	4
176 #define GUC_LOG_CONTROL_VERBOSITY_MASK	(0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
177 #define GUC_LOG_CONTROL_DEFAULT_LOGGING	(1 << 8)
178 
179 #endif /* _ABI_GUC_ACTIONS_ABI_H */
180