1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #define NUM_STEPS 5 7 #define H2G_DELAY 50000 8 #define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000) 9 #define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \ 10 GEN9_FREQ_SCALER) 11 enum test_type { 12 VARY_MIN, 13 VARY_MAX, 14 MAX_GRANTED 15 }; 16 17 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq) 18 { 19 int ret; 20 21 ret = intel_guc_slpc_set_min_freq(slpc, freq); 22 if (ret) 23 pr_err("Could not set min frequency to [%u]\n", freq); 24 else /* Delay to ensure h2g completes */ 25 delay_for_h2g(); 26 27 return ret; 28 } 29 30 static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq) 31 { 32 int ret; 33 34 ret = intel_guc_slpc_set_max_freq(slpc, freq); 35 if (ret) 36 pr_err("Could not set maximum frequency [%u]\n", 37 freq); 38 else /* Delay to ensure h2g completes */ 39 delay_for_h2g(); 40 41 return ret; 42 } 43 44 static int vary_max_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, 45 u32 *max_act_freq) 46 { 47 u32 step, max_freq, req_freq; 48 u32 act_freq; 49 int err = 0; 50 51 /* Go from max to min in 5 steps */ 52 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS; 53 *max_act_freq = slpc->min_freq; 54 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq; 55 max_freq -= step) { 56 err = slpc_set_max_freq(slpc, max_freq); 57 if (err) 58 break; 59 60 req_freq = intel_rps_read_punit_req_frequency(rps); 61 62 /* GuC requests freq in multiples of 50/3 MHz */ 63 if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) { 64 pr_err("SWReq is %d, should be at most %d\n", req_freq, 65 max_freq + FREQUENCY_REQ_UNIT); 66 err = -EINVAL; 67 } 68 69 act_freq = intel_rps_read_actual_frequency(rps); 70 if (act_freq > *max_act_freq) 71 *max_act_freq = act_freq; 72 73 if (err) 74 break; 75 } 76 77 return err; 78 } 79 80 static int vary_min_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, 81 u32 *max_act_freq) 82 { 83 u32 step, min_freq, req_freq; 84 u32 act_freq; 85 int err = 0; 86 87 /* Go from min to max in 5 steps */ 88 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS; 89 *max_act_freq = slpc->min_freq; 90 for (min_freq = slpc->min_freq; min_freq < slpc->rp0_freq; 91 min_freq += step) { 92 err = slpc_set_min_freq(slpc, min_freq); 93 if (err) 94 break; 95 96 req_freq = intel_rps_read_punit_req_frequency(rps); 97 98 /* GuC requests freq in multiples of 50/3 MHz */ 99 if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) { 100 pr_err("SWReq is %d, should be at least %d\n", req_freq, 101 min_freq - FREQUENCY_REQ_UNIT); 102 err = -EINVAL; 103 } 104 105 act_freq = intel_rps_read_actual_frequency(rps); 106 if (act_freq > *max_act_freq) 107 *max_act_freq = act_freq; 108 109 if (err) 110 break; 111 } 112 113 return err; 114 } 115 116 static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq) 117 { 118 struct intel_gt *gt = rps_to_gt(rps); 119 u32 perf_limit_reasons; 120 int err = 0; 121 122 err = slpc_set_min_freq(slpc, slpc->rp0_freq); 123 if (err) 124 return err; 125 126 *max_act_freq = intel_rps_read_actual_frequency(rps); 127 if (*max_act_freq != slpc->rp0_freq) { 128 /* Check if there was some throttling by pcode */ 129 perf_limit_reasons = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS); 130 131 /* If not, this is an error */ 132 if (!(perf_limit_reasons & GT0_PERF_LIMIT_REASONS_MASK)) { 133 pr_err("Pcode did not grant max freq\n"); 134 err = -EINVAL; 135 } else { 136 pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons); 137 } 138 } 139 140 return err; 141 } 142 143 static int run_test(struct intel_gt *gt, int test_type) 144 { 145 struct intel_guc_slpc *slpc = >->uc.guc.slpc; 146 struct intel_rps *rps = >->rps; 147 struct intel_engine_cs *engine; 148 enum intel_engine_id id; 149 struct igt_spinner spin; 150 u32 slpc_min_freq, slpc_max_freq; 151 int err = 0; 152 153 if (!intel_uc_uses_guc_slpc(>->uc)) 154 return 0; 155 156 if (igt_spinner_init(&spin, gt)) 157 return -ENOMEM; 158 159 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) { 160 pr_err("Could not get SLPC max freq\n"); 161 return -EIO; 162 } 163 164 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) { 165 pr_err("Could not get SLPC min freq\n"); 166 return -EIO; 167 } 168 169 if (slpc->min_freq == slpc->rp0_freq) { 170 pr_err("Min/Max are fused to the same value\n"); 171 return -EINVAL; 172 } 173 174 intel_gt_pm_wait_for_idle(gt); 175 intel_gt_pm_get(gt); 176 for_each_engine(engine, gt, id) { 177 struct i915_request *rq; 178 u32 max_act_freq; 179 180 if (!intel_engine_can_store_dword(engine)) 181 continue; 182 183 st_engine_heartbeat_disable(engine); 184 185 rq = igt_spinner_create_request(&spin, 186 engine->kernel_context, 187 MI_NOOP); 188 if (IS_ERR(rq)) { 189 err = PTR_ERR(rq); 190 st_engine_heartbeat_enable(engine); 191 break; 192 } 193 194 i915_request_add(rq); 195 196 if (!igt_wait_for_spinner(&spin, rq)) { 197 pr_err("%s: Spinner did not start\n", 198 engine->name); 199 igt_spinner_end(&spin); 200 st_engine_heartbeat_enable(engine); 201 intel_gt_set_wedged(engine->gt); 202 err = -EIO; 203 break; 204 } 205 206 switch (test_type) { 207 case VARY_MIN: 208 err = vary_min_freq(slpc, rps, &max_act_freq); 209 break; 210 211 case VARY_MAX: 212 err = vary_max_freq(slpc, rps, &max_act_freq); 213 break; 214 215 case MAX_GRANTED: 216 /* Media engines have a different RP0 */ 217 if (engine->class == VIDEO_DECODE_CLASS || 218 engine->class == VIDEO_ENHANCEMENT_CLASS) { 219 igt_spinner_end(&spin); 220 st_engine_heartbeat_enable(engine); 221 err = 0; 222 continue; 223 } 224 225 err = max_granted_freq(slpc, rps, &max_act_freq); 226 break; 227 } 228 229 pr_info("Max actual frequency for %s was %d\n", 230 engine->name, max_act_freq); 231 232 /* Actual frequency should rise above min */ 233 if (max_act_freq <= slpc_min_freq) { 234 pr_err("Actual freq did not rise above min\n"); 235 pr_err("Perf Limit Reasons: 0x%x\n", 236 intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS)); 237 err = -EINVAL; 238 } 239 240 igt_spinner_end(&spin); 241 st_engine_heartbeat_enable(engine); 242 243 if (err) 244 break; 245 } 246 247 /* Restore min/max frequencies */ 248 slpc_set_max_freq(slpc, slpc_max_freq); 249 slpc_set_min_freq(slpc, slpc_min_freq); 250 251 if (igt_flush_test(gt->i915)) 252 err = -EIO; 253 254 intel_gt_pm_put(gt); 255 igt_spinner_fini(&spin); 256 intel_gt_pm_wait_for_idle(gt); 257 258 return err; 259 } 260 261 static int live_slpc_vary_min(void *arg) 262 { 263 struct drm_i915_private *i915 = arg; 264 struct intel_gt *gt = to_gt(i915); 265 266 return run_test(gt, VARY_MIN); 267 } 268 269 static int live_slpc_vary_max(void *arg) 270 { 271 struct drm_i915_private *i915 = arg; 272 struct intel_gt *gt = to_gt(i915); 273 274 return run_test(gt, VARY_MAX); 275 } 276 277 /* check if pcode can grant RP0 */ 278 static int live_slpc_max_granted(void *arg) 279 { 280 struct drm_i915_private *i915 = arg; 281 struct intel_gt *gt = to_gt(i915); 282 283 return run_test(gt, MAX_GRANTED); 284 } 285 286 int intel_slpc_live_selftests(struct drm_i915_private *i915) 287 { 288 static const struct i915_subtest tests[] = { 289 SUBTEST(live_slpc_vary_max), 290 SUBTEST(live_slpc_vary_min), 291 SUBTEST(live_slpc_max_granted), 292 }; 293 294 if (intel_gt_is_wedged(to_gt(i915))) 295 return 0; 296 297 return i915_live_subtests(tests, i915); 298 } 299