1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #define NUM_STEPS 5 7 #define H2G_DELAY 50000 8 #define delay_for_h2g() usleep_range(H2G_DELAY, H2G_DELAY + 10000) 9 #define FREQUENCY_REQ_UNIT DIV_ROUND_CLOSEST(GT_FREQUENCY_MULTIPLIER, \ 10 GEN9_FREQ_SCALER) 11 enum test_type { 12 VARY_MIN, 13 VARY_MAX, 14 MAX_GRANTED, 15 SLPC_POWER, 16 }; 17 18 static int slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 freq) 19 { 20 int ret; 21 22 ret = intel_guc_slpc_set_min_freq(slpc, freq); 23 if (ret) 24 pr_err("Could not set min frequency to [%u]\n", freq); 25 else /* Delay to ensure h2g completes */ 26 delay_for_h2g(); 27 28 return ret; 29 } 30 31 static int slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 freq) 32 { 33 int ret; 34 35 ret = intel_guc_slpc_set_max_freq(slpc, freq); 36 if (ret) 37 pr_err("Could not set maximum frequency [%u]\n", 38 freq); 39 else /* Delay to ensure h2g completes */ 40 delay_for_h2g(); 41 42 return ret; 43 } 44 45 static int slpc_set_freq(struct intel_gt *gt, u32 freq) 46 { 47 int err; 48 struct intel_guc_slpc *slpc = >->uc.guc.slpc; 49 50 err = slpc_set_max_freq(slpc, freq); 51 if (err) { 52 pr_err("Unable to update max freq"); 53 return err; 54 } 55 56 err = slpc_set_min_freq(slpc, freq); 57 if (err) { 58 pr_err("Unable to update min freq"); 59 return err; 60 } 61 62 return err; 63 } 64 65 static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power) 66 { 67 int err = 0; 68 69 err = slpc_set_freq(gt, *freq); 70 if (err) 71 return err; 72 *freq = intel_rps_read_actual_frequency(>->rps); 73 *power = measure_power(>->rps, freq); 74 75 return err; 76 } 77 78 static int vary_max_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, 79 u32 *max_act_freq) 80 { 81 u32 step, max_freq, req_freq; 82 u32 act_freq; 83 int err = 0; 84 85 /* Go from max to min in 5 steps */ 86 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS; 87 *max_act_freq = slpc->min_freq; 88 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq; 89 max_freq -= step) { 90 err = slpc_set_max_freq(slpc, max_freq); 91 if (err) 92 break; 93 94 req_freq = intel_rps_read_punit_req_frequency(rps); 95 96 /* GuC requests freq in multiples of 50/3 MHz */ 97 if (req_freq > (max_freq + FREQUENCY_REQ_UNIT)) { 98 pr_err("SWReq is %d, should be at most %d\n", req_freq, 99 max_freq + FREQUENCY_REQ_UNIT); 100 err = -EINVAL; 101 } 102 103 act_freq = intel_rps_read_actual_frequency(rps); 104 if (act_freq > *max_act_freq) 105 *max_act_freq = act_freq; 106 107 if (err) 108 break; 109 } 110 111 return err; 112 } 113 114 static int vary_min_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, 115 u32 *max_act_freq) 116 { 117 u32 step, min_freq, req_freq; 118 u32 act_freq; 119 int err = 0; 120 121 /* Go from min to max in 5 steps */ 122 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS; 123 *max_act_freq = slpc->min_freq; 124 for (min_freq = slpc->min_freq; min_freq < slpc->rp0_freq; 125 min_freq += step) { 126 err = slpc_set_min_freq(slpc, min_freq); 127 if (err) 128 break; 129 130 req_freq = intel_rps_read_punit_req_frequency(rps); 131 132 /* GuC requests freq in multiples of 50/3 MHz */ 133 if (req_freq < (min_freq - FREQUENCY_REQ_UNIT)) { 134 pr_err("SWReq is %d, should be at least %d\n", req_freq, 135 min_freq - FREQUENCY_REQ_UNIT); 136 err = -EINVAL; 137 } 138 139 act_freq = intel_rps_read_actual_frequency(rps); 140 if (act_freq > *max_act_freq) 141 *max_act_freq = act_freq; 142 143 if (err) 144 break; 145 } 146 147 return err; 148 } 149 150 static int slpc_power(struct intel_gt *gt, struct intel_engine_cs *engine) 151 { 152 struct intel_guc_slpc *slpc = >->uc.guc.slpc; 153 struct { 154 u64 power; 155 int freq; 156 } min, max; 157 int err = 0; 158 159 /* 160 * Our fundamental assumption is that running at lower frequency 161 * actually saves power. Let's see if our RAPL measurement supports 162 * that theory. 163 */ 164 if (!librapl_supported(gt->i915)) 165 return 0; 166 167 min.freq = slpc->min_freq; 168 err = measure_power_at_freq(gt, &min.freq, &min.power); 169 170 if (err) 171 return err; 172 173 max.freq = slpc->rp0_freq; 174 err = measure_power_at_freq(gt, &max.freq, &max.power); 175 176 if (err) 177 return err; 178 179 pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n", 180 engine->name, 181 min.power, min.freq, 182 max.power, max.freq); 183 184 if (10 * min.freq >= 9 * max.freq) { 185 pr_notice("Could not control frequency, ran at [%uMHz, %uMhz]\n", 186 min.freq, max.freq); 187 } 188 189 if (11 * min.power > 10 * max.power) { 190 pr_err("%s: did not conserve power when setting lower frequency!\n", 191 engine->name); 192 err = -EINVAL; 193 } 194 195 /* Restore min/max frequencies */ 196 slpc_set_max_freq(slpc, slpc->rp0_freq); 197 slpc_set_min_freq(slpc, slpc->min_freq); 198 199 return err; 200 } 201 202 static int max_granted_freq(struct intel_guc_slpc *slpc, struct intel_rps *rps, u32 *max_act_freq) 203 { 204 struct intel_gt *gt = rps_to_gt(rps); 205 u32 perf_limit_reasons; 206 int err = 0; 207 208 err = slpc_set_min_freq(slpc, slpc->rp0_freq); 209 if (err) 210 return err; 211 212 *max_act_freq = intel_rps_read_actual_frequency(rps); 213 if (*max_act_freq != slpc->rp0_freq) { 214 /* Check if there was some throttling by pcode */ 215 perf_limit_reasons = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS); 216 217 /* If not, this is an error */ 218 if (!(perf_limit_reasons & GT0_PERF_LIMIT_REASONS_MASK)) { 219 pr_err("Pcode did not grant max freq\n"); 220 err = -EINVAL; 221 } else { 222 pr_info("Pcode throttled frequency 0x%x\n", perf_limit_reasons); 223 } 224 } 225 226 return err; 227 } 228 229 static int run_test(struct intel_gt *gt, int test_type) 230 { 231 struct intel_guc_slpc *slpc = >->uc.guc.slpc; 232 struct intel_rps *rps = >->rps; 233 struct intel_engine_cs *engine; 234 enum intel_engine_id id; 235 struct igt_spinner spin; 236 u32 slpc_min_freq, slpc_max_freq; 237 int err = 0; 238 239 if (!intel_uc_uses_guc_slpc(>->uc)) 240 return 0; 241 242 if (slpc->min_freq == slpc->rp0_freq) { 243 pr_err("Min/Max are fused to the same value\n"); 244 return -EINVAL; 245 } 246 247 if (igt_spinner_init(&spin, gt)) 248 return -ENOMEM; 249 250 if (intel_guc_slpc_get_max_freq(slpc, &slpc_max_freq)) { 251 pr_err("Could not get SLPC max freq\n"); 252 return -EIO; 253 } 254 255 if (intel_guc_slpc_get_min_freq(slpc, &slpc_min_freq)) { 256 pr_err("Could not get SLPC min freq\n"); 257 return -EIO; 258 } 259 260 /* 261 * Set min frequency to RPn so that we can test the whole 262 * range of RPn-RP0. This also turns off efficient freq 263 * usage and makes results more predictable. 264 */ 265 err = slpc_set_min_freq(slpc, slpc->min_freq); 266 if (err) { 267 pr_err("Unable to update min freq!"); 268 return err; 269 } 270 271 intel_gt_pm_wait_for_idle(gt); 272 intel_gt_pm_get(gt); 273 for_each_engine(engine, gt, id) { 274 struct i915_request *rq; 275 u32 max_act_freq; 276 277 if (!intel_engine_can_store_dword(engine)) 278 continue; 279 280 st_engine_heartbeat_disable(engine); 281 282 rq = igt_spinner_create_request(&spin, 283 engine->kernel_context, 284 MI_NOOP); 285 if (IS_ERR(rq)) { 286 err = PTR_ERR(rq); 287 st_engine_heartbeat_enable(engine); 288 break; 289 } 290 291 i915_request_add(rq); 292 293 if (!igt_wait_for_spinner(&spin, rq)) { 294 pr_err("%s: Spinner did not start\n", 295 engine->name); 296 igt_spinner_end(&spin); 297 st_engine_heartbeat_enable(engine); 298 intel_gt_set_wedged(engine->gt); 299 err = -EIO; 300 break; 301 } 302 303 switch (test_type) { 304 case VARY_MIN: 305 err = vary_min_freq(slpc, rps, &max_act_freq); 306 break; 307 308 case VARY_MAX: 309 err = vary_max_freq(slpc, rps, &max_act_freq); 310 break; 311 312 case MAX_GRANTED: 313 /* Media engines have a different RP0 */ 314 if (engine->class == VIDEO_DECODE_CLASS || 315 engine->class == VIDEO_ENHANCEMENT_CLASS) { 316 igt_spinner_end(&spin); 317 st_engine_heartbeat_enable(engine); 318 err = 0; 319 continue; 320 } 321 322 err = max_granted_freq(slpc, rps, &max_act_freq); 323 break; 324 325 case SLPC_POWER: 326 err = slpc_power(gt, engine); 327 break; 328 } 329 330 if (test_type != SLPC_POWER) { 331 pr_info("Max actual frequency for %s was %d\n", 332 engine->name, max_act_freq); 333 334 /* Actual frequency should rise above min */ 335 if (max_act_freq <= slpc->min_freq) { 336 pr_err("Actual freq did not rise above min\n"); 337 pr_err("Perf Limit Reasons: 0x%x\n", 338 intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS)); 339 err = -EINVAL; 340 } 341 } 342 343 igt_spinner_end(&spin); 344 st_engine_heartbeat_enable(engine); 345 346 if (err) 347 break; 348 } 349 350 /* Restore min/max frequencies */ 351 slpc_set_max_freq(slpc, slpc_max_freq); 352 slpc_set_min_freq(slpc, slpc_min_freq); 353 354 if (igt_flush_test(gt->i915)) 355 err = -EIO; 356 357 intel_gt_pm_put(gt); 358 igt_spinner_fini(&spin); 359 intel_gt_pm_wait_for_idle(gt); 360 361 return err; 362 } 363 364 static int live_slpc_vary_min(void *arg) 365 { 366 struct drm_i915_private *i915 = arg; 367 struct intel_gt *gt; 368 unsigned int i; 369 int ret; 370 371 for_each_gt(gt, i915, i) { 372 ret = run_test(gt, VARY_MIN); 373 if (ret) 374 return ret; 375 } 376 377 return ret; 378 } 379 380 static int live_slpc_vary_max(void *arg) 381 { 382 struct drm_i915_private *i915 = arg; 383 struct intel_gt *gt; 384 unsigned int i; 385 int ret; 386 387 for_each_gt(gt, i915, i) { 388 ret = run_test(gt, VARY_MAX); 389 if (ret) 390 return ret; 391 } 392 393 return ret; 394 } 395 396 /* check if pcode can grant RP0 */ 397 static int live_slpc_max_granted(void *arg) 398 { 399 struct drm_i915_private *i915 = arg; 400 struct intel_gt *gt; 401 unsigned int i; 402 int ret; 403 404 for_each_gt(gt, i915, i) { 405 ret = run_test(gt, MAX_GRANTED); 406 if (ret) 407 return ret; 408 } 409 410 return ret; 411 } 412 413 static int live_slpc_power(void *arg) 414 { 415 struct drm_i915_private *i915 = arg; 416 struct intel_gt *gt; 417 unsigned int i; 418 int ret; 419 420 for_each_gt(gt, i915, i) { 421 ret = run_test(gt, SLPC_POWER); 422 if (ret) 423 return ret; 424 } 425 426 return ret; 427 } 428 429 int intel_slpc_live_selftests(struct drm_i915_private *i915) 430 { 431 static const struct i915_subtest tests[] = { 432 SUBTEST(live_slpc_vary_max), 433 SUBTEST(live_slpc_vary_min), 434 SUBTEST(live_slpc_max_granted), 435 SUBTEST(live_slpc_power), 436 }; 437 438 struct intel_gt *gt; 439 unsigned int i; 440 441 for_each_gt(gt, i915, i) { 442 if (intel_gt_is_wedged(gt)) 443 return 0; 444 } 445 446 return i915_live_subtests(tests, i915); 447 } 448