1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include "gt/intel_engine_pm.h" 7 #include "gt/intel_gpu_commands.h" 8 #include "i915_selftest.h" 9 10 #include "gem/selftests/mock_context.h" 11 #include "selftests/igt_reset.h" 12 #include "selftests/igt_spinner.h" 13 14 struct live_mocs { 15 struct drm_i915_mocs_table table; 16 struct drm_i915_mocs_table *mocs; 17 struct drm_i915_mocs_table *l3cc; 18 struct i915_vma *scratch; 19 void *vaddr; 20 }; 21 22 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) 23 { 24 struct intel_context *ce; 25 26 ce = intel_context_create(engine); 27 if (IS_ERR(ce)) 28 return ce; 29 30 /* We build large requests to read the registers from the ring */ 31 ce->ring_size = SZ_16K; 32 33 return ce; 34 } 35 36 static int request_add_sync(struct i915_request *rq, int err) 37 { 38 i915_request_get(rq); 39 i915_request_add(rq); 40 if (i915_request_wait(rq, 0, HZ / 5) < 0) 41 err = -ETIME; 42 i915_request_put(rq); 43 44 return err; 45 } 46 47 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) 48 { 49 int err = 0; 50 51 i915_request_get(rq); 52 i915_request_add(rq); 53 if (spin && !igt_wait_for_spinner(spin, rq)) 54 err = -ETIME; 55 i915_request_put(rq); 56 57 return err; 58 } 59 60 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt) 61 { 62 unsigned int flags; 63 int err; 64 65 memset(arg, 0, sizeof(*arg)); 66 67 flags = get_mocs_settings(gt->i915, &arg->table); 68 if (!flags) 69 return -EINVAL; 70 71 if (flags & HAS_RENDER_L3CC) 72 arg->l3cc = &arg->table; 73 74 if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS)) 75 arg->mocs = &arg->table; 76 77 arg->scratch = 78 __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE); 79 if (IS_ERR(arg->scratch)) 80 return PTR_ERR(arg->scratch); 81 82 arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB); 83 if (IS_ERR(arg->vaddr)) { 84 err = PTR_ERR(arg->vaddr); 85 goto err_scratch; 86 } 87 88 return 0; 89 90 err_scratch: 91 i915_vma_unpin_and_release(&arg->scratch, 0); 92 return err; 93 } 94 95 static void live_mocs_fini(struct live_mocs *arg) 96 { 97 i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP); 98 } 99 100 static int read_regs(struct i915_request *rq, 101 u32 addr, unsigned int count, 102 u32 *offset) 103 { 104 unsigned int i; 105 u32 *cs; 106 107 GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32))); 108 109 cs = intel_ring_begin(rq, 4 * count); 110 if (IS_ERR(cs)) 111 return PTR_ERR(cs); 112 113 for (i = 0; i < count; i++) { 114 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; 115 *cs++ = addr; 116 *cs++ = *offset; 117 *cs++ = 0; 118 119 addr += sizeof(u32); 120 *offset += sizeof(u32); 121 } 122 123 intel_ring_advance(rq, cs); 124 125 return 0; 126 } 127 128 static int read_mocs_table(struct i915_request *rq, 129 const struct drm_i915_mocs_table *table, 130 u32 *offset) 131 { 132 u32 addr; 133 134 if (!table) 135 return 0; 136 137 if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) 138 addr = global_mocs_offset(); 139 else 140 addr = mocs_offset(rq->engine); 141 142 return read_regs(rq, addr, table->n_entries, offset); 143 } 144 145 static int read_l3cc_table(struct i915_request *rq, 146 const struct drm_i915_mocs_table *table, 147 u32 *offset) 148 { 149 u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 150 151 if (!table) 152 return 0; 153 154 return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); 155 } 156 157 static int check_mocs_table(struct intel_engine_cs *engine, 158 const struct drm_i915_mocs_table *table, 159 u32 **vaddr) 160 { 161 unsigned int i; 162 u32 expect; 163 164 if (!table) 165 return 0; 166 167 for_each_mocs(expect, table, i) { 168 if (**vaddr != expect) { 169 pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n", 170 engine->name, i, **vaddr, expect); 171 return -EINVAL; 172 } 173 ++*vaddr; 174 } 175 176 return 0; 177 } 178 179 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 180 { 181 /* 182 * Registers in this range are affected by the MCR selector 183 * which only controls CPU initiated MMIO. Routing does not 184 * work for CS access so we cannot verify them on this path. 185 */ 186 return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff; 187 } 188 189 static int check_l3cc_table(struct intel_engine_cs *engine, 190 const struct drm_i915_mocs_table *table, 191 u32 **vaddr) 192 { 193 /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */ 194 u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 195 unsigned int i; 196 u32 expect; 197 198 if (!table) 199 return 0; 200 201 for_each_l3cc(expect, table, i) { 202 if (!mcr_range(engine->i915, reg) && **vaddr != expect) { 203 pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n", 204 engine->name, i, **vaddr, expect); 205 return -EINVAL; 206 } 207 ++*vaddr; 208 reg += 4; 209 } 210 211 return 0; 212 } 213 214 static int check_mocs_engine(struct live_mocs *arg, 215 struct intel_context *ce) 216 { 217 struct i915_vma *vma = arg->scratch; 218 struct i915_request *rq; 219 u32 offset; 220 u32 *vaddr; 221 int err; 222 223 memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); 224 225 rq = intel_context_create_request(ce); 226 if (IS_ERR(rq)) 227 return PTR_ERR(rq); 228 229 i915_vma_lock(vma); 230 err = i915_request_await_object(rq, vma->obj, true); 231 if (!err) 232 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 233 i915_vma_unlock(vma); 234 235 /* Read the mocs tables back using SRM */ 236 offset = i915_ggtt_offset(vma); 237 if (!err) 238 err = read_mocs_table(rq, arg->mocs, &offset); 239 if (!err && ce->engine->class == RENDER_CLASS) 240 err = read_l3cc_table(rq, arg->l3cc, &offset); 241 offset -= i915_ggtt_offset(vma); 242 GEM_BUG_ON(offset > PAGE_SIZE); 243 244 err = request_add_sync(rq, err); 245 if (err) 246 return err; 247 248 /* Compare the results against the expected tables */ 249 vaddr = arg->vaddr; 250 if (!err) 251 err = check_mocs_table(ce->engine, arg->mocs, &vaddr); 252 if (!err && ce->engine->class == RENDER_CLASS) 253 err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); 254 if (err) 255 return err; 256 257 GEM_BUG_ON(arg->vaddr + offset != vaddr); 258 return 0; 259 } 260 261 static int live_mocs_kernel(void *arg) 262 { 263 struct intel_gt *gt = arg; 264 struct intel_engine_cs *engine; 265 enum intel_engine_id id; 266 struct live_mocs mocs; 267 int err; 268 269 /* Basic check the system is configured with the expected mocs table */ 270 271 err = live_mocs_init(&mocs, gt); 272 if (err) 273 return err; 274 275 for_each_engine(engine, gt, id) { 276 intel_engine_pm_get(engine); 277 err = check_mocs_engine(&mocs, engine->kernel_context); 278 intel_engine_pm_put(engine); 279 if (err) 280 break; 281 } 282 283 live_mocs_fini(&mocs); 284 return err; 285 } 286 287 static int live_mocs_clean(void *arg) 288 { 289 struct intel_gt *gt = arg; 290 struct intel_engine_cs *engine; 291 enum intel_engine_id id; 292 struct live_mocs mocs; 293 int err; 294 295 /* Every new context should see the same mocs table */ 296 297 err = live_mocs_init(&mocs, gt); 298 if (err) 299 return err; 300 301 for_each_engine(engine, gt, id) { 302 struct intel_context *ce; 303 304 ce = mocs_context_create(engine); 305 if (IS_ERR(ce)) { 306 err = PTR_ERR(ce); 307 break; 308 } 309 310 err = check_mocs_engine(&mocs, ce); 311 intel_context_put(ce); 312 if (err) 313 break; 314 } 315 316 live_mocs_fini(&mocs); 317 return err; 318 } 319 320 static int active_engine_reset(struct intel_context *ce, 321 const char *reason) 322 { 323 struct igt_spinner spin; 324 struct i915_request *rq; 325 int err; 326 327 err = igt_spinner_init(&spin, ce->engine->gt); 328 if (err) 329 return err; 330 331 rq = igt_spinner_create_request(&spin, ce, MI_NOOP); 332 if (IS_ERR(rq)) { 333 igt_spinner_fini(&spin); 334 return PTR_ERR(rq); 335 } 336 337 err = request_add_spin(rq, &spin); 338 if (err == 0) 339 err = intel_engine_reset(ce->engine, reason); 340 341 igt_spinner_end(&spin); 342 igt_spinner_fini(&spin); 343 344 return err; 345 } 346 347 static int __live_mocs_reset(struct live_mocs *mocs, 348 struct intel_context *ce) 349 { 350 struct intel_gt *gt = ce->engine->gt; 351 int err; 352 353 if (intel_has_reset_engine(gt)) { 354 err = intel_engine_reset(ce->engine, "mocs"); 355 if (err) 356 return err; 357 358 err = check_mocs_engine(mocs, ce); 359 if (err) 360 return err; 361 362 err = active_engine_reset(ce, "mocs"); 363 if (err) 364 return err; 365 366 err = check_mocs_engine(mocs, ce); 367 if (err) 368 return err; 369 } 370 371 if (intel_has_gpu_reset(gt)) { 372 intel_gt_reset(gt, ce->engine->mask, "mocs"); 373 374 err = check_mocs_engine(mocs, ce); 375 if (err) 376 return err; 377 } 378 379 return 0; 380 } 381 382 static int live_mocs_reset(void *arg) 383 { 384 struct intel_gt *gt = arg; 385 struct intel_engine_cs *engine; 386 enum intel_engine_id id; 387 struct live_mocs mocs; 388 int err = 0; 389 390 /* Check the mocs setup is retained over per-engine and global resets */ 391 392 err = live_mocs_init(&mocs, gt); 393 if (err) 394 return err; 395 396 igt_global_reset_lock(gt); 397 for_each_engine(engine, gt, id) { 398 struct intel_context *ce; 399 400 ce = mocs_context_create(engine); 401 if (IS_ERR(ce)) { 402 err = PTR_ERR(ce); 403 break; 404 } 405 406 intel_engine_pm_get(engine); 407 err = __live_mocs_reset(&mocs, ce); 408 intel_engine_pm_put(engine); 409 410 intel_context_put(ce); 411 if (err) 412 break; 413 } 414 igt_global_reset_unlock(gt); 415 416 live_mocs_fini(&mocs); 417 return err; 418 } 419 420 int intel_mocs_live_selftests(struct drm_i915_private *i915) 421 { 422 static const struct i915_subtest tests[] = { 423 SUBTEST(live_mocs_kernel), 424 SUBTEST(live_mocs_clean), 425 SUBTEST(live_mocs_reset), 426 }; 427 struct drm_i915_mocs_table table; 428 429 if (!get_mocs_settings(i915, &table)) 430 return 0; 431 432 return intel_gt_live_subtests(tests, &i915->gt); 433 } 434