1 /*
2  * SPDX-License-Identifier: MIT
3  *
4  * Copyright © 2019 Intel Corporation
5  */
6 
7 #include "gt/intel_engine_pm.h"
8 #include "gt/intel_gpu_commands.h"
9 #include "i915_selftest.h"
10 
11 #include "gem/selftests/mock_context.h"
12 #include "selftests/igt_reset.h"
13 #include "selftests/igt_spinner.h"
14 
15 struct live_mocs {
16 	struct drm_i915_mocs_table mocs;
17 	struct drm_i915_mocs_table l3cc;
18 	struct i915_vma *scratch;
19 	void *vaddr;
20 };
21 
22 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)
23 {
24 	struct intel_context *ce;
25 
26 	ce = intel_context_create(engine);
27 	if (IS_ERR(ce))
28 		return ce;
29 
30 	/* We build large requests to read the registers from the ring */
31 	ce->ring = __intel_context_ring_size(SZ_16K);
32 
33 	return ce;
34 }
35 
36 static int request_add_sync(struct i915_request *rq, int err)
37 {
38 	i915_request_get(rq);
39 	i915_request_add(rq);
40 	if (i915_request_wait(rq, 0, HZ / 5) < 0)
41 		err = -ETIME;
42 	i915_request_put(rq);
43 
44 	return err;
45 }
46 
47 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
48 {
49 	int err = 0;
50 
51 	i915_request_get(rq);
52 	i915_request_add(rq);
53 	if (spin && !igt_wait_for_spinner(spin, rq))
54 		err = -ETIME;
55 	i915_request_put(rq);
56 
57 	return err;
58 }
59 
60 static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
61 {
62 	struct drm_i915_mocs_table table;
63 	unsigned int flags;
64 	int err;
65 
66 	memset(arg, 0, sizeof(*arg));
67 
68 	flags = get_mocs_settings(gt->i915, &table);
69 	if (!flags)
70 		return -EINVAL;
71 
72 	if (flags & HAS_RENDER_L3CC)
73 		arg->l3cc = table;
74 
75 	if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
76 		arg->mocs = table;
77 
78 	arg->scratch = __vm_create_scratch_for_read(&gt->ggtt->vm, PAGE_SIZE);
79 	if (IS_ERR(arg->scratch))
80 		return PTR_ERR(arg->scratch);
81 
82 	arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
83 	if (IS_ERR(arg->vaddr)) {
84 		err = PTR_ERR(arg->vaddr);
85 		goto err_scratch;
86 	}
87 
88 	return 0;
89 
90 err_scratch:
91 	i915_vma_unpin_and_release(&arg->scratch, 0);
92 	return err;
93 }
94 
95 static void live_mocs_fini(struct live_mocs *arg)
96 {
97 	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
98 }
99 
100 static int read_regs(struct i915_request *rq,
101 		     u32 addr, unsigned int count,
102 		     u32 *offset)
103 {
104 	unsigned int i;
105 	u32 *cs;
106 
107 	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
108 
109 	cs = intel_ring_begin(rq, 4 * count);
110 	if (IS_ERR(cs))
111 		return PTR_ERR(cs);
112 
113 	for (i = 0; i < count; i++) {
114 		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
115 		*cs++ = addr;
116 		*cs++ = *offset;
117 		*cs++ = 0;
118 
119 		addr += sizeof(u32);
120 		*offset += sizeof(u32);
121 	}
122 
123 	intel_ring_advance(rq, cs);
124 
125 	return 0;
126 }
127 
128 static int read_mocs_table(struct i915_request *rq,
129 			   const struct drm_i915_mocs_table *table,
130 			   u32 *offset)
131 {
132 	u32 addr;
133 
134 	if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
135 		addr = global_mocs_offset();
136 	else
137 		addr = mocs_offset(rq->engine);
138 
139 	return read_regs(rq, addr, table->n_entries, offset);
140 }
141 
142 static int read_l3cc_table(struct i915_request *rq,
143 			   const struct drm_i915_mocs_table *table,
144 			   u32 *offset)
145 {
146 	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
147 
148 	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
149 }
150 
151 static int check_mocs_table(struct intel_engine_cs *engine,
152 			    const struct drm_i915_mocs_table *table,
153 			    u32 **vaddr)
154 {
155 	unsigned int i;
156 	u32 expect;
157 
158 	for_each_mocs(expect, table, i) {
159 		if (**vaddr != expect) {
160 			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
161 			       engine->name, i, **vaddr, expect);
162 			return -EINVAL;
163 		}
164 		++*vaddr;
165 	}
166 
167 	return 0;
168 }
169 
170 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
171 {
172 	/*
173 	 * Registers in this range are affected by the MCR selector
174 	 * which only controls CPU initiated MMIO. Routing does not
175 	 * work for CS access so we cannot verify them on this path.
176 	 */
177 	return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
178 }
179 
180 static int check_l3cc_table(struct intel_engine_cs *engine,
181 			    const struct drm_i915_mocs_table *table,
182 			    u32 **vaddr)
183 {
184 	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
185 	u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
186 	unsigned int i;
187 	u32 expect;
188 
189 	for_each_l3cc(expect, table, i) {
190 		if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
191 			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
192 			       engine->name, i, **vaddr, expect);
193 			return -EINVAL;
194 		}
195 		++*vaddr;
196 		reg += 4;
197 	}
198 
199 	return 0;
200 }
201 
202 static int check_mocs_engine(struct live_mocs *arg,
203 			     struct intel_context *ce)
204 {
205 	struct i915_vma *vma = arg->scratch;
206 	struct i915_request *rq;
207 	u32 offset;
208 	u32 *vaddr;
209 	int err;
210 
211 	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
212 
213 	rq = intel_context_create_request(ce);
214 	if (IS_ERR(rq))
215 		return PTR_ERR(rq);
216 
217 	i915_vma_lock(vma);
218 	err = i915_request_await_object(rq, vma->obj, true);
219 	if (!err)
220 		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
221 	i915_vma_unlock(vma);
222 
223 	/* Read the mocs tables back using SRM */
224 	offset = i915_ggtt_offset(vma);
225 	if (!err)
226 		err = read_mocs_table(rq, &arg->mocs, &offset);
227 	if (!err && ce->engine->class == RENDER_CLASS)
228 		err = read_l3cc_table(rq, &arg->l3cc, &offset);
229 	offset -= i915_ggtt_offset(vma);
230 	GEM_BUG_ON(offset > PAGE_SIZE);
231 
232 	err = request_add_sync(rq, err);
233 	if (err)
234 		return err;
235 
236 	/* Compare the results against the expected tables */
237 	vaddr = arg->vaddr;
238 	if (!err)
239 		err = check_mocs_table(ce->engine, &arg->mocs, &vaddr);
240 	if (!err && ce->engine->class == RENDER_CLASS)
241 		err = check_l3cc_table(ce->engine, &arg->l3cc, &vaddr);
242 	if (err)
243 		return err;
244 
245 	GEM_BUG_ON(arg->vaddr + offset != vaddr);
246 	return 0;
247 }
248 
249 static int live_mocs_kernel(void *arg)
250 {
251 	struct intel_gt *gt = arg;
252 	struct intel_engine_cs *engine;
253 	enum intel_engine_id id;
254 	struct live_mocs mocs;
255 	int err;
256 
257 	/* Basic check the system is configured with the expected mocs table */
258 
259 	err = live_mocs_init(&mocs, gt);
260 	if (err)
261 		return err;
262 
263 	for_each_engine(engine, gt, id) {
264 		intel_engine_pm_get(engine);
265 		err = check_mocs_engine(&mocs, engine->kernel_context);
266 		intel_engine_pm_put(engine);
267 		if (err)
268 			break;
269 	}
270 
271 	live_mocs_fini(&mocs);
272 	return err;
273 }
274 
275 static int live_mocs_clean(void *arg)
276 {
277 	struct intel_gt *gt = arg;
278 	struct intel_engine_cs *engine;
279 	enum intel_engine_id id;
280 	struct live_mocs mocs;
281 	int err;
282 
283 	/* Every new context should see the same mocs table */
284 
285 	err = live_mocs_init(&mocs, gt);
286 	if (err)
287 		return err;
288 
289 	for_each_engine(engine, gt, id) {
290 		struct intel_context *ce;
291 
292 		ce = mocs_context_create(engine);
293 		if (IS_ERR(ce)) {
294 			err = PTR_ERR(ce);
295 			break;
296 		}
297 
298 		err = check_mocs_engine(&mocs, ce);
299 		intel_context_put(ce);
300 		if (err)
301 			break;
302 	}
303 
304 	live_mocs_fini(&mocs);
305 	return err;
306 }
307 
308 static int active_engine_reset(struct intel_context *ce,
309 			       const char *reason)
310 {
311 	struct igt_spinner spin;
312 	struct i915_request *rq;
313 	int err;
314 
315 	err = igt_spinner_init(&spin, ce->engine->gt);
316 	if (err)
317 		return err;
318 
319 	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
320 	if (IS_ERR(rq)) {
321 		igt_spinner_fini(&spin);
322 		return PTR_ERR(rq);
323 	}
324 
325 	err = request_add_spin(rq, &spin);
326 	if (err == 0)
327 		err = intel_engine_reset(ce->engine, reason);
328 
329 	igt_spinner_end(&spin);
330 	igt_spinner_fini(&spin);
331 
332 	return err;
333 }
334 
335 static int __live_mocs_reset(struct live_mocs *mocs,
336 			     struct intel_context *ce)
337 {
338 	struct intel_gt *gt = ce->engine->gt;
339 	int err;
340 
341 	if (intel_has_reset_engine(gt)) {
342 		err = intel_engine_reset(ce->engine, "mocs");
343 		if (err)
344 			return err;
345 
346 		err = check_mocs_engine(mocs, ce);
347 		if (err)
348 			return err;
349 
350 		err = active_engine_reset(ce, "mocs");
351 		if (err)
352 			return err;
353 
354 		err = check_mocs_engine(mocs, ce);
355 		if (err)
356 			return err;
357 	}
358 
359 	if (intel_has_gpu_reset(gt)) {
360 		intel_gt_reset(gt, ce->engine->mask, "mocs");
361 
362 		err = check_mocs_engine(mocs, ce);
363 		if (err)
364 			return err;
365 	}
366 
367 	return 0;
368 }
369 
370 static int live_mocs_reset(void *arg)
371 {
372 	struct intel_gt *gt = arg;
373 	struct intel_engine_cs *engine;
374 	enum intel_engine_id id;
375 	struct live_mocs mocs;
376 	int err = 0;
377 
378 	/* Check the mocs setup is retained over per-engine and global resets */
379 
380 	err = live_mocs_init(&mocs, gt);
381 	if (err)
382 		return err;
383 
384 	igt_global_reset_lock(gt);
385 	for_each_engine(engine, gt, id) {
386 		struct intel_context *ce;
387 
388 		ce = mocs_context_create(engine);
389 		if (IS_ERR(ce)) {
390 			err = PTR_ERR(ce);
391 			break;
392 		}
393 
394 		intel_engine_pm_get(engine);
395 		err = __live_mocs_reset(&mocs, ce);
396 		intel_engine_pm_put(engine);
397 
398 		intel_context_put(ce);
399 		if (err)
400 			break;
401 	}
402 	igt_global_reset_unlock(gt);
403 
404 	live_mocs_fini(&mocs);
405 	return err;
406 }
407 
408 int intel_mocs_live_selftests(struct drm_i915_private *i915)
409 {
410 	static const struct i915_subtest tests[] = {
411 		SUBTEST(live_mocs_kernel),
412 		SUBTEST(live_mocs_clean),
413 		SUBTEST(live_mocs_reset),
414 	};
415 	struct drm_i915_mocs_table table;
416 
417 	if (!get_mocs_settings(i915, &table))
418 		return 0;
419 
420 	return intel_gt_live_subtests(tests, &i915->gt);
421 }
422