13fb33cd3SChris Wilson /* 23fb33cd3SChris Wilson * SPDX-License-Identifier: MIT 33fb33cd3SChris Wilson * 43fb33cd3SChris Wilson * Copyright © 2019 Intel Corporation 53fb33cd3SChris Wilson */ 63fb33cd3SChris Wilson 73fb33cd3SChris Wilson #include "gt/intel_engine_pm.h" 83fb33cd3SChris Wilson #include "i915_selftest.h" 93fb33cd3SChris Wilson 103fb33cd3SChris Wilson #include "gem/selftests/mock_context.h" 113fb33cd3SChris Wilson #include "selftests/igt_reset.h" 123fb33cd3SChris Wilson #include "selftests/igt_spinner.h" 133fb33cd3SChris Wilson 143fb33cd3SChris Wilson struct live_mocs { 150e744b51SChris Wilson struct drm_i915_mocs_table mocs; 160e744b51SChris Wilson struct drm_i915_mocs_table l3cc; 173fb33cd3SChris Wilson struct i915_vma *scratch; 183fb33cd3SChris Wilson void *vaddr; 193fb33cd3SChris Wilson }; 203fb33cd3SChris Wilson 21e36ba817SChris Wilson static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) 22e36ba817SChris Wilson { 23e36ba817SChris Wilson struct intel_context *ce; 24e36ba817SChris Wilson 25e36ba817SChris Wilson ce = intel_context_create(engine); 26e36ba817SChris Wilson if (IS_ERR(ce)) 27e36ba817SChris Wilson return ce; 28e36ba817SChris Wilson 29e36ba817SChris Wilson /* We build large requests to read the registers from the ring */ 30e36ba817SChris Wilson ce->ring = __intel_context_ring_size(SZ_16K); 31e36ba817SChris Wilson 32e36ba817SChris Wilson return ce; 33e36ba817SChris Wilson } 34e36ba817SChris Wilson 353fb33cd3SChris Wilson static int request_add_sync(struct i915_request *rq, int err) 363fb33cd3SChris Wilson { 373fb33cd3SChris Wilson i915_request_get(rq); 383fb33cd3SChris Wilson i915_request_add(rq); 393fb33cd3SChris Wilson if (i915_request_wait(rq, 0, HZ / 5) < 0) 403fb33cd3SChris Wilson err = -ETIME; 413fb33cd3SChris Wilson i915_request_put(rq); 423fb33cd3SChris Wilson 433fb33cd3SChris Wilson return err; 443fb33cd3SChris Wilson } 453fb33cd3SChris Wilson 463fb33cd3SChris Wilson static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) 473fb33cd3SChris Wilson { 483fb33cd3SChris Wilson int err = 0; 493fb33cd3SChris Wilson 503fb33cd3SChris Wilson i915_request_get(rq); 513fb33cd3SChris Wilson i915_request_add(rq); 523fb33cd3SChris Wilson if (spin && !igt_wait_for_spinner(spin, rq)) 533fb33cd3SChris Wilson err = -ETIME; 543fb33cd3SChris Wilson i915_request_put(rq); 553fb33cd3SChris Wilson 563fb33cd3SChris Wilson return err; 573fb33cd3SChris Wilson } 583fb33cd3SChris Wilson 593fb33cd3SChris Wilson static struct i915_vma *create_scratch(struct intel_gt *gt) 603fb33cd3SChris Wilson { 613fb33cd3SChris Wilson struct drm_i915_gem_object *obj; 623fb33cd3SChris Wilson struct i915_vma *vma; 633fb33cd3SChris Wilson int err; 643fb33cd3SChris Wilson 653fb33cd3SChris Wilson obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 663fb33cd3SChris Wilson if (IS_ERR(obj)) 673fb33cd3SChris Wilson return ERR_CAST(obj); 683fb33cd3SChris Wilson 693fb33cd3SChris Wilson i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED); 703fb33cd3SChris Wilson 713fb33cd3SChris Wilson vma = i915_vma_instance(obj, >->ggtt->vm, NULL); 723fb33cd3SChris Wilson if (IS_ERR(vma)) { 733fb33cd3SChris Wilson i915_gem_object_put(obj); 743fb33cd3SChris Wilson return vma; 753fb33cd3SChris Wilson } 763fb33cd3SChris Wilson 773fb33cd3SChris Wilson err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL); 783fb33cd3SChris Wilson if (err) { 793fb33cd3SChris Wilson i915_gem_object_put(obj); 803fb33cd3SChris Wilson return ERR_PTR(err); 813fb33cd3SChris Wilson } 823fb33cd3SChris Wilson 833fb33cd3SChris Wilson return vma; 843fb33cd3SChris Wilson } 853fb33cd3SChris Wilson 863fb33cd3SChris Wilson static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt) 873fb33cd3SChris Wilson { 880e744b51SChris Wilson struct drm_i915_mocs_table table; 890e744b51SChris Wilson unsigned int flags; 903fb33cd3SChris Wilson int err; 913fb33cd3SChris Wilson 920e744b51SChris Wilson memset(arg, 0, sizeof(*arg)); 930e744b51SChris Wilson 940e744b51SChris Wilson flags = get_mocs_settings(gt->i915, &table); 950e744b51SChris Wilson if (!flags) 963fb33cd3SChris Wilson return -EINVAL; 973fb33cd3SChris Wilson 980e744b51SChris Wilson if (flags & HAS_RENDER_L3CC) 990e744b51SChris Wilson arg->l3cc = table; 1000e744b51SChris Wilson 1010e744b51SChris Wilson if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS)) 1020e744b51SChris Wilson arg->mocs = table; 1030e744b51SChris Wilson 1043fb33cd3SChris Wilson arg->scratch = create_scratch(gt); 1053fb33cd3SChris Wilson if (IS_ERR(arg->scratch)) 1063fb33cd3SChris Wilson return PTR_ERR(arg->scratch); 1073fb33cd3SChris Wilson 1083fb33cd3SChris Wilson arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB); 1093fb33cd3SChris Wilson if (IS_ERR(arg->vaddr)) { 1103fb33cd3SChris Wilson err = PTR_ERR(arg->vaddr); 1113fb33cd3SChris Wilson goto err_scratch; 1123fb33cd3SChris Wilson } 1133fb33cd3SChris Wilson 1143fb33cd3SChris Wilson return 0; 1153fb33cd3SChris Wilson 1163fb33cd3SChris Wilson err_scratch: 1173fb33cd3SChris Wilson i915_vma_unpin_and_release(&arg->scratch, 0); 1183fb33cd3SChris Wilson return err; 1193fb33cd3SChris Wilson } 1203fb33cd3SChris Wilson 1213fb33cd3SChris Wilson static void live_mocs_fini(struct live_mocs *arg) 1223fb33cd3SChris Wilson { 1233fb33cd3SChris Wilson i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP); 1243fb33cd3SChris Wilson } 1253fb33cd3SChris Wilson 1263fb33cd3SChris Wilson static int read_regs(struct i915_request *rq, 1273fb33cd3SChris Wilson u32 addr, unsigned int count, 1283fb33cd3SChris Wilson uint32_t *offset) 1293fb33cd3SChris Wilson { 1303fb33cd3SChris Wilson unsigned int i; 1313fb33cd3SChris Wilson u32 *cs; 1323fb33cd3SChris Wilson 1333fb33cd3SChris Wilson GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32))); 1343fb33cd3SChris Wilson 1353fb33cd3SChris Wilson cs = intel_ring_begin(rq, 4 * count); 1363fb33cd3SChris Wilson if (IS_ERR(cs)) 1373fb33cd3SChris Wilson return PTR_ERR(cs); 1383fb33cd3SChris Wilson 1393fb33cd3SChris Wilson for (i = 0; i < count; i++) { 1403fb33cd3SChris Wilson *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; 1413fb33cd3SChris Wilson *cs++ = addr; 1423fb33cd3SChris Wilson *cs++ = *offset; 1433fb33cd3SChris Wilson *cs++ = 0; 1443fb33cd3SChris Wilson 1453fb33cd3SChris Wilson addr += sizeof(u32); 1463fb33cd3SChris Wilson *offset += sizeof(u32); 1473fb33cd3SChris Wilson } 1483fb33cd3SChris Wilson 1493fb33cd3SChris Wilson intel_ring_advance(rq, cs); 1503fb33cd3SChris Wilson 1513fb33cd3SChris Wilson return 0; 1523fb33cd3SChris Wilson } 1533fb33cd3SChris Wilson 1543fb33cd3SChris Wilson static int read_mocs_table(struct i915_request *rq, 1553fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 1563fb33cd3SChris Wilson uint32_t *offset) 1573fb33cd3SChris Wilson { 1583fb33cd3SChris Wilson u32 addr; 1593fb33cd3SChris Wilson 1605a833995SChris Wilson if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) 1613fb33cd3SChris Wilson addr = global_mocs_offset(); 1623fb33cd3SChris Wilson else 1633fb33cd3SChris Wilson addr = mocs_offset(rq->engine); 1643fb33cd3SChris Wilson 1653fb33cd3SChris Wilson return read_regs(rq, addr, table->n_entries, offset); 1663fb33cd3SChris Wilson } 1673fb33cd3SChris Wilson 1683fb33cd3SChris Wilson static int read_l3cc_table(struct i915_request *rq, 1693fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 1703fb33cd3SChris Wilson uint32_t *offset) 1713fb33cd3SChris Wilson { 1723fb33cd3SChris Wilson u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 1733fb33cd3SChris Wilson 1743fb33cd3SChris Wilson return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); 1753fb33cd3SChris Wilson } 1763fb33cd3SChris Wilson 1773fb33cd3SChris Wilson static int check_mocs_table(struct intel_engine_cs *engine, 1783fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 1793fb33cd3SChris Wilson uint32_t **vaddr) 1803fb33cd3SChris Wilson { 1813fb33cd3SChris Wilson unsigned int i; 1823fb33cd3SChris Wilson u32 expect; 1833fb33cd3SChris Wilson 1843fb33cd3SChris Wilson for_each_mocs(expect, table, i) { 1853fb33cd3SChris Wilson if (**vaddr != expect) { 1863fb33cd3SChris Wilson pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n", 1873fb33cd3SChris Wilson engine->name, i, **vaddr, expect); 1883fb33cd3SChris Wilson return -EINVAL; 1893fb33cd3SChris Wilson } 1903fb33cd3SChris Wilson ++*vaddr; 1913fb33cd3SChris Wilson } 1923fb33cd3SChris Wilson 1933fb33cd3SChris Wilson return 0; 1943fb33cd3SChris Wilson } 1953fb33cd3SChris Wilson 1963fb33cd3SChris Wilson static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1973fb33cd3SChris Wilson { 1983fb33cd3SChris Wilson /* 1993fb33cd3SChris Wilson * Registers in this range are affected by the MCR selector 2003fb33cd3SChris Wilson * which only controls CPU initiated MMIO. Routing does not 2013fb33cd3SChris Wilson * work for CS access so we cannot verify them on this path. 2023fb33cd3SChris Wilson */ 2033fb33cd3SChris Wilson return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff; 2043fb33cd3SChris Wilson } 2053fb33cd3SChris Wilson 2063fb33cd3SChris Wilson static int check_l3cc_table(struct intel_engine_cs *engine, 2073fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 2083fb33cd3SChris Wilson uint32_t **vaddr) 2093fb33cd3SChris Wilson { 2103fb33cd3SChris Wilson /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */ 2113fb33cd3SChris Wilson u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 2123fb33cd3SChris Wilson unsigned int i; 2133fb33cd3SChris Wilson u32 expect; 2143fb33cd3SChris Wilson 2153fb33cd3SChris Wilson for_each_l3cc(expect, table, i) { 2163fb33cd3SChris Wilson if (!mcr_range(engine->i915, reg) && **vaddr != expect) { 2173fb33cd3SChris Wilson pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n", 2183fb33cd3SChris Wilson engine->name, i, **vaddr, expect); 2193fb33cd3SChris Wilson return -EINVAL; 2203fb33cd3SChris Wilson } 2213fb33cd3SChris Wilson ++*vaddr; 2223fb33cd3SChris Wilson reg += 4; 2233fb33cd3SChris Wilson } 2243fb33cd3SChris Wilson 2253fb33cd3SChris Wilson return 0; 2263fb33cd3SChris Wilson } 2273fb33cd3SChris Wilson 2283fb33cd3SChris Wilson static int check_mocs_engine(struct live_mocs *arg, 2293fb33cd3SChris Wilson struct intel_context *ce) 2303fb33cd3SChris Wilson { 2313fb33cd3SChris Wilson struct i915_vma *vma = arg->scratch; 2323fb33cd3SChris Wilson struct i915_request *rq; 2333fb33cd3SChris Wilson u32 offset; 2343fb33cd3SChris Wilson u32 *vaddr; 2353fb33cd3SChris Wilson int err; 2363fb33cd3SChris Wilson 2373fb33cd3SChris Wilson memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); 2383fb33cd3SChris Wilson 2393fb33cd3SChris Wilson rq = intel_context_create_request(ce); 2403fb33cd3SChris Wilson if (IS_ERR(rq)) 2413fb33cd3SChris Wilson return PTR_ERR(rq); 2423fb33cd3SChris Wilson 2433fb33cd3SChris Wilson i915_vma_lock(vma); 2443fb33cd3SChris Wilson err = i915_request_await_object(rq, vma->obj, true); 2453fb33cd3SChris Wilson if (!err) 2463fb33cd3SChris Wilson err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2473fb33cd3SChris Wilson i915_vma_unlock(vma); 2483fb33cd3SChris Wilson 2493fb33cd3SChris Wilson /* Read the mocs tables back using SRM */ 2503fb33cd3SChris Wilson offset = i915_ggtt_offset(vma); 2513fb33cd3SChris Wilson if (!err) 2520e744b51SChris Wilson err = read_mocs_table(rq, &arg->mocs, &offset); 2533fb33cd3SChris Wilson if (!err && ce->engine->class == RENDER_CLASS) 2540e744b51SChris Wilson err = read_l3cc_table(rq, &arg->l3cc, &offset); 2553fb33cd3SChris Wilson offset -= i915_ggtt_offset(vma); 2563fb33cd3SChris Wilson GEM_BUG_ON(offset > PAGE_SIZE); 2573fb33cd3SChris Wilson 2583fb33cd3SChris Wilson err = request_add_sync(rq, err); 2593fb33cd3SChris Wilson if (err) 2603fb33cd3SChris Wilson return err; 2613fb33cd3SChris Wilson 2623fb33cd3SChris Wilson /* Compare the results against the expected tables */ 2633fb33cd3SChris Wilson vaddr = arg->vaddr; 2643fb33cd3SChris Wilson if (!err) 2650e744b51SChris Wilson err = check_mocs_table(ce->engine, &arg->mocs, &vaddr); 2663fb33cd3SChris Wilson if (!err && ce->engine->class == RENDER_CLASS) 2670e744b51SChris Wilson err = check_l3cc_table(ce->engine, &arg->l3cc, &vaddr); 2683fb33cd3SChris Wilson if (err) 2693fb33cd3SChris Wilson return err; 2703fb33cd3SChris Wilson 2713fb33cd3SChris Wilson GEM_BUG_ON(arg->vaddr + offset != vaddr); 2723fb33cd3SChris Wilson return 0; 2733fb33cd3SChris Wilson } 2743fb33cd3SChris Wilson 2753fb33cd3SChris Wilson static int live_mocs_kernel(void *arg) 2763fb33cd3SChris Wilson { 2773fb33cd3SChris Wilson struct intel_gt *gt = arg; 2783fb33cd3SChris Wilson struct intel_engine_cs *engine; 2793fb33cd3SChris Wilson enum intel_engine_id id; 2803fb33cd3SChris Wilson struct live_mocs mocs; 2813fb33cd3SChris Wilson int err; 2823fb33cd3SChris Wilson 2833fb33cd3SChris Wilson /* Basic check the system is configured with the expected mocs table */ 2843fb33cd3SChris Wilson 2853fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 2863fb33cd3SChris Wilson if (err) 2873fb33cd3SChris Wilson return err; 2883fb33cd3SChris Wilson 2893fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 290de5825beSChris Wilson intel_engine_pm_get(engine); 2913fb33cd3SChris Wilson err = check_mocs_engine(&mocs, engine->kernel_context); 292de5825beSChris Wilson intel_engine_pm_put(engine); 2933fb33cd3SChris Wilson if (err) 2943fb33cd3SChris Wilson break; 2953fb33cd3SChris Wilson } 2963fb33cd3SChris Wilson 2973fb33cd3SChris Wilson live_mocs_fini(&mocs); 2983fb33cd3SChris Wilson return err; 2993fb33cd3SChris Wilson } 3003fb33cd3SChris Wilson 3013fb33cd3SChris Wilson static int live_mocs_clean(void *arg) 3023fb33cd3SChris Wilson { 3033fb33cd3SChris Wilson struct intel_gt *gt = arg; 3043fb33cd3SChris Wilson struct intel_engine_cs *engine; 3053fb33cd3SChris Wilson enum intel_engine_id id; 3063fb33cd3SChris Wilson struct live_mocs mocs; 3073fb33cd3SChris Wilson int err; 3083fb33cd3SChris Wilson 3093fb33cd3SChris Wilson /* Every new context should see the same mocs table */ 3103fb33cd3SChris Wilson 3113fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 3123fb33cd3SChris Wilson if (err) 3133fb33cd3SChris Wilson return err; 3143fb33cd3SChris Wilson 3153fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 3163fb33cd3SChris Wilson struct intel_context *ce; 3173fb33cd3SChris Wilson 318e36ba817SChris Wilson ce = mocs_context_create(engine); 3193fb33cd3SChris Wilson if (IS_ERR(ce)) { 3203fb33cd3SChris Wilson err = PTR_ERR(ce); 3213fb33cd3SChris Wilson break; 3223fb33cd3SChris Wilson } 3233fb33cd3SChris Wilson 3243fb33cd3SChris Wilson err = check_mocs_engine(&mocs, ce); 3253fb33cd3SChris Wilson intel_context_put(ce); 3263fb33cd3SChris Wilson if (err) 3273fb33cd3SChris Wilson break; 3283fb33cd3SChris Wilson } 3293fb33cd3SChris Wilson 3303fb33cd3SChris Wilson live_mocs_fini(&mocs); 3313fb33cd3SChris Wilson return err; 3323fb33cd3SChris Wilson } 3333fb33cd3SChris Wilson 3343fb33cd3SChris Wilson static int active_engine_reset(struct intel_context *ce, 3353fb33cd3SChris Wilson const char *reason) 3363fb33cd3SChris Wilson { 3373fb33cd3SChris Wilson struct igt_spinner spin; 3383fb33cd3SChris Wilson struct i915_request *rq; 3393fb33cd3SChris Wilson int err; 3403fb33cd3SChris Wilson 3413fb33cd3SChris Wilson err = igt_spinner_init(&spin, ce->engine->gt); 3423fb33cd3SChris Wilson if (err) 3433fb33cd3SChris Wilson return err; 3443fb33cd3SChris Wilson 3453fb33cd3SChris Wilson rq = igt_spinner_create_request(&spin, ce, MI_NOOP); 3463fb33cd3SChris Wilson if (IS_ERR(rq)) { 3473fb33cd3SChris Wilson igt_spinner_fini(&spin); 3483fb33cd3SChris Wilson return PTR_ERR(rq); 3493fb33cd3SChris Wilson } 3503fb33cd3SChris Wilson 3513fb33cd3SChris Wilson err = request_add_spin(rq, &spin); 3523fb33cd3SChris Wilson if (err == 0) 3533fb33cd3SChris Wilson err = intel_engine_reset(ce->engine, reason); 3543fb33cd3SChris Wilson 3553fb33cd3SChris Wilson igt_spinner_end(&spin); 3563fb33cd3SChris Wilson igt_spinner_fini(&spin); 3573fb33cd3SChris Wilson 3583fb33cd3SChris Wilson return err; 3593fb33cd3SChris Wilson } 3603fb33cd3SChris Wilson 3613fb33cd3SChris Wilson static int __live_mocs_reset(struct live_mocs *mocs, 3623fb33cd3SChris Wilson struct intel_context *ce) 3633fb33cd3SChris Wilson { 364*8005f37cSChris Wilson struct intel_gt *gt = ce->engine->gt; 3653fb33cd3SChris Wilson int err; 3663fb33cd3SChris Wilson 367*8005f37cSChris Wilson if (intel_has_reset_engine(gt)) { 3683fb33cd3SChris Wilson err = intel_engine_reset(ce->engine, "mocs"); 3693fb33cd3SChris Wilson if (err) 3703fb33cd3SChris Wilson return err; 3713fb33cd3SChris Wilson 3723fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3733fb33cd3SChris Wilson if (err) 3743fb33cd3SChris Wilson return err; 3753fb33cd3SChris Wilson 3763fb33cd3SChris Wilson err = active_engine_reset(ce, "mocs"); 3773fb33cd3SChris Wilson if (err) 3783fb33cd3SChris Wilson return err; 3793fb33cd3SChris Wilson 3803fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3813fb33cd3SChris Wilson if (err) 3823fb33cd3SChris Wilson return err; 383*8005f37cSChris Wilson } 3843fb33cd3SChris Wilson 385*8005f37cSChris Wilson if (intel_has_gpu_reset(gt)) { 386*8005f37cSChris Wilson intel_gt_reset(gt, ce->engine->mask, "mocs"); 3873fb33cd3SChris Wilson 3883fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3893fb33cd3SChris Wilson if (err) 3903fb33cd3SChris Wilson return err; 391*8005f37cSChris Wilson } 3923fb33cd3SChris Wilson 3933fb33cd3SChris Wilson return 0; 3943fb33cd3SChris Wilson } 3953fb33cd3SChris Wilson 3963fb33cd3SChris Wilson static int live_mocs_reset(void *arg) 3973fb33cd3SChris Wilson { 3983fb33cd3SChris Wilson struct intel_gt *gt = arg; 3993fb33cd3SChris Wilson struct intel_engine_cs *engine; 4003fb33cd3SChris Wilson enum intel_engine_id id; 4013fb33cd3SChris Wilson struct live_mocs mocs; 4023fb33cd3SChris Wilson int err = 0; 4033fb33cd3SChris Wilson 4043fb33cd3SChris Wilson /* Check the mocs setup is retained over per-engine and global resets */ 4053fb33cd3SChris Wilson 4063fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 4073fb33cd3SChris Wilson if (err) 4083fb33cd3SChris Wilson return err; 4093fb33cd3SChris Wilson 4103fb33cd3SChris Wilson igt_global_reset_lock(gt); 4113fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 4123fb33cd3SChris Wilson struct intel_context *ce; 4133fb33cd3SChris Wilson 414e36ba817SChris Wilson ce = mocs_context_create(engine); 4153fb33cd3SChris Wilson if (IS_ERR(ce)) { 4163fb33cd3SChris Wilson err = PTR_ERR(ce); 4173fb33cd3SChris Wilson break; 4183fb33cd3SChris Wilson } 4193fb33cd3SChris Wilson 4203fb33cd3SChris Wilson intel_engine_pm_get(engine); 4213fb33cd3SChris Wilson err = __live_mocs_reset(&mocs, ce); 4223fb33cd3SChris Wilson intel_engine_pm_put(engine); 4233fb33cd3SChris Wilson 4243fb33cd3SChris Wilson intel_context_put(ce); 4253fb33cd3SChris Wilson if (err) 4263fb33cd3SChris Wilson break; 4273fb33cd3SChris Wilson } 4283fb33cd3SChris Wilson igt_global_reset_unlock(gt); 4293fb33cd3SChris Wilson 4303fb33cd3SChris Wilson live_mocs_fini(&mocs); 4313fb33cd3SChris Wilson return err; 4323fb33cd3SChris Wilson } 4333fb33cd3SChris Wilson 4343fb33cd3SChris Wilson int intel_mocs_live_selftests(struct drm_i915_private *i915) 4353fb33cd3SChris Wilson { 4363fb33cd3SChris Wilson static const struct i915_subtest tests[] = { 4373fb33cd3SChris Wilson SUBTEST(live_mocs_kernel), 4383fb33cd3SChris Wilson SUBTEST(live_mocs_clean), 4393fb33cd3SChris Wilson SUBTEST(live_mocs_reset), 4403fb33cd3SChris Wilson }; 4413fb33cd3SChris Wilson struct drm_i915_mocs_table table; 4423fb33cd3SChris Wilson 4433fb33cd3SChris Wilson if (!get_mocs_settings(i915, &table)) 4443fb33cd3SChris Wilson return 0; 4453fb33cd3SChris Wilson 4463fb33cd3SChris Wilson return intel_gt_live_subtests(tests, &i915->gt); 4473fb33cd3SChris Wilson } 448