124f90d66SChris Wilson // SPDX-License-Identifier: MIT 23fb33cd3SChris Wilson /* 33fb33cd3SChris Wilson * Copyright © 2019 Intel Corporation 43fb33cd3SChris Wilson */ 53fb33cd3SChris Wilson 63fb33cd3SChris Wilson #include "gt/intel_engine_pm.h" 745233ab2SChris Wilson #include "gt/intel_gpu_commands.h" 83fb33cd3SChris Wilson #include "i915_selftest.h" 93fb33cd3SChris Wilson 1056d7bd74SAndrzej Hajda #include "gem/selftests/igt_gem_utils.h" 113fb33cd3SChris Wilson #include "gem/selftests/mock_context.h" 123fb33cd3SChris Wilson #include "selftests/igt_reset.h" 133fb33cd3SChris Wilson #include "selftests/igt_spinner.h" 14064a1f35SRahul Kumar Singh #include "selftests/intel_scheduler_helpers.h" 153fb33cd3SChris Wilson 163fb33cd3SChris Wilson struct live_mocs { 178bb92516SChris Wilson struct drm_i915_mocs_table table; 188bb92516SChris Wilson struct drm_i915_mocs_table *mocs; 198bb92516SChris Wilson struct drm_i915_mocs_table *l3cc; 203fb33cd3SChris Wilson struct i915_vma *scratch; 213fb33cd3SChris Wilson void *vaddr; 223fb33cd3SChris Wilson }; 233fb33cd3SChris Wilson 24e36ba817SChris Wilson static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) 25e36ba817SChris Wilson { 26e36ba817SChris Wilson struct intel_context *ce; 27e36ba817SChris Wilson 28e36ba817SChris Wilson ce = intel_context_create(engine); 29e36ba817SChris Wilson if (IS_ERR(ce)) 30e36ba817SChris Wilson return ce; 31e36ba817SChris Wilson 32e36ba817SChris Wilson /* We build large requests to read the registers from the ring */ 3374e4b909SJason Ekstrand ce->ring_size = SZ_16K; 34e36ba817SChris Wilson 35e36ba817SChris Wilson return ce; 36e36ba817SChris Wilson } 37e36ba817SChris Wilson 383fb33cd3SChris Wilson static int request_add_sync(struct i915_request *rq, int err) 393fb33cd3SChris Wilson { 403fb33cd3SChris Wilson i915_request_get(rq); 413fb33cd3SChris Wilson i915_request_add(rq); 423fb33cd3SChris Wilson if (i915_request_wait(rq, 0, HZ / 5) < 0) 433fb33cd3SChris Wilson err = -ETIME; 443fb33cd3SChris Wilson i915_request_put(rq); 453fb33cd3SChris Wilson 463fb33cd3SChris Wilson return err; 473fb33cd3SChris Wilson } 483fb33cd3SChris Wilson 493fb33cd3SChris Wilson static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) 503fb33cd3SChris Wilson { 513fb33cd3SChris Wilson int err = 0; 523fb33cd3SChris Wilson 533fb33cd3SChris Wilson i915_request_get(rq); 543fb33cd3SChris Wilson i915_request_add(rq); 553fb33cd3SChris Wilson if (spin && !igt_wait_for_spinner(spin, rq)) 563fb33cd3SChris Wilson err = -ETIME; 573fb33cd3SChris Wilson i915_request_put(rq); 583fb33cd3SChris Wilson 593fb33cd3SChris Wilson return err; 603fb33cd3SChris Wilson } 613fb33cd3SChris Wilson 623fb33cd3SChris Wilson static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt) 633fb33cd3SChris Wilson { 640e744b51SChris Wilson unsigned int flags; 653fb33cd3SChris Wilson int err; 663fb33cd3SChris Wilson 670e744b51SChris Wilson memset(arg, 0, sizeof(*arg)); 680e744b51SChris Wilson 698bb92516SChris Wilson flags = get_mocs_settings(gt->i915, &arg->table); 700e744b51SChris Wilson if (!flags) 713fb33cd3SChris Wilson return -EINVAL; 723fb33cd3SChris Wilson 730e744b51SChris Wilson if (flags & HAS_RENDER_L3CC) 748bb92516SChris Wilson arg->l3cc = &arg->table; 750e744b51SChris Wilson 760e744b51SChris Wilson if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS)) 778bb92516SChris Wilson arg->mocs = &arg->table; 780e744b51SChris Wilson 792a665968SMaarten Lankhorst arg->scratch = 802a665968SMaarten Lankhorst __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE); 813fb33cd3SChris Wilson if (IS_ERR(arg->scratch)) 823fb33cd3SChris Wilson return PTR_ERR(arg->scratch); 833fb33cd3SChris Wilson 84e20e9b15SMaarten Lankhorst arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB); 853fb33cd3SChris Wilson if (IS_ERR(arg->vaddr)) { 863fb33cd3SChris Wilson err = PTR_ERR(arg->vaddr); 873fb33cd3SChris Wilson goto err_scratch; 883fb33cd3SChris Wilson } 893fb33cd3SChris Wilson 903fb33cd3SChris Wilson return 0; 913fb33cd3SChris Wilson 923fb33cd3SChris Wilson err_scratch: 933fb33cd3SChris Wilson i915_vma_unpin_and_release(&arg->scratch, 0); 943fb33cd3SChris Wilson return err; 953fb33cd3SChris Wilson } 963fb33cd3SChris Wilson 973fb33cd3SChris Wilson static void live_mocs_fini(struct live_mocs *arg) 983fb33cd3SChris Wilson { 993fb33cd3SChris Wilson i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP); 1003fb33cd3SChris Wilson } 1013fb33cd3SChris Wilson 1023fb33cd3SChris Wilson static int read_regs(struct i915_request *rq, 1033fb33cd3SChris Wilson u32 addr, unsigned int count, 104368fd0d7SJani Nikula u32 *offset) 1053fb33cd3SChris Wilson { 1063fb33cd3SChris Wilson unsigned int i; 1073fb33cd3SChris Wilson u32 *cs; 1083fb33cd3SChris Wilson 1093fb33cd3SChris Wilson GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32))); 1103fb33cd3SChris Wilson 1113fb33cd3SChris Wilson cs = intel_ring_begin(rq, 4 * count); 1123fb33cd3SChris Wilson if (IS_ERR(cs)) 1133fb33cd3SChris Wilson return PTR_ERR(cs); 1143fb33cd3SChris Wilson 1153fb33cd3SChris Wilson for (i = 0; i < count; i++) { 1163fb33cd3SChris Wilson *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT; 1173fb33cd3SChris Wilson *cs++ = addr; 1183fb33cd3SChris Wilson *cs++ = *offset; 1193fb33cd3SChris Wilson *cs++ = 0; 1203fb33cd3SChris Wilson 1213fb33cd3SChris Wilson addr += sizeof(u32); 1223fb33cd3SChris Wilson *offset += sizeof(u32); 1233fb33cd3SChris Wilson } 1243fb33cd3SChris Wilson 1253fb33cd3SChris Wilson intel_ring_advance(rq, cs); 1263fb33cd3SChris Wilson 1273fb33cd3SChris Wilson return 0; 1283fb33cd3SChris Wilson } 1293fb33cd3SChris Wilson 1303fb33cd3SChris Wilson static int read_mocs_table(struct i915_request *rq, 1313fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 132368fd0d7SJani Nikula u32 *offset) 1333fb33cd3SChris Wilson { 1343fb33cd3SChris Wilson u32 addr; 1353fb33cd3SChris Wilson 1368bb92516SChris Wilson if (!table) 1378bb92516SChris Wilson return 0; 1388bb92516SChris Wilson 1395a833995SChris Wilson if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) 1403fb33cd3SChris Wilson addr = global_mocs_offset(); 1413fb33cd3SChris Wilson else 1423fb33cd3SChris Wilson addr = mocs_offset(rq->engine); 1433fb33cd3SChris Wilson 1443fb33cd3SChris Wilson return read_regs(rq, addr, table->n_entries, offset); 1453fb33cd3SChris Wilson } 1463fb33cd3SChris Wilson 1473fb33cd3SChris Wilson static int read_l3cc_table(struct i915_request *rq, 1483fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 149368fd0d7SJani Nikula u32 *offset) 1503fb33cd3SChris Wilson { 1513fb33cd3SChris Wilson u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 1523fb33cd3SChris Wilson 1538bb92516SChris Wilson if (!table) 1548bb92516SChris Wilson return 0; 1558bb92516SChris Wilson 1563fb33cd3SChris Wilson return read_regs(rq, addr, (table->n_entries + 1) / 2, offset); 1573fb33cd3SChris Wilson } 1583fb33cd3SChris Wilson 1593fb33cd3SChris Wilson static int check_mocs_table(struct intel_engine_cs *engine, 1603fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 161368fd0d7SJani Nikula u32 **vaddr) 1623fb33cd3SChris Wilson { 1633fb33cd3SChris Wilson unsigned int i; 1643fb33cd3SChris Wilson u32 expect; 1653fb33cd3SChris Wilson 1668bb92516SChris Wilson if (!table) 1678bb92516SChris Wilson return 0; 1688bb92516SChris Wilson 1693fb33cd3SChris Wilson for_each_mocs(expect, table, i) { 1703fb33cd3SChris Wilson if (**vaddr != expect) { 1713fb33cd3SChris Wilson pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n", 1723fb33cd3SChris Wilson engine->name, i, **vaddr, expect); 1733fb33cd3SChris Wilson return -EINVAL; 1743fb33cd3SChris Wilson } 1753fb33cd3SChris Wilson ++*vaddr; 1763fb33cd3SChris Wilson } 1773fb33cd3SChris Wilson 1783fb33cd3SChris Wilson return 0; 1793fb33cd3SChris Wilson } 1803fb33cd3SChris Wilson 1813fb33cd3SChris Wilson static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1823fb33cd3SChris Wilson { 1833fb33cd3SChris Wilson /* 1843fb33cd3SChris Wilson * Registers in this range are affected by the MCR selector 1853fb33cd3SChris Wilson * which only controls CPU initiated MMIO. Routing does not 1863fb33cd3SChris Wilson * work for CS access so we cannot verify them on this path. 1873fb33cd3SChris Wilson */ 188c816723bSLucas De Marchi return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff; 1893fb33cd3SChris Wilson } 1903fb33cd3SChris Wilson 1913fb33cd3SChris Wilson static int check_l3cc_table(struct intel_engine_cs *engine, 1923fb33cd3SChris Wilson const struct drm_i915_mocs_table *table, 193368fd0d7SJani Nikula u32 **vaddr) 1943fb33cd3SChris Wilson { 1953fb33cd3SChris Wilson /* Can we read the MCR range 0xb00 directly? See intel_workarounds! */ 1963fb33cd3SChris Wilson u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0)); 1973fb33cd3SChris Wilson unsigned int i; 1983fb33cd3SChris Wilson u32 expect; 1993fb33cd3SChris Wilson 2008bb92516SChris Wilson if (!table) 2018bb92516SChris Wilson return 0; 2028bb92516SChris Wilson 2033fb33cd3SChris Wilson for_each_l3cc(expect, table, i) { 2043fb33cd3SChris Wilson if (!mcr_range(engine->i915, reg) && **vaddr != expect) { 2053fb33cd3SChris Wilson pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n", 2063fb33cd3SChris Wilson engine->name, i, **vaddr, expect); 2073fb33cd3SChris Wilson return -EINVAL; 2083fb33cd3SChris Wilson } 2093fb33cd3SChris Wilson ++*vaddr; 2103fb33cd3SChris Wilson reg += 4; 2113fb33cd3SChris Wilson } 2123fb33cd3SChris Wilson 2133fb33cd3SChris Wilson return 0; 2143fb33cd3SChris Wilson } 2153fb33cd3SChris Wilson 2163fb33cd3SChris Wilson static int check_mocs_engine(struct live_mocs *arg, 2173fb33cd3SChris Wilson struct intel_context *ce) 2183fb33cd3SChris Wilson { 2193fb33cd3SChris Wilson struct i915_vma *vma = arg->scratch; 2203fb33cd3SChris Wilson struct i915_request *rq; 2213fb33cd3SChris Wilson u32 offset; 2223fb33cd3SChris Wilson u32 *vaddr; 2233fb33cd3SChris Wilson int err; 2243fb33cd3SChris Wilson 2253fb33cd3SChris Wilson memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); 2263fb33cd3SChris Wilson 2273fb33cd3SChris Wilson rq = intel_context_create_request(ce); 2283fb33cd3SChris Wilson if (IS_ERR(rq)) 2293fb33cd3SChris Wilson return PTR_ERR(rq); 2303fb33cd3SChris Wilson 231*4f16749fSAndrzej Hajda err = igt_vma_move_to_active_unlocked(vma, rq, EXEC_OBJECT_WRITE); 2323fb33cd3SChris Wilson 2333fb33cd3SChris Wilson /* Read the mocs tables back using SRM */ 2343fb33cd3SChris Wilson offset = i915_ggtt_offset(vma); 2353fb33cd3SChris Wilson if (!err) 2368bb92516SChris Wilson err = read_mocs_table(rq, arg->mocs, &offset); 2373fb33cd3SChris Wilson if (!err && ce->engine->class == RENDER_CLASS) 2388bb92516SChris Wilson err = read_l3cc_table(rq, arg->l3cc, &offset); 2393fb33cd3SChris Wilson offset -= i915_ggtt_offset(vma); 2403fb33cd3SChris Wilson GEM_BUG_ON(offset > PAGE_SIZE); 2413fb33cd3SChris Wilson 2423fb33cd3SChris Wilson err = request_add_sync(rq, err); 2433fb33cd3SChris Wilson if (err) 2443fb33cd3SChris Wilson return err; 2453fb33cd3SChris Wilson 2463fb33cd3SChris Wilson /* Compare the results against the expected tables */ 2473fb33cd3SChris Wilson vaddr = arg->vaddr; 2483fb33cd3SChris Wilson if (!err) 2498bb92516SChris Wilson err = check_mocs_table(ce->engine, arg->mocs, &vaddr); 2503fb33cd3SChris Wilson if (!err && ce->engine->class == RENDER_CLASS) 2518bb92516SChris Wilson err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr); 2523fb33cd3SChris Wilson if (err) 2533fb33cd3SChris Wilson return err; 2543fb33cd3SChris Wilson 2553fb33cd3SChris Wilson GEM_BUG_ON(arg->vaddr + offset != vaddr); 2563fb33cd3SChris Wilson return 0; 2573fb33cd3SChris Wilson } 2583fb33cd3SChris Wilson 2593fb33cd3SChris Wilson static int live_mocs_kernel(void *arg) 2603fb33cd3SChris Wilson { 2613fb33cd3SChris Wilson struct intel_gt *gt = arg; 2623fb33cd3SChris Wilson struct intel_engine_cs *engine; 2633fb33cd3SChris Wilson enum intel_engine_id id; 2643fb33cd3SChris Wilson struct live_mocs mocs; 2653fb33cd3SChris Wilson int err; 2663fb33cd3SChris Wilson 2673fb33cd3SChris Wilson /* Basic check the system is configured with the expected mocs table */ 2683fb33cd3SChris Wilson 2693fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 2703fb33cd3SChris Wilson if (err) 2713fb33cd3SChris Wilson return err; 2723fb33cd3SChris Wilson 2733fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 274de5825beSChris Wilson intel_engine_pm_get(engine); 2753fb33cd3SChris Wilson err = check_mocs_engine(&mocs, engine->kernel_context); 276de5825beSChris Wilson intel_engine_pm_put(engine); 2773fb33cd3SChris Wilson if (err) 2783fb33cd3SChris Wilson break; 2793fb33cd3SChris Wilson } 2803fb33cd3SChris Wilson 2813fb33cd3SChris Wilson live_mocs_fini(&mocs); 2823fb33cd3SChris Wilson return err; 2833fb33cd3SChris Wilson } 2843fb33cd3SChris Wilson 2853fb33cd3SChris Wilson static int live_mocs_clean(void *arg) 2863fb33cd3SChris Wilson { 2873fb33cd3SChris Wilson struct intel_gt *gt = arg; 2883fb33cd3SChris Wilson struct intel_engine_cs *engine; 2893fb33cd3SChris Wilson enum intel_engine_id id; 2903fb33cd3SChris Wilson struct live_mocs mocs; 2913fb33cd3SChris Wilson int err; 2923fb33cd3SChris Wilson 2933fb33cd3SChris Wilson /* Every new context should see the same mocs table */ 2943fb33cd3SChris Wilson 2953fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 2963fb33cd3SChris Wilson if (err) 2973fb33cd3SChris Wilson return err; 2983fb33cd3SChris Wilson 2993fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 3003fb33cd3SChris Wilson struct intel_context *ce; 3013fb33cd3SChris Wilson 302e36ba817SChris Wilson ce = mocs_context_create(engine); 3033fb33cd3SChris Wilson if (IS_ERR(ce)) { 3043fb33cd3SChris Wilson err = PTR_ERR(ce); 3053fb33cd3SChris Wilson break; 3063fb33cd3SChris Wilson } 3073fb33cd3SChris Wilson 3083fb33cd3SChris Wilson err = check_mocs_engine(&mocs, ce); 3093fb33cd3SChris Wilson intel_context_put(ce); 3103fb33cd3SChris Wilson if (err) 3113fb33cd3SChris Wilson break; 3123fb33cd3SChris Wilson } 3133fb33cd3SChris Wilson 3143fb33cd3SChris Wilson live_mocs_fini(&mocs); 3153fb33cd3SChris Wilson return err; 3163fb33cd3SChris Wilson } 3173fb33cd3SChris Wilson 3183fb33cd3SChris Wilson static int active_engine_reset(struct intel_context *ce, 319064a1f35SRahul Kumar Singh const char *reason, 320064a1f35SRahul Kumar Singh bool using_guc) 3213fb33cd3SChris Wilson { 3223fb33cd3SChris Wilson struct igt_spinner spin; 3233fb33cd3SChris Wilson struct i915_request *rq; 3243fb33cd3SChris Wilson int err; 3253fb33cd3SChris Wilson 3263fb33cd3SChris Wilson err = igt_spinner_init(&spin, ce->engine->gt); 3273fb33cd3SChris Wilson if (err) 3283fb33cd3SChris Wilson return err; 3293fb33cd3SChris Wilson 3303fb33cd3SChris Wilson rq = igt_spinner_create_request(&spin, ce, MI_NOOP); 3313fb33cd3SChris Wilson if (IS_ERR(rq)) { 3323fb33cd3SChris Wilson igt_spinner_fini(&spin); 3333fb33cd3SChris Wilson return PTR_ERR(rq); 3343fb33cd3SChris Wilson } 3353fb33cd3SChris Wilson 3363fb33cd3SChris Wilson err = request_add_spin(rq, &spin); 337064a1f35SRahul Kumar Singh if (err == 0 && !using_guc) 3383fb33cd3SChris Wilson err = intel_engine_reset(ce->engine, reason); 3393fb33cd3SChris Wilson 340064a1f35SRahul Kumar Singh /* Ensure the reset happens and kills the engine */ 341064a1f35SRahul Kumar Singh if (err == 0) 342064a1f35SRahul Kumar Singh err = intel_selftest_wait_for_rq(rq); 343064a1f35SRahul Kumar Singh 3443fb33cd3SChris Wilson igt_spinner_end(&spin); 3453fb33cd3SChris Wilson igt_spinner_fini(&spin); 3463fb33cd3SChris Wilson 3473fb33cd3SChris Wilson return err; 3483fb33cd3SChris Wilson } 3493fb33cd3SChris Wilson 3503fb33cd3SChris Wilson static int __live_mocs_reset(struct live_mocs *mocs, 351064a1f35SRahul Kumar Singh struct intel_context *ce, bool using_guc) 3523fb33cd3SChris Wilson { 3538005f37cSChris Wilson struct intel_gt *gt = ce->engine->gt; 3543fb33cd3SChris Wilson int err; 3553fb33cd3SChris Wilson 3568005f37cSChris Wilson if (intel_has_reset_engine(gt)) { 357064a1f35SRahul Kumar Singh if (!using_guc) { 3583fb33cd3SChris Wilson err = intel_engine_reset(ce->engine, "mocs"); 3593fb33cd3SChris Wilson if (err) 3603fb33cd3SChris Wilson return err; 3613fb33cd3SChris Wilson 3623fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3633fb33cd3SChris Wilson if (err) 3643fb33cd3SChris Wilson return err; 365064a1f35SRahul Kumar Singh } 3663fb33cd3SChris Wilson 367064a1f35SRahul Kumar Singh err = active_engine_reset(ce, "mocs", using_guc); 3683fb33cd3SChris Wilson if (err) 3693fb33cd3SChris Wilson return err; 3703fb33cd3SChris Wilson 3713fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3723fb33cd3SChris Wilson if (err) 3733fb33cd3SChris Wilson return err; 3748005f37cSChris Wilson } 3753fb33cd3SChris Wilson 3768005f37cSChris Wilson if (intel_has_gpu_reset(gt)) { 3778005f37cSChris Wilson intel_gt_reset(gt, ce->engine->mask, "mocs"); 3783fb33cd3SChris Wilson 3793fb33cd3SChris Wilson err = check_mocs_engine(mocs, ce); 3803fb33cd3SChris Wilson if (err) 3813fb33cd3SChris Wilson return err; 3828005f37cSChris Wilson } 3833fb33cd3SChris Wilson 3843fb33cd3SChris Wilson return 0; 3853fb33cd3SChris Wilson } 3863fb33cd3SChris Wilson 3873fb33cd3SChris Wilson static int live_mocs_reset(void *arg) 3883fb33cd3SChris Wilson { 3893fb33cd3SChris Wilson struct intel_gt *gt = arg; 3903fb33cd3SChris Wilson struct intel_engine_cs *engine; 3913fb33cd3SChris Wilson enum intel_engine_id id; 3923fb33cd3SChris Wilson struct live_mocs mocs; 3933fb33cd3SChris Wilson int err = 0; 3943fb33cd3SChris Wilson 3953fb33cd3SChris Wilson /* Check the mocs setup is retained over per-engine and global resets */ 3963fb33cd3SChris Wilson 3973fb33cd3SChris Wilson err = live_mocs_init(&mocs, gt); 3983fb33cd3SChris Wilson if (err) 3993fb33cd3SChris Wilson return err; 4003fb33cd3SChris Wilson 4013fb33cd3SChris Wilson igt_global_reset_lock(gt); 4023fb33cd3SChris Wilson for_each_engine(engine, gt, id) { 403064a1f35SRahul Kumar Singh bool using_guc = intel_engine_uses_guc(engine); 404064a1f35SRahul Kumar Singh struct intel_selftest_saved_policy saved; 4053fb33cd3SChris Wilson struct intel_context *ce; 406064a1f35SRahul Kumar Singh int err2; 407064a1f35SRahul Kumar Singh 408617e87c0SJohn Harrison err = intel_selftest_modify_policy(engine, &saved, 409617e87c0SJohn Harrison SELFTEST_SCHEDULER_MODIFY_FAST_RESET); 410064a1f35SRahul Kumar Singh if (err) 411064a1f35SRahul Kumar Singh break; 4123fb33cd3SChris Wilson 413e36ba817SChris Wilson ce = mocs_context_create(engine); 4143fb33cd3SChris Wilson if (IS_ERR(ce)) { 4153fb33cd3SChris Wilson err = PTR_ERR(ce); 416064a1f35SRahul Kumar Singh goto restore; 4173fb33cd3SChris Wilson } 4183fb33cd3SChris Wilson 4193fb33cd3SChris Wilson intel_engine_pm_get(engine); 4203fb33cd3SChris Wilson 421064a1f35SRahul Kumar Singh err = __live_mocs_reset(&mocs, ce, using_guc); 422064a1f35SRahul Kumar Singh 423064a1f35SRahul Kumar Singh intel_engine_pm_put(engine); 4243fb33cd3SChris Wilson intel_context_put(ce); 425064a1f35SRahul Kumar Singh 426064a1f35SRahul Kumar Singh restore: 427064a1f35SRahul Kumar Singh err2 = intel_selftest_restore_policy(engine, &saved); 428064a1f35SRahul Kumar Singh if (err == 0) 429064a1f35SRahul Kumar Singh err = err2; 4303fb33cd3SChris Wilson if (err) 4313fb33cd3SChris Wilson break; 4323fb33cd3SChris Wilson } 4333fb33cd3SChris Wilson igt_global_reset_unlock(gt); 4343fb33cd3SChris Wilson 4353fb33cd3SChris Wilson live_mocs_fini(&mocs); 4363fb33cd3SChris Wilson return err; 4373fb33cd3SChris Wilson } 4383fb33cd3SChris Wilson 4393fb33cd3SChris Wilson int intel_mocs_live_selftests(struct drm_i915_private *i915) 4403fb33cd3SChris Wilson { 4413fb33cd3SChris Wilson static const struct i915_subtest tests[] = { 4423fb33cd3SChris Wilson SUBTEST(live_mocs_kernel), 4433fb33cd3SChris Wilson SUBTEST(live_mocs_clean), 4443fb33cd3SChris Wilson SUBTEST(live_mocs_reset), 4453fb33cd3SChris Wilson }; 4463fb33cd3SChris Wilson struct drm_i915_mocs_table table; 4473fb33cd3SChris Wilson 4483fb33cd3SChris Wilson if (!get_mocs_settings(i915, &table)) 4493fb33cd3SChris Wilson return 0; 4503fb33cd3SChris Wilson 451c14adcbdSMichał Winiarski return intel_gt_live_subtests(tests, to_gt(i915)); 4523fb33cd3SChris Wilson } 453