1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/kthread.h> 26 27 #include "gem/i915_gem_context.h" 28 #include "gt/intel_gt.h" 29 #include "intel_engine_pm.h" 30 31 #include "i915_selftest.h" 32 #include "selftests/i915_random.h" 33 #include "selftests/igt_flush_test.h" 34 #include "selftests/igt_reset.h" 35 #include "selftests/igt_atomic.h" 36 37 #include "selftests/mock_drm.h" 38 39 #include "gem/selftests/mock_context.h" 40 #include "gem/selftests/igt_gem_utils.h" 41 42 #define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests */ 43 44 struct hang { 45 struct intel_gt *gt; 46 struct drm_i915_gem_object *hws; 47 struct drm_i915_gem_object *obj; 48 struct i915_gem_context *ctx; 49 u32 *seqno; 50 u32 *batch; 51 }; 52 53 static int hang_init(struct hang *h, struct intel_gt *gt) 54 { 55 void *vaddr; 56 int err; 57 58 memset(h, 0, sizeof(*h)); 59 h->gt = gt; 60 61 h->ctx = kernel_context(gt->i915); 62 if (IS_ERR(h->ctx)) 63 return PTR_ERR(h->ctx); 64 65 GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx)); 66 67 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 68 if (IS_ERR(h->hws)) { 69 err = PTR_ERR(h->hws); 70 goto err_ctx; 71 } 72 73 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 74 if (IS_ERR(h->obj)) { 75 err = PTR_ERR(h->obj); 76 goto err_hws; 77 } 78 79 i915_gem_object_set_cache_coherency(h->hws, I915_CACHE_LLC); 80 vaddr = i915_gem_object_pin_map(h->hws, I915_MAP_WB); 81 if (IS_ERR(vaddr)) { 82 err = PTR_ERR(vaddr); 83 goto err_obj; 84 } 85 h->seqno = memset(vaddr, 0xff, PAGE_SIZE); 86 87 vaddr = i915_gem_object_pin_map(h->obj, 88 i915_coherent_map_type(gt->i915)); 89 if (IS_ERR(vaddr)) { 90 err = PTR_ERR(vaddr); 91 goto err_unpin_hws; 92 } 93 h->batch = vaddr; 94 95 return 0; 96 97 err_unpin_hws: 98 i915_gem_object_unpin_map(h->hws); 99 err_obj: 100 i915_gem_object_put(h->obj); 101 err_hws: 102 i915_gem_object_put(h->hws); 103 err_ctx: 104 kernel_context_close(h->ctx); 105 return err; 106 } 107 108 static u64 hws_address(const struct i915_vma *hws, 109 const struct i915_request *rq) 110 { 111 return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context); 112 } 113 114 static int move_to_active(struct i915_vma *vma, 115 struct i915_request *rq, 116 unsigned int flags) 117 { 118 int err; 119 120 i915_vma_lock(vma); 121 err = i915_request_await_object(rq, vma->obj, 122 flags & EXEC_OBJECT_WRITE); 123 if (err == 0) 124 err = i915_vma_move_to_active(vma, rq, flags); 125 i915_vma_unlock(vma); 126 127 return err; 128 } 129 130 static struct i915_request * 131 hang_create_request(struct hang *h, struct intel_engine_cs *engine) 132 { 133 struct intel_gt *gt = h->gt; 134 struct i915_address_space *vm = i915_gem_context_get_vm_rcu(h->ctx); 135 struct drm_i915_gem_object *obj; 136 struct i915_request *rq = NULL; 137 struct i915_vma *hws, *vma; 138 unsigned int flags; 139 void *vaddr; 140 u32 *batch; 141 int err; 142 143 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); 144 if (IS_ERR(obj)) { 145 i915_vm_put(vm); 146 return ERR_CAST(obj); 147 } 148 149 vaddr = i915_gem_object_pin_map(obj, i915_coherent_map_type(gt->i915)); 150 if (IS_ERR(vaddr)) { 151 i915_gem_object_put(obj); 152 i915_vm_put(vm); 153 return ERR_CAST(vaddr); 154 } 155 156 i915_gem_object_unpin_map(h->obj); 157 i915_gem_object_put(h->obj); 158 159 h->obj = obj; 160 h->batch = vaddr; 161 162 vma = i915_vma_instance(h->obj, vm, NULL); 163 if (IS_ERR(vma)) { 164 i915_vm_put(vm); 165 return ERR_CAST(vma); 166 } 167 168 hws = i915_vma_instance(h->hws, vm, NULL); 169 if (IS_ERR(hws)) { 170 i915_vm_put(vm); 171 return ERR_CAST(hws); 172 } 173 174 err = i915_vma_pin(vma, 0, 0, PIN_USER); 175 if (err) { 176 i915_vm_put(vm); 177 return ERR_PTR(err); 178 } 179 180 err = i915_vma_pin(hws, 0, 0, PIN_USER); 181 if (err) 182 goto unpin_vma; 183 184 rq = igt_request_alloc(h->ctx, engine); 185 if (IS_ERR(rq)) { 186 err = PTR_ERR(rq); 187 goto unpin_hws; 188 } 189 190 err = move_to_active(vma, rq, 0); 191 if (err) 192 goto cancel_rq; 193 194 err = move_to_active(hws, rq, 0); 195 if (err) 196 goto cancel_rq; 197 198 batch = h->batch; 199 if (INTEL_GEN(gt->i915) >= 8) { 200 *batch++ = MI_STORE_DWORD_IMM_GEN4; 201 *batch++ = lower_32_bits(hws_address(hws, rq)); 202 *batch++ = upper_32_bits(hws_address(hws, rq)); 203 *batch++ = rq->fence.seqno; 204 *batch++ = MI_ARB_CHECK; 205 206 memset(batch, 0, 1024); 207 batch += 1024 / sizeof(*batch); 208 209 *batch++ = MI_ARB_CHECK; 210 *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; 211 *batch++ = lower_32_bits(vma->node.start); 212 *batch++ = upper_32_bits(vma->node.start); 213 } else if (INTEL_GEN(gt->i915) >= 6) { 214 *batch++ = MI_STORE_DWORD_IMM_GEN4; 215 *batch++ = 0; 216 *batch++ = lower_32_bits(hws_address(hws, rq)); 217 *batch++ = rq->fence.seqno; 218 *batch++ = MI_ARB_CHECK; 219 220 memset(batch, 0, 1024); 221 batch += 1024 / sizeof(*batch); 222 223 *batch++ = MI_ARB_CHECK; 224 *batch++ = MI_BATCH_BUFFER_START | 1 << 8; 225 *batch++ = lower_32_bits(vma->node.start); 226 } else if (INTEL_GEN(gt->i915) >= 4) { 227 *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; 228 *batch++ = 0; 229 *batch++ = lower_32_bits(hws_address(hws, rq)); 230 *batch++ = rq->fence.seqno; 231 *batch++ = MI_ARB_CHECK; 232 233 memset(batch, 0, 1024); 234 batch += 1024 / sizeof(*batch); 235 236 *batch++ = MI_ARB_CHECK; 237 *batch++ = MI_BATCH_BUFFER_START | 2 << 6; 238 *batch++ = lower_32_bits(vma->node.start); 239 } else { 240 *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; 241 *batch++ = lower_32_bits(hws_address(hws, rq)); 242 *batch++ = rq->fence.seqno; 243 *batch++ = MI_ARB_CHECK; 244 245 memset(batch, 0, 1024); 246 batch += 1024 / sizeof(*batch); 247 248 *batch++ = MI_ARB_CHECK; 249 *batch++ = MI_BATCH_BUFFER_START | 2 << 6; 250 *batch++ = lower_32_bits(vma->node.start); 251 } 252 *batch++ = MI_BATCH_BUFFER_END; /* not reached */ 253 intel_gt_chipset_flush(engine->gt); 254 255 if (rq->engine->emit_init_breadcrumb) { 256 err = rq->engine->emit_init_breadcrumb(rq); 257 if (err) 258 goto cancel_rq; 259 } 260 261 flags = 0; 262 if (INTEL_GEN(gt->i915) <= 5) 263 flags |= I915_DISPATCH_SECURE; 264 265 err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); 266 267 cancel_rq: 268 if (err) { 269 i915_request_skip(rq, err); 270 i915_request_add(rq); 271 } 272 unpin_hws: 273 i915_vma_unpin(hws); 274 unpin_vma: 275 i915_vma_unpin(vma); 276 i915_vm_put(vm); 277 return err ? ERR_PTR(err) : rq; 278 } 279 280 static u32 hws_seqno(const struct hang *h, const struct i915_request *rq) 281 { 282 return READ_ONCE(h->seqno[rq->fence.context % (PAGE_SIZE/sizeof(u32))]); 283 } 284 285 static void hang_fini(struct hang *h) 286 { 287 *h->batch = MI_BATCH_BUFFER_END; 288 intel_gt_chipset_flush(h->gt); 289 290 i915_gem_object_unpin_map(h->obj); 291 i915_gem_object_put(h->obj); 292 293 i915_gem_object_unpin_map(h->hws); 294 i915_gem_object_put(h->hws); 295 296 kernel_context_close(h->ctx); 297 298 igt_flush_test(h->gt->i915); 299 } 300 301 static bool wait_until_running(struct hang *h, struct i915_request *rq) 302 { 303 return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq), 304 rq->fence.seqno), 305 10) && 306 wait_for(i915_seqno_passed(hws_seqno(h, rq), 307 rq->fence.seqno), 308 1000)); 309 } 310 311 static int igt_hang_sanitycheck(void *arg) 312 { 313 struct intel_gt *gt = arg; 314 struct i915_request *rq; 315 struct intel_engine_cs *engine; 316 enum intel_engine_id id; 317 struct hang h; 318 int err; 319 320 /* Basic check that we can execute our hanging batch */ 321 322 err = hang_init(&h, gt); 323 if (err) 324 return err; 325 326 for_each_engine(engine, gt, id) { 327 struct intel_wedge_me w; 328 long timeout; 329 330 if (!intel_engine_can_store_dword(engine)) 331 continue; 332 333 rq = hang_create_request(&h, engine); 334 if (IS_ERR(rq)) { 335 err = PTR_ERR(rq); 336 pr_err("Failed to create request for %s, err=%d\n", 337 engine->name, err); 338 goto fini; 339 } 340 341 i915_request_get(rq); 342 343 *h.batch = MI_BATCH_BUFFER_END; 344 intel_gt_chipset_flush(engine->gt); 345 346 i915_request_add(rq); 347 348 timeout = 0; 349 intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */) 350 timeout = i915_request_wait(rq, 0, 351 MAX_SCHEDULE_TIMEOUT); 352 if (intel_gt_is_wedged(gt)) 353 timeout = -EIO; 354 355 i915_request_put(rq); 356 357 if (timeout < 0) { 358 err = timeout; 359 pr_err("Wait for request failed on %s, err=%d\n", 360 engine->name, err); 361 goto fini; 362 } 363 } 364 365 fini: 366 hang_fini(&h); 367 return err; 368 } 369 370 static bool wait_for_idle(struct intel_engine_cs *engine) 371 { 372 return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0; 373 } 374 375 static int igt_reset_nop(void *arg) 376 { 377 struct intel_gt *gt = arg; 378 struct i915_gpu_error *global = >->i915->gpu_error; 379 struct intel_engine_cs *engine; 380 struct i915_gem_context *ctx; 381 unsigned int reset_count, count; 382 enum intel_engine_id id; 383 struct drm_file *file; 384 IGT_TIMEOUT(end_time); 385 int err = 0; 386 387 /* Check that we can reset during non-user portions of requests */ 388 389 file = mock_file(gt->i915); 390 if (IS_ERR(file)) 391 return PTR_ERR(file); 392 393 ctx = live_context(gt->i915, file); 394 if (IS_ERR(ctx)) { 395 err = PTR_ERR(ctx); 396 goto out; 397 } 398 399 i915_gem_context_clear_bannable(ctx); 400 reset_count = i915_reset_count(global); 401 count = 0; 402 do { 403 for_each_engine(engine, gt, id) { 404 int i; 405 406 for (i = 0; i < 16; i++) { 407 struct i915_request *rq; 408 409 rq = igt_request_alloc(ctx, engine); 410 if (IS_ERR(rq)) { 411 err = PTR_ERR(rq); 412 break; 413 } 414 415 i915_request_add(rq); 416 } 417 } 418 419 igt_global_reset_lock(gt); 420 intel_gt_reset(gt, ALL_ENGINES, NULL); 421 igt_global_reset_unlock(gt); 422 423 if (intel_gt_is_wedged(gt)) { 424 err = -EIO; 425 break; 426 } 427 428 if (i915_reset_count(global) != reset_count + ++count) { 429 pr_err("Full GPU reset not recorded!\n"); 430 err = -EINVAL; 431 break; 432 } 433 434 err = igt_flush_test(gt->i915); 435 if (err) 436 break; 437 } while (time_before(jiffies, end_time)); 438 pr_info("%s: %d resets\n", __func__, count); 439 440 err = igt_flush_test(gt->i915); 441 out: 442 mock_file_free(gt->i915, file); 443 if (intel_gt_is_wedged(gt)) 444 err = -EIO; 445 return err; 446 } 447 448 static int igt_reset_nop_engine(void *arg) 449 { 450 struct intel_gt *gt = arg; 451 struct i915_gpu_error *global = >->i915->gpu_error; 452 struct intel_engine_cs *engine; 453 struct i915_gem_context *ctx; 454 enum intel_engine_id id; 455 struct drm_file *file; 456 int err = 0; 457 458 /* Check that we can engine-reset during non-user portions */ 459 460 if (!intel_has_reset_engine(gt)) 461 return 0; 462 463 file = mock_file(gt->i915); 464 if (IS_ERR(file)) 465 return PTR_ERR(file); 466 467 ctx = live_context(gt->i915, file); 468 if (IS_ERR(ctx)) { 469 err = PTR_ERR(ctx); 470 goto out; 471 } 472 473 i915_gem_context_clear_bannable(ctx); 474 for_each_engine(engine, gt, id) { 475 unsigned int reset_count, reset_engine_count; 476 unsigned int count; 477 IGT_TIMEOUT(end_time); 478 479 reset_count = i915_reset_count(global); 480 reset_engine_count = i915_reset_engine_count(global, engine); 481 count = 0; 482 483 set_bit(I915_RESET_ENGINE + id, >->reset.flags); 484 do { 485 int i; 486 487 if (!wait_for_idle(engine)) { 488 pr_err("%s failed to idle before reset\n", 489 engine->name); 490 err = -EIO; 491 break; 492 } 493 494 for (i = 0; i < 16; i++) { 495 struct i915_request *rq; 496 497 rq = igt_request_alloc(ctx, engine); 498 if (IS_ERR(rq)) { 499 err = PTR_ERR(rq); 500 break; 501 } 502 503 i915_request_add(rq); 504 } 505 err = intel_engine_reset(engine, NULL); 506 if (err) { 507 pr_err("i915_reset_engine failed\n"); 508 break; 509 } 510 511 if (i915_reset_count(global) != reset_count) { 512 pr_err("Full GPU reset recorded! (engine reset expected)\n"); 513 err = -EINVAL; 514 break; 515 } 516 517 if (i915_reset_engine_count(global, engine) != 518 reset_engine_count + ++count) { 519 pr_err("%s engine reset not recorded!\n", 520 engine->name); 521 err = -EINVAL; 522 break; 523 } 524 } while (time_before(jiffies, end_time)); 525 clear_bit(I915_RESET_ENGINE + id, >->reset.flags); 526 pr_info("%s(%s): %d resets\n", __func__, engine->name, count); 527 528 if (err) 529 break; 530 531 err = igt_flush_test(gt->i915); 532 if (err) 533 break; 534 } 535 536 err = igt_flush_test(gt->i915); 537 out: 538 mock_file_free(gt->i915, file); 539 if (intel_gt_is_wedged(gt)) 540 err = -EIO; 541 return err; 542 } 543 544 static int __igt_reset_engine(struct intel_gt *gt, bool active) 545 { 546 struct i915_gpu_error *global = >->i915->gpu_error; 547 struct intel_engine_cs *engine; 548 enum intel_engine_id id; 549 struct hang h; 550 int err = 0; 551 552 /* Check that we can issue an engine reset on an idle engine (no-op) */ 553 554 if (!intel_has_reset_engine(gt)) 555 return 0; 556 557 if (active) { 558 err = hang_init(&h, gt); 559 if (err) 560 return err; 561 } 562 563 for_each_engine(engine, gt, id) { 564 unsigned int reset_count, reset_engine_count; 565 IGT_TIMEOUT(end_time); 566 567 if (active && !intel_engine_can_store_dword(engine)) 568 continue; 569 570 if (!wait_for_idle(engine)) { 571 pr_err("%s failed to idle before reset\n", 572 engine->name); 573 err = -EIO; 574 break; 575 } 576 577 reset_count = i915_reset_count(global); 578 reset_engine_count = i915_reset_engine_count(global, engine); 579 580 intel_engine_pm_get(engine); 581 set_bit(I915_RESET_ENGINE + id, >->reset.flags); 582 do { 583 if (active) { 584 struct i915_request *rq; 585 586 rq = hang_create_request(&h, engine); 587 if (IS_ERR(rq)) { 588 err = PTR_ERR(rq); 589 break; 590 } 591 592 i915_request_get(rq); 593 i915_request_add(rq); 594 595 if (!wait_until_running(&h, rq)) { 596 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 597 598 pr_err("%s: Failed to start request %llx, at %x\n", 599 __func__, rq->fence.seqno, hws_seqno(&h, rq)); 600 intel_engine_dump(engine, &p, 601 "%s\n", engine->name); 602 603 i915_request_put(rq); 604 err = -EIO; 605 break; 606 } 607 608 i915_request_put(rq); 609 } 610 611 err = intel_engine_reset(engine, NULL); 612 if (err) { 613 pr_err("i915_reset_engine failed\n"); 614 break; 615 } 616 617 if (i915_reset_count(global) != reset_count) { 618 pr_err("Full GPU reset recorded! (engine reset expected)\n"); 619 err = -EINVAL; 620 break; 621 } 622 623 if (i915_reset_engine_count(global, engine) != 624 ++reset_engine_count) { 625 pr_err("%s engine reset not recorded!\n", 626 engine->name); 627 err = -EINVAL; 628 break; 629 } 630 } while (time_before(jiffies, end_time)); 631 clear_bit(I915_RESET_ENGINE + id, >->reset.flags); 632 intel_engine_pm_put(engine); 633 634 if (err) 635 break; 636 637 err = igt_flush_test(gt->i915); 638 if (err) 639 break; 640 } 641 642 if (intel_gt_is_wedged(gt)) 643 err = -EIO; 644 645 if (active) 646 hang_fini(&h); 647 648 return err; 649 } 650 651 static int igt_reset_idle_engine(void *arg) 652 { 653 return __igt_reset_engine(arg, false); 654 } 655 656 static int igt_reset_active_engine(void *arg) 657 { 658 return __igt_reset_engine(arg, true); 659 } 660 661 struct active_engine { 662 struct task_struct *task; 663 struct intel_engine_cs *engine; 664 unsigned long resets; 665 unsigned int flags; 666 }; 667 668 #define TEST_ACTIVE BIT(0) 669 #define TEST_OTHERS BIT(1) 670 #define TEST_SELF BIT(2) 671 #define TEST_PRIORITY BIT(3) 672 673 static int active_request_put(struct i915_request *rq) 674 { 675 int err = 0; 676 677 if (!rq) 678 return 0; 679 680 if (i915_request_wait(rq, 0, 5 * HZ) < 0) { 681 GEM_TRACE("%s timed out waiting for completion of fence %llx:%lld\n", 682 rq->engine->name, 683 rq->fence.context, 684 rq->fence.seqno); 685 GEM_TRACE_DUMP(); 686 687 intel_gt_set_wedged(rq->engine->gt); 688 err = -EIO; 689 } 690 691 i915_request_put(rq); 692 693 return err; 694 } 695 696 static int active_engine(void *data) 697 { 698 I915_RND_STATE(prng); 699 struct active_engine *arg = data; 700 struct intel_engine_cs *engine = arg->engine; 701 struct i915_request *rq[8] = {}; 702 struct i915_gem_context *ctx[ARRAY_SIZE(rq)]; 703 struct drm_file *file; 704 unsigned long count = 0; 705 int err = 0; 706 707 file = mock_file(engine->i915); 708 if (IS_ERR(file)) 709 return PTR_ERR(file); 710 711 for (count = 0; count < ARRAY_SIZE(ctx); count++) { 712 ctx[count] = live_context(engine->i915, file); 713 if (IS_ERR(ctx[count])) { 714 err = PTR_ERR(ctx[count]); 715 while (--count) 716 i915_gem_context_put(ctx[count]); 717 goto err_file; 718 } 719 } 720 721 while (!kthread_should_stop()) { 722 unsigned int idx = count++ & (ARRAY_SIZE(rq) - 1); 723 struct i915_request *old = rq[idx]; 724 struct i915_request *new; 725 726 new = igt_request_alloc(ctx[idx], engine); 727 if (IS_ERR(new)) { 728 err = PTR_ERR(new); 729 break; 730 } 731 732 if (arg->flags & TEST_PRIORITY) 733 ctx[idx]->sched.priority = 734 i915_prandom_u32_max_state(512, &prng); 735 736 rq[idx] = i915_request_get(new); 737 i915_request_add(new); 738 739 err = active_request_put(old); 740 if (err) 741 break; 742 743 cond_resched(); 744 } 745 746 for (count = 0; count < ARRAY_SIZE(rq); count++) { 747 int err__ = active_request_put(rq[count]); 748 749 /* Keep the first error */ 750 if (!err) 751 err = err__; 752 } 753 754 err_file: 755 mock_file_free(engine->i915, file); 756 return err; 757 } 758 759 static int __igt_reset_engines(struct intel_gt *gt, 760 const char *test_name, 761 unsigned int flags) 762 { 763 struct i915_gpu_error *global = >->i915->gpu_error; 764 struct intel_engine_cs *engine, *other; 765 enum intel_engine_id id, tmp; 766 struct hang h; 767 int err = 0; 768 769 /* Check that issuing a reset on one engine does not interfere 770 * with any other engine. 771 */ 772 773 if (!intel_has_reset_engine(gt)) 774 return 0; 775 776 if (flags & TEST_ACTIVE) { 777 err = hang_init(&h, gt); 778 if (err) 779 return err; 780 781 if (flags & TEST_PRIORITY) 782 h.ctx->sched.priority = 1024; 783 } 784 785 for_each_engine(engine, gt, id) { 786 struct active_engine threads[I915_NUM_ENGINES] = {}; 787 unsigned long device = i915_reset_count(global); 788 unsigned long count = 0, reported; 789 IGT_TIMEOUT(end_time); 790 791 if (flags & TEST_ACTIVE && 792 !intel_engine_can_store_dword(engine)) 793 continue; 794 795 if (!wait_for_idle(engine)) { 796 pr_err("i915_reset_engine(%s:%s): failed to idle before reset\n", 797 engine->name, test_name); 798 err = -EIO; 799 break; 800 } 801 802 memset(threads, 0, sizeof(threads)); 803 for_each_engine(other, gt, tmp) { 804 struct task_struct *tsk; 805 806 threads[tmp].resets = 807 i915_reset_engine_count(global, other); 808 809 if (!(flags & TEST_OTHERS)) 810 continue; 811 812 if (other == engine && !(flags & TEST_SELF)) 813 continue; 814 815 threads[tmp].engine = other; 816 threads[tmp].flags = flags; 817 818 tsk = kthread_run(active_engine, &threads[tmp], 819 "igt/%s", other->name); 820 if (IS_ERR(tsk)) { 821 err = PTR_ERR(tsk); 822 goto unwind; 823 } 824 825 threads[tmp].task = tsk; 826 get_task_struct(tsk); 827 } 828 829 intel_engine_pm_get(engine); 830 set_bit(I915_RESET_ENGINE + id, >->reset.flags); 831 do { 832 struct i915_request *rq = NULL; 833 834 if (flags & TEST_ACTIVE) { 835 rq = hang_create_request(&h, engine); 836 if (IS_ERR(rq)) { 837 err = PTR_ERR(rq); 838 break; 839 } 840 841 i915_request_get(rq); 842 i915_request_add(rq); 843 844 if (!wait_until_running(&h, rq)) { 845 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 846 847 pr_err("%s: Failed to start request %llx, at %x\n", 848 __func__, rq->fence.seqno, hws_seqno(&h, rq)); 849 intel_engine_dump(engine, &p, 850 "%s\n", engine->name); 851 852 i915_request_put(rq); 853 err = -EIO; 854 break; 855 } 856 } 857 858 err = intel_engine_reset(engine, NULL); 859 if (err) { 860 pr_err("i915_reset_engine(%s:%s): failed, err=%d\n", 861 engine->name, test_name, err); 862 break; 863 } 864 865 count++; 866 867 if (rq) { 868 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 869 struct drm_printer p = 870 drm_info_printer(gt->i915->drm.dev); 871 872 pr_err("i915_reset_engine(%s:%s):" 873 " failed to complete request after reset\n", 874 engine->name, test_name); 875 intel_engine_dump(engine, &p, 876 "%s\n", engine->name); 877 i915_request_put(rq); 878 879 GEM_TRACE_DUMP(); 880 intel_gt_set_wedged(gt); 881 err = -EIO; 882 break; 883 } 884 885 i915_request_put(rq); 886 } 887 888 if (!(flags & TEST_SELF) && !wait_for_idle(engine)) { 889 struct drm_printer p = 890 drm_info_printer(gt->i915->drm.dev); 891 892 pr_err("i915_reset_engine(%s:%s):" 893 " failed to idle after reset\n", 894 engine->name, test_name); 895 intel_engine_dump(engine, &p, 896 "%s\n", engine->name); 897 898 err = -EIO; 899 break; 900 } 901 } while (time_before(jiffies, end_time)); 902 clear_bit(I915_RESET_ENGINE + id, >->reset.flags); 903 intel_engine_pm_put(engine); 904 pr_info("i915_reset_engine(%s:%s): %lu resets\n", 905 engine->name, test_name, count); 906 907 reported = i915_reset_engine_count(global, engine); 908 reported -= threads[engine->id].resets; 909 if (reported != count) { 910 pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n", 911 engine->name, test_name, count, reported); 912 if (!err) 913 err = -EINVAL; 914 } 915 916 unwind: 917 for_each_engine(other, gt, tmp) { 918 int ret; 919 920 if (!threads[tmp].task) 921 continue; 922 923 ret = kthread_stop(threads[tmp].task); 924 if (ret) { 925 pr_err("kthread for other engine %s failed, err=%d\n", 926 other->name, ret); 927 if (!err) 928 err = ret; 929 } 930 put_task_struct(threads[tmp].task); 931 932 if (other->uabi_class != engine->uabi_class && 933 threads[tmp].resets != 934 i915_reset_engine_count(global, other)) { 935 pr_err("Innocent engine %s was reset (count=%ld)\n", 936 other->name, 937 i915_reset_engine_count(global, other) - 938 threads[tmp].resets); 939 if (!err) 940 err = -EINVAL; 941 } 942 } 943 944 if (device != i915_reset_count(global)) { 945 pr_err("Global reset (count=%ld)!\n", 946 i915_reset_count(global) - device); 947 if (!err) 948 err = -EINVAL; 949 } 950 951 if (err) 952 break; 953 954 err = igt_flush_test(gt->i915); 955 if (err) 956 break; 957 } 958 959 if (intel_gt_is_wedged(gt)) 960 err = -EIO; 961 962 if (flags & TEST_ACTIVE) 963 hang_fini(&h); 964 965 return err; 966 } 967 968 static int igt_reset_engines(void *arg) 969 { 970 static const struct { 971 const char *name; 972 unsigned int flags; 973 } phases[] = { 974 { "idle", 0 }, 975 { "active", TEST_ACTIVE }, 976 { "others-idle", TEST_OTHERS }, 977 { "others-active", TEST_OTHERS | TEST_ACTIVE }, 978 { 979 "others-priority", 980 TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY 981 }, 982 { 983 "self-priority", 984 TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY | TEST_SELF, 985 }, 986 { } 987 }; 988 struct intel_gt *gt = arg; 989 typeof(*phases) *p; 990 int err; 991 992 for (p = phases; p->name; p++) { 993 if (p->flags & TEST_PRIORITY) { 994 if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY)) 995 continue; 996 } 997 998 err = __igt_reset_engines(arg, p->name, p->flags); 999 if (err) 1000 return err; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask) 1007 { 1008 u32 count = i915_reset_count(>->i915->gpu_error); 1009 1010 intel_gt_reset(gt, mask, NULL); 1011 1012 return count; 1013 } 1014 1015 static int igt_reset_wait(void *arg) 1016 { 1017 struct intel_gt *gt = arg; 1018 struct i915_gpu_error *global = >->i915->gpu_error; 1019 struct intel_engine_cs *engine = gt->engine[RCS0]; 1020 struct i915_request *rq; 1021 unsigned int reset_count; 1022 struct hang h; 1023 long timeout; 1024 int err; 1025 1026 if (!engine || !intel_engine_can_store_dword(engine)) 1027 return 0; 1028 1029 /* Check that we detect a stuck waiter and issue a reset */ 1030 1031 igt_global_reset_lock(gt); 1032 1033 err = hang_init(&h, gt); 1034 if (err) 1035 goto unlock; 1036 1037 rq = hang_create_request(&h, engine); 1038 if (IS_ERR(rq)) { 1039 err = PTR_ERR(rq); 1040 goto fini; 1041 } 1042 1043 i915_request_get(rq); 1044 i915_request_add(rq); 1045 1046 if (!wait_until_running(&h, rq)) { 1047 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 1048 1049 pr_err("%s: Failed to start request %llx, at %x\n", 1050 __func__, rq->fence.seqno, hws_seqno(&h, rq)); 1051 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); 1052 1053 intel_gt_set_wedged(gt); 1054 1055 err = -EIO; 1056 goto out_rq; 1057 } 1058 1059 reset_count = fake_hangcheck(gt, ALL_ENGINES); 1060 1061 timeout = i915_request_wait(rq, 0, 10); 1062 if (timeout < 0) { 1063 pr_err("i915_request_wait failed on a stuck request: err=%ld\n", 1064 timeout); 1065 err = timeout; 1066 goto out_rq; 1067 } 1068 1069 if (i915_reset_count(global) == reset_count) { 1070 pr_err("No GPU reset recorded!\n"); 1071 err = -EINVAL; 1072 goto out_rq; 1073 } 1074 1075 out_rq: 1076 i915_request_put(rq); 1077 fini: 1078 hang_fini(&h); 1079 unlock: 1080 igt_global_reset_unlock(gt); 1081 1082 if (intel_gt_is_wedged(gt)) 1083 return -EIO; 1084 1085 return err; 1086 } 1087 1088 struct evict_vma { 1089 struct completion completion; 1090 struct i915_vma *vma; 1091 }; 1092 1093 static int evict_vma(void *data) 1094 { 1095 struct evict_vma *arg = data; 1096 struct i915_address_space *vm = arg->vma->vm; 1097 struct drm_mm_node evict = arg->vma->node; 1098 int err; 1099 1100 complete(&arg->completion); 1101 1102 mutex_lock(&vm->mutex); 1103 err = i915_gem_evict_for_node(vm, &evict, 0); 1104 mutex_unlock(&vm->mutex); 1105 1106 return err; 1107 } 1108 1109 static int evict_fence(void *data) 1110 { 1111 struct evict_vma *arg = data; 1112 int err; 1113 1114 complete(&arg->completion); 1115 1116 /* Mark the fence register as dirty to force the mmio update. */ 1117 err = i915_gem_object_set_tiling(arg->vma->obj, I915_TILING_Y, 512); 1118 if (err) { 1119 pr_err("Invalid Y-tiling settings; err:%d\n", err); 1120 return err; 1121 } 1122 1123 err = i915_vma_pin(arg->vma, 0, 0, PIN_GLOBAL | PIN_MAPPABLE); 1124 if (err) { 1125 pr_err("Unable to pin vma for Y-tiled fence; err:%d\n", err); 1126 return err; 1127 } 1128 1129 err = i915_vma_pin_fence(arg->vma); 1130 i915_vma_unpin(arg->vma); 1131 if (err) { 1132 pr_err("Unable to pin Y-tiled fence; err:%d\n", err); 1133 return err; 1134 } 1135 1136 i915_vma_unpin_fence(arg->vma); 1137 1138 return 0; 1139 } 1140 1141 static int __igt_reset_evict_vma(struct intel_gt *gt, 1142 struct i915_address_space *vm, 1143 int (*fn)(void *), 1144 unsigned int flags) 1145 { 1146 struct intel_engine_cs *engine = gt->engine[RCS0]; 1147 struct drm_i915_gem_object *obj; 1148 struct task_struct *tsk = NULL; 1149 struct i915_request *rq; 1150 struct evict_vma arg; 1151 struct hang h; 1152 unsigned int pin_flags; 1153 int err; 1154 1155 if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE) 1156 return 0; 1157 1158 if (!engine || !intel_engine_can_store_dword(engine)) 1159 return 0; 1160 1161 /* Check that we can recover an unbind stuck on a hanging request */ 1162 1163 err = hang_init(&h, gt); 1164 if (err) 1165 return err; 1166 1167 obj = i915_gem_object_create_internal(gt->i915, SZ_1M); 1168 if (IS_ERR(obj)) { 1169 err = PTR_ERR(obj); 1170 goto fini; 1171 } 1172 1173 if (flags & EXEC_OBJECT_NEEDS_FENCE) { 1174 err = i915_gem_object_set_tiling(obj, I915_TILING_X, 512); 1175 if (err) { 1176 pr_err("Invalid X-tiling settings; err:%d\n", err); 1177 goto out_obj; 1178 } 1179 } 1180 1181 arg.vma = i915_vma_instance(obj, vm, NULL); 1182 if (IS_ERR(arg.vma)) { 1183 err = PTR_ERR(arg.vma); 1184 goto out_obj; 1185 } 1186 1187 rq = hang_create_request(&h, engine); 1188 if (IS_ERR(rq)) { 1189 err = PTR_ERR(rq); 1190 goto out_obj; 1191 } 1192 1193 pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER; 1194 1195 if (flags & EXEC_OBJECT_NEEDS_FENCE) 1196 pin_flags |= PIN_MAPPABLE; 1197 1198 err = i915_vma_pin(arg.vma, 0, 0, pin_flags); 1199 if (err) { 1200 i915_request_add(rq); 1201 goto out_obj; 1202 } 1203 1204 if (flags & EXEC_OBJECT_NEEDS_FENCE) { 1205 err = i915_vma_pin_fence(arg.vma); 1206 if (err) { 1207 pr_err("Unable to pin X-tiled fence; err:%d\n", err); 1208 i915_vma_unpin(arg.vma); 1209 i915_request_add(rq); 1210 goto out_obj; 1211 } 1212 } 1213 1214 i915_vma_lock(arg.vma); 1215 err = i915_request_await_object(rq, arg.vma->obj, 1216 flags & EXEC_OBJECT_WRITE); 1217 if (err == 0) 1218 err = i915_vma_move_to_active(arg.vma, rq, flags); 1219 i915_vma_unlock(arg.vma); 1220 1221 if (flags & EXEC_OBJECT_NEEDS_FENCE) 1222 i915_vma_unpin_fence(arg.vma); 1223 i915_vma_unpin(arg.vma); 1224 1225 i915_request_get(rq); 1226 i915_request_add(rq); 1227 if (err) 1228 goto out_rq; 1229 1230 if (!wait_until_running(&h, rq)) { 1231 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 1232 1233 pr_err("%s: Failed to start request %llx, at %x\n", 1234 __func__, rq->fence.seqno, hws_seqno(&h, rq)); 1235 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); 1236 1237 intel_gt_set_wedged(gt); 1238 goto out_reset; 1239 } 1240 1241 init_completion(&arg.completion); 1242 1243 tsk = kthread_run(fn, &arg, "igt/evict_vma"); 1244 if (IS_ERR(tsk)) { 1245 err = PTR_ERR(tsk); 1246 tsk = NULL; 1247 goto out_reset; 1248 } 1249 get_task_struct(tsk); 1250 1251 wait_for_completion(&arg.completion); 1252 1253 if (wait_for(!list_empty(&rq->fence.cb_list), 10)) { 1254 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 1255 1256 pr_err("igt/evict_vma kthread did not wait\n"); 1257 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); 1258 1259 intel_gt_set_wedged(gt); 1260 goto out_reset; 1261 } 1262 1263 out_reset: 1264 igt_global_reset_lock(gt); 1265 fake_hangcheck(gt, rq->engine->mask); 1266 igt_global_reset_unlock(gt); 1267 1268 if (tsk) { 1269 struct intel_wedge_me w; 1270 1271 /* The reset, even indirectly, should take less than 10ms. */ 1272 intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */) 1273 err = kthread_stop(tsk); 1274 1275 put_task_struct(tsk); 1276 } 1277 1278 out_rq: 1279 i915_request_put(rq); 1280 out_obj: 1281 i915_gem_object_put(obj); 1282 fini: 1283 hang_fini(&h); 1284 if (intel_gt_is_wedged(gt)) 1285 return -EIO; 1286 1287 return err; 1288 } 1289 1290 static int igt_reset_evict_ggtt(void *arg) 1291 { 1292 struct intel_gt *gt = arg; 1293 1294 return __igt_reset_evict_vma(gt, >->ggtt->vm, 1295 evict_vma, EXEC_OBJECT_WRITE); 1296 } 1297 1298 static int igt_reset_evict_ppgtt(void *arg) 1299 { 1300 struct intel_gt *gt = arg; 1301 struct i915_gem_context *ctx; 1302 struct i915_address_space *vm; 1303 struct drm_file *file; 1304 int err; 1305 1306 file = mock_file(gt->i915); 1307 if (IS_ERR(file)) 1308 return PTR_ERR(file); 1309 1310 ctx = live_context(gt->i915, file); 1311 if (IS_ERR(ctx)) { 1312 err = PTR_ERR(ctx); 1313 goto out; 1314 } 1315 1316 err = 0; 1317 vm = i915_gem_context_get_vm_rcu(ctx); 1318 if (!i915_is_ggtt(vm)) { 1319 /* aliasing == global gtt locking, covered above */ 1320 err = __igt_reset_evict_vma(gt, vm, 1321 evict_vma, EXEC_OBJECT_WRITE); 1322 } 1323 i915_vm_put(vm); 1324 1325 out: 1326 mock_file_free(gt->i915, file); 1327 return err; 1328 } 1329 1330 static int igt_reset_evict_fence(void *arg) 1331 { 1332 struct intel_gt *gt = arg; 1333 1334 return __igt_reset_evict_vma(gt, >->ggtt->vm, 1335 evict_fence, EXEC_OBJECT_NEEDS_FENCE); 1336 } 1337 1338 static int wait_for_others(struct intel_gt *gt, 1339 struct intel_engine_cs *exclude) 1340 { 1341 struct intel_engine_cs *engine; 1342 enum intel_engine_id id; 1343 1344 for_each_engine(engine, gt, id) { 1345 if (engine == exclude) 1346 continue; 1347 1348 if (!wait_for_idle(engine)) 1349 return -EIO; 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int igt_reset_queue(void *arg) 1356 { 1357 struct intel_gt *gt = arg; 1358 struct i915_gpu_error *global = >->i915->gpu_error; 1359 struct intel_engine_cs *engine; 1360 enum intel_engine_id id; 1361 struct hang h; 1362 int err; 1363 1364 /* Check that we replay pending requests following a hang */ 1365 1366 igt_global_reset_lock(gt); 1367 1368 err = hang_init(&h, gt); 1369 if (err) 1370 goto unlock; 1371 1372 for_each_engine(engine, gt, id) { 1373 struct i915_request *prev; 1374 IGT_TIMEOUT(end_time); 1375 unsigned int count; 1376 1377 if (!intel_engine_can_store_dword(engine)) 1378 continue; 1379 1380 prev = hang_create_request(&h, engine); 1381 if (IS_ERR(prev)) { 1382 err = PTR_ERR(prev); 1383 goto fini; 1384 } 1385 1386 i915_request_get(prev); 1387 i915_request_add(prev); 1388 1389 count = 0; 1390 do { 1391 struct i915_request *rq; 1392 unsigned int reset_count; 1393 1394 rq = hang_create_request(&h, engine); 1395 if (IS_ERR(rq)) { 1396 err = PTR_ERR(rq); 1397 goto fini; 1398 } 1399 1400 i915_request_get(rq); 1401 i915_request_add(rq); 1402 1403 /* 1404 * XXX We don't handle resetting the kernel context 1405 * very well. If we trigger a device reset twice in 1406 * quick succession while the kernel context is 1407 * executing, we may end up skipping the breadcrumb. 1408 * This is really only a problem for the selftest as 1409 * normally there is a large interlude between resets 1410 * (hangcheck), or we focus on resetting just one 1411 * engine and so avoid repeatedly resetting innocents. 1412 */ 1413 err = wait_for_others(gt, engine); 1414 if (err) { 1415 pr_err("%s(%s): Failed to idle other inactive engines after device reset\n", 1416 __func__, engine->name); 1417 i915_request_put(rq); 1418 i915_request_put(prev); 1419 1420 GEM_TRACE_DUMP(); 1421 intel_gt_set_wedged(gt); 1422 goto fini; 1423 } 1424 1425 if (!wait_until_running(&h, prev)) { 1426 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 1427 1428 pr_err("%s(%s): Failed to start request %llx, at %x\n", 1429 __func__, engine->name, 1430 prev->fence.seqno, hws_seqno(&h, prev)); 1431 intel_engine_dump(engine, &p, 1432 "%s\n", engine->name); 1433 1434 i915_request_put(rq); 1435 i915_request_put(prev); 1436 1437 intel_gt_set_wedged(gt); 1438 1439 err = -EIO; 1440 goto fini; 1441 } 1442 1443 reset_count = fake_hangcheck(gt, BIT(id)); 1444 1445 if (prev->fence.error != -EIO) { 1446 pr_err("GPU reset not recorded on hanging request [fence.error=%d]!\n", 1447 prev->fence.error); 1448 i915_request_put(rq); 1449 i915_request_put(prev); 1450 err = -EINVAL; 1451 goto fini; 1452 } 1453 1454 if (rq->fence.error) { 1455 pr_err("Fence error status not zero [%d] after unrelated reset\n", 1456 rq->fence.error); 1457 i915_request_put(rq); 1458 i915_request_put(prev); 1459 err = -EINVAL; 1460 goto fini; 1461 } 1462 1463 if (i915_reset_count(global) == reset_count) { 1464 pr_err("No GPU reset recorded!\n"); 1465 i915_request_put(rq); 1466 i915_request_put(prev); 1467 err = -EINVAL; 1468 goto fini; 1469 } 1470 1471 i915_request_put(prev); 1472 prev = rq; 1473 count++; 1474 } while (time_before(jiffies, end_time)); 1475 pr_info("%s: Completed %d resets\n", engine->name, count); 1476 1477 *h.batch = MI_BATCH_BUFFER_END; 1478 intel_gt_chipset_flush(engine->gt); 1479 1480 i915_request_put(prev); 1481 1482 err = igt_flush_test(gt->i915); 1483 if (err) 1484 break; 1485 } 1486 1487 fini: 1488 hang_fini(&h); 1489 unlock: 1490 igt_global_reset_unlock(gt); 1491 1492 if (intel_gt_is_wedged(gt)) 1493 return -EIO; 1494 1495 return err; 1496 } 1497 1498 static int igt_handle_error(void *arg) 1499 { 1500 struct intel_gt *gt = arg; 1501 struct i915_gpu_error *global = >->i915->gpu_error; 1502 struct intel_engine_cs *engine = gt->engine[RCS0]; 1503 struct hang h; 1504 struct i915_request *rq; 1505 struct i915_gpu_state *error; 1506 int err; 1507 1508 /* Check that we can issue a global GPU and engine reset */ 1509 1510 if (!intel_has_reset_engine(gt)) 1511 return 0; 1512 1513 if (!engine || !intel_engine_can_store_dword(engine)) 1514 return 0; 1515 1516 err = hang_init(&h, gt); 1517 if (err) 1518 return err; 1519 1520 rq = hang_create_request(&h, engine); 1521 if (IS_ERR(rq)) { 1522 err = PTR_ERR(rq); 1523 goto err_fini; 1524 } 1525 1526 i915_request_get(rq); 1527 i915_request_add(rq); 1528 1529 if (!wait_until_running(&h, rq)) { 1530 struct drm_printer p = drm_info_printer(gt->i915->drm.dev); 1531 1532 pr_err("%s: Failed to start request %llx, at %x\n", 1533 __func__, rq->fence.seqno, hws_seqno(&h, rq)); 1534 intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name); 1535 1536 intel_gt_set_wedged(gt); 1537 1538 err = -EIO; 1539 goto err_request; 1540 } 1541 1542 /* Temporarily disable error capture */ 1543 error = xchg(&global->first_error, (void *)-1); 1544 1545 intel_gt_handle_error(gt, engine->mask, 0, NULL); 1546 1547 xchg(&global->first_error, error); 1548 1549 if (rq->fence.error != -EIO) { 1550 pr_err("Guilty request not identified!\n"); 1551 err = -EINVAL; 1552 goto err_request; 1553 } 1554 1555 err_request: 1556 i915_request_put(rq); 1557 err_fini: 1558 hang_fini(&h); 1559 return err; 1560 } 1561 1562 static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, 1563 const struct igt_atomic_section *p, 1564 const char *mode) 1565 { 1566 struct tasklet_struct * const t = &engine->execlists.tasklet; 1567 int err; 1568 1569 GEM_TRACE("i915_reset_engine(%s:%s) under %s\n", 1570 engine->name, mode, p->name); 1571 1572 tasklet_disable(t); 1573 p->critical_section_begin(); 1574 1575 err = intel_engine_reset(engine, NULL); 1576 1577 p->critical_section_end(); 1578 tasklet_enable(t); 1579 1580 if (err) 1581 pr_err("i915_reset_engine(%s:%s) failed under %s\n", 1582 engine->name, mode, p->name); 1583 1584 return err; 1585 } 1586 1587 static int igt_atomic_reset_engine(struct intel_engine_cs *engine, 1588 const struct igt_atomic_section *p) 1589 { 1590 struct i915_request *rq; 1591 struct hang h; 1592 int err; 1593 1594 err = __igt_atomic_reset_engine(engine, p, "idle"); 1595 if (err) 1596 return err; 1597 1598 err = hang_init(&h, engine->gt); 1599 if (err) 1600 return err; 1601 1602 rq = hang_create_request(&h, engine); 1603 if (IS_ERR(rq)) { 1604 err = PTR_ERR(rq); 1605 goto out; 1606 } 1607 1608 i915_request_get(rq); 1609 i915_request_add(rq); 1610 1611 if (wait_until_running(&h, rq)) { 1612 err = __igt_atomic_reset_engine(engine, p, "active"); 1613 } else { 1614 pr_err("%s(%s): Failed to start request %llx, at %x\n", 1615 __func__, engine->name, 1616 rq->fence.seqno, hws_seqno(&h, rq)); 1617 intel_gt_set_wedged(engine->gt); 1618 err = -EIO; 1619 } 1620 1621 if (err == 0) { 1622 struct intel_wedge_me w; 1623 1624 intel_wedge_on_timeout(&w, engine->gt, HZ / 20 /* 50ms */) 1625 i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT); 1626 if (intel_gt_is_wedged(engine->gt)) 1627 err = -EIO; 1628 } 1629 1630 i915_request_put(rq); 1631 out: 1632 hang_fini(&h); 1633 return err; 1634 } 1635 1636 static int igt_reset_engines_atomic(void *arg) 1637 { 1638 struct intel_gt *gt = arg; 1639 const typeof(*igt_atomic_phases) *p; 1640 int err = 0; 1641 1642 /* Check that the engines resets are usable from atomic context */ 1643 1644 if (!intel_has_reset_engine(gt)) 1645 return 0; 1646 1647 if (USES_GUC_SUBMISSION(gt->i915)) 1648 return 0; 1649 1650 igt_global_reset_lock(gt); 1651 1652 /* Flush any requests before we get started and check basics */ 1653 if (!igt_force_reset(gt)) 1654 goto unlock; 1655 1656 for (p = igt_atomic_phases; p->name; p++) { 1657 struct intel_engine_cs *engine; 1658 enum intel_engine_id id; 1659 1660 for_each_engine(engine, gt, id) { 1661 err = igt_atomic_reset_engine(engine, p); 1662 if (err) 1663 goto out; 1664 } 1665 } 1666 1667 out: 1668 /* As we poke around the guts, do a full reset before continuing. */ 1669 igt_force_reset(gt); 1670 unlock: 1671 igt_global_reset_unlock(gt); 1672 1673 return err; 1674 } 1675 1676 int intel_hangcheck_live_selftests(struct drm_i915_private *i915) 1677 { 1678 static const struct i915_subtest tests[] = { 1679 SUBTEST(igt_hang_sanitycheck), 1680 SUBTEST(igt_reset_nop), 1681 SUBTEST(igt_reset_nop_engine), 1682 SUBTEST(igt_reset_idle_engine), 1683 SUBTEST(igt_reset_active_engine), 1684 SUBTEST(igt_reset_engines), 1685 SUBTEST(igt_reset_engines_atomic), 1686 SUBTEST(igt_reset_queue), 1687 SUBTEST(igt_reset_wait), 1688 SUBTEST(igt_reset_evict_ggtt), 1689 SUBTEST(igt_reset_evict_ppgtt), 1690 SUBTEST(igt_reset_evict_fence), 1691 SUBTEST(igt_handle_error), 1692 }; 1693 struct intel_gt *gt = &i915->gt; 1694 intel_wakeref_t wakeref; 1695 int err; 1696 1697 if (!intel_has_gpu_reset(gt)) 1698 return 0; 1699 1700 if (intel_gt_is_wedged(gt)) 1701 return -EIO; /* we're long past hope of a successful reset */ 1702 1703 wakeref = intel_runtime_pm_get(gt->uncore->rpm); 1704 1705 err = intel_gt_live_subtests(tests, gt); 1706 1707 intel_runtime_pm_put(gt->uncore->rpm, wakeref); 1708 1709 return err; 1710 } 1711