1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * Hardware workarounds are register programming documented to be executed in 22 * the driver that fall outside of the normal programming sequences for a 23 * platform. There are some basic categories of workarounds, depending on 24 * how/when they are applied: 25 * 26 * - Context workarounds: workarounds that touch registers that are 27 * saved/restored to/from the HW context image. The list is emitted (via Load 28 * Register Immediate commands) once when initializing the device and saved in 29 * the default context. That default context is then used on every context 30 * creation to have a "primed golden context", i.e. a context image that 31 * already contains the changes needed to all the registers. 32 * 33 * - Engine workarounds: the list of these WAs is applied whenever the specific 34 * engine is reset. It's also possible that a set of engine classes share a 35 * common power domain and they are reset together. This happens on some 36 * platforms with render and compute engines. In this case (at least) one of 37 * them need to keeep the workaround programming: the approach taken in the 38 * driver is to tie those workarounds to the first compute/render engine that 39 * is registered. When executing with GuC submission, engine resets are 40 * outside of kernel driver control, hence the list of registers involved in 41 * written once, on engine initialization, and then passed to GuC, that 42 * saves/restores their values before/after the reset takes place. See 43 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 44 * 45 * - GT workarounds: the list of these WAs is applied whenever these registers 46 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 47 * 48 * - Register whitelist: some workarounds need to be implemented in userspace, 49 * but need to touch privileged registers. The whitelist in the kernel 50 * instructs the hardware to allow the access to happen. From the kernel side, 51 * this is just a special case of a MMIO workaround (as we write the list of 52 * these to/be-whitelisted registers to some special HW registers). 53 * 54 * - Workaround batchbuffers: buffers that get executed automatically by the 55 * hardware on every HW context restore. These buffers are created and 56 * programmed in the default context so the hardware always go through those 57 * programming sequences when switching contexts. The support for workaround 58 * batchbuffers is enabled these hardware mechanisms: 59 * 60 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 61 * context, pointing the hardware to jump to that location when that offset 62 * is reached in the context restore. Workaround batchbuffer in the driver 63 * currently uses this mechanism for all platforms. 64 * 65 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 66 * pointing the hardware to a buffer to continue executing after the 67 * engine registers are restored in a context restore sequence. This is 68 * currently not used in the driver. 69 * 70 * - Other: There are WAs that, due to their nature, cannot be applied from a 71 * central place. Those are peppered around the rest of the code, as needed. 72 * Workarounds related to the display IP are the main example. 73 * 74 * .. [1] Technically, some registers are powercontext saved & restored, so they 75 * survive a suspend/resume. In practice, writing them again is not too 76 * costly and simplifies things, so it's the approach taken in the driver. 77 */ 78 79 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 80 const char *name, const char *engine_name) 81 { 82 wal->gt = gt; 83 wal->name = name; 84 wal->engine_name = engine_name; 85 } 86 87 #define WA_LIST_CHUNK (1 << 4) 88 89 static void wa_init_finish(struct i915_wa_list *wal) 90 { 91 /* Trim unused entries. */ 92 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 93 struct i915_wa *list = kmemdup(wal->list, 94 wal->count * sizeof(*list), 95 GFP_KERNEL); 96 97 if (list) { 98 kfree(wal->list); 99 wal->list = list; 100 } 101 } 102 103 if (!wal->count) 104 return; 105 106 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 107 wal->wa_count, wal->name, wal->engine_name); 108 } 109 110 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 111 { 112 unsigned int addr = i915_mmio_reg_offset(wa->reg); 113 struct drm_i915_private *i915 = wal->gt->i915; 114 unsigned int start = 0, end = wal->count; 115 const unsigned int grow = WA_LIST_CHUNK; 116 struct i915_wa *wa_; 117 118 GEM_BUG_ON(!is_power_of_2(grow)); 119 120 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 121 struct i915_wa *list; 122 123 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 124 GFP_KERNEL); 125 if (!list) { 126 drm_err(&i915->drm, "No space for workaround init!\n"); 127 return; 128 } 129 130 if (wal->list) { 131 memcpy(list, wal->list, sizeof(*wa) * wal->count); 132 kfree(wal->list); 133 } 134 135 wal->list = list; 136 } 137 138 while (start < end) { 139 unsigned int mid = start + (end - start) / 2; 140 141 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 142 start = mid + 1; 143 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 144 end = mid; 145 } else { 146 wa_ = &wal->list[mid]; 147 148 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 149 drm_err(&i915->drm, 150 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 151 i915_mmio_reg_offset(wa_->reg), 152 wa_->clr, wa_->set); 153 154 wa_->set &= ~wa->clr; 155 } 156 157 wal->wa_count++; 158 wa_->set |= wa->set; 159 wa_->clr |= wa->clr; 160 wa_->read |= wa->read; 161 return; 162 } 163 } 164 165 wal->wa_count++; 166 wa_ = &wal->list[wal->count++]; 167 *wa_ = *wa; 168 169 while (wa_-- > wal->list) { 170 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 171 i915_mmio_reg_offset(wa_[1].reg)); 172 if (i915_mmio_reg_offset(wa_[1].reg) > 173 i915_mmio_reg_offset(wa_[0].reg)) 174 break; 175 176 swap(wa_[1], wa_[0]); 177 } 178 } 179 180 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 181 u32 clear, u32 set, u32 read_mask, bool masked_reg) 182 { 183 struct i915_wa wa = { 184 .reg = reg, 185 .clr = clear, 186 .set = set, 187 .read = read_mask, 188 .masked_reg = masked_reg, 189 }; 190 191 _wa_add(wal, &wa); 192 } 193 194 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 195 u32 clear, u32 set, u32 read_mask, bool masked_reg) 196 { 197 struct i915_wa wa = { 198 .mcr_reg = reg, 199 .clr = clear, 200 .set = set, 201 .read = read_mask, 202 .masked_reg = masked_reg, 203 .is_mcr = 1, 204 }; 205 206 _wa_add(wal, &wa); 207 } 208 209 static void 210 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 211 { 212 wa_add(wal, reg, clear, set, clear, false); 213 } 214 215 static void 216 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 217 { 218 wa_mcr_add(wal, reg, clear, set, clear, false); 219 } 220 221 static void 222 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 223 { 224 wa_write_clr_set(wal, reg, ~0, set); 225 } 226 227 static void 228 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 229 { 230 wa_write_clr_set(wal, reg, set, set); 231 } 232 233 static void 234 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 235 { 236 wa_mcr_write_clr_set(wal, reg, set, set); 237 } 238 239 static void 240 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 241 { 242 wa_write_clr_set(wal, reg, clr, 0); 243 } 244 245 static void 246 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 247 { 248 wa_mcr_write_clr_set(wal, reg, clr, 0); 249 } 250 251 /* 252 * WA operations on "masked register". A masked register has the upper 16 bits 253 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 254 * portion of the register without a rmw: you simply write in the upper 16 bits 255 * the mask of bits you are going to modify. 256 * 257 * The wa_masked_* family of functions already does the necessary operations to 258 * calculate the mask based on the parameters passed, so user only has to 259 * provide the lower 16 bits of that register. 260 */ 261 262 static void 263 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 264 { 265 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 266 } 267 268 static void 269 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 270 { 271 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 272 } 273 274 static void 275 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 276 { 277 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 278 } 279 280 static void 281 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 282 { 283 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 284 } 285 286 static void 287 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 288 u32 mask, u32 val) 289 { 290 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 291 } 292 293 static void 294 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 295 u32 mask, u32 val) 296 { 297 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 298 } 299 300 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 301 struct i915_wa_list *wal) 302 { 303 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 304 } 305 306 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 307 struct i915_wa_list *wal) 308 { 309 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 310 } 311 312 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 313 struct i915_wa_list *wal) 314 { 315 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 316 317 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 318 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 319 320 /* WaDisablePartialInstShootdown:bdw,chv */ 321 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 322 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 323 324 /* Use Force Non-Coherent whenever executing a 3D context. This is a 325 * workaround for a possible hang in the unlikely event a TLB 326 * invalidation occurs during a PSD flush. 327 */ 328 /* WaForceEnableNonCoherent:bdw,chv */ 329 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 330 wa_masked_en(wal, HDC_CHICKEN0, 331 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 332 HDC_FORCE_NON_COHERENT); 333 334 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 335 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 336 * polygons in the same 8x4 pixel/sample area to be processed without 337 * stalling waiting for the earlier ones to write to Hierarchical Z 338 * buffer." 339 * 340 * This optimization is off by default for BDW and CHV; turn it on. 341 */ 342 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 343 344 /* Wa4x4STCOptimizationDisable:bdw,chv */ 345 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 346 347 /* 348 * BSpec recommends 8x4 when MSAA is used, 349 * however in practice 16x4 seems fastest. 350 * 351 * Note that PS/WM thread counts depend on the WIZ hashing 352 * disable bit, which we don't touch here, but it's good 353 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 354 */ 355 wa_masked_field_set(wal, GEN7_GT_MODE, 356 GEN6_WIZ_HASHING_MASK, 357 GEN6_WIZ_HASHING_16x4); 358 } 359 360 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 361 struct i915_wa_list *wal) 362 { 363 struct drm_i915_private *i915 = engine->i915; 364 365 gen8_ctx_workarounds_init(engine, wal); 366 367 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 368 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 369 370 /* WaDisableDopClockGating:bdw 371 * 372 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 373 * to disable EUTC clock gating. 374 */ 375 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 376 DOP_CLOCK_GATING_DISABLE); 377 378 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 379 GEN8_SAMPLER_POWER_BYPASS_DIS); 380 381 wa_masked_en(wal, HDC_CHICKEN0, 382 /* WaForceContextSaveRestoreNonCoherent:bdw */ 383 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 384 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 385 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 386 } 387 388 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 389 struct i915_wa_list *wal) 390 { 391 gen8_ctx_workarounds_init(engine, wal); 392 393 /* WaDisableThreadStallDopClockGating:chv */ 394 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 395 396 /* Improve HiZ throughput on CHV. */ 397 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 398 } 399 400 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 401 struct i915_wa_list *wal) 402 { 403 struct drm_i915_private *i915 = engine->i915; 404 405 if (HAS_LLC(i915)) { 406 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 407 * 408 * Must match Display Engine. See 409 * WaCompressedResourceDisplayNewHashMode. 410 */ 411 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 412 GEN9_PBE_COMPRESSED_HASH_SELECTION); 413 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 414 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 415 } 416 417 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 418 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 419 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 420 FLOW_CONTROL_ENABLE | 421 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 422 423 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 424 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 425 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 426 GEN9_ENABLE_YV12_BUGFIX | 427 GEN9_ENABLE_GPGPU_PREEMPTION); 428 429 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 430 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 431 wa_masked_en(wal, CACHE_MODE_1, 432 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 433 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 434 435 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 436 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 437 GEN9_CCS_TLB_PREFETCH_ENABLE); 438 439 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 440 wa_masked_en(wal, HDC_CHICKEN0, 441 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 442 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 443 444 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 445 * both tied to WaForceContextSaveRestoreNonCoherent 446 * in some hsds for skl. We keep the tie for all gen9. The 447 * documentation is a bit hazy and so we want to get common behaviour, 448 * even though there is no clear evidence we would need both on kbl/bxt. 449 * This area has been source of system hangs so we play it safe 450 * and mimic the skl regardless of what bspec says. 451 * 452 * Use Force Non-Coherent whenever executing a 3D context. This 453 * is a workaround for a possible hang in the unlikely event 454 * a TLB invalidation occurs during a PSD flush. 455 */ 456 457 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 458 wa_masked_en(wal, HDC_CHICKEN0, 459 HDC_FORCE_NON_COHERENT); 460 461 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 462 if (IS_SKYLAKE(i915) || 463 IS_KABYLAKE(i915) || 464 IS_COFFEELAKE(i915) || 465 IS_COMETLAKE(i915)) 466 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 467 GEN8_SAMPLER_POWER_BYPASS_DIS); 468 469 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 470 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 471 472 /* 473 * Supporting preemption with fine-granularity requires changes in the 474 * batch buffer programming. Since we can't break old userspace, we 475 * need to set our default preemption level to safe value. Userspace is 476 * still able to use more fine-grained preemption levels, since in 477 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 478 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 479 * not real HW workarounds, but merely a way to start using preemption 480 * while maintaining old contract with userspace. 481 */ 482 483 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 484 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 485 486 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 487 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 488 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 489 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 490 491 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 492 if (IS_GEN9_LP(i915)) 493 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 494 } 495 496 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 497 struct i915_wa_list *wal) 498 { 499 struct intel_gt *gt = engine->gt; 500 u8 vals[3] = { 0, 0, 0 }; 501 unsigned int i; 502 503 for (i = 0; i < 3; i++) { 504 u8 ss; 505 506 /* 507 * Only consider slices where one, and only one, subslice has 7 508 * EUs 509 */ 510 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 511 continue; 512 513 /* 514 * subslice_7eu[i] != 0 (because of the check above) and 515 * ss_max == 4 (maximum number of subslices possible per slice) 516 * 517 * -> 0 <= ss <= 3; 518 */ 519 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 520 vals[i] = 3 - ss; 521 } 522 523 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 524 return; 525 526 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 527 wa_masked_field_set(wal, GEN7_GT_MODE, 528 GEN9_IZ_HASHING_MASK(2) | 529 GEN9_IZ_HASHING_MASK(1) | 530 GEN9_IZ_HASHING_MASK(0), 531 GEN9_IZ_HASHING(2, vals[2]) | 532 GEN9_IZ_HASHING(1, vals[1]) | 533 GEN9_IZ_HASHING(0, vals[0])); 534 } 535 536 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 537 struct i915_wa_list *wal) 538 { 539 gen9_ctx_workarounds_init(engine, wal); 540 skl_tune_iz_hashing(engine, wal); 541 } 542 543 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 544 struct i915_wa_list *wal) 545 { 546 gen9_ctx_workarounds_init(engine, wal); 547 548 /* WaDisableThreadStallDopClockGating:bxt */ 549 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 550 STALL_DOP_GATING_DISABLE); 551 552 /* WaToEnableHwFixForPushConstHWBug:bxt */ 553 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 554 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 555 } 556 557 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 558 struct i915_wa_list *wal) 559 { 560 struct drm_i915_private *i915 = engine->i915; 561 562 gen9_ctx_workarounds_init(engine, wal); 563 564 /* WaToEnableHwFixForPushConstHWBug:kbl */ 565 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 566 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 567 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 568 569 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 570 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 571 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 572 } 573 574 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 575 struct i915_wa_list *wal) 576 { 577 gen9_ctx_workarounds_init(engine, wal); 578 579 /* WaToEnableHwFixForPushConstHWBug:glk */ 580 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 581 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 582 } 583 584 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 585 struct i915_wa_list *wal) 586 { 587 gen9_ctx_workarounds_init(engine, wal); 588 589 /* WaToEnableHwFixForPushConstHWBug:cfl */ 590 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 591 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 592 593 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 594 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 595 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 596 } 597 598 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 599 struct i915_wa_list *wal) 600 { 601 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 602 wa_write(wal, 603 GEN8_L3CNTLREG, 604 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 605 GEN8_ERRDETBCTRL); 606 607 /* WaForceEnableNonCoherent:icl 608 * This is not the same workaround as in early Gen9 platforms, where 609 * lacking this could cause system hangs, but coherency performance 610 * overhead is high and only a few compute workloads really need it 611 * (the register is whitelisted in hardware now, so UMDs can opt in 612 * for coherency if they have a good reason). 613 */ 614 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 615 616 /* WaEnableFloatBlendOptimization:icl */ 617 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 618 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 619 0 /* write-only, so skip validation */, 620 true); 621 622 /* WaDisableGPGPUMidThreadPreemption:icl */ 623 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 624 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 625 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 626 627 /* allow headerless messages for preemptible GPGPU context */ 628 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 629 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 630 631 /* Wa_1604278689:icl,ehl */ 632 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 633 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 634 0, /* write-only register; skip validation */ 635 0xFFFFFFFF); 636 637 /* Wa_1406306137:icl,ehl */ 638 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 639 } 640 641 /* 642 * These settings aren't actually workarounds, but general tuning settings that 643 * need to be programmed on dg2 platform. 644 */ 645 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 646 struct i915_wa_list *wal) 647 { 648 wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 649 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 650 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 651 wa_mcr_add(wal, 652 XEHP_FF_MODE2, 653 FF_MODE2_TDS_TIMER_MASK, 654 FF_MODE2_TDS_TIMER_128, 655 0, false); 656 } 657 658 /* 659 * These settings aren't actually workarounds, but general tuning settings that 660 * need to be programmed on several platforms. 661 */ 662 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 663 struct i915_wa_list *wal) 664 { 665 /* 666 * Although some platforms refer to it as Wa_1604555607, we need to 667 * program it even on those that don't explicitly list that 668 * workaround. 669 * 670 * Note that the programming of this register is further modified 671 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 672 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 673 * value when read. The default value for this register is zero for all 674 * fields and there are no bit masks. So instead of doing a RMW we 675 * should just write TDS timer value. For the same reason read 676 * verification is ignored. 677 */ 678 wa_add(wal, 679 GEN12_FF_MODE2, 680 FF_MODE2_TDS_TIMER_MASK, 681 FF_MODE2_TDS_TIMER_128, 682 0, false); 683 } 684 685 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 686 struct i915_wa_list *wal) 687 { 688 struct drm_i915_private *i915 = engine->i915; 689 690 gen12_ctx_gt_tuning_init(engine, wal); 691 692 /* 693 * Wa_1409142259:tgl,dg1,adl-p 694 * Wa_1409347922:tgl,dg1,adl-p 695 * Wa_1409252684:tgl,dg1,adl-p 696 * Wa_1409217633:tgl,dg1,adl-p 697 * Wa_1409207793:tgl,dg1,adl-p 698 * Wa_1409178076:tgl,dg1,adl-p 699 * Wa_1408979724:tgl,dg1,adl-p 700 * Wa_14010443199:tgl,rkl,dg1,adl-p 701 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 702 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 703 */ 704 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 705 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 706 707 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 708 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 709 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 710 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 711 712 /* 713 * Wa_16011163337 714 * 715 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 716 * to Wa_1608008084. 717 */ 718 wa_add(wal, 719 GEN12_FF_MODE2, 720 FF_MODE2_GS_TIMER_MASK, 721 FF_MODE2_GS_TIMER_224, 722 0, false); 723 724 if (!IS_DG1(i915)) 725 /* Wa_1806527549 */ 726 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 727 } 728 729 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 730 struct i915_wa_list *wal) 731 { 732 gen12_ctx_workarounds_init(engine, wal); 733 734 /* Wa_1409044764 */ 735 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 736 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 737 738 /* Wa_22010493298 */ 739 wa_masked_en(wal, HIZ_CHICKEN, 740 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 741 } 742 743 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 744 struct i915_wa_list *wal) 745 { 746 dg2_ctx_gt_tuning_init(engine, wal); 747 748 /* Wa_16011186671:dg2_g11 */ 749 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 750 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 751 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 752 } 753 754 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 755 /* Wa_14010469329:dg2_g10 */ 756 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 757 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 758 759 /* 760 * Wa_22010465075:dg2_g10 761 * Wa_22010613112:dg2_g10 762 * Wa_14010698770:dg2_g10 763 */ 764 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 765 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 766 } 767 768 /* Wa_16013271637:dg2 */ 769 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 770 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 771 772 /* Wa_14014947963:dg2 */ 773 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 774 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 775 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 776 777 /* Wa_15010599737:dg2 */ 778 wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 779 } 780 781 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 782 struct i915_wa_list *wal) 783 { 784 /* 785 * This is a "fake" workaround defined by software to ensure we 786 * maintain reliable, backward-compatible behavior for userspace with 787 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 788 * 789 * The per-context setting of MI_MODE[12] determines whether the bits 790 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 791 * in the traditional manner or whether they should instead use a new 792 * tgl+ meaning that breaks backward compatibility, but allows nesting 793 * into 3rd-level batchbuffers. When this new capability was first 794 * added in TGL, it remained off by default unless a context 795 * intentionally opted in to the new behavior. However Xe_HPG now 796 * flips this on by default and requires that we explicitly opt out if 797 * we don't want the new behavior. 798 * 799 * From a SW perspective, we want to maintain the backward-compatible 800 * behavior for userspace, so we'll apply a fake workaround to set it 801 * back to the legacy behavior on platforms where the hardware default 802 * is to break compatibility. At the moment there is no Linux 803 * userspace that utilizes third-level batchbuffers, so this will avoid 804 * userspace from needing to make any changes. using the legacy 805 * meaning is the correct thing to do. If/when we have userspace 806 * consumers that want to utilize third-level batch nesting, we can 807 * provide a context parameter to allow them to opt-in. 808 */ 809 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 810 } 811 812 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 813 struct i915_wa_list *wal) 814 { 815 u8 mocs; 816 817 /* 818 * Some blitter commands do not have a field for MOCS, those 819 * commands will use MOCS index pointed by BLIT_CCTL. 820 * BLIT_CCTL registers are needed to be programmed to un-cached. 821 */ 822 if (engine->class == COPY_ENGINE_CLASS) { 823 mocs = engine->gt->mocs.uc_index; 824 wa_write_clr_set(wal, 825 BLIT_CCTL(engine->mmio_base), 826 BLIT_CCTL_MASK, 827 BLIT_CCTL_MOCS(mocs, mocs)); 828 } 829 } 830 831 /* 832 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 833 * defined by the hardware team, but it programming general context registers. 834 * Adding those context register programming in context workaround 835 * allow us to use the wa framework for proper application and validation. 836 */ 837 static void 838 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 839 struct i915_wa_list *wal) 840 { 841 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 842 fakewa_disable_nestedbb_mode(engine, wal); 843 844 gen12_ctx_gt_mocs_init(engine, wal); 845 } 846 847 static void 848 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 849 struct i915_wa_list *wal, 850 const char *name) 851 { 852 struct drm_i915_private *i915 = engine->i915; 853 854 wa_init_start(wal, engine->gt, name, engine->name); 855 856 /* Applies to all engines */ 857 /* 858 * Fake workarounds are not the actual workaround but 859 * programming of context registers using workaround framework. 860 */ 861 if (GRAPHICS_VER(i915) >= 12) 862 gen12_ctx_gt_fake_wa_init(engine, wal); 863 864 if (engine->class != RENDER_CLASS) 865 goto done; 866 867 if (IS_PONTEVECCHIO(i915)) 868 ; /* noop; none at this time */ 869 else if (IS_DG2(i915)) 870 dg2_ctx_workarounds_init(engine, wal); 871 else if (IS_XEHPSDV(i915)) 872 ; /* noop; none at this time */ 873 else if (IS_DG1(i915)) 874 dg1_ctx_workarounds_init(engine, wal); 875 else if (GRAPHICS_VER(i915) == 12) 876 gen12_ctx_workarounds_init(engine, wal); 877 else if (GRAPHICS_VER(i915) == 11) 878 icl_ctx_workarounds_init(engine, wal); 879 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 880 cfl_ctx_workarounds_init(engine, wal); 881 else if (IS_GEMINILAKE(i915)) 882 glk_ctx_workarounds_init(engine, wal); 883 else if (IS_KABYLAKE(i915)) 884 kbl_ctx_workarounds_init(engine, wal); 885 else if (IS_BROXTON(i915)) 886 bxt_ctx_workarounds_init(engine, wal); 887 else if (IS_SKYLAKE(i915)) 888 skl_ctx_workarounds_init(engine, wal); 889 else if (IS_CHERRYVIEW(i915)) 890 chv_ctx_workarounds_init(engine, wal); 891 else if (IS_BROADWELL(i915)) 892 bdw_ctx_workarounds_init(engine, wal); 893 else if (GRAPHICS_VER(i915) == 7) 894 gen7_ctx_workarounds_init(engine, wal); 895 else if (GRAPHICS_VER(i915) == 6) 896 gen6_ctx_workarounds_init(engine, wal); 897 else if (GRAPHICS_VER(i915) < 8) 898 ; 899 else 900 MISSING_CASE(GRAPHICS_VER(i915)); 901 902 done: 903 wa_init_finish(wal); 904 } 905 906 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 907 { 908 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 909 } 910 911 int intel_engine_emit_ctx_wa(struct i915_request *rq) 912 { 913 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 914 struct i915_wa *wa; 915 unsigned int i; 916 u32 *cs; 917 int ret; 918 919 if (wal->count == 0) 920 return 0; 921 922 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 923 if (ret) 924 return ret; 925 926 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 927 if (IS_ERR(cs)) 928 return PTR_ERR(cs); 929 930 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 931 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 932 *cs++ = i915_mmio_reg_offset(wa->reg); 933 *cs++ = wa->set; 934 } 935 *cs++ = MI_NOOP; 936 937 intel_ring_advance(rq, cs); 938 939 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 940 if (ret) 941 return ret; 942 943 return 0; 944 } 945 946 static void 947 gen4_gt_workarounds_init(struct intel_gt *gt, 948 struct i915_wa_list *wal) 949 { 950 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 951 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 952 } 953 954 static void 955 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 956 { 957 gen4_gt_workarounds_init(gt, wal); 958 959 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 960 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 961 } 962 963 static void 964 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 965 { 966 g4x_gt_workarounds_init(gt, wal); 967 968 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 969 } 970 971 static void 972 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 973 { 974 } 975 976 static void 977 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 978 { 979 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 980 wa_masked_dis(wal, 981 GEN7_COMMON_SLICE_CHICKEN1, 982 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 983 984 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 985 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 986 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 987 988 /* WaForceL3Serialization:ivb */ 989 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 990 } 991 992 static void 993 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 994 { 995 /* WaForceL3Serialization:vlv */ 996 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 997 998 /* 999 * WaIncreaseL3CreditsForVLVB0:vlv 1000 * This is the hardware default actually. 1001 */ 1002 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1003 } 1004 1005 static void 1006 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1007 { 1008 /* L3 caching of data atomics doesn't work -- disable it. */ 1009 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1010 1011 wa_add(wal, 1012 HSW_ROW_CHICKEN3, 0, 1013 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1014 0 /* XXX does this reg exist? */, true); 1015 1016 /* WaVSRefCountFullforceMissDisable:hsw */ 1017 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1018 } 1019 1020 static void 1021 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1022 { 1023 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1024 unsigned int slice, subslice; 1025 u32 mcr, mcr_mask; 1026 1027 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1028 1029 /* 1030 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1031 * Before any MMIO read into slice/subslice specific registers, MCR 1032 * packet control register needs to be programmed to point to any 1033 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1034 * This means each subsequent MMIO read will be forwarded to an 1035 * specific s/ss combination, but this is OK since these registers 1036 * are consistent across s/ss in almost all cases. In the rare 1037 * occasions, such as INSTDONE, where this value is dependent 1038 * on s/ss combo, the read should be done with read_subslice_reg. 1039 */ 1040 slice = ffs(sseu->slice_mask) - 1; 1041 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1042 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1043 GEM_BUG_ON(!subslice); 1044 subslice--; 1045 1046 /* 1047 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1048 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1049 */ 1050 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1051 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1052 1053 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1054 1055 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1056 } 1057 1058 static void 1059 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1060 { 1061 struct drm_i915_private *i915 = gt->i915; 1062 1063 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1064 gen9_wa_init_mcr(i915, wal); 1065 1066 /* WaDisableKillLogic:bxt,skl,kbl */ 1067 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1068 wa_write_or(wal, 1069 GAM_ECOCHK, 1070 ECOCHK_DIS_TLB); 1071 1072 if (HAS_LLC(i915)) { 1073 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1074 * 1075 * Must match Display Engine. See 1076 * WaCompressedResourceDisplayNewHashMode. 1077 */ 1078 wa_write_or(wal, 1079 MMCD_MISC_CTRL, 1080 MMCD_PCLA | MMCD_HOTSPOT_EN); 1081 } 1082 1083 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1084 wa_write_or(wal, 1085 GAM_ECOCHK, 1086 BDW_DISABLE_HDC_INVALIDATION); 1087 } 1088 1089 static void 1090 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1091 { 1092 gen9_gt_workarounds_init(gt, wal); 1093 1094 /* WaDisableGafsUnitClkGating:skl */ 1095 wa_write_or(wal, 1096 GEN7_UCGCTL4, 1097 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1098 1099 /* WaInPlaceDecompressionHang:skl */ 1100 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1101 wa_write_or(wal, 1102 GEN9_GAMT_ECO_REG_RW_IA, 1103 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1104 } 1105 1106 static void 1107 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1108 { 1109 gen9_gt_workarounds_init(gt, wal); 1110 1111 /* WaDisableDynamicCreditSharing:kbl */ 1112 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1113 wa_write_or(wal, 1114 GAMT_CHKN_BIT_REG, 1115 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1116 1117 /* WaDisableGafsUnitClkGating:kbl */ 1118 wa_write_or(wal, 1119 GEN7_UCGCTL4, 1120 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1121 1122 /* WaInPlaceDecompressionHang:kbl */ 1123 wa_write_or(wal, 1124 GEN9_GAMT_ECO_REG_RW_IA, 1125 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1126 } 1127 1128 static void 1129 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1130 { 1131 gen9_gt_workarounds_init(gt, wal); 1132 } 1133 1134 static void 1135 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1136 { 1137 gen9_gt_workarounds_init(gt, wal); 1138 1139 /* WaDisableGafsUnitClkGating:cfl */ 1140 wa_write_or(wal, 1141 GEN7_UCGCTL4, 1142 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1143 1144 /* WaInPlaceDecompressionHang:cfl */ 1145 wa_write_or(wal, 1146 GEN9_GAMT_ECO_REG_RW_IA, 1147 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1148 } 1149 1150 static void __set_mcr_steering(struct i915_wa_list *wal, 1151 i915_reg_t steering_reg, 1152 unsigned int slice, unsigned int subslice) 1153 { 1154 u32 mcr, mcr_mask; 1155 1156 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1157 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1158 1159 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1160 } 1161 1162 static void debug_dump_steering(struct intel_gt *gt) 1163 { 1164 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1165 1166 if (drm_debug_enabled(DRM_UT_DRIVER)) 1167 intel_gt_mcr_report_steering(&p, gt, false); 1168 } 1169 1170 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1171 unsigned int slice, unsigned int subslice) 1172 { 1173 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1174 1175 gt->default_steering.groupid = slice; 1176 gt->default_steering.instanceid = subslice; 1177 1178 debug_dump_steering(gt); 1179 } 1180 1181 static void 1182 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1183 { 1184 const struct sseu_dev_info *sseu = >->info.sseu; 1185 unsigned int subslice; 1186 1187 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1188 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1189 1190 /* 1191 * Although a platform may have subslices, we need to always steer 1192 * reads to the lowest instance that isn't fused off. When Render 1193 * Power Gating is enabled, grabbing forcewake will only power up a 1194 * single subslice (the "minconfig") if there isn't a real workload 1195 * that needs to be run; this means that if we steer register reads to 1196 * one of the higher subslices, we run the risk of reading back 0's or 1197 * random garbage. 1198 */ 1199 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1200 1201 /* 1202 * If the subslice we picked above also steers us to a valid L3 bank, 1203 * then we can just rely on the default steering and won't need to 1204 * worry about explicitly re-steering L3BANK reads later. 1205 */ 1206 if (gt->info.l3bank_mask & BIT(subslice)) 1207 gt->steering_table[L3BANK] = NULL; 1208 1209 __add_mcr_wa(gt, wal, 0, subslice); 1210 } 1211 1212 static void 1213 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1214 { 1215 const struct sseu_dev_info *sseu = >->info.sseu; 1216 unsigned long slice, subslice = 0, slice_mask = 0; 1217 u32 lncf_mask = 0; 1218 int i; 1219 1220 /* 1221 * On Xe_HP the steering increases in complexity. There are now several 1222 * more units that require steering and we're not guaranteed to be able 1223 * to find a common setting for all of them. These are: 1224 * - GSLICE (fusable) 1225 * - DSS (sub-unit within gslice; fusable) 1226 * - L3 Bank (fusable) 1227 * - MSLICE (fusable) 1228 * - LNCF (sub-unit within mslice; always present if mslice is present) 1229 * 1230 * We'll do our default/implicit steering based on GSLICE (in the 1231 * sliceid field) and DSS (in the subsliceid field). If we can 1232 * find overlap between the valid MSLICE and/or LNCF values with 1233 * a suitable GSLICE, then we can just re-use the default value and 1234 * skip and explicit steering at runtime. 1235 * 1236 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1237 * a valid sliceid value. DSS steering is the only type of steering 1238 * that utilizes the 'subsliceid' bits. 1239 * 1240 * Also note that, even though the steering domain is called "GSlice" 1241 * and it is encoded in the register using the gslice format, the spec 1242 * says that the combined (geometry | compute) fuse should be used to 1243 * select the steering. 1244 */ 1245 1246 /* Find the potential gslice candidates */ 1247 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1248 GEN_DSS_PER_GSLICE); 1249 1250 /* 1251 * Find the potential LNCF candidates. Either LNCF within a valid 1252 * mslice is fine. 1253 */ 1254 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1255 lncf_mask |= (0x3 << (i * 2)); 1256 1257 /* 1258 * Are there any sliceid values that work for both GSLICE and LNCF 1259 * steering? 1260 */ 1261 if (slice_mask & lncf_mask) { 1262 slice_mask &= lncf_mask; 1263 gt->steering_table[LNCF] = NULL; 1264 } 1265 1266 /* How about sliceid values that also work for MSLICE steering? */ 1267 if (slice_mask & gt->info.mslice_mask) { 1268 slice_mask &= gt->info.mslice_mask; 1269 gt->steering_table[MSLICE] = NULL; 1270 } 1271 1272 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1273 gt->steering_table[GAM] = NULL; 1274 1275 slice = __ffs(slice_mask); 1276 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1277 GEN_DSS_PER_GSLICE; 1278 1279 __add_mcr_wa(gt, wal, slice, subslice); 1280 1281 /* 1282 * SQIDI ranges are special because they use different steering 1283 * registers than everything else we work with. On XeHP SDV and 1284 * DG2-G10, any value in the steering registers will work fine since 1285 * all instances are present, but DG2-G11 only has SQIDI instances at 1286 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1287 * we'll just steer to a hardcoded "2" since that value will work 1288 * everywhere. 1289 */ 1290 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1291 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1292 1293 /* 1294 * On DG2, GAM registers have a dedicated steering control register 1295 * and must always be programmed to a hardcoded groupid of "1." 1296 */ 1297 if (IS_DG2(gt->i915)) 1298 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1299 } 1300 1301 static void 1302 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1303 { 1304 unsigned int dss; 1305 1306 /* 1307 * Setup implicit steering for COMPUTE and DSS ranges to the first 1308 * non-fused-off DSS. All other types of MCR registers will be 1309 * explicitly steered. 1310 */ 1311 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1312 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1313 } 1314 1315 static void 1316 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1317 { 1318 struct drm_i915_private *i915 = gt->i915; 1319 1320 icl_wa_init_mcr(gt, wal); 1321 1322 /* WaModifyGamTlbPartitioning:icl */ 1323 wa_write_clr_set(wal, 1324 GEN11_GACB_PERF_CTRL, 1325 GEN11_HASH_CTRL_MASK, 1326 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1327 1328 /* Wa_1405766107:icl 1329 * Formerly known as WaCL2SFHalfMaxAlloc 1330 */ 1331 wa_write_or(wal, 1332 GEN11_LSN_UNSLCVC, 1333 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1334 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1335 1336 /* Wa_220166154:icl 1337 * Formerly known as WaDisCtxReload 1338 */ 1339 wa_write_or(wal, 1340 GEN8_GAMW_ECO_DEV_RW_IA, 1341 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1342 1343 /* Wa_1406463099:icl 1344 * Formerly known as WaGamTlbPendError 1345 */ 1346 wa_write_or(wal, 1347 GAMT_CHKN_BIT_REG, 1348 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1349 1350 /* Wa_1407352427:icl,ehl */ 1351 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1352 PSDUNIT_CLKGATE_DIS); 1353 1354 /* Wa_1406680159:icl,ehl */ 1355 wa_mcr_write_or(wal, 1356 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1357 GWUNIT_CLKGATE_DIS); 1358 1359 /* Wa_1607087056:icl,ehl,jsl */ 1360 if (IS_ICELAKE(i915) || 1361 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1362 wa_write_or(wal, 1363 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1364 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1365 1366 /* 1367 * This is not a documented workaround, but rather an optimization 1368 * to reduce sampler power. 1369 */ 1370 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1371 } 1372 1373 /* 1374 * Though there are per-engine instances of these registers, 1375 * they retain their value through engine resets and should 1376 * only be provided on the GT workaround list rather than 1377 * the engine-specific workaround list. 1378 */ 1379 static void 1380 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1381 { 1382 struct intel_engine_cs *engine; 1383 int id; 1384 1385 for_each_engine(engine, gt, id) { 1386 if (engine->class != VIDEO_DECODE_CLASS || 1387 (engine->instance % 2)) 1388 continue; 1389 1390 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1391 IECPUNIT_CLKGATE_DIS); 1392 } 1393 } 1394 1395 static void 1396 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1397 { 1398 icl_wa_init_mcr(gt, wal); 1399 1400 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1401 wa_14011060649(gt, wal); 1402 1403 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1404 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1405 } 1406 1407 static void 1408 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1409 { 1410 struct drm_i915_private *i915 = gt->i915; 1411 1412 gen12_gt_workarounds_init(gt, wal); 1413 1414 /* Wa_1409420604:tgl */ 1415 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1416 wa_mcr_write_or(wal, 1417 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1418 CPSSUNIT_CLKGATE_DIS); 1419 1420 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1421 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1422 wa_write_or(wal, 1423 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1424 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1425 1426 /* Wa_1408615072:tgl[a0] */ 1427 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1428 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1429 VSUNIT_CLKGATE_DIS_TGL); 1430 } 1431 1432 static void 1433 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1434 { 1435 struct drm_i915_private *i915 = gt->i915; 1436 1437 gen12_gt_workarounds_init(gt, wal); 1438 1439 /* Wa_1607087056:dg1 */ 1440 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1441 wa_write_or(wal, 1442 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1443 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1444 1445 /* Wa_1409420604:dg1 */ 1446 if (IS_DG1(i915)) 1447 wa_mcr_write_or(wal, 1448 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1449 CPSSUNIT_CLKGATE_DIS); 1450 1451 /* Wa_1408615072:dg1 */ 1452 /* Empirical testing shows this register is unaffected by engine reset. */ 1453 if (IS_DG1(i915)) 1454 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1455 VSUNIT_CLKGATE_DIS_TGL); 1456 } 1457 1458 static void 1459 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1460 { 1461 struct drm_i915_private *i915 = gt->i915; 1462 1463 xehp_init_mcr(gt, wal); 1464 1465 /* Wa_1409757795:xehpsdv */ 1466 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1467 1468 /* Wa_16011155590:xehpsdv */ 1469 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1470 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1471 TSGUNIT_CLKGATE_DIS); 1472 1473 /* Wa_14011780169:xehpsdv */ 1474 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1475 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1476 GAMTLBVDBOX7_CLKGATE_DIS | 1477 GAMTLBVDBOX6_CLKGATE_DIS | 1478 GAMTLBVDBOX5_CLKGATE_DIS | 1479 GAMTLBVDBOX4_CLKGATE_DIS | 1480 GAMTLBVDBOX3_CLKGATE_DIS | 1481 GAMTLBVDBOX2_CLKGATE_DIS | 1482 GAMTLBVDBOX1_CLKGATE_DIS | 1483 GAMTLBVDBOX0_CLKGATE_DIS | 1484 GAMTLBKCR_CLKGATE_DIS | 1485 GAMTLBGUC_CLKGATE_DIS | 1486 GAMTLBBLT_CLKGATE_DIS); 1487 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1488 GAMTLBGFXA1_CLKGATE_DIS | 1489 GAMTLBCOMPA0_CLKGATE_DIS | 1490 GAMTLBCOMPA1_CLKGATE_DIS | 1491 GAMTLBCOMPB0_CLKGATE_DIS | 1492 GAMTLBCOMPB1_CLKGATE_DIS | 1493 GAMTLBCOMPC0_CLKGATE_DIS | 1494 GAMTLBCOMPC1_CLKGATE_DIS | 1495 GAMTLBCOMPD0_CLKGATE_DIS | 1496 GAMTLBCOMPD1_CLKGATE_DIS | 1497 GAMTLBMERT_CLKGATE_DIS | 1498 GAMTLBVEBOX3_CLKGATE_DIS | 1499 GAMTLBVEBOX2_CLKGATE_DIS | 1500 GAMTLBVEBOX1_CLKGATE_DIS | 1501 GAMTLBVEBOX0_CLKGATE_DIS); 1502 } 1503 1504 /* Wa_16012725990:xehpsdv */ 1505 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1506 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1507 1508 /* Wa_14011060649:xehpsdv */ 1509 wa_14011060649(gt, wal); 1510 } 1511 1512 static void 1513 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1514 { 1515 struct intel_engine_cs *engine; 1516 int id; 1517 1518 xehp_init_mcr(gt, wal); 1519 1520 /* Wa_14011060649:dg2 */ 1521 wa_14011060649(gt, wal); 1522 1523 /* 1524 * Although there are per-engine instances of these registers, 1525 * they technically exist outside the engine itself and are not 1526 * impacted by engine resets. Furthermore, they're part of the 1527 * GuC blacklist so trying to treat them as engine workarounds 1528 * will result in GuC initialization failure and a wedged GPU. 1529 */ 1530 for_each_engine(engine, gt, id) { 1531 if (engine->class != VIDEO_DECODE_CLASS) 1532 continue; 1533 1534 /* Wa_16010515920:dg2_g10 */ 1535 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1536 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1537 ALNUNIT_CLKGATE_DIS); 1538 } 1539 1540 if (IS_DG2_G10(gt->i915)) { 1541 /* Wa_22010523718:dg2 */ 1542 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1543 CG3DDISCFEG_CLKGATE_DIS); 1544 1545 /* Wa_14011006942:dg2 */ 1546 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1547 DSS_ROUTER_CLKGATE_DIS); 1548 } 1549 1550 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1551 /* Wa_14010948348:dg2_g10 */ 1552 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1553 1554 /* Wa_14011037102:dg2_g10 */ 1555 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1556 1557 /* Wa_14011371254:dg2_g10 */ 1558 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1559 1560 /* Wa_14011431319:dg2_g10 */ 1561 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1562 GAMTLBVDBOX7_CLKGATE_DIS | 1563 GAMTLBVDBOX6_CLKGATE_DIS | 1564 GAMTLBVDBOX5_CLKGATE_DIS | 1565 GAMTLBVDBOX4_CLKGATE_DIS | 1566 GAMTLBVDBOX3_CLKGATE_DIS | 1567 GAMTLBVDBOX2_CLKGATE_DIS | 1568 GAMTLBVDBOX1_CLKGATE_DIS | 1569 GAMTLBVDBOX0_CLKGATE_DIS | 1570 GAMTLBKCR_CLKGATE_DIS | 1571 GAMTLBGUC_CLKGATE_DIS | 1572 GAMTLBBLT_CLKGATE_DIS); 1573 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1574 GAMTLBGFXA1_CLKGATE_DIS | 1575 GAMTLBCOMPA0_CLKGATE_DIS | 1576 GAMTLBCOMPA1_CLKGATE_DIS | 1577 GAMTLBCOMPB0_CLKGATE_DIS | 1578 GAMTLBCOMPB1_CLKGATE_DIS | 1579 GAMTLBCOMPC0_CLKGATE_DIS | 1580 GAMTLBCOMPC1_CLKGATE_DIS | 1581 GAMTLBCOMPD0_CLKGATE_DIS | 1582 GAMTLBCOMPD1_CLKGATE_DIS | 1583 GAMTLBMERT_CLKGATE_DIS | 1584 GAMTLBVEBOX3_CLKGATE_DIS | 1585 GAMTLBVEBOX2_CLKGATE_DIS | 1586 GAMTLBVEBOX1_CLKGATE_DIS | 1587 GAMTLBVEBOX0_CLKGATE_DIS); 1588 1589 /* Wa_14010569222:dg2_g10 */ 1590 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1591 GAMEDIA_CLKGATE_DIS); 1592 1593 /* Wa_14011028019:dg2_g10 */ 1594 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1595 } 1596 1597 /* Wa_14014830051:dg2 */ 1598 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1599 1600 /* 1601 * The following are not actually "workarounds" but rather 1602 * recommended tuning settings documented in the bspec's 1603 * performance guide section. 1604 */ 1605 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1606 1607 /* Wa_14015795083 */ 1608 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1609 } 1610 1611 static void 1612 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1613 { 1614 pvc_init_mcr(gt, wal); 1615 1616 /* Wa_14015795083 */ 1617 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1618 } 1619 1620 static void 1621 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1622 { 1623 /* FIXME: Actual workarounds will be added in future patch(es) */ 1624 1625 /* 1626 * Unlike older platforms, we no longer setup implicit steering here; 1627 * all MCR accesses are explicitly steered. 1628 */ 1629 debug_dump_steering(gt); 1630 } 1631 1632 static void 1633 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1634 { 1635 /* FIXME: Actual workarounds will be added in future patch(es) */ 1636 1637 debug_dump_steering(gt); 1638 } 1639 1640 static void 1641 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1642 { 1643 struct drm_i915_private *i915 = gt->i915; 1644 1645 if (gt->type == GT_MEDIA) { 1646 if (MEDIA_VER(i915) >= 13) 1647 xelpmp_gt_workarounds_init(gt, wal); 1648 else 1649 MISSING_CASE(MEDIA_VER(i915)); 1650 1651 return; 1652 } 1653 1654 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1655 xelpg_gt_workarounds_init(gt, wal); 1656 else if (IS_PONTEVECCHIO(i915)) 1657 pvc_gt_workarounds_init(gt, wal); 1658 else if (IS_DG2(i915)) 1659 dg2_gt_workarounds_init(gt, wal); 1660 else if (IS_XEHPSDV(i915)) 1661 xehpsdv_gt_workarounds_init(gt, wal); 1662 else if (IS_DG1(i915)) 1663 dg1_gt_workarounds_init(gt, wal); 1664 else if (IS_TIGERLAKE(i915)) 1665 tgl_gt_workarounds_init(gt, wal); 1666 else if (GRAPHICS_VER(i915) == 12) 1667 gen12_gt_workarounds_init(gt, wal); 1668 else if (GRAPHICS_VER(i915) == 11) 1669 icl_gt_workarounds_init(gt, wal); 1670 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1671 cfl_gt_workarounds_init(gt, wal); 1672 else if (IS_GEMINILAKE(i915)) 1673 glk_gt_workarounds_init(gt, wal); 1674 else if (IS_KABYLAKE(i915)) 1675 kbl_gt_workarounds_init(gt, wal); 1676 else if (IS_BROXTON(i915)) 1677 gen9_gt_workarounds_init(gt, wal); 1678 else if (IS_SKYLAKE(i915)) 1679 skl_gt_workarounds_init(gt, wal); 1680 else if (IS_HASWELL(i915)) 1681 hsw_gt_workarounds_init(gt, wal); 1682 else if (IS_VALLEYVIEW(i915)) 1683 vlv_gt_workarounds_init(gt, wal); 1684 else if (IS_IVYBRIDGE(i915)) 1685 ivb_gt_workarounds_init(gt, wal); 1686 else if (GRAPHICS_VER(i915) == 6) 1687 snb_gt_workarounds_init(gt, wal); 1688 else if (GRAPHICS_VER(i915) == 5) 1689 ilk_gt_workarounds_init(gt, wal); 1690 else if (IS_G4X(i915)) 1691 g4x_gt_workarounds_init(gt, wal); 1692 else if (GRAPHICS_VER(i915) == 4) 1693 gen4_gt_workarounds_init(gt, wal); 1694 else if (GRAPHICS_VER(i915) <= 8) 1695 ; 1696 else 1697 MISSING_CASE(GRAPHICS_VER(i915)); 1698 } 1699 1700 void intel_gt_init_workarounds(struct intel_gt *gt) 1701 { 1702 struct i915_wa_list *wal = >->wa_list; 1703 1704 wa_init_start(wal, gt, "GT", "global"); 1705 gt_init_workarounds(gt, wal); 1706 wa_init_finish(wal); 1707 } 1708 1709 static enum forcewake_domains 1710 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1711 { 1712 enum forcewake_domains fw = 0; 1713 struct i915_wa *wa; 1714 unsigned int i; 1715 1716 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1717 fw |= intel_uncore_forcewake_for_reg(uncore, 1718 wa->reg, 1719 FW_REG_READ | 1720 FW_REG_WRITE); 1721 1722 return fw; 1723 } 1724 1725 static bool 1726 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1727 const char *name, const char *from) 1728 { 1729 if ((cur ^ wa->set) & wa->read) { 1730 drm_err(>->i915->drm, 1731 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1732 name, from, i915_mmio_reg_offset(wa->reg), 1733 cur, cur & wa->read, wa->set & wa->read); 1734 1735 return false; 1736 } 1737 1738 return true; 1739 } 1740 1741 static void wa_list_apply(const struct i915_wa_list *wal) 1742 { 1743 struct intel_gt *gt = wal->gt; 1744 struct intel_uncore *uncore = gt->uncore; 1745 enum forcewake_domains fw; 1746 unsigned long flags; 1747 struct i915_wa *wa; 1748 unsigned int i; 1749 1750 if (!wal->count) 1751 return; 1752 1753 fw = wal_get_fw_for_rmw(uncore, wal); 1754 1755 spin_lock_irqsave(&uncore->lock, flags); 1756 intel_uncore_forcewake_get__locked(uncore, fw); 1757 1758 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1759 u32 val, old = 0; 1760 1761 /* open-coded rmw due to steering */ 1762 if (wa->clr) 1763 old = wa->is_mcr ? 1764 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1765 intel_uncore_read_fw(uncore, wa->reg); 1766 val = (old & ~wa->clr) | wa->set; 1767 if (val != old || !wa->clr) { 1768 if (wa->is_mcr) 1769 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1770 else 1771 intel_uncore_write_fw(uncore, wa->reg, val); 1772 } 1773 1774 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1775 u32 val = wa->is_mcr ? 1776 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1777 intel_uncore_read_fw(uncore, wa->reg); 1778 1779 wa_verify(gt, wa, val, wal->name, "application"); 1780 } 1781 } 1782 1783 intel_uncore_forcewake_put__locked(uncore, fw); 1784 spin_unlock_irqrestore(&uncore->lock, flags); 1785 } 1786 1787 void intel_gt_apply_workarounds(struct intel_gt *gt) 1788 { 1789 wa_list_apply(>->wa_list); 1790 } 1791 1792 static bool wa_list_verify(struct intel_gt *gt, 1793 const struct i915_wa_list *wal, 1794 const char *from) 1795 { 1796 struct intel_uncore *uncore = gt->uncore; 1797 struct i915_wa *wa; 1798 enum forcewake_domains fw; 1799 unsigned long flags; 1800 unsigned int i; 1801 bool ok = true; 1802 1803 fw = wal_get_fw_for_rmw(uncore, wal); 1804 1805 spin_lock_irqsave(&uncore->lock, flags); 1806 intel_uncore_forcewake_get__locked(uncore, fw); 1807 1808 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1809 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1810 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1811 intel_uncore_read_fw(uncore, wa->reg), 1812 wal->name, from); 1813 1814 intel_uncore_forcewake_put__locked(uncore, fw); 1815 spin_unlock_irqrestore(&uncore->lock, flags); 1816 1817 return ok; 1818 } 1819 1820 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1821 { 1822 return wa_list_verify(gt, >->wa_list, from); 1823 } 1824 1825 __maybe_unused 1826 static bool is_nonpriv_flags_valid(u32 flags) 1827 { 1828 /* Check only valid flag bits are set */ 1829 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1830 return false; 1831 1832 /* NB: Only 3 out of 4 enum values are valid for access field */ 1833 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1834 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1835 return false; 1836 1837 return true; 1838 } 1839 1840 static void 1841 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1842 { 1843 struct i915_wa wa = { 1844 .reg = reg 1845 }; 1846 1847 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1848 return; 1849 1850 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1851 return; 1852 1853 wa.reg.reg |= flags; 1854 _wa_add(wal, &wa); 1855 } 1856 1857 static void 1858 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1859 { 1860 struct i915_wa wa = { 1861 .mcr_reg = reg, 1862 .is_mcr = 1, 1863 }; 1864 1865 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1866 return; 1867 1868 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1869 return; 1870 1871 wa.mcr_reg.reg |= flags; 1872 _wa_add(wal, &wa); 1873 } 1874 1875 static void 1876 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1877 { 1878 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1879 } 1880 1881 static void 1882 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1883 { 1884 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1885 } 1886 1887 static void gen9_whitelist_build(struct i915_wa_list *w) 1888 { 1889 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1890 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1891 1892 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1893 whitelist_reg(w, GEN8_CS_CHICKEN1); 1894 1895 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1896 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1897 1898 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1899 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1900 } 1901 1902 static void skl_whitelist_build(struct intel_engine_cs *engine) 1903 { 1904 struct i915_wa_list *w = &engine->whitelist; 1905 1906 if (engine->class != RENDER_CLASS) 1907 return; 1908 1909 gen9_whitelist_build(w); 1910 1911 /* WaDisableLSQCROPERFforOCL:skl */ 1912 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1913 } 1914 1915 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1916 { 1917 if (engine->class != RENDER_CLASS) 1918 return; 1919 1920 gen9_whitelist_build(&engine->whitelist); 1921 } 1922 1923 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1924 { 1925 struct i915_wa_list *w = &engine->whitelist; 1926 1927 if (engine->class != RENDER_CLASS) 1928 return; 1929 1930 gen9_whitelist_build(w); 1931 1932 /* WaDisableLSQCROPERFforOCL:kbl */ 1933 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1934 } 1935 1936 static void glk_whitelist_build(struct intel_engine_cs *engine) 1937 { 1938 struct i915_wa_list *w = &engine->whitelist; 1939 1940 if (engine->class != RENDER_CLASS) 1941 return; 1942 1943 gen9_whitelist_build(w); 1944 1945 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1946 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1947 } 1948 1949 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1950 { 1951 struct i915_wa_list *w = &engine->whitelist; 1952 1953 if (engine->class != RENDER_CLASS) 1954 return; 1955 1956 gen9_whitelist_build(w); 1957 1958 /* 1959 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1960 * 1961 * This covers 4 register which are next to one another : 1962 * - PS_INVOCATION_COUNT 1963 * - PS_INVOCATION_COUNT_UDW 1964 * - PS_DEPTH_COUNT 1965 * - PS_DEPTH_COUNT_UDW 1966 */ 1967 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1968 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1969 RING_FORCE_TO_NONPRIV_RANGE_4); 1970 } 1971 1972 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1973 { 1974 struct i915_wa_list *w = &engine->whitelist; 1975 1976 if (engine->class != RENDER_CLASS) 1977 whitelist_reg_ext(w, 1978 RING_CTX_TIMESTAMP(engine->mmio_base), 1979 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1980 } 1981 1982 static void cml_whitelist_build(struct intel_engine_cs *engine) 1983 { 1984 allow_read_ctx_timestamp(engine); 1985 1986 cfl_whitelist_build(engine); 1987 } 1988 1989 static void icl_whitelist_build(struct intel_engine_cs *engine) 1990 { 1991 struct i915_wa_list *w = &engine->whitelist; 1992 1993 allow_read_ctx_timestamp(engine); 1994 1995 switch (engine->class) { 1996 case RENDER_CLASS: 1997 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1998 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1999 2000 /* WaAllowUMDToModifySamplerMode:icl */ 2001 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2002 2003 /* WaEnableStateCacheRedirectToCS:icl */ 2004 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2005 2006 /* 2007 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2008 * 2009 * This covers 4 register which are next to one another : 2010 * - PS_INVOCATION_COUNT 2011 * - PS_INVOCATION_COUNT_UDW 2012 * - PS_DEPTH_COUNT 2013 * - PS_DEPTH_COUNT_UDW 2014 */ 2015 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2016 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2017 RING_FORCE_TO_NONPRIV_RANGE_4); 2018 break; 2019 2020 case VIDEO_DECODE_CLASS: 2021 /* hucStatusRegOffset */ 2022 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2023 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2024 /* hucUKernelHdrInfoRegOffset */ 2025 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2026 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2027 /* hucStatus2RegOffset */ 2028 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2029 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2030 break; 2031 2032 default: 2033 break; 2034 } 2035 } 2036 2037 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2038 { 2039 struct i915_wa_list *w = &engine->whitelist; 2040 2041 allow_read_ctx_timestamp(engine); 2042 2043 switch (engine->class) { 2044 case RENDER_CLASS: 2045 /* 2046 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2047 * Wa_1408556865:tgl 2048 * 2049 * This covers 4 registers which are next to one another : 2050 * - PS_INVOCATION_COUNT 2051 * - PS_INVOCATION_COUNT_UDW 2052 * - PS_DEPTH_COUNT 2053 * - PS_DEPTH_COUNT_UDW 2054 */ 2055 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2056 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2057 RING_FORCE_TO_NONPRIV_RANGE_4); 2058 2059 /* 2060 * Wa_1808121037:tgl 2061 * Wa_14012131227:dg1 2062 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2063 */ 2064 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2065 2066 /* Wa_1806527549:tgl */ 2067 whitelist_reg(w, HIZ_CHICKEN); 2068 break; 2069 default: 2070 break; 2071 } 2072 } 2073 2074 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2075 { 2076 struct i915_wa_list *w = &engine->whitelist; 2077 2078 tgl_whitelist_build(engine); 2079 2080 /* GEN:BUG:1409280441:dg1 */ 2081 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2082 (engine->class == RENDER_CLASS || 2083 engine->class == COPY_ENGINE_CLASS)) 2084 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2085 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2086 } 2087 2088 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2089 { 2090 allow_read_ctx_timestamp(engine); 2091 } 2092 2093 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2094 { 2095 struct i915_wa_list *w = &engine->whitelist; 2096 2097 allow_read_ctx_timestamp(engine); 2098 2099 switch (engine->class) { 2100 case RENDER_CLASS: 2101 /* 2102 * Wa_1507100340:dg2_g10 2103 * 2104 * This covers 4 registers which are next to one another : 2105 * - PS_INVOCATION_COUNT 2106 * - PS_INVOCATION_COUNT_UDW 2107 * - PS_DEPTH_COUNT 2108 * - PS_DEPTH_COUNT_UDW 2109 */ 2110 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2111 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2112 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2113 RING_FORCE_TO_NONPRIV_RANGE_4); 2114 2115 break; 2116 case COMPUTE_CLASS: 2117 /* Wa_16011157294:dg2_g10 */ 2118 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2119 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2120 break; 2121 default: 2122 break; 2123 } 2124 } 2125 2126 static void blacklist_trtt(struct intel_engine_cs *engine) 2127 { 2128 struct i915_wa_list *w = &engine->whitelist; 2129 2130 /* 2131 * Prevent read/write access to [0x4400, 0x4600) which covers 2132 * the TRTT range across all engines. Note that normally userspace 2133 * cannot access the other engines' trtt control, but for simplicity 2134 * we cover the entire range on each engine. 2135 */ 2136 whitelist_reg_ext(w, _MMIO(0x4400), 2137 RING_FORCE_TO_NONPRIV_DENY | 2138 RING_FORCE_TO_NONPRIV_RANGE_64); 2139 whitelist_reg_ext(w, _MMIO(0x4500), 2140 RING_FORCE_TO_NONPRIV_DENY | 2141 RING_FORCE_TO_NONPRIV_RANGE_64); 2142 } 2143 2144 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2145 { 2146 allow_read_ctx_timestamp(engine); 2147 2148 /* Wa_16014440446:pvc */ 2149 blacklist_trtt(engine); 2150 } 2151 2152 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2153 { 2154 struct drm_i915_private *i915 = engine->i915; 2155 struct i915_wa_list *w = &engine->whitelist; 2156 2157 wa_init_start(w, engine->gt, "whitelist", engine->name); 2158 2159 if (IS_PONTEVECCHIO(i915)) 2160 pvc_whitelist_build(engine); 2161 else if (IS_DG2(i915)) 2162 dg2_whitelist_build(engine); 2163 else if (IS_XEHPSDV(i915)) 2164 xehpsdv_whitelist_build(engine); 2165 else if (IS_DG1(i915)) 2166 dg1_whitelist_build(engine); 2167 else if (GRAPHICS_VER(i915) == 12) 2168 tgl_whitelist_build(engine); 2169 else if (GRAPHICS_VER(i915) == 11) 2170 icl_whitelist_build(engine); 2171 else if (IS_COMETLAKE(i915)) 2172 cml_whitelist_build(engine); 2173 else if (IS_COFFEELAKE(i915)) 2174 cfl_whitelist_build(engine); 2175 else if (IS_GEMINILAKE(i915)) 2176 glk_whitelist_build(engine); 2177 else if (IS_KABYLAKE(i915)) 2178 kbl_whitelist_build(engine); 2179 else if (IS_BROXTON(i915)) 2180 bxt_whitelist_build(engine); 2181 else if (IS_SKYLAKE(i915)) 2182 skl_whitelist_build(engine); 2183 else if (GRAPHICS_VER(i915) <= 8) 2184 ; 2185 else 2186 MISSING_CASE(GRAPHICS_VER(i915)); 2187 2188 wa_init_finish(w); 2189 } 2190 2191 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2192 { 2193 const struct i915_wa_list *wal = &engine->whitelist; 2194 struct intel_uncore *uncore = engine->uncore; 2195 const u32 base = engine->mmio_base; 2196 struct i915_wa *wa; 2197 unsigned int i; 2198 2199 if (!wal->count) 2200 return; 2201 2202 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2203 intel_uncore_write(uncore, 2204 RING_FORCE_TO_NONPRIV(base, i), 2205 i915_mmio_reg_offset(wa->reg)); 2206 2207 /* And clear the rest just in case of garbage */ 2208 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2209 intel_uncore_write(uncore, 2210 RING_FORCE_TO_NONPRIV(base, i), 2211 i915_mmio_reg_offset(RING_NOPID(base))); 2212 } 2213 2214 /* 2215 * engine_fake_wa_init(), a place holder to program the registers 2216 * which are not part of an official workaround defined by the 2217 * hardware team. 2218 * Adding programming of those register inside workaround will 2219 * allow utilizing wa framework to proper application and verification. 2220 */ 2221 static void 2222 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2223 { 2224 u8 mocs_w, mocs_r; 2225 2226 /* 2227 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2228 * by the command streamer when executing commands that don't have 2229 * a way to explicitly specify a MOCS setting. The default should 2230 * usually reference whichever MOCS entry corresponds to uncached 2231 * behavior, although use of a WB cached entry is recommended by the 2232 * spec in certain circumstances on specific platforms. 2233 */ 2234 if (GRAPHICS_VER(engine->i915) >= 12) { 2235 mocs_r = engine->gt->mocs.uc_index; 2236 mocs_w = engine->gt->mocs.uc_index; 2237 2238 if (HAS_L3_CCS_READ(engine->i915) && 2239 engine->class == COMPUTE_CLASS) { 2240 mocs_r = engine->gt->mocs.wb_index; 2241 2242 /* 2243 * Even on the few platforms where MOCS 0 is a 2244 * legitimate table entry, it's never the correct 2245 * setting to use here; we can assume the MOCS init 2246 * just forgot to initialize wb_index. 2247 */ 2248 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2249 } 2250 2251 wa_masked_field_set(wal, 2252 RING_CMD_CCTL(engine->mmio_base), 2253 CMD_CCTL_MOCS_MASK, 2254 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2255 } 2256 } 2257 2258 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2259 { 2260 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2261 GEN_DSS_PER_GSLICE; 2262 } 2263 2264 static void 2265 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2266 { 2267 struct drm_i915_private *i915 = engine->i915; 2268 2269 if (IS_DG2(i915)) { 2270 /* Wa_1509235366:dg2 */ 2271 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2272 GLOBAL_INVALIDATION_MODE); 2273 } 2274 2275 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2276 /* Wa_14013392000:dg2_g11 */ 2277 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2278 } 2279 2280 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2281 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2282 /* Wa_1509727124:dg2 */ 2283 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2284 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2285 } 2286 2287 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2288 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2289 /* Wa_14012419201:dg2 */ 2290 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2291 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2292 } 2293 2294 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2295 IS_DG2_G11(i915)) { 2296 /* 2297 * Wa_22012826095:dg2 2298 * Wa_22013059131:dg2 2299 */ 2300 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2301 MAXREQS_PER_BANK, 2302 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2303 2304 /* Wa_22013059131:dg2 */ 2305 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2306 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2307 } 2308 2309 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2310 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2311 needs_wa_1308578152(engine)) { 2312 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2313 GEN12_REPLAY_MODE_GRANULARITY); 2314 } 2315 2316 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2317 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2318 /* Wa_22013037850:dg2 */ 2319 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2320 DISABLE_128B_EVICTION_COMMAND_UDW); 2321 2322 /* Wa_22012856258:dg2 */ 2323 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2324 GEN12_DISABLE_READ_SUPPRESSION); 2325 2326 /* 2327 * Wa_22010960976:dg2 2328 * Wa_14013347512:dg2 2329 */ 2330 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2331 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2332 } 2333 2334 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2335 /* 2336 * Wa_1608949956:dg2_g10 2337 * Wa_14010198302:dg2_g10 2338 */ 2339 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2340 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2341 2342 /* 2343 * Wa_14010918519:dg2_g10 2344 * 2345 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2346 * so ignoring verification. 2347 */ 2348 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2349 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2350 0, false); 2351 } 2352 2353 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2354 /* Wa_22010430635:dg2 */ 2355 wa_mcr_masked_en(wal, 2356 GEN9_ROW_CHICKEN4, 2357 GEN12_DISABLE_GRF_CLEAR); 2358 2359 /* Wa_14010648519:dg2 */ 2360 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2361 } 2362 2363 /* Wa_14013202645:dg2 */ 2364 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2365 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2366 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2367 2368 /* Wa_22012532006:dg2 */ 2369 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2370 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2371 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2372 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2373 2374 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2375 /* Wa_14010680813:dg2_g10 */ 2376 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2377 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2378 } 2379 2380 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2381 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2382 /* Wa_14012362059:dg2 */ 2383 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2384 } 2385 2386 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2387 IS_DG2_G10(i915)) { 2388 /* Wa_22014600077:dg2 */ 2389 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2390 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2391 0 /* Wa_14012342262 write-only reg, so skip verification */, 2392 true); 2393 } 2394 2395 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2396 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2397 /* 2398 * Wa_1607138336:tgl[a0],dg1[a0] 2399 * Wa_1607063988:tgl[a0],dg1[a0] 2400 */ 2401 wa_write_or(wal, 2402 GEN9_CTX_PREEMPT_REG, 2403 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2404 } 2405 2406 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2407 /* 2408 * Wa_1606679103:tgl 2409 * (see also Wa_1606682166:icl) 2410 */ 2411 wa_write_or(wal, 2412 GEN7_SARCHKMD, 2413 GEN7_DISABLE_SAMPLER_PREFETCH); 2414 } 2415 2416 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2417 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2418 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2419 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2420 2421 /* 2422 * Wa_1407928979:tgl A* 2423 * Wa_18011464164:tgl[B0+],dg1[B0+] 2424 * Wa_22010931296:tgl[B0+],dg1[B0+] 2425 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2426 */ 2427 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2428 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2429 } 2430 2431 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2432 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2433 /* 2434 * Wa_1606700617:tgl,dg1,adl-p 2435 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2436 * Wa_14010826681:tgl,dg1,rkl,adl-p 2437 * Wa_18019627453:dg2 2438 */ 2439 wa_masked_en(wal, 2440 GEN9_CS_DEBUG_MODE1, 2441 FF_DOP_CLOCK_GATE_DISABLE); 2442 } 2443 2444 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2445 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2446 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2447 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2448 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2449 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2450 2451 /* 2452 * Wa_1409085225:tgl 2453 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2454 */ 2455 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2456 } 2457 2458 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2459 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2460 /* 2461 * Wa_1607030317:tgl 2462 * Wa_1607186500:tgl 2463 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2464 * 2465 * On TGL and RKL there are multiple entries for this WA in the 2466 * BSpec; some indicate this is an A0-only WA, others indicate 2467 * it applies to all steppings so we trust the "all steppings." 2468 * For DG1 this only applies to A0. 2469 */ 2470 wa_masked_en(wal, 2471 RING_PSMI_CTL(RENDER_RING_BASE), 2472 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2473 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2474 } 2475 2476 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2477 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2478 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2479 wa_mcr_masked_en(wal, 2480 GEN10_SAMPLER_MODE, 2481 ENABLE_SMALLPL); 2482 } 2483 2484 if (GRAPHICS_VER(i915) == 11) { 2485 /* This is not an Wa. Enable for better image quality */ 2486 wa_masked_en(wal, 2487 _3D_CHICKEN3, 2488 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2489 2490 /* 2491 * Wa_1405543622:icl 2492 * Formerly known as WaGAPZPriorityScheme 2493 */ 2494 wa_write_or(wal, 2495 GEN8_GARBCNTL, 2496 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2497 2498 /* 2499 * Wa_1604223664:icl 2500 * Formerly known as WaL3BankAddressHashing 2501 */ 2502 wa_write_clr_set(wal, 2503 GEN8_GARBCNTL, 2504 GEN11_HASH_CTRL_EXCL_MASK, 2505 GEN11_HASH_CTRL_EXCL_BIT0); 2506 wa_write_clr_set(wal, 2507 GEN11_GLBLINVL, 2508 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2509 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2510 2511 /* 2512 * Wa_1405733216:icl 2513 * Formerly known as WaDisableCleanEvicts 2514 */ 2515 wa_mcr_write_or(wal, 2516 GEN8_L3SQCREG4, 2517 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2518 2519 /* Wa_1606682166:icl */ 2520 wa_write_or(wal, 2521 GEN7_SARCHKMD, 2522 GEN7_DISABLE_SAMPLER_PREFETCH); 2523 2524 /* Wa_1409178092:icl */ 2525 wa_mcr_write_clr_set(wal, 2526 GEN11_SCRATCH2, 2527 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2528 0); 2529 2530 /* WaEnable32PlaneMode:icl */ 2531 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2532 GEN11_ENABLE_32_PLANE_MODE); 2533 2534 /* 2535 * Wa_1408615072:icl,ehl (vsunit) 2536 * Wa_1407596294:icl,ehl (hsunit) 2537 */ 2538 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2539 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2540 2541 /* 2542 * Wa_1408767742:icl[a2..forever],ehl[all] 2543 * Wa_1605460711:icl[a0..c0] 2544 */ 2545 wa_write_or(wal, 2546 GEN7_FF_THREAD_MODE, 2547 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2548 2549 /* Wa_22010271021 */ 2550 wa_masked_en(wal, 2551 GEN9_CS_DEBUG_MODE1, 2552 FF_DOP_CLOCK_GATE_DISABLE); 2553 } 2554 2555 /* 2556 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2557 * beyond) allow the kernel-mode driver to choose between two different 2558 * options for controlling preemption granularity and behavior. 2559 * 2560 * Option 1 (hardware default): 2561 * Preemption settings are controlled in a global manner via 2562 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2563 * and settings chosen by the kernel-mode driver will apply to all 2564 * userspace clients. 2565 * 2566 * Option 2: 2567 * Preemption settings are controlled on a per-context basis via 2568 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2569 * context switch and is writable by userspace (e.g., via 2570 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2571 * which allows different userspace drivers/clients to select 2572 * different settings, or to change those settings on the fly in 2573 * response to runtime needs. This option was known by name 2574 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2575 * that name is somewhat misleading as other non-granularity 2576 * preemption settings are also impacted by this decision. 2577 * 2578 * On Linux, our policy has always been to let userspace drivers 2579 * control preemption granularity/settings (Option 2). This was 2580 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2581 * userspace developed before object-level preemption was enabled would 2582 * not behave well if i915 were to go with Option 1 and enable that 2583 * preemption in a global manner). On gen9 each context would have 2584 * object-level preemption disabled by default (see 2585 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2586 * userspace drivers could opt-in to object-level preemption as they 2587 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2588 * even though it is no longer necessary for ABI compatibility when 2589 * enabling a new platform, it does ensure that userspace will be able 2590 * to implement any workarounds that show up requiring temporary 2591 * adjustments to preemption behavior at runtime. 2592 * 2593 * Notes/Workarounds: 2594 * - Wa_14015141709: On DG2 and early steppings of MTL, 2595 * CS_CHICKEN1[0] does not disable object-level preemption as 2596 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2597 * using Option 1). Effectively this means userspace is unable 2598 * to disable object-level preemption on these platforms/steppings 2599 * despite the setting here. 2600 * 2601 * - Wa_16013994831: May require that userspace program 2602 * CS_CHICKEN1[10] when certain runtime conditions are true. 2603 * Userspace requires Option 2 to be in effect for their update of 2604 * CS_CHICKEN1[10] to be effective. 2605 * 2606 * Other workarounds may appear in the future that will also require 2607 * Option 2 behavior to allow proper userspace implementation. 2608 */ 2609 if (GRAPHICS_VER(i915) >= 9) 2610 wa_masked_en(wal, 2611 GEN7_FF_SLICE_CS_CHICKEN1, 2612 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2613 2614 if (IS_SKYLAKE(i915) || 2615 IS_KABYLAKE(i915) || 2616 IS_COFFEELAKE(i915) || 2617 IS_COMETLAKE(i915)) { 2618 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2619 wa_write_or(wal, 2620 GEN8_GARBCNTL, 2621 GEN9_GAPS_TSV_CREDIT_DISABLE); 2622 } 2623 2624 if (IS_BROXTON(i915)) { 2625 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2626 wa_masked_en(wal, 2627 FF_SLICE_CS_CHICKEN2, 2628 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2629 } 2630 2631 if (GRAPHICS_VER(i915) == 9) { 2632 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2633 wa_masked_en(wal, 2634 GEN9_CSFE_CHICKEN1_RCS, 2635 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2636 2637 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2638 wa_mcr_write_or(wal, 2639 BDW_SCRATCH1, 2640 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2641 2642 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2643 if (IS_GEN9_LP(i915)) 2644 wa_mcr_write_clr_set(wal, 2645 GEN8_L3SQCREG1, 2646 L3_PRIO_CREDITS_MASK, 2647 L3_GENERAL_PRIO_CREDITS(62) | 2648 L3_HIGH_PRIO_CREDITS(2)); 2649 2650 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2651 wa_mcr_write_or(wal, 2652 GEN8_L3SQCREG4, 2653 GEN8_LQSC_FLUSH_COHERENT_LINES); 2654 2655 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2656 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2657 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2658 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2659 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2660 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2661 EVICTION_PERF_FIX_ENABLE, 0); 2662 } 2663 2664 if (IS_HASWELL(i915)) { 2665 /* WaSampleCChickenBitEnable:hsw */ 2666 wa_masked_en(wal, 2667 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2668 2669 wa_masked_dis(wal, 2670 CACHE_MODE_0_GEN7, 2671 /* enable HiZ Raw Stall Optimization */ 2672 HIZ_RAW_STALL_OPT_DISABLE); 2673 } 2674 2675 if (IS_VALLEYVIEW(i915)) { 2676 /* WaDisableEarlyCull:vlv */ 2677 wa_masked_en(wal, 2678 _3D_CHICKEN3, 2679 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2680 2681 /* 2682 * WaVSThreadDispatchOverride:ivb,vlv 2683 * 2684 * This actually overrides the dispatch 2685 * mode for all thread types. 2686 */ 2687 wa_write_clr_set(wal, 2688 GEN7_FF_THREAD_MODE, 2689 GEN7_FF_SCHED_MASK, 2690 GEN7_FF_TS_SCHED_HW | 2691 GEN7_FF_VS_SCHED_HW | 2692 GEN7_FF_DS_SCHED_HW); 2693 2694 /* WaPsdDispatchEnable:vlv */ 2695 /* WaDisablePSDDualDispatchEnable:vlv */ 2696 wa_masked_en(wal, 2697 GEN7_HALF_SLICE_CHICKEN1, 2698 GEN7_MAX_PS_THREAD_DEP | 2699 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2700 } 2701 2702 if (IS_IVYBRIDGE(i915)) { 2703 /* WaDisableEarlyCull:ivb */ 2704 wa_masked_en(wal, 2705 _3D_CHICKEN3, 2706 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2707 2708 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2709 /* enable HiZ Raw Stall Optimization */ 2710 wa_masked_dis(wal, 2711 CACHE_MODE_0_GEN7, 2712 HIZ_RAW_STALL_OPT_DISABLE); 2713 } 2714 2715 /* 2716 * WaVSThreadDispatchOverride:ivb,vlv 2717 * 2718 * This actually overrides the dispatch 2719 * mode for all thread types. 2720 */ 2721 wa_write_clr_set(wal, 2722 GEN7_FF_THREAD_MODE, 2723 GEN7_FF_SCHED_MASK, 2724 GEN7_FF_TS_SCHED_HW | 2725 GEN7_FF_VS_SCHED_HW | 2726 GEN7_FF_DS_SCHED_HW); 2727 2728 /* WaDisablePSDDualDispatchEnable:ivb */ 2729 if (IS_IVB_GT1(i915)) 2730 wa_masked_en(wal, 2731 GEN7_HALF_SLICE_CHICKEN1, 2732 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2733 } 2734 2735 if (GRAPHICS_VER(i915) == 7) { 2736 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2737 wa_masked_en(wal, 2738 RING_MODE_GEN7(RENDER_RING_BASE), 2739 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2740 2741 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2742 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2743 2744 /* 2745 * BSpec says this must be set, even though 2746 * WaDisable4x2SubspanOptimization:ivb,hsw 2747 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2748 */ 2749 wa_masked_en(wal, 2750 CACHE_MODE_1, 2751 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2752 2753 /* 2754 * BSpec recommends 8x4 when MSAA is used, 2755 * however in practice 16x4 seems fastest. 2756 * 2757 * Note that PS/WM thread counts depend on the WIZ hashing 2758 * disable bit, which we don't touch here, but it's good 2759 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2760 */ 2761 wa_masked_field_set(wal, 2762 GEN7_GT_MODE, 2763 GEN6_WIZ_HASHING_MASK, 2764 GEN6_WIZ_HASHING_16x4); 2765 } 2766 2767 if (IS_GRAPHICS_VER(i915, 6, 7)) 2768 /* 2769 * We need to disable the AsyncFlip performance optimisations in 2770 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2771 * already be programmed to '1' on all products. 2772 * 2773 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2774 */ 2775 wa_masked_en(wal, 2776 RING_MI_MODE(RENDER_RING_BASE), 2777 ASYNC_FLIP_PERF_DISABLE); 2778 2779 if (GRAPHICS_VER(i915) == 6) { 2780 /* 2781 * Required for the hardware to program scanline values for 2782 * waiting 2783 * WaEnableFlushTlbInvalidationMode:snb 2784 */ 2785 wa_masked_en(wal, 2786 GFX_MODE, 2787 GFX_TLB_INVALIDATE_EXPLICIT); 2788 2789 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2790 wa_masked_en(wal, 2791 _3D_CHICKEN, 2792 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2793 2794 wa_masked_en(wal, 2795 _3D_CHICKEN3, 2796 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2797 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2798 /* 2799 * Bspec says: 2800 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2801 * to normal and 3DSTATE_SF number of SF output attributes 2802 * is more than 16." 2803 */ 2804 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2805 2806 /* 2807 * BSpec recommends 8x4 when MSAA is used, 2808 * however in practice 16x4 seems fastest. 2809 * 2810 * Note that PS/WM thread counts depend on the WIZ hashing 2811 * disable bit, which we don't touch here, but it's good 2812 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2813 */ 2814 wa_masked_field_set(wal, 2815 GEN6_GT_MODE, 2816 GEN6_WIZ_HASHING_MASK, 2817 GEN6_WIZ_HASHING_16x4); 2818 2819 /* WaDisable_RenderCache_OperationalFlush:snb */ 2820 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2821 2822 /* 2823 * From the Sandybridge PRM, volume 1 part 3, page 24: 2824 * "If this bit is set, STCunit will have LRA as replacement 2825 * policy. [...] This bit must be reset. LRA replacement 2826 * policy is not supported." 2827 */ 2828 wa_masked_dis(wal, 2829 CACHE_MODE_0, 2830 CM0_STC_EVICT_DISABLE_LRA_SNB); 2831 } 2832 2833 if (IS_GRAPHICS_VER(i915, 4, 6)) 2834 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2835 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2836 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2837 /* XXX bit doesn't stick on Broadwater */ 2838 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2839 2840 if (GRAPHICS_VER(i915) == 4) 2841 /* 2842 * Disable CONSTANT_BUFFER before it is loaded from the context 2843 * image. For as it is loaded, it is executed and the stored 2844 * address may no longer be valid, leading to a GPU hang. 2845 * 2846 * This imposes the requirement that userspace reload their 2847 * CONSTANT_BUFFER on every batch, fortunately a requirement 2848 * they are already accustomed to from before contexts were 2849 * enabled. 2850 */ 2851 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2852 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2853 0 /* XXX bit doesn't stick on Broadwater */, 2854 true); 2855 } 2856 2857 static void 2858 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2859 { 2860 struct drm_i915_private *i915 = engine->i915; 2861 2862 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2863 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2864 wa_write(wal, 2865 RING_SEMA_WAIT_POLL(engine->mmio_base), 2866 1); 2867 } 2868 } 2869 2870 static void 2871 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2872 { 2873 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2874 /* Wa_14014999345:pvc */ 2875 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2876 } 2877 } 2878 2879 /* 2880 * The bspec performance guide has recommended MMIO tuning settings. These 2881 * aren't truly "workarounds" but we want to program them with the same 2882 * workaround infrastructure to ensure that they're automatically added to 2883 * the GuC save/restore lists, re-applied at the right times, and checked for 2884 * any conflicting programming requested by real workarounds. 2885 * 2886 * Programming settings should be added here only if their registers are not 2887 * part of an engine's register state context. If a register is part of a 2888 * context, then any tuning settings should be programmed in an appropriate 2889 * function invoked by __intel_engine_init_ctx_wa(). 2890 */ 2891 static void 2892 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2893 struct i915_wa_list *wal) 2894 { 2895 if (IS_PONTEVECCHIO(i915)) { 2896 wa_write(wal, XEHPC_L3SCRUB, 2897 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2898 } 2899 2900 if (IS_DG2(i915)) { 2901 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2902 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2903 2904 /* 2905 * This is also listed as Wa_22012654132 for certain DG2 2906 * steppings, but the tuning setting programming is a superset 2907 * since it applies to all DG2 variants and steppings. 2908 * 2909 * Note that register 0xE420 is write-only and cannot be read 2910 * back for verification on DG2 (due to Wa_14012342262), so 2911 * we need to explicitly skip the readback. 2912 */ 2913 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2914 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2915 0 /* write-only, so skip validation */, 2916 true); 2917 } 2918 2919 /* 2920 * This tuning setting proves beneficial only on ATS-M designs; the 2921 * default "age based" setting is optimal on regular DG2 and other 2922 * platforms. 2923 */ 2924 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2925 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2926 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2927 } 2928 2929 /* 2930 * The workarounds in this function apply to shared registers in 2931 * the general render reset domain that aren't tied to a 2932 * specific engine. Since all render+compute engines get reset 2933 * together, and the contents of these registers are lost during 2934 * the shared render domain reset, we'll define such workarounds 2935 * here and then add them to just a single RCS or CCS engine's 2936 * workaround list (whichever engine has the XXXX flag). 2937 */ 2938 static void 2939 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2940 { 2941 struct drm_i915_private *i915 = engine->i915; 2942 2943 add_render_compute_tuning_settings(i915, wal); 2944 2945 if (IS_PONTEVECCHIO(i915)) { 2946 /* Wa_16016694945 */ 2947 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 2948 } 2949 2950 if (IS_XEHPSDV(i915)) { 2951 /* Wa_1409954639 */ 2952 wa_mcr_masked_en(wal, 2953 GEN8_ROW_CHICKEN, 2954 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2955 2956 /* Wa_1607196519 */ 2957 wa_mcr_masked_en(wal, 2958 GEN9_ROW_CHICKEN4, 2959 GEN12_DISABLE_GRF_CLEAR); 2960 2961 /* Wa_14010670810:xehpsdv */ 2962 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2963 2964 /* Wa_14010449647:xehpsdv */ 2965 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2966 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2967 2968 /* Wa_18011725039:xehpsdv */ 2969 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2970 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2971 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2972 } 2973 2974 /* Wa_14012362059:xehpsdv */ 2975 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2976 2977 /* Wa_14014368820:xehpsdv */ 2978 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2979 GLOBAL_INVALIDATION_MODE); 2980 } 2981 2982 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 2983 /* Wa_14015227452:dg2,pvc */ 2984 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2985 2986 /* Wa_22014226127:dg2,pvc */ 2987 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2988 2989 /* Wa_16015675438:dg2,pvc */ 2990 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2991 2992 /* Wa_18018781329:dg2,pvc */ 2993 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2994 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2995 wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2996 wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2997 } 2998 2999 if (IS_DG2(i915)) { 3000 /* 3001 * Wa_16011620976:dg2_g11 3002 * Wa_22015475538:dg2 3003 */ 3004 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3005 3006 /* Wa_18017747507:dg2 */ 3007 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3008 } 3009 } 3010 3011 static void 3012 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3013 { 3014 if (GRAPHICS_VER(engine->i915) < 4) 3015 return; 3016 3017 engine_fake_wa_init(engine, wal); 3018 3019 /* 3020 * These are common workarounds that just need to applied 3021 * to a single RCS/CCS engine's workaround list since 3022 * they're reset as part of the general render domain reset. 3023 */ 3024 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3025 general_render_compute_wa_init(engine, wal); 3026 3027 if (engine->class == COMPUTE_CLASS) 3028 ccs_engine_wa_init(engine, wal); 3029 else if (engine->class == RENDER_CLASS) 3030 rcs_engine_wa_init(engine, wal); 3031 else 3032 xcs_engine_wa_init(engine, wal); 3033 } 3034 3035 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3036 { 3037 struct i915_wa_list *wal = &engine->wa_list; 3038 3039 wa_init_start(wal, engine->gt, "engine", engine->name); 3040 engine_init_workarounds(engine, wal); 3041 wa_init_finish(wal); 3042 } 3043 3044 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3045 { 3046 wa_list_apply(&engine->wa_list); 3047 } 3048 3049 static const struct i915_range mcr_ranges_gen8[] = { 3050 { .start = 0x5500, .end = 0x55ff }, 3051 { .start = 0x7000, .end = 0x7fff }, 3052 { .start = 0x9400, .end = 0x97ff }, 3053 { .start = 0xb000, .end = 0xb3ff }, 3054 { .start = 0xe000, .end = 0xe7ff }, 3055 {}, 3056 }; 3057 3058 static const struct i915_range mcr_ranges_gen12[] = { 3059 { .start = 0x8150, .end = 0x815f }, 3060 { .start = 0x9520, .end = 0x955f }, 3061 { .start = 0xb100, .end = 0xb3ff }, 3062 { .start = 0xde80, .end = 0xe8ff }, 3063 { .start = 0x24a00, .end = 0x24a7f }, 3064 {}, 3065 }; 3066 3067 static const struct i915_range mcr_ranges_xehp[] = { 3068 { .start = 0x4000, .end = 0x4aff }, 3069 { .start = 0x5200, .end = 0x52ff }, 3070 { .start = 0x5400, .end = 0x7fff }, 3071 { .start = 0x8140, .end = 0x815f }, 3072 { .start = 0x8c80, .end = 0x8dff }, 3073 { .start = 0x94d0, .end = 0x955f }, 3074 { .start = 0x9680, .end = 0x96ff }, 3075 { .start = 0xb000, .end = 0xb3ff }, 3076 { .start = 0xc800, .end = 0xcfff }, 3077 { .start = 0xd800, .end = 0xd8ff }, 3078 { .start = 0xdc00, .end = 0xffff }, 3079 { .start = 0x17000, .end = 0x17fff }, 3080 { .start = 0x24a00, .end = 0x24a7f }, 3081 {}, 3082 }; 3083 3084 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3085 { 3086 const struct i915_range *mcr_ranges; 3087 int i; 3088 3089 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3090 mcr_ranges = mcr_ranges_xehp; 3091 else if (GRAPHICS_VER(i915) >= 12) 3092 mcr_ranges = mcr_ranges_gen12; 3093 else if (GRAPHICS_VER(i915) >= 8) 3094 mcr_ranges = mcr_ranges_gen8; 3095 else 3096 return false; 3097 3098 /* 3099 * Registers in these ranges are affected by the MCR selector 3100 * which only controls CPU initiated MMIO. Routing does not 3101 * work for CS access so we cannot verify them on this path. 3102 */ 3103 for (i = 0; mcr_ranges[i].start; i++) 3104 if (offset >= mcr_ranges[i].start && 3105 offset <= mcr_ranges[i].end) 3106 return true; 3107 3108 return false; 3109 } 3110 3111 static int 3112 wa_list_srm(struct i915_request *rq, 3113 const struct i915_wa_list *wal, 3114 struct i915_vma *vma) 3115 { 3116 struct drm_i915_private *i915 = rq->engine->i915; 3117 unsigned int i, count = 0; 3118 const struct i915_wa *wa; 3119 u32 srm, *cs; 3120 3121 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3122 if (GRAPHICS_VER(i915) >= 8) 3123 srm++; 3124 3125 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3126 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3127 count++; 3128 } 3129 3130 cs = intel_ring_begin(rq, 4 * count); 3131 if (IS_ERR(cs)) 3132 return PTR_ERR(cs); 3133 3134 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3135 u32 offset = i915_mmio_reg_offset(wa->reg); 3136 3137 if (mcr_range(i915, offset)) 3138 continue; 3139 3140 *cs++ = srm; 3141 *cs++ = offset; 3142 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3143 *cs++ = 0; 3144 } 3145 intel_ring_advance(rq, cs); 3146 3147 return 0; 3148 } 3149 3150 static int engine_wa_list_verify(struct intel_context *ce, 3151 const struct i915_wa_list * const wal, 3152 const char *from) 3153 { 3154 const struct i915_wa *wa; 3155 struct i915_request *rq; 3156 struct i915_vma *vma; 3157 struct i915_gem_ww_ctx ww; 3158 unsigned int i; 3159 u32 *results; 3160 int err; 3161 3162 if (!wal->count) 3163 return 0; 3164 3165 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3166 wal->count * sizeof(u32)); 3167 if (IS_ERR(vma)) 3168 return PTR_ERR(vma); 3169 3170 intel_engine_pm_get(ce->engine); 3171 i915_gem_ww_ctx_init(&ww, false); 3172 retry: 3173 err = i915_gem_object_lock(vma->obj, &ww); 3174 if (err == 0) 3175 err = intel_context_pin_ww(ce, &ww); 3176 if (err) 3177 goto err_pm; 3178 3179 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3180 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3181 if (err) 3182 goto err_unpin; 3183 3184 rq = i915_request_create(ce); 3185 if (IS_ERR(rq)) { 3186 err = PTR_ERR(rq); 3187 goto err_vma; 3188 } 3189 3190 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3191 if (err == 0) 3192 err = wa_list_srm(rq, wal, vma); 3193 3194 i915_request_get(rq); 3195 if (err) 3196 i915_request_set_error_once(rq, err); 3197 i915_request_add(rq); 3198 3199 if (err) 3200 goto err_rq; 3201 3202 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3203 err = -ETIME; 3204 goto err_rq; 3205 } 3206 3207 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3208 if (IS_ERR(results)) { 3209 err = PTR_ERR(results); 3210 goto err_rq; 3211 } 3212 3213 err = 0; 3214 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3215 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3216 continue; 3217 3218 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3219 err = -ENXIO; 3220 } 3221 3222 i915_gem_object_unpin_map(vma->obj); 3223 3224 err_rq: 3225 i915_request_put(rq); 3226 err_vma: 3227 i915_vma_unpin(vma); 3228 err_unpin: 3229 intel_context_unpin(ce); 3230 err_pm: 3231 if (err == -EDEADLK) { 3232 err = i915_gem_ww_ctx_backoff(&ww); 3233 if (!err) 3234 goto retry; 3235 } 3236 i915_gem_ww_ctx_fini(&ww); 3237 intel_engine_pm_put(ce->engine); 3238 i915_vma_put(vma); 3239 return err; 3240 } 3241 3242 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3243 const char *from) 3244 { 3245 return engine_wa_list_verify(engine->kernel_context, 3246 &engine->wa_list, 3247 from); 3248 } 3249 3250 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3251 #include "selftest_workarounds.c" 3252 #endif 3253