1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_gpu_commands.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) { 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 kfree(wal->list); 106 } 107 108 wal->list = list; 109 } 110 111 while (start < end) { 112 unsigned int mid = start + (end - start) / 2; 113 114 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 115 start = mid + 1; 116 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 117 end = mid; 118 } else { 119 wa_ = &wal->list[mid]; 120 121 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 122 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 123 i915_mmio_reg_offset(wa_->reg), 124 wa_->clr, wa_->set); 125 126 wa_->set &= ~wa->clr; 127 } 128 129 wal->wa_count++; 130 wa_->set |= wa->set; 131 wa_->clr |= wa->clr; 132 wa_->read |= wa->read; 133 return; 134 } 135 } 136 137 wal->wa_count++; 138 wa_ = &wal->list[wal->count++]; 139 *wa_ = *wa; 140 141 while (wa_-- > wal->list) { 142 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 143 i915_mmio_reg_offset(wa_[1].reg)); 144 if (i915_mmio_reg_offset(wa_[1].reg) > 145 i915_mmio_reg_offset(wa_[0].reg)) 146 break; 147 148 swap(wa_[1], wa_[0]); 149 } 150 } 151 152 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 153 u32 clear, u32 set, u32 read_mask, bool masked_reg) 154 { 155 struct i915_wa wa = { 156 .reg = reg, 157 .clr = clear, 158 .set = set, 159 .read = read_mask, 160 .masked_reg = masked_reg, 161 }; 162 163 _wa_add(wal, &wa); 164 } 165 166 static void 167 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 168 { 169 wa_add(wal, reg, clear, set, clear, false); 170 } 171 172 static void 173 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 174 { 175 wa_write_clr_set(wal, reg, ~0, set); 176 } 177 178 static void 179 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 180 { 181 wa_write_clr_set(wal, reg, set, set); 182 } 183 184 static void 185 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 186 { 187 wa_write_clr_set(wal, reg, clr, 0); 188 } 189 190 /* 191 * WA operations on "masked register". A masked register has the upper 16 bits 192 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 193 * portion of the register without a rmw: you simply write in the upper 16 bits 194 * the mask of bits you are going to modify. 195 * 196 * The wa_masked_* family of functions already does the necessary operations to 197 * calculate the mask based on the parameters passed, so user only has to 198 * provide the lower 16 bits of that register. 199 */ 200 201 static void 202 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 203 { 204 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 205 } 206 207 static void 208 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 209 { 210 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 211 } 212 213 static void 214 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 215 u32 mask, u32 val) 216 { 217 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 218 } 219 220 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 221 struct i915_wa_list *wal) 222 { 223 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 224 } 225 226 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 227 struct i915_wa_list *wal) 228 { 229 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 230 } 231 232 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 233 struct i915_wa_list *wal) 234 { 235 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 236 237 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 238 wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE); 239 240 /* WaDisablePartialInstShootdown:bdw,chv */ 241 wa_masked_en(wal, GEN8_ROW_CHICKEN, 242 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 243 244 /* Use Force Non-Coherent whenever executing a 3D context. This is a 245 * workaround for a possible hang in the unlikely event a TLB 246 * invalidation occurs during a PSD flush. 247 */ 248 /* WaForceEnableNonCoherent:bdw,chv */ 249 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 250 wa_masked_en(wal, HDC_CHICKEN0, 251 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 252 HDC_FORCE_NON_COHERENT); 253 254 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 255 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 256 * polygons in the same 8x4 pixel/sample area to be processed without 257 * stalling waiting for the earlier ones to write to Hierarchical Z 258 * buffer." 259 * 260 * This optimization is off by default for BDW and CHV; turn it on. 261 */ 262 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 263 264 /* Wa4x4STCOptimizationDisable:bdw,chv */ 265 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 266 267 /* 268 * BSpec recommends 8x4 when MSAA is used, 269 * however in practice 16x4 seems fastest. 270 * 271 * Note that PS/WM thread counts depend on the WIZ hashing 272 * disable bit, which we don't touch here, but it's good 273 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 274 */ 275 wa_masked_field_set(wal, GEN7_GT_MODE, 276 GEN6_WIZ_HASHING_MASK, 277 GEN6_WIZ_HASHING_16x4); 278 } 279 280 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 281 struct i915_wa_list *wal) 282 { 283 struct drm_i915_private *i915 = engine->i915; 284 285 gen8_ctx_workarounds_init(engine, wal); 286 287 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 288 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 289 290 /* WaDisableDopClockGating:bdw 291 * 292 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 293 * to disable EUTC clock gating. 294 */ 295 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 296 DOP_CLOCK_GATING_DISABLE); 297 298 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 299 GEN8_SAMPLER_POWER_BYPASS_DIS); 300 301 wa_masked_en(wal, HDC_CHICKEN0, 302 /* WaForceContextSaveRestoreNonCoherent:bdw */ 303 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 304 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 305 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 306 } 307 308 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 309 struct i915_wa_list *wal) 310 { 311 gen8_ctx_workarounds_init(engine, wal); 312 313 /* WaDisableThreadStallDopClockGating:chv */ 314 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 315 316 /* Improve HiZ throughput on CHV. */ 317 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 318 } 319 320 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 321 struct i915_wa_list *wal) 322 { 323 struct drm_i915_private *i915 = engine->i915; 324 325 if (HAS_LLC(i915)) { 326 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 327 * 328 * Must match Display Engine. See 329 * WaCompressedResourceDisplayNewHashMode. 330 */ 331 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 332 GEN9_PBE_COMPRESSED_HASH_SELECTION); 333 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 334 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 335 } 336 337 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 338 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 339 wa_masked_en(wal, GEN8_ROW_CHICKEN, 340 FLOW_CONTROL_ENABLE | 341 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 342 343 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 344 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 345 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 346 GEN9_ENABLE_YV12_BUGFIX | 347 GEN9_ENABLE_GPGPU_PREEMPTION); 348 349 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 350 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 351 wa_masked_en(wal, CACHE_MODE_1, 352 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 353 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 354 355 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 356 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 357 GEN9_CCS_TLB_PREFETCH_ENABLE); 358 359 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 360 wa_masked_en(wal, HDC_CHICKEN0, 361 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 362 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 363 364 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 365 * both tied to WaForceContextSaveRestoreNonCoherent 366 * in some hsds for skl. We keep the tie for all gen9. The 367 * documentation is a bit hazy and so we want to get common behaviour, 368 * even though there is no clear evidence we would need both on kbl/bxt. 369 * This area has been source of system hangs so we play it safe 370 * and mimic the skl regardless of what bspec says. 371 * 372 * Use Force Non-Coherent whenever executing a 3D context. This 373 * is a workaround for a possible hang in the unlikely event 374 * a TLB invalidation occurs during a PSD flush. 375 */ 376 377 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 378 wa_masked_en(wal, HDC_CHICKEN0, 379 HDC_FORCE_NON_COHERENT); 380 381 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 382 if (IS_SKYLAKE(i915) || 383 IS_KABYLAKE(i915) || 384 IS_COFFEELAKE(i915) || 385 IS_COMETLAKE(i915)) 386 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 387 GEN8_SAMPLER_POWER_BYPASS_DIS); 388 389 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 390 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 391 392 /* 393 * Supporting preemption with fine-granularity requires changes in the 394 * batch buffer programming. Since we can't break old userspace, we 395 * need to set our default preemption level to safe value. Userspace is 396 * still able to use more fine-grained preemption levels, since in 397 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 398 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 399 * not real HW workarounds, but merely a way to start using preemption 400 * while maintaining old contract with userspace. 401 */ 402 403 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 404 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 405 406 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 407 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 408 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 409 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 410 411 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 412 if (IS_GEN9_LP(i915)) 413 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 414 } 415 416 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 417 struct i915_wa_list *wal) 418 { 419 struct intel_gt *gt = engine->gt; 420 u8 vals[3] = { 0, 0, 0 }; 421 unsigned int i; 422 423 for (i = 0; i < 3; i++) { 424 u8 ss; 425 426 /* 427 * Only consider slices where one, and only one, subslice has 7 428 * EUs 429 */ 430 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 431 continue; 432 433 /* 434 * subslice_7eu[i] != 0 (because of the check above) and 435 * ss_max == 4 (maximum number of subslices possible per slice) 436 * 437 * -> 0 <= ss <= 3; 438 */ 439 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 440 vals[i] = 3 - ss; 441 } 442 443 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 444 return; 445 446 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 447 wa_masked_field_set(wal, GEN7_GT_MODE, 448 GEN9_IZ_HASHING_MASK(2) | 449 GEN9_IZ_HASHING_MASK(1) | 450 GEN9_IZ_HASHING_MASK(0), 451 GEN9_IZ_HASHING(2, vals[2]) | 452 GEN9_IZ_HASHING(1, vals[1]) | 453 GEN9_IZ_HASHING(0, vals[0])); 454 } 455 456 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 457 struct i915_wa_list *wal) 458 { 459 gen9_ctx_workarounds_init(engine, wal); 460 skl_tune_iz_hashing(engine, wal); 461 } 462 463 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 464 struct i915_wa_list *wal) 465 { 466 gen9_ctx_workarounds_init(engine, wal); 467 468 /* WaDisableThreadStallDopClockGating:bxt */ 469 wa_masked_en(wal, GEN8_ROW_CHICKEN, 470 STALL_DOP_GATING_DISABLE); 471 472 /* WaToEnableHwFixForPushConstHWBug:bxt */ 473 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 474 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 475 } 476 477 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 478 struct i915_wa_list *wal) 479 { 480 struct drm_i915_private *i915 = engine->i915; 481 482 gen9_ctx_workarounds_init(engine, wal); 483 484 /* WaToEnableHwFixForPushConstHWBug:kbl */ 485 if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER)) 486 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 487 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 488 489 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 490 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 491 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 492 } 493 494 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 495 struct i915_wa_list *wal) 496 { 497 gen9_ctx_workarounds_init(engine, wal); 498 499 /* WaToEnableHwFixForPushConstHWBug:glk */ 500 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 501 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 502 } 503 504 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 505 struct i915_wa_list *wal) 506 { 507 gen9_ctx_workarounds_init(engine, wal); 508 509 /* WaToEnableHwFixForPushConstHWBug:cfl */ 510 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 511 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 512 513 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 514 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 515 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 516 } 517 518 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 522 wa_write(wal, 523 GEN8_L3CNTLREG, 524 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 525 GEN8_ERRDETBCTRL); 526 527 /* WaForceEnableNonCoherent:icl 528 * This is not the same workaround as in early Gen9 platforms, where 529 * lacking this could cause system hangs, but coherency performance 530 * overhead is high and only a few compute workloads really need it 531 * (the register is whitelisted in hardware now, so UMDs can opt in 532 * for coherency if they have a good reason). 533 */ 534 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 535 536 /* WaEnableFloatBlendOptimization:icl */ 537 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 538 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 539 0 /* write-only, so skip validation */, 540 true); 541 542 /* WaDisableGPGPUMidThreadPreemption:icl */ 543 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 544 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 545 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 546 547 /* allow headerless messages for preemptible GPGPU context */ 548 wa_masked_en(wal, GEN10_SAMPLER_MODE, 549 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 550 551 /* Wa_1604278689:icl,ehl */ 552 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 553 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 554 0, /* write-only register; skip validation */ 555 0xFFFFFFFF); 556 557 /* Wa_1406306137:icl,ehl */ 558 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 559 } 560 561 /* 562 * These settings aren't actually workarounds, but general tuning settings that 563 * need to be programmed on several platforms. 564 */ 565 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 566 struct i915_wa_list *wal) 567 { 568 /* 569 * Although some platforms refer to it as Wa_1604555607, we need to 570 * program it even on those that don't explicitly list that 571 * workaround. 572 * 573 * Note that the programming of this register is further modified 574 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 575 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 576 * value when read. The default value for this register is zero for all 577 * fields and there are no bit masks. So instead of doing a RMW we 578 * should just write TDS timer value. For the same reason read 579 * verification is ignored. 580 */ 581 wa_add(wal, 582 FF_MODE2, 583 FF_MODE2_TDS_TIMER_MASK, 584 FF_MODE2_TDS_TIMER_128, 585 0, false); 586 } 587 588 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 589 struct i915_wa_list *wal) 590 { 591 gen12_ctx_gt_tuning_init(engine, wal); 592 593 /* 594 * Wa_1409142259:tgl,dg1,adl-p 595 * Wa_1409347922:tgl,dg1,adl-p 596 * Wa_1409252684:tgl,dg1,adl-p 597 * Wa_1409217633:tgl,dg1,adl-p 598 * Wa_1409207793:tgl,dg1,adl-p 599 * Wa_1409178076:tgl,dg1,adl-p 600 * Wa_1408979724:tgl,dg1,adl-p 601 * Wa_14010443199:tgl,rkl,dg1,adl-p 602 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 603 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 604 */ 605 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 606 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 607 608 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 609 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 610 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 611 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 612 613 /* 614 * Wa_16011163337 615 * 616 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 617 * to Wa_1608008084. 618 */ 619 wa_add(wal, 620 FF_MODE2, 621 FF_MODE2_GS_TIMER_MASK, 622 FF_MODE2_GS_TIMER_224, 623 0, false); 624 625 /* 626 * Wa_14012131227:dg1 627 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 628 */ 629 wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, 630 GEN9_RHWO_OPTIMIZATION_DISABLE); 631 } 632 633 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 634 struct i915_wa_list *wal) 635 { 636 gen12_ctx_workarounds_init(engine, wal); 637 638 /* Wa_1409044764 */ 639 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 640 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 641 642 /* Wa_22010493298 */ 643 wa_masked_en(wal, HIZ_CHICKEN, 644 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 645 } 646 647 static void 648 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 649 struct i915_wa_list *wal, 650 const char *name) 651 { 652 struct drm_i915_private *i915 = engine->i915; 653 654 if (engine->class != RENDER_CLASS) 655 return; 656 657 wa_init_start(wal, name, engine->name); 658 659 if (IS_DG1(i915)) 660 dg1_ctx_workarounds_init(engine, wal); 661 else if (GRAPHICS_VER(i915) == 12) 662 gen12_ctx_workarounds_init(engine, wal); 663 else if (GRAPHICS_VER(i915) == 11) 664 icl_ctx_workarounds_init(engine, wal); 665 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 666 cfl_ctx_workarounds_init(engine, wal); 667 else if (IS_GEMINILAKE(i915)) 668 glk_ctx_workarounds_init(engine, wal); 669 else if (IS_KABYLAKE(i915)) 670 kbl_ctx_workarounds_init(engine, wal); 671 else if (IS_BROXTON(i915)) 672 bxt_ctx_workarounds_init(engine, wal); 673 else if (IS_SKYLAKE(i915)) 674 skl_ctx_workarounds_init(engine, wal); 675 else if (IS_CHERRYVIEW(i915)) 676 chv_ctx_workarounds_init(engine, wal); 677 else if (IS_BROADWELL(i915)) 678 bdw_ctx_workarounds_init(engine, wal); 679 else if (GRAPHICS_VER(i915) == 7) 680 gen7_ctx_workarounds_init(engine, wal); 681 else if (GRAPHICS_VER(i915) == 6) 682 gen6_ctx_workarounds_init(engine, wal); 683 else if (GRAPHICS_VER(i915) < 8) 684 ; 685 else 686 MISSING_CASE(GRAPHICS_VER(i915)); 687 688 wa_init_finish(wal); 689 } 690 691 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 692 { 693 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 694 } 695 696 int intel_engine_emit_ctx_wa(struct i915_request *rq) 697 { 698 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 699 struct i915_wa *wa; 700 unsigned int i; 701 u32 *cs; 702 int ret; 703 704 if (wal->count == 0) 705 return 0; 706 707 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 708 if (ret) 709 return ret; 710 711 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 712 if (IS_ERR(cs)) 713 return PTR_ERR(cs); 714 715 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 716 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 717 *cs++ = i915_mmio_reg_offset(wa->reg); 718 *cs++ = wa->set; 719 } 720 *cs++ = MI_NOOP; 721 722 intel_ring_advance(rq, cs); 723 724 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 725 if (ret) 726 return ret; 727 728 return 0; 729 } 730 731 static void 732 gen4_gt_workarounds_init(struct drm_i915_private *i915, 733 struct i915_wa_list *wal) 734 { 735 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 736 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 737 } 738 739 static void 740 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 741 { 742 gen4_gt_workarounds_init(i915, wal); 743 744 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 745 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 746 } 747 748 static void 749 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 750 { 751 g4x_gt_workarounds_init(i915, wal); 752 753 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 754 } 755 756 static void 757 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 758 { 759 } 760 761 static void 762 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 763 { 764 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 765 wa_masked_dis(wal, 766 GEN7_COMMON_SLICE_CHICKEN1, 767 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 768 769 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 770 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 771 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 772 773 /* WaForceL3Serialization:ivb */ 774 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 775 } 776 777 static void 778 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 779 { 780 /* WaForceL3Serialization:vlv */ 781 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 782 783 /* 784 * WaIncreaseL3CreditsForVLVB0:vlv 785 * This is the hardware default actually. 786 */ 787 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 788 } 789 790 static void 791 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 792 { 793 /* L3 caching of data atomics doesn't work -- disable it. */ 794 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 795 796 wa_add(wal, 797 HSW_ROW_CHICKEN3, 0, 798 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 799 0 /* XXX does this reg exist? */, true); 800 801 /* WaVSRefCountFullforceMissDisable:hsw */ 802 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 803 } 804 805 static void 806 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 807 { 808 /* WaDisableKillLogic:bxt,skl,kbl */ 809 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 810 wa_write_or(wal, 811 GAM_ECOCHK, 812 ECOCHK_DIS_TLB); 813 814 if (HAS_LLC(i915)) { 815 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 816 * 817 * Must match Display Engine. See 818 * WaCompressedResourceDisplayNewHashMode. 819 */ 820 wa_write_or(wal, 821 MMCD_MISC_CTRL, 822 MMCD_PCLA | MMCD_HOTSPOT_EN); 823 } 824 825 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 826 wa_write_or(wal, 827 GAM_ECOCHK, 828 BDW_DISABLE_HDC_INVALIDATION); 829 } 830 831 static void 832 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 833 { 834 gen9_gt_workarounds_init(i915, wal); 835 836 /* WaDisableGafsUnitClkGating:skl */ 837 wa_write_or(wal, 838 GEN7_UCGCTL4, 839 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 840 841 /* WaInPlaceDecompressionHang:skl */ 842 if (IS_SKL_GT_STEP(i915, STEP_A0, STEP_H0)) 843 wa_write_or(wal, 844 GEN9_GAMT_ECO_REG_RW_IA, 845 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 846 } 847 848 static void 849 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 850 { 851 gen9_gt_workarounds_init(i915, wal); 852 853 /* WaDisableDynamicCreditSharing:kbl */ 854 if (IS_KBL_GT_STEP(i915, 0, STEP_C0)) 855 wa_write_or(wal, 856 GAMT_CHKN_BIT_REG, 857 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 858 859 /* WaDisableGafsUnitClkGating:kbl */ 860 wa_write_or(wal, 861 GEN7_UCGCTL4, 862 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 863 864 /* WaInPlaceDecompressionHang:kbl */ 865 wa_write_or(wal, 866 GEN9_GAMT_ECO_REG_RW_IA, 867 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 868 } 869 870 static void 871 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 872 { 873 gen9_gt_workarounds_init(i915, wal); 874 } 875 876 static void 877 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 878 { 879 gen9_gt_workarounds_init(i915, wal); 880 881 /* WaDisableGafsUnitClkGating:cfl */ 882 wa_write_or(wal, 883 GEN7_UCGCTL4, 884 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 885 886 /* WaInPlaceDecompressionHang:cfl */ 887 wa_write_or(wal, 888 GEN9_GAMT_ECO_REG_RW_IA, 889 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 890 } 891 892 static void __set_mcr_steering(struct i915_wa_list *wal, 893 i915_reg_t steering_reg, 894 unsigned int slice, unsigned int subslice) 895 { 896 u32 mcr, mcr_mask; 897 898 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 899 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 900 901 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 902 } 903 904 static void __add_mcr_wa(struct drm_i915_private *i915, struct i915_wa_list *wal, 905 unsigned int slice, unsigned int subslice) 906 { 907 drm_dbg(&i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); 908 909 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 910 } 911 912 static void 913 icl_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 914 { 915 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; 916 unsigned int slice, subslice; 917 918 GEM_BUG_ON(GRAPHICS_VER(i915) < 11); 919 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 920 slice = 0; 921 922 /* 923 * Although a platform may have subslices, we need to always steer 924 * reads to the lowest instance that isn't fused off. When Render 925 * Power Gating is enabled, grabbing forcewake will only power up a 926 * single subslice (the "minconfig") if there isn't a real workload 927 * that needs to be run; this means that if we steer register reads to 928 * one of the higher subslices, we run the risk of reading back 0's or 929 * random garbage. 930 */ 931 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); 932 933 /* 934 * If the subslice we picked above also steers us to a valid L3 bank, 935 * then we can just rely on the default steering and won't need to 936 * worry about explicitly re-steering L3BANK reads later. 937 */ 938 if (i915->gt.info.l3bank_mask & BIT(subslice)) 939 i915->gt.steering_table[L3BANK] = NULL; 940 941 __add_mcr_wa(i915, wal, slice, subslice); 942 } 943 944 static void 945 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 946 { 947 struct drm_i915_private *i915 = gt->i915; 948 const struct sseu_dev_info *sseu = >->info.sseu; 949 unsigned long slice, subslice = 0, slice_mask = 0; 950 u64 dss_mask = 0; 951 u32 lncf_mask = 0; 952 int i; 953 954 /* 955 * On Xe_HP the steering increases in complexity. There are now several 956 * more units that require steering and we're not guaranteed to be able 957 * to find a common setting for all of them. These are: 958 * - GSLICE (fusable) 959 * - DSS (sub-unit within gslice; fusable) 960 * - L3 Bank (fusable) 961 * - MSLICE (fusable) 962 * - LNCF (sub-unit within mslice; always present if mslice is present) 963 * 964 * We'll do our default/implicit steering based on GSLICE (in the 965 * sliceid field) and DSS (in the subsliceid field). If we can 966 * find overlap between the valid MSLICE and/or LNCF values with 967 * a suitable GSLICE, then we can just re-use the default value and 968 * skip and explicit steering at runtime. 969 * 970 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 971 * a valid sliceid value. DSS steering is the only type of steering 972 * that utilizes the 'subsliceid' bits. 973 * 974 * Also note that, even though the steering domain is called "GSlice" 975 * and it is encoded in the register using the gslice format, the spec 976 * says that the combined (geometry | compute) fuse should be used to 977 * select the steering. 978 */ 979 980 /* Find the potential gslice candidates */ 981 dss_mask = intel_sseu_get_subslices(sseu, 0); 982 slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE); 983 984 /* 985 * Find the potential LNCF candidates. Either LNCF within a valid 986 * mslice is fine. 987 */ 988 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 989 lncf_mask |= (0x3 << (i * 2)); 990 991 /* 992 * Are there any sliceid values that work for both GSLICE and LNCF 993 * steering? 994 */ 995 if (slice_mask & lncf_mask) { 996 slice_mask &= lncf_mask; 997 gt->steering_table[LNCF] = NULL; 998 } 999 1000 /* How about sliceid values that also work for MSLICE steering? */ 1001 if (slice_mask & gt->info.mslice_mask) { 1002 slice_mask &= gt->info.mslice_mask; 1003 gt->steering_table[MSLICE] = NULL; 1004 } 1005 1006 slice = __ffs(slice_mask); 1007 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); 1008 WARN_ON(subslice > GEN_DSS_PER_GSLICE); 1009 WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); 1010 1011 __add_mcr_wa(i915, wal, slice, subslice); 1012 1013 /* 1014 * SQIDI ranges are special because they use different steering 1015 * registers than everything else we work with. On XeHP SDV and 1016 * DG2-G10, any value in the steering registers will work fine since 1017 * all instances are present, but DG2-G11 only has SQIDI instances at 1018 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1019 * we'll just steer to a hardcoded "2" since that value will work 1020 * everywhere. 1021 */ 1022 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1023 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1024 } 1025 1026 static void 1027 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1028 { 1029 icl_wa_init_mcr(i915, wal); 1030 1031 /* WaModifyGamTlbPartitioning:icl */ 1032 wa_write_clr_set(wal, 1033 GEN11_GACB_PERF_CTRL, 1034 GEN11_HASH_CTRL_MASK, 1035 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1036 1037 /* Wa_1405766107:icl 1038 * Formerly known as WaCL2SFHalfMaxAlloc 1039 */ 1040 wa_write_or(wal, 1041 GEN11_LSN_UNSLCVC, 1042 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1043 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1044 1045 /* Wa_220166154:icl 1046 * Formerly known as WaDisCtxReload 1047 */ 1048 wa_write_or(wal, 1049 GEN8_GAMW_ECO_DEV_RW_IA, 1050 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1051 1052 /* Wa_1406463099:icl 1053 * Formerly known as WaGamTlbPendError 1054 */ 1055 wa_write_or(wal, 1056 GAMT_CHKN_BIT_REG, 1057 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1058 1059 /* Wa_1607087056:icl,ehl,jsl */ 1060 if (IS_ICELAKE(i915) || 1061 IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0)) 1062 wa_write_or(wal, 1063 SLICE_UNIT_LEVEL_CLKGATE, 1064 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1065 1066 /* 1067 * This is not a documented workaround, but rather an optimization 1068 * to reduce sampler power. 1069 */ 1070 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1071 } 1072 1073 /* 1074 * Though there are per-engine instances of these registers, 1075 * they retain their value through engine resets and should 1076 * only be provided on the GT workaround list rather than 1077 * the engine-specific workaround list. 1078 */ 1079 static void 1080 wa_14011060649(struct drm_i915_private *i915, struct i915_wa_list *wal) 1081 { 1082 struct intel_engine_cs *engine; 1083 struct intel_gt *gt = &i915->gt; 1084 int id; 1085 1086 for_each_engine(engine, gt, id) { 1087 if (engine->class != VIDEO_DECODE_CLASS || 1088 (engine->instance % 2)) 1089 continue; 1090 1091 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1092 IECPUNIT_CLKGATE_DIS); 1093 } 1094 } 1095 1096 static void 1097 gen12_gt_workarounds_init(struct drm_i915_private *i915, 1098 struct i915_wa_list *wal) 1099 { 1100 icl_wa_init_mcr(i915, wal); 1101 1102 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1103 wa_14011060649(i915, wal); 1104 1105 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1106 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1107 } 1108 1109 static void 1110 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1111 { 1112 gen12_gt_workarounds_init(i915, wal); 1113 1114 /* Wa_1409420604:tgl */ 1115 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1116 wa_write_or(wal, 1117 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1118 CPSSUNIT_CLKGATE_DIS); 1119 1120 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1121 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1122 wa_write_or(wal, 1123 SLICE_UNIT_LEVEL_CLKGATE, 1124 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1125 1126 /* Wa_1408615072:tgl[a0] */ 1127 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1128 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1129 VSUNIT_CLKGATE_DIS_TGL); 1130 } 1131 1132 static void 1133 dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1134 { 1135 gen12_gt_workarounds_init(i915, wal); 1136 1137 /* Wa_1607087056:dg1 */ 1138 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0)) 1139 wa_write_or(wal, 1140 SLICE_UNIT_LEVEL_CLKGATE, 1141 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1142 1143 /* Wa_1409420604:dg1 */ 1144 if (IS_DG1(i915)) 1145 wa_write_or(wal, 1146 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1147 CPSSUNIT_CLKGATE_DIS); 1148 1149 /* Wa_1408615072:dg1 */ 1150 /* Empirical testing shows this register is unaffected by engine reset. */ 1151 if (IS_DG1(i915)) 1152 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1153 VSUNIT_CLKGATE_DIS_TGL); 1154 } 1155 1156 static void 1157 xehpsdv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1158 { 1159 xehp_init_mcr(&i915->gt, wal); 1160 } 1161 1162 static void 1163 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1164 { 1165 if (IS_XEHPSDV(i915)) 1166 xehpsdv_gt_workarounds_init(i915, wal); 1167 else if (IS_DG1(i915)) 1168 dg1_gt_workarounds_init(i915, wal); 1169 else if (IS_TIGERLAKE(i915)) 1170 tgl_gt_workarounds_init(i915, wal); 1171 else if (GRAPHICS_VER(i915) == 12) 1172 gen12_gt_workarounds_init(i915, wal); 1173 else if (GRAPHICS_VER(i915) == 11) 1174 icl_gt_workarounds_init(i915, wal); 1175 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1176 cfl_gt_workarounds_init(i915, wal); 1177 else if (IS_GEMINILAKE(i915)) 1178 glk_gt_workarounds_init(i915, wal); 1179 else if (IS_KABYLAKE(i915)) 1180 kbl_gt_workarounds_init(i915, wal); 1181 else if (IS_BROXTON(i915)) 1182 gen9_gt_workarounds_init(i915, wal); 1183 else if (IS_SKYLAKE(i915)) 1184 skl_gt_workarounds_init(i915, wal); 1185 else if (IS_HASWELL(i915)) 1186 hsw_gt_workarounds_init(i915, wal); 1187 else if (IS_VALLEYVIEW(i915)) 1188 vlv_gt_workarounds_init(i915, wal); 1189 else if (IS_IVYBRIDGE(i915)) 1190 ivb_gt_workarounds_init(i915, wal); 1191 else if (GRAPHICS_VER(i915) == 6) 1192 snb_gt_workarounds_init(i915, wal); 1193 else if (GRAPHICS_VER(i915) == 5) 1194 ilk_gt_workarounds_init(i915, wal); 1195 else if (IS_G4X(i915)) 1196 g4x_gt_workarounds_init(i915, wal); 1197 else if (GRAPHICS_VER(i915) == 4) 1198 gen4_gt_workarounds_init(i915, wal); 1199 else if (GRAPHICS_VER(i915) <= 8) 1200 ; 1201 else 1202 MISSING_CASE(GRAPHICS_VER(i915)); 1203 } 1204 1205 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1206 { 1207 struct i915_wa_list *wal = &i915->gt_wa_list; 1208 1209 wa_init_start(wal, "GT", "global"); 1210 gt_init_workarounds(i915, wal); 1211 wa_init_finish(wal); 1212 } 1213 1214 static enum forcewake_domains 1215 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1216 { 1217 enum forcewake_domains fw = 0; 1218 struct i915_wa *wa; 1219 unsigned int i; 1220 1221 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1222 fw |= intel_uncore_forcewake_for_reg(uncore, 1223 wa->reg, 1224 FW_REG_READ | 1225 FW_REG_WRITE); 1226 1227 return fw; 1228 } 1229 1230 static bool 1231 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1232 { 1233 if ((cur ^ wa->set) & wa->read) { 1234 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1235 name, from, i915_mmio_reg_offset(wa->reg), 1236 cur, cur & wa->read, wa->set & wa->read); 1237 1238 return false; 1239 } 1240 1241 return true; 1242 } 1243 1244 static void 1245 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1246 { 1247 struct intel_uncore *uncore = gt->uncore; 1248 enum forcewake_domains fw; 1249 unsigned long flags; 1250 struct i915_wa *wa; 1251 unsigned int i; 1252 1253 if (!wal->count) 1254 return; 1255 1256 fw = wal_get_fw_for_rmw(uncore, wal); 1257 1258 spin_lock_irqsave(&uncore->lock, flags); 1259 intel_uncore_forcewake_get__locked(uncore, fw); 1260 1261 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1262 u32 val, old = 0; 1263 1264 /* open-coded rmw due to steering */ 1265 old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; 1266 val = (old & ~wa->clr) | wa->set; 1267 if (val != old || !wa->clr) 1268 intel_uncore_write_fw(uncore, wa->reg, val); 1269 1270 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1271 wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), 1272 wal->name, "application"); 1273 } 1274 1275 intel_uncore_forcewake_put__locked(uncore, fw); 1276 spin_unlock_irqrestore(&uncore->lock, flags); 1277 } 1278 1279 void intel_gt_apply_workarounds(struct intel_gt *gt) 1280 { 1281 wa_list_apply(gt, >->i915->gt_wa_list); 1282 } 1283 1284 static bool wa_list_verify(struct intel_gt *gt, 1285 const struct i915_wa_list *wal, 1286 const char *from) 1287 { 1288 struct intel_uncore *uncore = gt->uncore; 1289 struct i915_wa *wa; 1290 enum forcewake_domains fw; 1291 unsigned long flags; 1292 unsigned int i; 1293 bool ok = true; 1294 1295 fw = wal_get_fw_for_rmw(uncore, wal); 1296 1297 spin_lock_irqsave(&uncore->lock, flags); 1298 intel_uncore_forcewake_get__locked(uncore, fw); 1299 1300 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1301 ok &= wa_verify(wa, 1302 intel_gt_read_register_fw(gt, wa->reg), 1303 wal->name, from); 1304 1305 intel_uncore_forcewake_put__locked(uncore, fw); 1306 spin_unlock_irqrestore(&uncore->lock, flags); 1307 1308 return ok; 1309 } 1310 1311 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1312 { 1313 return wa_list_verify(gt, >->i915->gt_wa_list, from); 1314 } 1315 1316 __maybe_unused 1317 static bool is_nonpriv_flags_valid(u32 flags) 1318 { 1319 /* Check only valid flag bits are set */ 1320 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1321 return false; 1322 1323 /* NB: Only 3 out of 4 enum values are valid for access field */ 1324 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1325 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1326 return false; 1327 1328 return true; 1329 } 1330 1331 static void 1332 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1333 { 1334 struct i915_wa wa = { 1335 .reg = reg 1336 }; 1337 1338 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1339 return; 1340 1341 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1342 return; 1343 1344 wa.reg.reg |= flags; 1345 _wa_add(wal, &wa); 1346 } 1347 1348 static void 1349 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1350 { 1351 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1352 } 1353 1354 static void gen9_whitelist_build(struct i915_wa_list *w) 1355 { 1356 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1357 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1358 1359 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1360 whitelist_reg(w, GEN8_CS_CHICKEN1); 1361 1362 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1363 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1364 1365 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1366 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1367 } 1368 1369 static void skl_whitelist_build(struct intel_engine_cs *engine) 1370 { 1371 struct i915_wa_list *w = &engine->whitelist; 1372 1373 if (engine->class != RENDER_CLASS) 1374 return; 1375 1376 gen9_whitelist_build(w); 1377 1378 /* WaDisableLSQCROPERFforOCL:skl */ 1379 whitelist_reg(w, GEN8_L3SQCREG4); 1380 } 1381 1382 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1383 { 1384 if (engine->class != RENDER_CLASS) 1385 return; 1386 1387 gen9_whitelist_build(&engine->whitelist); 1388 } 1389 1390 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1391 { 1392 struct i915_wa_list *w = &engine->whitelist; 1393 1394 if (engine->class != RENDER_CLASS) 1395 return; 1396 1397 gen9_whitelist_build(w); 1398 1399 /* WaDisableLSQCROPERFforOCL:kbl */ 1400 whitelist_reg(w, GEN8_L3SQCREG4); 1401 } 1402 1403 static void glk_whitelist_build(struct intel_engine_cs *engine) 1404 { 1405 struct i915_wa_list *w = &engine->whitelist; 1406 1407 if (engine->class != RENDER_CLASS) 1408 return; 1409 1410 gen9_whitelist_build(w); 1411 1412 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1413 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1414 } 1415 1416 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1417 { 1418 struct i915_wa_list *w = &engine->whitelist; 1419 1420 if (engine->class != RENDER_CLASS) 1421 return; 1422 1423 gen9_whitelist_build(w); 1424 1425 /* 1426 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1427 * 1428 * This covers 4 register which are next to one another : 1429 * - PS_INVOCATION_COUNT 1430 * - PS_INVOCATION_COUNT_UDW 1431 * - PS_DEPTH_COUNT 1432 * - PS_DEPTH_COUNT_UDW 1433 */ 1434 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1435 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1436 RING_FORCE_TO_NONPRIV_RANGE_4); 1437 } 1438 1439 static void cml_whitelist_build(struct intel_engine_cs *engine) 1440 { 1441 struct i915_wa_list *w = &engine->whitelist; 1442 1443 if (engine->class != RENDER_CLASS) 1444 whitelist_reg_ext(w, 1445 RING_CTX_TIMESTAMP(engine->mmio_base), 1446 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1447 1448 cfl_whitelist_build(engine); 1449 } 1450 1451 static void icl_whitelist_build(struct intel_engine_cs *engine) 1452 { 1453 struct i915_wa_list *w = &engine->whitelist; 1454 1455 switch (engine->class) { 1456 case RENDER_CLASS: 1457 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1458 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1459 1460 /* WaAllowUMDToModifySamplerMode:icl */ 1461 whitelist_reg(w, GEN10_SAMPLER_MODE); 1462 1463 /* WaEnableStateCacheRedirectToCS:icl */ 1464 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1465 1466 /* 1467 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1468 * 1469 * This covers 4 register which are next to one another : 1470 * - PS_INVOCATION_COUNT 1471 * - PS_INVOCATION_COUNT_UDW 1472 * - PS_DEPTH_COUNT 1473 * - PS_DEPTH_COUNT_UDW 1474 */ 1475 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1476 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1477 RING_FORCE_TO_NONPRIV_RANGE_4); 1478 break; 1479 1480 case VIDEO_DECODE_CLASS: 1481 /* hucStatusRegOffset */ 1482 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1483 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1484 /* hucUKernelHdrInfoRegOffset */ 1485 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1486 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1487 /* hucStatus2RegOffset */ 1488 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1489 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1490 whitelist_reg_ext(w, 1491 RING_CTX_TIMESTAMP(engine->mmio_base), 1492 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1493 break; 1494 1495 default: 1496 whitelist_reg_ext(w, 1497 RING_CTX_TIMESTAMP(engine->mmio_base), 1498 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1499 break; 1500 } 1501 } 1502 1503 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1504 { 1505 struct i915_wa_list *w = &engine->whitelist; 1506 1507 switch (engine->class) { 1508 case RENDER_CLASS: 1509 /* 1510 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1511 * Wa_1408556865:tgl 1512 * 1513 * This covers 4 registers which are next to one another : 1514 * - PS_INVOCATION_COUNT 1515 * - PS_INVOCATION_COUNT_UDW 1516 * - PS_DEPTH_COUNT 1517 * - PS_DEPTH_COUNT_UDW 1518 */ 1519 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1520 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1521 RING_FORCE_TO_NONPRIV_RANGE_4); 1522 1523 /* Wa_1808121037:tgl */ 1524 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1525 1526 /* Wa_1806527549:tgl */ 1527 whitelist_reg(w, HIZ_CHICKEN); 1528 break; 1529 default: 1530 whitelist_reg_ext(w, 1531 RING_CTX_TIMESTAMP(engine->mmio_base), 1532 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1533 break; 1534 } 1535 } 1536 1537 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1538 { 1539 struct i915_wa_list *w = &engine->whitelist; 1540 1541 tgl_whitelist_build(engine); 1542 1543 /* GEN:BUG:1409280441:dg1 */ 1544 if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) && 1545 (engine->class == RENDER_CLASS || 1546 engine->class == COPY_ENGINE_CLASS)) 1547 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1548 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1549 } 1550 1551 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1552 { 1553 struct drm_i915_private *i915 = engine->i915; 1554 struct i915_wa_list *w = &engine->whitelist; 1555 1556 wa_init_start(w, "whitelist", engine->name); 1557 1558 if (IS_DG1(i915)) 1559 dg1_whitelist_build(engine); 1560 else if (GRAPHICS_VER(i915) == 12) 1561 tgl_whitelist_build(engine); 1562 else if (GRAPHICS_VER(i915) == 11) 1563 icl_whitelist_build(engine); 1564 else if (IS_COMETLAKE(i915)) 1565 cml_whitelist_build(engine); 1566 else if (IS_COFFEELAKE(i915)) 1567 cfl_whitelist_build(engine); 1568 else if (IS_GEMINILAKE(i915)) 1569 glk_whitelist_build(engine); 1570 else if (IS_KABYLAKE(i915)) 1571 kbl_whitelist_build(engine); 1572 else if (IS_BROXTON(i915)) 1573 bxt_whitelist_build(engine); 1574 else if (IS_SKYLAKE(i915)) 1575 skl_whitelist_build(engine); 1576 else if (GRAPHICS_VER(i915) <= 8) 1577 ; 1578 else 1579 MISSING_CASE(GRAPHICS_VER(i915)); 1580 1581 wa_init_finish(w); 1582 } 1583 1584 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1585 { 1586 const struct i915_wa_list *wal = &engine->whitelist; 1587 struct intel_uncore *uncore = engine->uncore; 1588 const u32 base = engine->mmio_base; 1589 struct i915_wa *wa; 1590 unsigned int i; 1591 1592 if (!wal->count) 1593 return; 1594 1595 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1596 intel_uncore_write(uncore, 1597 RING_FORCE_TO_NONPRIV(base, i), 1598 i915_mmio_reg_offset(wa->reg)); 1599 1600 /* And clear the rest just in case of garbage */ 1601 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1602 intel_uncore_write(uncore, 1603 RING_FORCE_TO_NONPRIV(base, i), 1604 i915_mmio_reg_offset(RING_NOPID(base))); 1605 } 1606 1607 static void 1608 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1609 { 1610 struct drm_i915_private *i915 = engine->i915; 1611 1612 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1613 IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) { 1614 /* 1615 * Wa_1607138336:tgl[a0],dg1[a0] 1616 * Wa_1607063988:tgl[a0],dg1[a0] 1617 */ 1618 wa_write_or(wal, 1619 GEN9_CTX_PREEMPT_REG, 1620 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1621 } 1622 1623 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) { 1624 /* 1625 * Wa_1606679103:tgl 1626 * (see also Wa_1606682166:icl) 1627 */ 1628 wa_write_or(wal, 1629 GEN7_SARCHKMD, 1630 GEN7_DISABLE_SAMPLER_PREFETCH); 1631 } 1632 1633 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 1634 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1635 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 1636 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1637 1638 /* 1639 * Wa_1407928979:tgl A* 1640 * Wa_18011464164:tgl[B0+],dg1[B0+] 1641 * Wa_22010931296:tgl[B0+],dg1[B0+] 1642 * Wa_14010919138:rkl,dg1,adl-s,adl-p 1643 */ 1644 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1645 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1646 1647 /* 1648 * Wa_1606700617:tgl,dg1,adl-p 1649 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 1650 * Wa_14010826681:tgl,dg1,rkl,adl-p 1651 */ 1652 wa_masked_en(wal, 1653 GEN9_CS_DEBUG_MODE1, 1654 FF_DOP_CLOCK_GATE_DISABLE); 1655 } 1656 1657 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 1658 IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1659 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1660 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 1661 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1662 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1663 1664 /* 1665 * Wa_1409085225:tgl 1666 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 1667 */ 1668 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1669 } 1670 1671 1672 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1673 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1674 /* 1675 * Wa_1607030317:tgl 1676 * Wa_1607186500:tgl 1677 * Wa_1607297627:tgl,rkl,dg1[a0] 1678 * 1679 * On TGL and RKL there are multiple entries for this WA in the 1680 * BSpec; some indicate this is an A0-only WA, others indicate 1681 * it applies to all steppings so we trust the "all steppings." 1682 * For DG1 this only applies to A0. 1683 */ 1684 wa_masked_en(wal, 1685 GEN6_RC_SLEEP_PSMI_CONTROL, 1686 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1687 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1688 } 1689 1690 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 1691 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 1692 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 1693 wa_masked_en(wal, 1694 GEN10_SAMPLER_MODE, 1695 ENABLE_SMALLPL); 1696 } 1697 1698 if (GRAPHICS_VER(i915) == 11) { 1699 /* This is not an Wa. Enable for better image quality */ 1700 wa_masked_en(wal, 1701 _3D_CHICKEN3, 1702 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1703 1704 /* 1705 * Wa_1405543622:icl 1706 * Formerly known as WaGAPZPriorityScheme 1707 */ 1708 wa_write_or(wal, 1709 GEN8_GARBCNTL, 1710 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1711 1712 /* 1713 * Wa_1604223664:icl 1714 * Formerly known as WaL3BankAddressHashing 1715 */ 1716 wa_write_clr_set(wal, 1717 GEN8_GARBCNTL, 1718 GEN11_HASH_CTRL_EXCL_MASK, 1719 GEN11_HASH_CTRL_EXCL_BIT0); 1720 wa_write_clr_set(wal, 1721 GEN11_GLBLINVL, 1722 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1723 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1724 1725 /* 1726 * Wa_1405733216:icl 1727 * Formerly known as WaDisableCleanEvicts 1728 */ 1729 wa_write_or(wal, 1730 GEN8_L3SQCREG4, 1731 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1732 1733 /* Wa_1606682166:icl */ 1734 wa_write_or(wal, 1735 GEN7_SARCHKMD, 1736 GEN7_DISABLE_SAMPLER_PREFETCH); 1737 1738 /* Wa_1409178092:icl */ 1739 wa_write_clr_set(wal, 1740 GEN11_SCRATCH2, 1741 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1742 0); 1743 1744 /* WaEnable32PlaneMode:icl */ 1745 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1746 GEN11_ENABLE_32_PLANE_MODE); 1747 1748 /* 1749 * Wa_1408615072:icl,ehl (vsunit) 1750 * Wa_1407596294:icl,ehl (hsunit) 1751 */ 1752 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1753 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1754 1755 /* Wa_1407352427:icl,ehl */ 1756 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1757 PSDUNIT_CLKGATE_DIS); 1758 1759 /* Wa_1406680159:icl,ehl */ 1760 wa_write_or(wal, 1761 SUBSLICE_UNIT_LEVEL_CLKGATE, 1762 GWUNIT_CLKGATE_DIS); 1763 1764 /* 1765 * Wa_1408767742:icl[a2..forever],ehl[all] 1766 * Wa_1605460711:icl[a0..c0] 1767 */ 1768 wa_write_or(wal, 1769 GEN7_FF_THREAD_MODE, 1770 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1771 1772 /* Wa_22010271021 */ 1773 wa_masked_en(wal, 1774 GEN9_CS_DEBUG_MODE1, 1775 FF_DOP_CLOCK_GATE_DISABLE); 1776 } 1777 1778 if (IS_GRAPHICS_VER(i915, 9, 12)) { 1779 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1780 wa_masked_en(wal, 1781 GEN7_FF_SLICE_CS_CHICKEN1, 1782 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1783 } 1784 1785 if (IS_SKYLAKE(i915) || 1786 IS_KABYLAKE(i915) || 1787 IS_COFFEELAKE(i915) || 1788 IS_COMETLAKE(i915)) { 1789 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1790 wa_write_or(wal, 1791 GEN8_GARBCNTL, 1792 GEN9_GAPS_TSV_CREDIT_DISABLE); 1793 } 1794 1795 if (IS_BROXTON(i915)) { 1796 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1797 wa_masked_en(wal, 1798 FF_SLICE_CS_CHICKEN2, 1799 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1800 } 1801 1802 if (GRAPHICS_VER(i915) == 9) { 1803 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1804 wa_masked_en(wal, 1805 GEN9_CSFE_CHICKEN1_RCS, 1806 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1807 1808 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1809 wa_write_or(wal, 1810 BDW_SCRATCH1, 1811 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1812 1813 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1814 if (IS_GEN9_LP(i915)) 1815 wa_write_clr_set(wal, 1816 GEN8_L3SQCREG1, 1817 L3_PRIO_CREDITS_MASK, 1818 L3_GENERAL_PRIO_CREDITS(62) | 1819 L3_HIGH_PRIO_CREDITS(2)); 1820 1821 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1822 wa_write_or(wal, 1823 GEN8_L3SQCREG4, 1824 GEN8_LQSC_FLUSH_COHERENT_LINES); 1825 1826 /* Disable atomics in L3 to prevent unrecoverable hangs */ 1827 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 1828 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 1829 wa_write_clr_set(wal, GEN8_L3SQCREG4, 1830 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 1831 wa_write_clr_set(wal, GEN9_SCRATCH1, 1832 EVICTION_PERF_FIX_ENABLE, 0); 1833 } 1834 1835 if (IS_HASWELL(i915)) { 1836 /* WaSampleCChickenBitEnable:hsw */ 1837 wa_masked_en(wal, 1838 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 1839 1840 wa_masked_dis(wal, 1841 CACHE_MODE_0_GEN7, 1842 /* enable HiZ Raw Stall Optimization */ 1843 HIZ_RAW_STALL_OPT_DISABLE); 1844 } 1845 1846 if (IS_VALLEYVIEW(i915)) { 1847 /* WaDisableEarlyCull:vlv */ 1848 wa_masked_en(wal, 1849 _3D_CHICKEN3, 1850 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1851 1852 /* 1853 * WaVSThreadDispatchOverride:ivb,vlv 1854 * 1855 * This actually overrides the dispatch 1856 * mode for all thread types. 1857 */ 1858 wa_write_clr_set(wal, 1859 GEN7_FF_THREAD_MODE, 1860 GEN7_FF_SCHED_MASK, 1861 GEN7_FF_TS_SCHED_HW | 1862 GEN7_FF_VS_SCHED_HW | 1863 GEN7_FF_DS_SCHED_HW); 1864 1865 /* WaPsdDispatchEnable:vlv */ 1866 /* WaDisablePSDDualDispatchEnable:vlv */ 1867 wa_masked_en(wal, 1868 GEN7_HALF_SLICE_CHICKEN1, 1869 GEN7_MAX_PS_THREAD_DEP | 1870 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 1871 } 1872 1873 if (IS_IVYBRIDGE(i915)) { 1874 /* WaDisableEarlyCull:ivb */ 1875 wa_masked_en(wal, 1876 _3D_CHICKEN3, 1877 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1878 1879 if (0) { /* causes HiZ corruption on ivb:gt1 */ 1880 /* enable HiZ Raw Stall Optimization */ 1881 wa_masked_dis(wal, 1882 CACHE_MODE_0_GEN7, 1883 HIZ_RAW_STALL_OPT_DISABLE); 1884 } 1885 1886 /* 1887 * WaVSThreadDispatchOverride:ivb,vlv 1888 * 1889 * This actually overrides the dispatch 1890 * mode for all thread types. 1891 */ 1892 wa_write_clr_set(wal, 1893 GEN7_FF_THREAD_MODE, 1894 GEN7_FF_SCHED_MASK, 1895 GEN7_FF_TS_SCHED_HW | 1896 GEN7_FF_VS_SCHED_HW | 1897 GEN7_FF_DS_SCHED_HW); 1898 1899 /* WaDisablePSDDualDispatchEnable:ivb */ 1900 if (IS_IVB_GT1(i915)) 1901 wa_masked_en(wal, 1902 GEN7_HALF_SLICE_CHICKEN1, 1903 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 1904 } 1905 1906 if (GRAPHICS_VER(i915) == 7) { 1907 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1908 wa_masked_en(wal, 1909 GFX_MODE_GEN7, 1910 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1911 1912 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 1913 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 1914 1915 /* 1916 * BSpec says this must be set, even though 1917 * WaDisable4x2SubspanOptimization:ivb,hsw 1918 * WaDisable4x2SubspanOptimization isn't listed for VLV. 1919 */ 1920 wa_masked_en(wal, 1921 CACHE_MODE_1, 1922 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 1923 1924 /* 1925 * BSpec recommends 8x4 when MSAA is used, 1926 * however in practice 16x4 seems fastest. 1927 * 1928 * Note that PS/WM thread counts depend on the WIZ hashing 1929 * disable bit, which we don't touch here, but it's good 1930 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 1931 */ 1932 wa_masked_field_set(wal, 1933 GEN7_GT_MODE, 1934 GEN6_WIZ_HASHING_MASK, 1935 GEN6_WIZ_HASHING_16x4); 1936 } 1937 1938 if (IS_GRAPHICS_VER(i915, 6, 7)) 1939 /* 1940 * We need to disable the AsyncFlip performance optimisations in 1941 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1942 * already be programmed to '1' on all products. 1943 * 1944 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1945 */ 1946 wa_masked_en(wal, 1947 MI_MODE, 1948 ASYNC_FLIP_PERF_DISABLE); 1949 1950 if (GRAPHICS_VER(i915) == 6) { 1951 /* 1952 * Required for the hardware to program scanline values for 1953 * waiting 1954 * WaEnableFlushTlbInvalidationMode:snb 1955 */ 1956 wa_masked_en(wal, 1957 GFX_MODE, 1958 GFX_TLB_INVALIDATE_EXPLICIT); 1959 1960 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 1961 wa_masked_en(wal, 1962 _3D_CHICKEN, 1963 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 1964 1965 wa_masked_en(wal, 1966 _3D_CHICKEN3, 1967 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 1968 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 1969 /* 1970 * Bspec says: 1971 * "This bit must be set if 3DSTATE_CLIP clip mode is set 1972 * to normal and 3DSTATE_SF number of SF output attributes 1973 * is more than 16." 1974 */ 1975 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 1976 1977 /* 1978 * BSpec recommends 8x4 when MSAA is used, 1979 * however in practice 16x4 seems fastest. 1980 * 1981 * Note that PS/WM thread counts depend on the WIZ hashing 1982 * disable bit, which we don't touch here, but it's good 1983 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 1984 */ 1985 wa_masked_field_set(wal, 1986 GEN6_GT_MODE, 1987 GEN6_WIZ_HASHING_MASK, 1988 GEN6_WIZ_HASHING_16x4); 1989 1990 /* WaDisable_RenderCache_OperationalFlush:snb */ 1991 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1992 1993 /* 1994 * From the Sandybridge PRM, volume 1 part 3, page 24: 1995 * "If this bit is set, STCunit will have LRA as replacement 1996 * policy. [...] This bit must be reset. LRA replacement 1997 * policy is not supported." 1998 */ 1999 wa_masked_dis(wal, 2000 CACHE_MODE_0, 2001 CM0_STC_EVICT_DISABLE_LRA_SNB); 2002 } 2003 2004 if (IS_GRAPHICS_VER(i915, 4, 6)) 2005 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2006 wa_add(wal, MI_MODE, 2007 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2008 /* XXX bit doesn't stick on Broadwater */ 2009 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2010 2011 if (GRAPHICS_VER(i915) == 4) 2012 /* 2013 * Disable CONSTANT_BUFFER before it is loaded from the context 2014 * image. For as it is loaded, it is executed and the stored 2015 * address may no longer be valid, leading to a GPU hang. 2016 * 2017 * This imposes the requirement that userspace reload their 2018 * CONSTANT_BUFFER on every batch, fortunately a requirement 2019 * they are already accustomed to from before contexts were 2020 * enabled. 2021 */ 2022 wa_add(wal, ECOSKPD, 2023 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2024 0 /* XXX bit doesn't stick on Broadwater */, 2025 true); 2026 } 2027 2028 static void 2029 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2030 { 2031 struct drm_i915_private *i915 = engine->i915; 2032 2033 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2034 if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) { 2035 wa_write(wal, 2036 RING_SEMA_WAIT_POLL(engine->mmio_base), 2037 1); 2038 } 2039 } 2040 2041 static void 2042 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2043 { 2044 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2045 return; 2046 2047 if (engine->class == RENDER_CLASS) 2048 rcs_engine_wa_init(engine, wal); 2049 else 2050 xcs_engine_wa_init(engine, wal); 2051 } 2052 2053 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2054 { 2055 struct i915_wa_list *wal = &engine->wa_list; 2056 2057 if (GRAPHICS_VER(engine->i915) < 4) 2058 return; 2059 2060 wa_init_start(wal, "engine", engine->name); 2061 engine_init_workarounds(engine, wal); 2062 wa_init_finish(wal); 2063 } 2064 2065 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2066 { 2067 wa_list_apply(engine->gt, &engine->wa_list); 2068 } 2069 2070 struct mcr_range { 2071 u32 start; 2072 u32 end; 2073 }; 2074 2075 static const struct mcr_range mcr_ranges_gen8[] = { 2076 { .start = 0x5500, .end = 0x55ff }, 2077 { .start = 0x7000, .end = 0x7fff }, 2078 { .start = 0x9400, .end = 0x97ff }, 2079 { .start = 0xb000, .end = 0xb3ff }, 2080 { .start = 0xe000, .end = 0xe7ff }, 2081 {}, 2082 }; 2083 2084 static const struct mcr_range mcr_ranges_gen12[] = { 2085 { .start = 0x8150, .end = 0x815f }, 2086 { .start = 0x9520, .end = 0x955f }, 2087 { .start = 0xb100, .end = 0xb3ff }, 2088 { .start = 0xde80, .end = 0xe8ff }, 2089 { .start = 0x24a00, .end = 0x24a7f }, 2090 {}, 2091 }; 2092 2093 static const struct mcr_range mcr_ranges_xehp[] = { 2094 { .start = 0x4000, .end = 0x4aff }, 2095 { .start = 0x5200, .end = 0x52ff }, 2096 { .start = 0x5400, .end = 0x7fff }, 2097 { .start = 0x8140, .end = 0x815f }, 2098 { .start = 0x8c80, .end = 0x8dff }, 2099 { .start = 0x94d0, .end = 0x955f }, 2100 { .start = 0x9680, .end = 0x96ff }, 2101 { .start = 0xb000, .end = 0xb3ff }, 2102 { .start = 0xc800, .end = 0xcfff }, 2103 { .start = 0xd800, .end = 0xd8ff }, 2104 { .start = 0xdc00, .end = 0xffff }, 2105 { .start = 0x17000, .end = 0x17fff }, 2106 { .start = 0x24a00, .end = 0x24a7f }, 2107 {}, 2108 }; 2109 2110 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2111 { 2112 const struct mcr_range *mcr_ranges; 2113 int i; 2114 2115 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2116 mcr_ranges = mcr_ranges_xehp; 2117 else if (GRAPHICS_VER(i915) >= 12) 2118 mcr_ranges = mcr_ranges_gen12; 2119 else if (GRAPHICS_VER(i915) >= 8) 2120 mcr_ranges = mcr_ranges_gen8; 2121 else 2122 return false; 2123 2124 /* 2125 * Registers in these ranges are affected by the MCR selector 2126 * which only controls CPU initiated MMIO. Routing does not 2127 * work for CS access so we cannot verify them on this path. 2128 */ 2129 for (i = 0; mcr_ranges[i].start; i++) 2130 if (offset >= mcr_ranges[i].start && 2131 offset <= mcr_ranges[i].end) 2132 return true; 2133 2134 return false; 2135 } 2136 2137 static int 2138 wa_list_srm(struct i915_request *rq, 2139 const struct i915_wa_list *wal, 2140 struct i915_vma *vma) 2141 { 2142 struct drm_i915_private *i915 = rq->engine->i915; 2143 unsigned int i, count = 0; 2144 const struct i915_wa *wa; 2145 u32 srm, *cs; 2146 2147 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2148 if (GRAPHICS_VER(i915) >= 8) 2149 srm++; 2150 2151 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2152 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2153 count++; 2154 } 2155 2156 cs = intel_ring_begin(rq, 4 * count); 2157 if (IS_ERR(cs)) 2158 return PTR_ERR(cs); 2159 2160 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2161 u32 offset = i915_mmio_reg_offset(wa->reg); 2162 2163 if (mcr_range(i915, offset)) 2164 continue; 2165 2166 *cs++ = srm; 2167 *cs++ = offset; 2168 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2169 *cs++ = 0; 2170 } 2171 intel_ring_advance(rq, cs); 2172 2173 return 0; 2174 } 2175 2176 static int engine_wa_list_verify(struct intel_context *ce, 2177 const struct i915_wa_list * const wal, 2178 const char *from) 2179 { 2180 const struct i915_wa *wa; 2181 struct i915_request *rq; 2182 struct i915_vma *vma; 2183 struct i915_gem_ww_ctx ww; 2184 unsigned int i; 2185 u32 *results; 2186 int err; 2187 2188 if (!wal->count) 2189 return 0; 2190 2191 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2192 wal->count * sizeof(u32)); 2193 if (IS_ERR(vma)) 2194 return PTR_ERR(vma); 2195 2196 intel_engine_pm_get(ce->engine); 2197 i915_gem_ww_ctx_init(&ww, false); 2198 retry: 2199 err = i915_gem_object_lock(vma->obj, &ww); 2200 if (err == 0) 2201 err = intel_context_pin_ww(ce, &ww); 2202 if (err) 2203 goto err_pm; 2204 2205 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2206 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2207 if (err) 2208 goto err_unpin; 2209 2210 rq = i915_request_create(ce); 2211 if (IS_ERR(rq)) { 2212 err = PTR_ERR(rq); 2213 goto err_vma; 2214 } 2215 2216 err = i915_request_await_object(rq, vma->obj, true); 2217 if (err == 0) 2218 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2219 if (err == 0) 2220 err = wa_list_srm(rq, wal, vma); 2221 2222 i915_request_get(rq); 2223 if (err) 2224 i915_request_set_error_once(rq, err); 2225 i915_request_add(rq); 2226 2227 if (err) 2228 goto err_rq; 2229 2230 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2231 err = -ETIME; 2232 goto err_rq; 2233 } 2234 2235 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2236 if (IS_ERR(results)) { 2237 err = PTR_ERR(results); 2238 goto err_rq; 2239 } 2240 2241 err = 0; 2242 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2243 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2244 continue; 2245 2246 if (!wa_verify(wa, results[i], wal->name, from)) 2247 err = -ENXIO; 2248 } 2249 2250 i915_gem_object_unpin_map(vma->obj); 2251 2252 err_rq: 2253 i915_request_put(rq); 2254 err_vma: 2255 i915_vma_unpin(vma); 2256 err_unpin: 2257 intel_context_unpin(ce); 2258 err_pm: 2259 if (err == -EDEADLK) { 2260 err = i915_gem_ww_ctx_backoff(&ww); 2261 if (!err) 2262 goto retry; 2263 } 2264 i915_gem_ww_ctx_fini(&ww); 2265 intel_engine_pm_put(ce->engine); 2266 i915_vma_put(vma); 2267 return err; 2268 } 2269 2270 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2271 const char *from) 2272 { 2273 return engine_wa_list_verify(engine->kernel_context, 2274 &engine->wa_list, 2275 from); 2276 } 2277 2278 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2279 #include "selftest_workarounds.c" 2280 #endif 2281