1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * Hardware workarounds are register programming documented to be executed in 22 * the driver that fall outside of the normal programming sequences for a 23 * platform. There are some basic categories of workarounds, depending on 24 * how/when they are applied: 25 * 26 * - Context workarounds: workarounds that touch registers that are 27 * saved/restored to/from the HW context image. The list is emitted (via Load 28 * Register Immediate commands) once when initializing the device and saved in 29 * the default context. That default context is then used on every context 30 * creation to have a "primed golden context", i.e. a context image that 31 * already contains the changes needed to all the registers. 32 * 33 * Context workarounds should be implemented in the \*_ctx_workarounds_init() 34 * variants respective to the targeted platforms. 35 * 36 * - Engine workarounds: the list of these WAs is applied whenever the specific 37 * engine is reset. It's also possible that a set of engine classes share a 38 * common power domain and they are reset together. This happens on some 39 * platforms with render and compute engines. In this case (at least) one of 40 * them need to keeep the workaround programming: the approach taken in the 41 * driver is to tie those workarounds to the first compute/render engine that 42 * is registered. When executing with GuC submission, engine resets are 43 * outside of kernel driver control, hence the list of registers involved in 44 * written once, on engine initialization, and then passed to GuC, that 45 * saves/restores their values before/after the reset takes place. See 46 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 47 * 48 * Workarounds for registers specific to RCS and CCS should be implemented in 49 * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for 50 * registers belonging to BCS, VCS or VECS should be implemented in 51 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific 52 * engine's MMIO range but that are part of of the common RCS/CCS reset domain 53 * should be implemented in general_render_compute_wa_init(). 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * GT workarounds should be implemented in the \*_gt_workarounds_init() 59 * variants respective to the targeted platforms. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * Register whitelisting should be done in the \*_whitelist_build() variants 68 * respective to the targeted platforms. 69 * 70 * - Workaround batchbuffers: buffers that get executed automatically by the 71 * hardware on every HW context restore. These buffers are created and 72 * programmed in the default context so the hardware always go through those 73 * programming sequences when switching contexts. The support for workaround 74 * batchbuffers is enabled these hardware mechanisms: 75 * 76 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 77 * context, pointing the hardware to jump to that location when that offset 78 * is reached in the context restore. Workaround batchbuffer in the driver 79 * currently uses this mechanism for all platforms. 80 * 81 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 82 * pointing the hardware to a buffer to continue executing after the 83 * engine registers are restored in a context restore sequence. This is 84 * currently not used in the driver. 85 * 86 * - Other: There are WAs that, due to their nature, cannot be applied from a 87 * central place. Those are peppered around the rest of the code, as needed. 88 * Workarounds related to the display IP are the main example. 89 * 90 * .. [1] Technically, some registers are powercontext saved & restored, so they 91 * survive a suspend/resume. In practice, writing them again is not too 92 * costly and simplifies things, so it's the approach taken in the driver. 93 */ 94 95 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 96 const char *name, const char *engine_name) 97 { 98 wal->gt = gt; 99 wal->name = name; 100 wal->engine_name = engine_name; 101 } 102 103 #define WA_LIST_CHUNK (1 << 4) 104 105 static void wa_init_finish(struct i915_wa_list *wal) 106 { 107 /* Trim unused entries. */ 108 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 109 struct i915_wa *list = kmemdup(wal->list, 110 wal->count * sizeof(*list), 111 GFP_KERNEL); 112 113 if (list) { 114 kfree(wal->list); 115 wal->list = list; 116 } 117 } 118 119 if (!wal->count) 120 return; 121 122 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 123 wal->wa_count, wal->name, wal->engine_name); 124 } 125 126 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 127 { 128 unsigned int addr = i915_mmio_reg_offset(wa->reg); 129 struct drm_i915_private *i915 = wal->gt->i915; 130 unsigned int start = 0, end = wal->count; 131 const unsigned int grow = WA_LIST_CHUNK; 132 struct i915_wa *wa_; 133 134 GEM_BUG_ON(!is_power_of_2(grow)); 135 136 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 137 struct i915_wa *list; 138 139 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 140 GFP_KERNEL); 141 if (!list) { 142 drm_err(&i915->drm, "No space for workaround init!\n"); 143 return; 144 } 145 146 if (wal->list) { 147 memcpy(list, wal->list, sizeof(*wa) * wal->count); 148 kfree(wal->list); 149 } 150 151 wal->list = list; 152 } 153 154 while (start < end) { 155 unsigned int mid = start + (end - start) / 2; 156 157 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 158 start = mid + 1; 159 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 160 end = mid; 161 } else { 162 wa_ = &wal->list[mid]; 163 164 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 165 drm_err(&i915->drm, 166 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 167 i915_mmio_reg_offset(wa_->reg), 168 wa_->clr, wa_->set); 169 170 wa_->set &= ~wa->clr; 171 } 172 173 wal->wa_count++; 174 wa_->set |= wa->set; 175 wa_->clr |= wa->clr; 176 wa_->read |= wa->read; 177 return; 178 } 179 } 180 181 wal->wa_count++; 182 wa_ = &wal->list[wal->count++]; 183 *wa_ = *wa; 184 185 while (wa_-- > wal->list) { 186 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 187 i915_mmio_reg_offset(wa_[1].reg)); 188 if (i915_mmio_reg_offset(wa_[1].reg) > 189 i915_mmio_reg_offset(wa_[0].reg)) 190 break; 191 192 swap(wa_[1], wa_[0]); 193 } 194 } 195 196 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 197 u32 clear, u32 set, u32 read_mask, bool masked_reg) 198 { 199 struct i915_wa wa = { 200 .reg = reg, 201 .clr = clear, 202 .set = set, 203 .read = read_mask, 204 .masked_reg = masked_reg, 205 }; 206 207 _wa_add(wal, &wa); 208 } 209 210 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 211 u32 clear, u32 set, u32 read_mask, bool masked_reg) 212 { 213 struct i915_wa wa = { 214 .mcr_reg = reg, 215 .clr = clear, 216 .set = set, 217 .read = read_mask, 218 .masked_reg = masked_reg, 219 .is_mcr = 1, 220 }; 221 222 _wa_add(wal, &wa); 223 } 224 225 static void 226 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 227 { 228 wa_add(wal, reg, clear, set, clear, false); 229 } 230 231 static void 232 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 233 { 234 wa_mcr_add(wal, reg, clear, set, clear, false); 235 } 236 237 static void 238 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 239 { 240 wa_write_clr_set(wal, reg, ~0, set); 241 } 242 243 static void 244 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 245 { 246 wa_mcr_write_clr_set(wal, reg, ~0, set); 247 } 248 249 static void 250 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 251 { 252 wa_write_clr_set(wal, reg, set, set); 253 } 254 255 static void 256 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 257 { 258 wa_mcr_write_clr_set(wal, reg, set, set); 259 } 260 261 static void 262 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 263 { 264 wa_write_clr_set(wal, reg, clr, 0); 265 } 266 267 static void 268 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 269 { 270 wa_mcr_write_clr_set(wal, reg, clr, 0); 271 } 272 273 /* 274 * WA operations on "masked register". A masked register has the upper 16 bits 275 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 276 * portion of the register without a rmw: you simply write in the upper 16 bits 277 * the mask of bits you are going to modify. 278 * 279 * The wa_masked_* family of functions already does the necessary operations to 280 * calculate the mask based on the parameters passed, so user only has to 281 * provide the lower 16 bits of that register. 282 */ 283 284 static void 285 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 286 { 287 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 288 } 289 290 static void 291 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 292 { 293 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 294 } 295 296 static void 297 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 298 { 299 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 300 } 301 302 static void 303 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 304 { 305 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 306 } 307 308 static void 309 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 310 u32 mask, u32 val) 311 { 312 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 313 } 314 315 static void 316 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 317 u32 mask, u32 val) 318 { 319 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 320 } 321 322 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 323 struct i915_wa_list *wal) 324 { 325 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 326 } 327 328 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 329 struct i915_wa_list *wal) 330 { 331 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 332 } 333 334 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 335 struct i915_wa_list *wal) 336 { 337 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 338 339 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 340 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 341 342 /* WaDisablePartialInstShootdown:bdw,chv */ 343 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 344 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 345 346 /* Use Force Non-Coherent whenever executing a 3D context. This is a 347 * workaround for a possible hang in the unlikely event a TLB 348 * invalidation occurs during a PSD flush. 349 */ 350 /* WaForceEnableNonCoherent:bdw,chv */ 351 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 352 wa_masked_en(wal, HDC_CHICKEN0, 353 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 354 HDC_FORCE_NON_COHERENT); 355 356 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 357 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 358 * polygons in the same 8x4 pixel/sample area to be processed without 359 * stalling waiting for the earlier ones to write to Hierarchical Z 360 * buffer." 361 * 362 * This optimization is off by default for BDW and CHV; turn it on. 363 */ 364 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 365 366 /* Wa4x4STCOptimizationDisable:bdw,chv */ 367 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 368 369 /* 370 * BSpec recommends 8x4 when MSAA is used, 371 * however in practice 16x4 seems fastest. 372 * 373 * Note that PS/WM thread counts depend on the WIZ hashing 374 * disable bit, which we don't touch here, but it's good 375 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 376 */ 377 wa_masked_field_set(wal, GEN7_GT_MODE, 378 GEN6_WIZ_HASHING_MASK, 379 GEN6_WIZ_HASHING_16x4); 380 } 381 382 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 383 struct i915_wa_list *wal) 384 { 385 struct drm_i915_private *i915 = engine->i915; 386 387 gen8_ctx_workarounds_init(engine, wal); 388 389 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 390 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 391 392 /* WaDisableDopClockGating:bdw 393 * 394 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 395 * to disable EUTC clock gating. 396 */ 397 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 398 DOP_CLOCK_GATING_DISABLE); 399 400 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 401 GEN8_SAMPLER_POWER_BYPASS_DIS); 402 403 wa_masked_en(wal, HDC_CHICKEN0, 404 /* WaForceContextSaveRestoreNonCoherent:bdw */ 405 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 406 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 407 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 408 } 409 410 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 411 struct i915_wa_list *wal) 412 { 413 gen8_ctx_workarounds_init(engine, wal); 414 415 /* WaDisableThreadStallDopClockGating:chv */ 416 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 417 418 /* Improve HiZ throughput on CHV. */ 419 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 420 } 421 422 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 423 struct i915_wa_list *wal) 424 { 425 struct drm_i915_private *i915 = engine->i915; 426 427 if (HAS_LLC(i915)) { 428 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 429 * 430 * Must match Display Engine. See 431 * WaCompressedResourceDisplayNewHashMode. 432 */ 433 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 434 GEN9_PBE_COMPRESSED_HASH_SELECTION); 435 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 436 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 437 } 438 439 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 440 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 441 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 442 FLOW_CONTROL_ENABLE | 443 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 444 445 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 446 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 447 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 448 GEN9_ENABLE_YV12_BUGFIX | 449 GEN9_ENABLE_GPGPU_PREEMPTION); 450 451 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 452 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 453 wa_masked_en(wal, CACHE_MODE_1, 454 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 455 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 456 457 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 458 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 459 GEN9_CCS_TLB_PREFETCH_ENABLE); 460 461 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 462 wa_masked_en(wal, HDC_CHICKEN0, 463 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 464 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 465 466 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 467 * both tied to WaForceContextSaveRestoreNonCoherent 468 * in some hsds for skl. We keep the tie for all gen9. The 469 * documentation is a bit hazy and so we want to get common behaviour, 470 * even though there is no clear evidence we would need both on kbl/bxt. 471 * This area has been source of system hangs so we play it safe 472 * and mimic the skl regardless of what bspec says. 473 * 474 * Use Force Non-Coherent whenever executing a 3D context. This 475 * is a workaround for a possible hang in the unlikely event 476 * a TLB invalidation occurs during a PSD flush. 477 */ 478 479 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 480 wa_masked_en(wal, HDC_CHICKEN0, 481 HDC_FORCE_NON_COHERENT); 482 483 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 484 if (IS_SKYLAKE(i915) || 485 IS_KABYLAKE(i915) || 486 IS_COFFEELAKE(i915) || 487 IS_COMETLAKE(i915)) 488 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 489 GEN8_SAMPLER_POWER_BYPASS_DIS); 490 491 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 492 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 493 494 /* 495 * Supporting preemption with fine-granularity requires changes in the 496 * batch buffer programming. Since we can't break old userspace, we 497 * need to set our default preemption level to safe value. Userspace is 498 * still able to use more fine-grained preemption levels, since in 499 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 500 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 501 * not real HW workarounds, but merely a way to start using preemption 502 * while maintaining old contract with userspace. 503 */ 504 505 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 506 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 507 508 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 509 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 510 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 511 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 512 513 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 514 if (IS_GEN9_LP(i915)) 515 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 516 } 517 518 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 struct intel_gt *gt = engine->gt; 522 u8 vals[3] = { 0, 0, 0 }; 523 unsigned int i; 524 525 for (i = 0; i < 3; i++) { 526 u8 ss; 527 528 /* 529 * Only consider slices where one, and only one, subslice has 7 530 * EUs 531 */ 532 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 533 continue; 534 535 /* 536 * subslice_7eu[i] != 0 (because of the check above) and 537 * ss_max == 4 (maximum number of subslices possible per slice) 538 * 539 * -> 0 <= ss <= 3; 540 */ 541 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 542 vals[i] = 3 - ss; 543 } 544 545 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 546 return; 547 548 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 549 wa_masked_field_set(wal, GEN7_GT_MODE, 550 GEN9_IZ_HASHING_MASK(2) | 551 GEN9_IZ_HASHING_MASK(1) | 552 GEN9_IZ_HASHING_MASK(0), 553 GEN9_IZ_HASHING(2, vals[2]) | 554 GEN9_IZ_HASHING(1, vals[1]) | 555 GEN9_IZ_HASHING(0, vals[0])); 556 } 557 558 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 559 struct i915_wa_list *wal) 560 { 561 gen9_ctx_workarounds_init(engine, wal); 562 skl_tune_iz_hashing(engine, wal); 563 } 564 565 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 566 struct i915_wa_list *wal) 567 { 568 gen9_ctx_workarounds_init(engine, wal); 569 570 /* WaDisableThreadStallDopClockGating:bxt */ 571 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 572 STALL_DOP_GATING_DISABLE); 573 574 /* WaToEnableHwFixForPushConstHWBug:bxt */ 575 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 576 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 577 } 578 579 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 580 struct i915_wa_list *wal) 581 { 582 struct drm_i915_private *i915 = engine->i915; 583 584 gen9_ctx_workarounds_init(engine, wal); 585 586 /* WaToEnableHwFixForPushConstHWBug:kbl */ 587 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 588 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 589 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 590 591 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 592 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 593 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 594 } 595 596 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 597 struct i915_wa_list *wal) 598 { 599 gen9_ctx_workarounds_init(engine, wal); 600 601 /* WaToEnableHwFixForPushConstHWBug:glk */ 602 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 603 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 604 } 605 606 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 607 struct i915_wa_list *wal) 608 { 609 gen9_ctx_workarounds_init(engine, wal); 610 611 /* WaToEnableHwFixForPushConstHWBug:cfl */ 612 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 613 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 614 615 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 616 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 617 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 618 } 619 620 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 621 struct i915_wa_list *wal) 622 { 623 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 624 wa_write(wal, 625 GEN8_L3CNTLREG, 626 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 627 GEN8_ERRDETBCTRL); 628 629 /* WaForceEnableNonCoherent:icl 630 * This is not the same workaround as in early Gen9 platforms, where 631 * lacking this could cause system hangs, but coherency performance 632 * overhead is high and only a few compute workloads really need it 633 * (the register is whitelisted in hardware now, so UMDs can opt in 634 * for coherency if they have a good reason). 635 */ 636 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 637 638 /* WaEnableFloatBlendOptimization:icl */ 639 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 640 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 641 0 /* write-only, so skip validation */, 642 true); 643 644 /* WaDisableGPGPUMidThreadPreemption:icl */ 645 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 646 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 647 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 648 649 /* allow headerless messages for preemptible GPGPU context */ 650 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 651 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 652 653 /* Wa_1604278689:icl,ehl */ 654 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 655 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 656 0, /* write-only register; skip validation */ 657 0xFFFFFFFF); 658 659 /* Wa_1406306137:icl,ehl */ 660 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 661 } 662 663 /* 664 * These settings aren't actually workarounds, but general tuning settings that 665 * need to be programmed on dg2 platform. 666 */ 667 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 668 struct i915_wa_list *wal) 669 { 670 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 671 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 672 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 673 wa_mcr_add(wal, 674 XEHP_FF_MODE2, 675 FF_MODE2_TDS_TIMER_MASK, 676 FF_MODE2_TDS_TIMER_128, 677 0, false); 678 } 679 680 /* 681 * These settings aren't actually workarounds, but general tuning settings that 682 * need to be programmed on several platforms. 683 */ 684 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 685 struct i915_wa_list *wal) 686 { 687 /* 688 * Although some platforms refer to it as Wa_1604555607, we need to 689 * program it even on those that don't explicitly list that 690 * workaround. 691 * 692 * Note that the programming of this register is further modified 693 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 694 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 695 * value when read. The default value for this register is zero for all 696 * fields and there are no bit masks. So instead of doing a RMW we 697 * should just write TDS timer value. For the same reason read 698 * verification is ignored. 699 */ 700 wa_add(wal, 701 GEN12_FF_MODE2, 702 FF_MODE2_TDS_TIMER_MASK, 703 FF_MODE2_TDS_TIMER_128, 704 0, false); 705 } 706 707 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 708 struct i915_wa_list *wal) 709 { 710 struct drm_i915_private *i915 = engine->i915; 711 712 gen12_ctx_gt_tuning_init(engine, wal); 713 714 /* 715 * Wa_1409142259:tgl,dg1,adl-p 716 * Wa_1409347922:tgl,dg1,adl-p 717 * Wa_1409252684:tgl,dg1,adl-p 718 * Wa_1409217633:tgl,dg1,adl-p 719 * Wa_1409207793:tgl,dg1,adl-p 720 * Wa_1409178076:tgl,dg1,adl-p 721 * Wa_1408979724:tgl,dg1,adl-p 722 * Wa_14010443199:tgl,rkl,dg1,adl-p 723 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 724 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 725 */ 726 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 727 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 728 729 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 730 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 731 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 732 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 733 734 /* 735 * Wa_16011163337 736 * 737 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 738 * to Wa_1608008084. 739 */ 740 wa_add(wal, 741 GEN12_FF_MODE2, 742 FF_MODE2_GS_TIMER_MASK, 743 FF_MODE2_GS_TIMER_224, 744 0, false); 745 746 if (!IS_DG1(i915)) 747 /* Wa_1806527549 */ 748 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 749 } 750 751 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 752 struct i915_wa_list *wal) 753 { 754 gen12_ctx_workarounds_init(engine, wal); 755 756 /* Wa_1409044764 */ 757 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 758 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 759 760 /* Wa_22010493298 */ 761 wa_masked_en(wal, HIZ_CHICKEN, 762 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 763 } 764 765 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 766 struct i915_wa_list *wal) 767 { 768 dg2_ctx_gt_tuning_init(engine, wal); 769 770 /* Wa_16011186671:dg2_g11 */ 771 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 772 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 773 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 774 } 775 776 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 777 /* Wa_14010469329:dg2_g10 */ 778 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 779 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 780 781 /* 782 * Wa_22010465075:dg2_g10 783 * Wa_22010613112:dg2_g10 784 * Wa_14010698770:dg2_g10 785 */ 786 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 787 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 788 } 789 790 /* Wa_16013271637:dg2 */ 791 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 792 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 793 794 /* Wa_14014947963:dg2 */ 795 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 796 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 797 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 798 799 /* Wa_18018764978:dg2 */ 800 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || 801 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 802 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 803 804 /* Wa_15010599737:dg2 */ 805 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 806 807 /* Wa_18019271663:dg2 */ 808 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 809 } 810 811 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, 812 struct i915_wa_list *wal) 813 { 814 struct drm_i915_private *i915 = engine->i915; 815 816 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 817 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 818 /* Wa_14014947963 */ 819 wa_masked_field_set(wal, VF_PREEMPTION, 820 PREEMPTION_VERTEX_COUNT, 0x4000); 821 822 /* Wa_16013271637 */ 823 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 824 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 825 826 /* Wa_18019627453 */ 827 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); 828 829 /* Wa_18018764978 */ 830 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 831 } 832 833 /* Wa_18019271663 */ 834 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 835 } 836 837 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 838 struct i915_wa_list *wal) 839 { 840 /* 841 * This is a "fake" workaround defined by software to ensure we 842 * maintain reliable, backward-compatible behavior for userspace with 843 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 844 * 845 * The per-context setting of MI_MODE[12] determines whether the bits 846 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 847 * in the traditional manner or whether they should instead use a new 848 * tgl+ meaning that breaks backward compatibility, but allows nesting 849 * into 3rd-level batchbuffers. When this new capability was first 850 * added in TGL, it remained off by default unless a context 851 * intentionally opted in to the new behavior. However Xe_HPG now 852 * flips this on by default and requires that we explicitly opt out if 853 * we don't want the new behavior. 854 * 855 * From a SW perspective, we want to maintain the backward-compatible 856 * behavior for userspace, so we'll apply a fake workaround to set it 857 * back to the legacy behavior on platforms where the hardware default 858 * is to break compatibility. At the moment there is no Linux 859 * userspace that utilizes third-level batchbuffers, so this will avoid 860 * userspace from needing to make any changes. using the legacy 861 * meaning is the correct thing to do. If/when we have userspace 862 * consumers that want to utilize third-level batch nesting, we can 863 * provide a context parameter to allow them to opt-in. 864 */ 865 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 866 } 867 868 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 869 struct i915_wa_list *wal) 870 { 871 u8 mocs; 872 873 /* 874 * Some blitter commands do not have a field for MOCS, those 875 * commands will use MOCS index pointed by BLIT_CCTL. 876 * BLIT_CCTL registers are needed to be programmed to un-cached. 877 */ 878 if (engine->class == COPY_ENGINE_CLASS) { 879 mocs = engine->gt->mocs.uc_index; 880 wa_write_clr_set(wal, 881 BLIT_CCTL(engine->mmio_base), 882 BLIT_CCTL_MASK, 883 BLIT_CCTL_MOCS(mocs, mocs)); 884 } 885 } 886 887 /* 888 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 889 * defined by the hardware team, but it programming general context registers. 890 * Adding those context register programming in context workaround 891 * allow us to use the wa framework for proper application and validation. 892 */ 893 static void 894 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 895 struct i915_wa_list *wal) 896 { 897 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 898 fakewa_disable_nestedbb_mode(engine, wal); 899 900 gen12_ctx_gt_mocs_init(engine, wal); 901 } 902 903 static void 904 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 905 struct i915_wa_list *wal, 906 const char *name) 907 { 908 struct drm_i915_private *i915 = engine->i915; 909 910 wa_init_start(wal, engine->gt, name, engine->name); 911 912 /* Applies to all engines */ 913 /* 914 * Fake workarounds are not the actual workaround but 915 * programming of context registers using workaround framework. 916 */ 917 if (GRAPHICS_VER(i915) >= 12) 918 gen12_ctx_gt_fake_wa_init(engine, wal); 919 920 if (engine->class != RENDER_CLASS) 921 goto done; 922 923 if (IS_METEORLAKE(i915)) 924 mtl_ctx_workarounds_init(engine, wal); 925 else if (IS_PONTEVECCHIO(i915)) 926 ; /* noop; none at this time */ 927 else if (IS_DG2(i915)) 928 dg2_ctx_workarounds_init(engine, wal); 929 else if (IS_XEHPSDV(i915)) 930 ; /* noop; none at this time */ 931 else if (IS_DG1(i915)) 932 dg1_ctx_workarounds_init(engine, wal); 933 else if (GRAPHICS_VER(i915) == 12) 934 gen12_ctx_workarounds_init(engine, wal); 935 else if (GRAPHICS_VER(i915) == 11) 936 icl_ctx_workarounds_init(engine, wal); 937 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 938 cfl_ctx_workarounds_init(engine, wal); 939 else if (IS_GEMINILAKE(i915)) 940 glk_ctx_workarounds_init(engine, wal); 941 else if (IS_KABYLAKE(i915)) 942 kbl_ctx_workarounds_init(engine, wal); 943 else if (IS_BROXTON(i915)) 944 bxt_ctx_workarounds_init(engine, wal); 945 else if (IS_SKYLAKE(i915)) 946 skl_ctx_workarounds_init(engine, wal); 947 else if (IS_CHERRYVIEW(i915)) 948 chv_ctx_workarounds_init(engine, wal); 949 else if (IS_BROADWELL(i915)) 950 bdw_ctx_workarounds_init(engine, wal); 951 else if (GRAPHICS_VER(i915) == 7) 952 gen7_ctx_workarounds_init(engine, wal); 953 else if (GRAPHICS_VER(i915) == 6) 954 gen6_ctx_workarounds_init(engine, wal); 955 else if (GRAPHICS_VER(i915) < 8) 956 ; 957 else 958 MISSING_CASE(GRAPHICS_VER(i915)); 959 960 done: 961 wa_init_finish(wal); 962 } 963 964 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 965 { 966 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 967 } 968 969 int intel_engine_emit_ctx_wa(struct i915_request *rq) 970 { 971 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 972 struct i915_wa *wa; 973 unsigned int i; 974 u32 *cs; 975 int ret; 976 977 if (wal->count == 0) 978 return 0; 979 980 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 981 if (ret) 982 return ret; 983 984 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 985 if (IS_ERR(cs)) 986 return PTR_ERR(cs); 987 988 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 989 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 990 *cs++ = i915_mmio_reg_offset(wa->reg); 991 *cs++ = wa->set; 992 } 993 *cs++ = MI_NOOP; 994 995 intel_ring_advance(rq, cs); 996 997 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 998 if (ret) 999 return ret; 1000 1001 return 0; 1002 } 1003 1004 static void 1005 gen4_gt_workarounds_init(struct intel_gt *gt, 1006 struct i915_wa_list *wal) 1007 { 1008 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 1009 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1010 } 1011 1012 static void 1013 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1014 { 1015 gen4_gt_workarounds_init(gt, wal); 1016 1017 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 1018 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 1019 } 1020 1021 static void 1022 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1023 { 1024 g4x_gt_workarounds_init(gt, wal); 1025 1026 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 1027 } 1028 1029 static void 1030 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1031 { 1032 } 1033 1034 static void 1035 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1036 { 1037 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 1038 wa_masked_dis(wal, 1039 GEN7_COMMON_SLICE_CHICKEN1, 1040 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 1041 1042 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 1043 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 1044 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 1045 1046 /* WaForceL3Serialization:ivb */ 1047 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1048 } 1049 1050 static void 1051 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1052 { 1053 /* WaForceL3Serialization:vlv */ 1054 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1055 1056 /* 1057 * WaIncreaseL3CreditsForVLVB0:vlv 1058 * This is the hardware default actually. 1059 */ 1060 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1061 } 1062 1063 static void 1064 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1065 { 1066 /* L3 caching of data atomics doesn't work -- disable it. */ 1067 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1068 1069 wa_add(wal, 1070 HSW_ROW_CHICKEN3, 0, 1071 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1072 0 /* XXX does this reg exist? */, true); 1073 1074 /* WaVSRefCountFullforceMissDisable:hsw */ 1075 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1076 } 1077 1078 static void 1079 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1080 { 1081 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1082 unsigned int slice, subslice; 1083 u32 mcr, mcr_mask; 1084 1085 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1086 1087 /* 1088 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1089 * Before any MMIO read into slice/subslice specific registers, MCR 1090 * packet control register needs to be programmed to point to any 1091 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1092 * This means each subsequent MMIO read will be forwarded to an 1093 * specific s/ss combination, but this is OK since these registers 1094 * are consistent across s/ss in almost all cases. In the rare 1095 * occasions, such as INSTDONE, where this value is dependent 1096 * on s/ss combo, the read should be done with read_subslice_reg. 1097 */ 1098 slice = ffs(sseu->slice_mask) - 1; 1099 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1100 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1101 GEM_BUG_ON(!subslice); 1102 subslice--; 1103 1104 /* 1105 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1106 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1107 */ 1108 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1109 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1110 1111 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1112 1113 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1114 } 1115 1116 static void 1117 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1118 { 1119 struct drm_i915_private *i915 = gt->i915; 1120 1121 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1122 gen9_wa_init_mcr(i915, wal); 1123 1124 /* WaDisableKillLogic:bxt,skl,kbl */ 1125 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1126 wa_write_or(wal, 1127 GAM_ECOCHK, 1128 ECOCHK_DIS_TLB); 1129 1130 if (HAS_LLC(i915)) { 1131 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1132 * 1133 * Must match Display Engine. See 1134 * WaCompressedResourceDisplayNewHashMode. 1135 */ 1136 wa_write_or(wal, 1137 MMCD_MISC_CTRL, 1138 MMCD_PCLA | MMCD_HOTSPOT_EN); 1139 } 1140 1141 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1142 wa_write_or(wal, 1143 GAM_ECOCHK, 1144 BDW_DISABLE_HDC_INVALIDATION); 1145 } 1146 1147 static void 1148 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1149 { 1150 gen9_gt_workarounds_init(gt, wal); 1151 1152 /* WaDisableGafsUnitClkGating:skl */ 1153 wa_write_or(wal, 1154 GEN7_UCGCTL4, 1155 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1156 1157 /* WaInPlaceDecompressionHang:skl */ 1158 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1159 wa_write_or(wal, 1160 GEN9_GAMT_ECO_REG_RW_IA, 1161 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1162 } 1163 1164 static void 1165 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1166 { 1167 gen9_gt_workarounds_init(gt, wal); 1168 1169 /* WaDisableDynamicCreditSharing:kbl */ 1170 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1171 wa_write_or(wal, 1172 GAMT_CHKN_BIT_REG, 1173 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1174 1175 /* WaDisableGafsUnitClkGating:kbl */ 1176 wa_write_or(wal, 1177 GEN7_UCGCTL4, 1178 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1179 1180 /* WaInPlaceDecompressionHang:kbl */ 1181 wa_write_or(wal, 1182 GEN9_GAMT_ECO_REG_RW_IA, 1183 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1184 } 1185 1186 static void 1187 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1188 { 1189 gen9_gt_workarounds_init(gt, wal); 1190 } 1191 1192 static void 1193 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1194 { 1195 gen9_gt_workarounds_init(gt, wal); 1196 1197 /* WaDisableGafsUnitClkGating:cfl */ 1198 wa_write_or(wal, 1199 GEN7_UCGCTL4, 1200 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1201 1202 /* WaInPlaceDecompressionHang:cfl */ 1203 wa_write_or(wal, 1204 GEN9_GAMT_ECO_REG_RW_IA, 1205 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1206 } 1207 1208 static void __set_mcr_steering(struct i915_wa_list *wal, 1209 i915_reg_t steering_reg, 1210 unsigned int slice, unsigned int subslice) 1211 { 1212 u32 mcr, mcr_mask; 1213 1214 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1215 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1216 1217 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1218 } 1219 1220 static void debug_dump_steering(struct intel_gt *gt) 1221 { 1222 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1223 1224 if (drm_debug_enabled(DRM_UT_DRIVER)) 1225 intel_gt_mcr_report_steering(&p, gt, false); 1226 } 1227 1228 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1229 unsigned int slice, unsigned int subslice) 1230 { 1231 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1232 1233 gt->default_steering.groupid = slice; 1234 gt->default_steering.instanceid = subslice; 1235 1236 debug_dump_steering(gt); 1237 } 1238 1239 static void 1240 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1241 { 1242 const struct sseu_dev_info *sseu = >->info.sseu; 1243 unsigned int subslice; 1244 1245 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1246 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1247 1248 /* 1249 * Although a platform may have subslices, we need to always steer 1250 * reads to the lowest instance that isn't fused off. When Render 1251 * Power Gating is enabled, grabbing forcewake will only power up a 1252 * single subslice (the "minconfig") if there isn't a real workload 1253 * that needs to be run; this means that if we steer register reads to 1254 * one of the higher subslices, we run the risk of reading back 0's or 1255 * random garbage. 1256 */ 1257 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1258 1259 /* 1260 * If the subslice we picked above also steers us to a valid L3 bank, 1261 * then we can just rely on the default steering and won't need to 1262 * worry about explicitly re-steering L3BANK reads later. 1263 */ 1264 if (gt->info.l3bank_mask & BIT(subslice)) 1265 gt->steering_table[L3BANK] = NULL; 1266 1267 __add_mcr_wa(gt, wal, 0, subslice); 1268 } 1269 1270 static void 1271 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1272 { 1273 const struct sseu_dev_info *sseu = >->info.sseu; 1274 unsigned long slice, subslice = 0, slice_mask = 0; 1275 u32 lncf_mask = 0; 1276 int i; 1277 1278 /* 1279 * On Xe_HP the steering increases in complexity. There are now several 1280 * more units that require steering and we're not guaranteed to be able 1281 * to find a common setting for all of them. These are: 1282 * - GSLICE (fusable) 1283 * - DSS (sub-unit within gslice; fusable) 1284 * - L3 Bank (fusable) 1285 * - MSLICE (fusable) 1286 * - LNCF (sub-unit within mslice; always present if mslice is present) 1287 * 1288 * We'll do our default/implicit steering based on GSLICE (in the 1289 * sliceid field) and DSS (in the subsliceid field). If we can 1290 * find overlap between the valid MSLICE and/or LNCF values with 1291 * a suitable GSLICE, then we can just re-use the default value and 1292 * skip and explicit steering at runtime. 1293 * 1294 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1295 * a valid sliceid value. DSS steering is the only type of steering 1296 * that utilizes the 'subsliceid' bits. 1297 * 1298 * Also note that, even though the steering domain is called "GSlice" 1299 * and it is encoded in the register using the gslice format, the spec 1300 * says that the combined (geometry | compute) fuse should be used to 1301 * select the steering. 1302 */ 1303 1304 /* Find the potential gslice candidates */ 1305 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1306 GEN_DSS_PER_GSLICE); 1307 1308 /* 1309 * Find the potential LNCF candidates. Either LNCF within a valid 1310 * mslice is fine. 1311 */ 1312 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1313 lncf_mask |= (0x3 << (i * 2)); 1314 1315 /* 1316 * Are there any sliceid values that work for both GSLICE and LNCF 1317 * steering? 1318 */ 1319 if (slice_mask & lncf_mask) { 1320 slice_mask &= lncf_mask; 1321 gt->steering_table[LNCF] = NULL; 1322 } 1323 1324 /* How about sliceid values that also work for MSLICE steering? */ 1325 if (slice_mask & gt->info.mslice_mask) { 1326 slice_mask &= gt->info.mslice_mask; 1327 gt->steering_table[MSLICE] = NULL; 1328 } 1329 1330 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1331 gt->steering_table[GAM] = NULL; 1332 1333 slice = __ffs(slice_mask); 1334 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1335 GEN_DSS_PER_GSLICE; 1336 1337 __add_mcr_wa(gt, wal, slice, subslice); 1338 1339 /* 1340 * SQIDI ranges are special because they use different steering 1341 * registers than everything else we work with. On XeHP SDV and 1342 * DG2-G10, any value in the steering registers will work fine since 1343 * all instances are present, but DG2-G11 only has SQIDI instances at 1344 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1345 * we'll just steer to a hardcoded "2" since that value will work 1346 * everywhere. 1347 */ 1348 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1349 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1350 1351 /* 1352 * On DG2, GAM registers have a dedicated steering control register 1353 * and must always be programmed to a hardcoded groupid of "1." 1354 */ 1355 if (IS_DG2(gt->i915)) 1356 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1357 } 1358 1359 static void 1360 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1361 { 1362 unsigned int dss; 1363 1364 /* 1365 * Setup implicit steering for COMPUTE and DSS ranges to the first 1366 * non-fused-off DSS. All other types of MCR registers will be 1367 * explicitly steered. 1368 */ 1369 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1370 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1371 } 1372 1373 static void 1374 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1375 { 1376 struct drm_i915_private *i915 = gt->i915; 1377 1378 icl_wa_init_mcr(gt, wal); 1379 1380 /* WaModifyGamTlbPartitioning:icl */ 1381 wa_write_clr_set(wal, 1382 GEN11_GACB_PERF_CTRL, 1383 GEN11_HASH_CTRL_MASK, 1384 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1385 1386 /* Wa_1405766107:icl 1387 * Formerly known as WaCL2SFHalfMaxAlloc 1388 */ 1389 wa_write_or(wal, 1390 GEN11_LSN_UNSLCVC, 1391 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1392 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1393 1394 /* Wa_220166154:icl 1395 * Formerly known as WaDisCtxReload 1396 */ 1397 wa_write_or(wal, 1398 GEN8_GAMW_ECO_DEV_RW_IA, 1399 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1400 1401 /* Wa_1406463099:icl 1402 * Formerly known as WaGamTlbPendError 1403 */ 1404 wa_write_or(wal, 1405 GAMT_CHKN_BIT_REG, 1406 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1407 1408 /* 1409 * Wa_1408615072:icl,ehl (vsunit) 1410 * Wa_1407596294:icl,ehl (hsunit) 1411 */ 1412 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1413 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1414 1415 /* Wa_1407352427:icl,ehl */ 1416 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1417 PSDUNIT_CLKGATE_DIS); 1418 1419 /* Wa_1406680159:icl,ehl */ 1420 wa_mcr_write_or(wal, 1421 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1422 GWUNIT_CLKGATE_DIS); 1423 1424 /* Wa_1607087056:icl,ehl,jsl */ 1425 if (IS_ICELAKE(i915) || 1426 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1427 wa_write_or(wal, 1428 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1429 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1430 1431 /* 1432 * This is not a documented workaround, but rather an optimization 1433 * to reduce sampler power. 1434 */ 1435 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1436 } 1437 1438 /* 1439 * Though there are per-engine instances of these registers, 1440 * they retain their value through engine resets and should 1441 * only be provided on the GT workaround list rather than 1442 * the engine-specific workaround list. 1443 */ 1444 static void 1445 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1446 { 1447 struct intel_engine_cs *engine; 1448 int id; 1449 1450 for_each_engine(engine, gt, id) { 1451 if (engine->class != VIDEO_DECODE_CLASS || 1452 (engine->instance % 2)) 1453 continue; 1454 1455 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1456 IECPUNIT_CLKGATE_DIS); 1457 } 1458 } 1459 1460 static void 1461 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1462 { 1463 icl_wa_init_mcr(gt, wal); 1464 1465 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1466 wa_14011060649(gt, wal); 1467 1468 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1469 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1470 } 1471 1472 static void 1473 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1474 { 1475 struct drm_i915_private *i915 = gt->i915; 1476 1477 gen12_gt_workarounds_init(gt, wal); 1478 1479 /* Wa_1409420604:tgl */ 1480 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1481 wa_mcr_write_or(wal, 1482 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1483 CPSSUNIT_CLKGATE_DIS); 1484 1485 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1486 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1487 wa_write_or(wal, 1488 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1489 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1490 1491 /* Wa_1408615072:tgl[a0] */ 1492 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1493 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1494 VSUNIT_CLKGATE_DIS_TGL); 1495 } 1496 1497 static void 1498 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1499 { 1500 struct drm_i915_private *i915 = gt->i915; 1501 1502 gen12_gt_workarounds_init(gt, wal); 1503 1504 /* Wa_1607087056:dg1 */ 1505 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1506 wa_write_or(wal, 1507 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1508 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1509 1510 /* Wa_1409420604:dg1 */ 1511 if (IS_DG1(i915)) 1512 wa_mcr_write_or(wal, 1513 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1514 CPSSUNIT_CLKGATE_DIS); 1515 1516 /* Wa_1408615072:dg1 */ 1517 /* Empirical testing shows this register is unaffected by engine reset. */ 1518 if (IS_DG1(i915)) 1519 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1520 VSUNIT_CLKGATE_DIS_TGL); 1521 } 1522 1523 static void 1524 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1525 { 1526 struct drm_i915_private *i915 = gt->i915; 1527 1528 xehp_init_mcr(gt, wal); 1529 1530 /* Wa_1409757795:xehpsdv */ 1531 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1532 1533 /* Wa_18011725039:xehpsdv */ 1534 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 1535 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 1536 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 1537 } 1538 1539 /* Wa_16011155590:xehpsdv */ 1540 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1541 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1542 TSGUNIT_CLKGATE_DIS); 1543 1544 /* Wa_14011780169:xehpsdv */ 1545 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1546 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1547 GAMTLBVDBOX7_CLKGATE_DIS | 1548 GAMTLBVDBOX6_CLKGATE_DIS | 1549 GAMTLBVDBOX5_CLKGATE_DIS | 1550 GAMTLBVDBOX4_CLKGATE_DIS | 1551 GAMTLBVDBOX3_CLKGATE_DIS | 1552 GAMTLBVDBOX2_CLKGATE_DIS | 1553 GAMTLBVDBOX1_CLKGATE_DIS | 1554 GAMTLBVDBOX0_CLKGATE_DIS | 1555 GAMTLBKCR_CLKGATE_DIS | 1556 GAMTLBGUC_CLKGATE_DIS | 1557 GAMTLBBLT_CLKGATE_DIS); 1558 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1559 GAMTLBGFXA1_CLKGATE_DIS | 1560 GAMTLBCOMPA0_CLKGATE_DIS | 1561 GAMTLBCOMPA1_CLKGATE_DIS | 1562 GAMTLBCOMPB0_CLKGATE_DIS | 1563 GAMTLBCOMPB1_CLKGATE_DIS | 1564 GAMTLBCOMPC0_CLKGATE_DIS | 1565 GAMTLBCOMPC1_CLKGATE_DIS | 1566 GAMTLBCOMPD0_CLKGATE_DIS | 1567 GAMTLBCOMPD1_CLKGATE_DIS | 1568 GAMTLBMERT_CLKGATE_DIS | 1569 GAMTLBVEBOX3_CLKGATE_DIS | 1570 GAMTLBVEBOX2_CLKGATE_DIS | 1571 GAMTLBVEBOX1_CLKGATE_DIS | 1572 GAMTLBVEBOX0_CLKGATE_DIS); 1573 } 1574 1575 /* Wa_16012725990:xehpsdv */ 1576 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1577 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1578 1579 /* Wa_14011060649:xehpsdv */ 1580 wa_14011060649(gt, wal); 1581 1582 /* Wa_14012362059:xehpsdv */ 1583 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1584 1585 /* Wa_14014368820:xehpsdv */ 1586 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1587 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1588 1589 /* Wa_14010670810:xehpsdv */ 1590 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1591 } 1592 1593 static void 1594 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1595 { 1596 struct intel_engine_cs *engine; 1597 int id; 1598 1599 xehp_init_mcr(gt, wal); 1600 1601 /* Wa_14011060649:dg2 */ 1602 wa_14011060649(gt, wal); 1603 1604 /* 1605 * Although there are per-engine instances of these registers, 1606 * they technically exist outside the engine itself and are not 1607 * impacted by engine resets. Furthermore, they're part of the 1608 * GuC blacklist so trying to treat them as engine workarounds 1609 * will result in GuC initialization failure and a wedged GPU. 1610 */ 1611 for_each_engine(engine, gt, id) { 1612 if (engine->class != VIDEO_DECODE_CLASS) 1613 continue; 1614 1615 /* Wa_16010515920:dg2_g10 */ 1616 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1617 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1618 ALNUNIT_CLKGATE_DIS); 1619 } 1620 1621 if (IS_DG2_G10(gt->i915)) { 1622 /* Wa_22010523718:dg2 */ 1623 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1624 CG3DDISCFEG_CLKGATE_DIS); 1625 1626 /* Wa_14011006942:dg2 */ 1627 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1628 DSS_ROUTER_CLKGATE_DIS); 1629 } 1630 1631 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) || 1632 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) { 1633 /* Wa_14012362059:dg2 */ 1634 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1635 } 1636 1637 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1638 /* Wa_14010948348:dg2_g10 */ 1639 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1640 1641 /* Wa_14011037102:dg2_g10 */ 1642 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1643 1644 /* Wa_14011371254:dg2_g10 */ 1645 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1646 1647 /* Wa_14011431319:dg2_g10 */ 1648 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1649 GAMTLBVDBOX7_CLKGATE_DIS | 1650 GAMTLBVDBOX6_CLKGATE_DIS | 1651 GAMTLBVDBOX5_CLKGATE_DIS | 1652 GAMTLBVDBOX4_CLKGATE_DIS | 1653 GAMTLBVDBOX3_CLKGATE_DIS | 1654 GAMTLBVDBOX2_CLKGATE_DIS | 1655 GAMTLBVDBOX1_CLKGATE_DIS | 1656 GAMTLBVDBOX0_CLKGATE_DIS | 1657 GAMTLBKCR_CLKGATE_DIS | 1658 GAMTLBGUC_CLKGATE_DIS | 1659 GAMTLBBLT_CLKGATE_DIS); 1660 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1661 GAMTLBGFXA1_CLKGATE_DIS | 1662 GAMTLBCOMPA0_CLKGATE_DIS | 1663 GAMTLBCOMPA1_CLKGATE_DIS | 1664 GAMTLBCOMPB0_CLKGATE_DIS | 1665 GAMTLBCOMPB1_CLKGATE_DIS | 1666 GAMTLBCOMPC0_CLKGATE_DIS | 1667 GAMTLBCOMPC1_CLKGATE_DIS | 1668 GAMTLBCOMPD0_CLKGATE_DIS | 1669 GAMTLBCOMPD1_CLKGATE_DIS | 1670 GAMTLBMERT_CLKGATE_DIS | 1671 GAMTLBVEBOX3_CLKGATE_DIS | 1672 GAMTLBVEBOX2_CLKGATE_DIS | 1673 GAMTLBVEBOX1_CLKGATE_DIS | 1674 GAMTLBVEBOX0_CLKGATE_DIS); 1675 1676 /* Wa_14010569222:dg2_g10 */ 1677 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1678 GAMEDIA_CLKGATE_DIS); 1679 1680 /* Wa_14011028019:dg2_g10 */ 1681 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1682 1683 /* Wa_14010680813:dg2_g10 */ 1684 wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL, 1685 CONTROL_BLOCK_CLKGATE_DIS | 1686 EGRESS_BLOCK_CLKGATE_DIS | 1687 TAG_BLOCK_CLKGATE_DIS); 1688 } 1689 1690 /* Wa_14014830051:dg2 */ 1691 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1692 1693 /* 1694 * The following are not actually "workarounds" but rather 1695 * recommended tuning settings documented in the bspec's 1696 * performance guide section. 1697 */ 1698 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1699 1700 /* Wa_14015795083 */ 1701 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1702 1703 /* Wa_18018781329 */ 1704 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1705 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1706 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1707 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1708 1709 /* Wa_1509235366:dg2 */ 1710 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1711 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1712 1713 /* Wa_14010648519:dg2 */ 1714 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1715 } 1716 1717 static void 1718 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1719 { 1720 pvc_init_mcr(gt, wal); 1721 1722 /* Wa_14015795083 */ 1723 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1724 1725 /* Wa_18018781329 */ 1726 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1727 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1728 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1729 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1730 1731 /* Wa_16016694945 */ 1732 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 1733 } 1734 1735 static void 1736 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1737 { 1738 if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) || 1739 IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) { 1740 /* Wa_14014830051 */ 1741 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1742 1743 /* Wa_18018781329 */ 1744 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1745 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1746 } 1747 1748 /* 1749 * Unlike older platforms, we no longer setup implicit steering here; 1750 * all MCR accesses are explicitly steered. 1751 */ 1752 debug_dump_steering(gt); 1753 } 1754 1755 static void 1756 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1757 { 1758 if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0)) { 1759 /* 1760 * Wa_18018781329 1761 * 1762 * Note that although these registers are MCR on the primary 1763 * GT, the media GT's versions are regular singleton registers. 1764 */ 1765 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); 1766 wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1767 wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1768 } 1769 1770 debug_dump_steering(gt); 1771 } 1772 1773 /* 1774 * The bspec performance guide has recommended MMIO tuning settings. These 1775 * aren't truly "workarounds" but we want to program them through the 1776 * workaround infrastructure to make sure they're (re)applied at the proper 1777 * times. 1778 * 1779 * The programming in this function is for settings that persist through 1780 * engine resets and also are not part of any engine's register state context. 1781 * I.e., settings that only need to be re-applied in the event of a full GT 1782 * reset. 1783 */ 1784 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) 1785 { 1786 if (IS_PONTEVECCHIO(gt->i915)) { 1787 wa_mcr_write(wal, XEHPC_L3SCRUB, 1788 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 1789 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); 1790 } 1791 1792 if (IS_DG2(gt->i915)) 1793 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1794 } 1795 1796 static void 1797 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1798 { 1799 struct drm_i915_private *i915 = gt->i915; 1800 1801 gt_tuning_settings(gt, wal); 1802 1803 if (gt->type == GT_MEDIA) { 1804 if (MEDIA_VER(i915) >= 13) 1805 xelpmp_gt_workarounds_init(gt, wal); 1806 else 1807 MISSING_CASE(MEDIA_VER(i915)); 1808 1809 return; 1810 } 1811 1812 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1813 xelpg_gt_workarounds_init(gt, wal); 1814 else if (IS_PONTEVECCHIO(i915)) 1815 pvc_gt_workarounds_init(gt, wal); 1816 else if (IS_DG2(i915)) 1817 dg2_gt_workarounds_init(gt, wal); 1818 else if (IS_XEHPSDV(i915)) 1819 xehpsdv_gt_workarounds_init(gt, wal); 1820 else if (IS_DG1(i915)) 1821 dg1_gt_workarounds_init(gt, wal); 1822 else if (IS_TIGERLAKE(i915)) 1823 tgl_gt_workarounds_init(gt, wal); 1824 else if (GRAPHICS_VER(i915) == 12) 1825 gen12_gt_workarounds_init(gt, wal); 1826 else if (GRAPHICS_VER(i915) == 11) 1827 icl_gt_workarounds_init(gt, wal); 1828 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1829 cfl_gt_workarounds_init(gt, wal); 1830 else if (IS_GEMINILAKE(i915)) 1831 glk_gt_workarounds_init(gt, wal); 1832 else if (IS_KABYLAKE(i915)) 1833 kbl_gt_workarounds_init(gt, wal); 1834 else if (IS_BROXTON(i915)) 1835 gen9_gt_workarounds_init(gt, wal); 1836 else if (IS_SKYLAKE(i915)) 1837 skl_gt_workarounds_init(gt, wal); 1838 else if (IS_HASWELL(i915)) 1839 hsw_gt_workarounds_init(gt, wal); 1840 else if (IS_VALLEYVIEW(i915)) 1841 vlv_gt_workarounds_init(gt, wal); 1842 else if (IS_IVYBRIDGE(i915)) 1843 ivb_gt_workarounds_init(gt, wal); 1844 else if (GRAPHICS_VER(i915) == 6) 1845 snb_gt_workarounds_init(gt, wal); 1846 else if (GRAPHICS_VER(i915) == 5) 1847 ilk_gt_workarounds_init(gt, wal); 1848 else if (IS_G4X(i915)) 1849 g4x_gt_workarounds_init(gt, wal); 1850 else if (GRAPHICS_VER(i915) == 4) 1851 gen4_gt_workarounds_init(gt, wal); 1852 else if (GRAPHICS_VER(i915) <= 8) 1853 ; 1854 else 1855 MISSING_CASE(GRAPHICS_VER(i915)); 1856 } 1857 1858 void intel_gt_init_workarounds(struct intel_gt *gt) 1859 { 1860 struct i915_wa_list *wal = >->wa_list; 1861 1862 wa_init_start(wal, gt, "GT", "global"); 1863 gt_init_workarounds(gt, wal); 1864 wa_init_finish(wal); 1865 } 1866 1867 static enum forcewake_domains 1868 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1869 { 1870 enum forcewake_domains fw = 0; 1871 struct i915_wa *wa; 1872 unsigned int i; 1873 1874 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1875 fw |= intel_uncore_forcewake_for_reg(uncore, 1876 wa->reg, 1877 FW_REG_READ | 1878 FW_REG_WRITE); 1879 1880 return fw; 1881 } 1882 1883 static bool 1884 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1885 const char *name, const char *from) 1886 { 1887 if ((cur ^ wa->set) & wa->read) { 1888 drm_err(>->i915->drm, 1889 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1890 name, from, i915_mmio_reg_offset(wa->reg), 1891 cur, cur & wa->read, wa->set & wa->read); 1892 1893 return false; 1894 } 1895 1896 return true; 1897 } 1898 1899 static void wa_list_apply(const struct i915_wa_list *wal) 1900 { 1901 struct intel_gt *gt = wal->gt; 1902 struct intel_uncore *uncore = gt->uncore; 1903 enum forcewake_domains fw; 1904 unsigned long flags; 1905 struct i915_wa *wa; 1906 unsigned int i; 1907 1908 if (!wal->count) 1909 return; 1910 1911 fw = wal_get_fw_for_rmw(uncore, wal); 1912 1913 intel_gt_mcr_lock(gt, &flags); 1914 spin_lock(&uncore->lock); 1915 intel_uncore_forcewake_get__locked(uncore, fw); 1916 1917 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1918 u32 val, old = 0; 1919 1920 /* open-coded rmw due to steering */ 1921 if (wa->clr) 1922 old = wa->is_mcr ? 1923 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1924 intel_uncore_read_fw(uncore, wa->reg); 1925 val = (old & ~wa->clr) | wa->set; 1926 if (val != old || !wa->clr) { 1927 if (wa->is_mcr) 1928 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1929 else 1930 intel_uncore_write_fw(uncore, wa->reg, val); 1931 } 1932 1933 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1934 u32 val = wa->is_mcr ? 1935 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1936 intel_uncore_read_fw(uncore, wa->reg); 1937 1938 wa_verify(gt, wa, val, wal->name, "application"); 1939 } 1940 } 1941 1942 intel_uncore_forcewake_put__locked(uncore, fw); 1943 spin_unlock(&uncore->lock); 1944 intel_gt_mcr_unlock(gt, flags); 1945 } 1946 1947 void intel_gt_apply_workarounds(struct intel_gt *gt) 1948 { 1949 wa_list_apply(>->wa_list); 1950 } 1951 1952 static bool wa_list_verify(struct intel_gt *gt, 1953 const struct i915_wa_list *wal, 1954 const char *from) 1955 { 1956 struct intel_uncore *uncore = gt->uncore; 1957 struct i915_wa *wa; 1958 enum forcewake_domains fw; 1959 unsigned long flags; 1960 unsigned int i; 1961 bool ok = true; 1962 1963 fw = wal_get_fw_for_rmw(uncore, wal); 1964 1965 intel_gt_mcr_lock(gt, &flags); 1966 spin_lock(&uncore->lock); 1967 intel_uncore_forcewake_get__locked(uncore, fw); 1968 1969 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1970 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1971 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1972 intel_uncore_read_fw(uncore, wa->reg), 1973 wal->name, from); 1974 1975 intel_uncore_forcewake_put__locked(uncore, fw); 1976 spin_unlock(&uncore->lock); 1977 intel_gt_mcr_unlock(gt, flags); 1978 1979 return ok; 1980 } 1981 1982 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1983 { 1984 return wa_list_verify(gt, >->wa_list, from); 1985 } 1986 1987 __maybe_unused 1988 static bool is_nonpriv_flags_valid(u32 flags) 1989 { 1990 /* Check only valid flag bits are set */ 1991 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1992 return false; 1993 1994 /* NB: Only 3 out of 4 enum values are valid for access field */ 1995 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1996 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1997 return false; 1998 1999 return true; 2000 } 2001 2002 static void 2003 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 2004 { 2005 struct i915_wa wa = { 2006 .reg = reg 2007 }; 2008 2009 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 2010 return; 2011 2012 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 2013 return; 2014 2015 wa.reg.reg |= flags; 2016 _wa_add(wal, &wa); 2017 } 2018 2019 static void 2020 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 2021 { 2022 struct i915_wa wa = { 2023 .mcr_reg = reg, 2024 .is_mcr = 1, 2025 }; 2026 2027 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 2028 return; 2029 2030 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 2031 return; 2032 2033 wa.mcr_reg.reg |= flags; 2034 _wa_add(wal, &wa); 2035 } 2036 2037 static void 2038 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 2039 { 2040 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 2041 } 2042 2043 static void 2044 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 2045 { 2046 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 2047 } 2048 2049 static void gen9_whitelist_build(struct i915_wa_list *w) 2050 { 2051 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 2052 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2053 2054 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 2055 whitelist_reg(w, GEN8_CS_CHICKEN1); 2056 2057 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 2058 whitelist_reg(w, GEN8_HDC_CHICKEN1); 2059 2060 /* WaSendPushConstantsFromMMIO:skl,bxt */ 2061 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 2062 } 2063 2064 static void skl_whitelist_build(struct intel_engine_cs *engine) 2065 { 2066 struct i915_wa_list *w = &engine->whitelist; 2067 2068 if (engine->class != RENDER_CLASS) 2069 return; 2070 2071 gen9_whitelist_build(w); 2072 2073 /* WaDisableLSQCROPERFforOCL:skl */ 2074 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 2075 } 2076 2077 static void bxt_whitelist_build(struct intel_engine_cs *engine) 2078 { 2079 if (engine->class != RENDER_CLASS) 2080 return; 2081 2082 gen9_whitelist_build(&engine->whitelist); 2083 } 2084 2085 static void kbl_whitelist_build(struct intel_engine_cs *engine) 2086 { 2087 struct i915_wa_list *w = &engine->whitelist; 2088 2089 if (engine->class != RENDER_CLASS) 2090 return; 2091 2092 gen9_whitelist_build(w); 2093 2094 /* WaDisableLSQCROPERFforOCL:kbl */ 2095 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 2096 } 2097 2098 static void glk_whitelist_build(struct intel_engine_cs *engine) 2099 { 2100 struct i915_wa_list *w = &engine->whitelist; 2101 2102 if (engine->class != RENDER_CLASS) 2103 return; 2104 2105 gen9_whitelist_build(w); 2106 2107 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 2108 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2109 } 2110 2111 static void cfl_whitelist_build(struct intel_engine_cs *engine) 2112 { 2113 struct i915_wa_list *w = &engine->whitelist; 2114 2115 if (engine->class != RENDER_CLASS) 2116 return; 2117 2118 gen9_whitelist_build(w); 2119 2120 /* 2121 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 2122 * 2123 * This covers 4 register which are next to one another : 2124 * - PS_INVOCATION_COUNT 2125 * - PS_INVOCATION_COUNT_UDW 2126 * - PS_DEPTH_COUNT 2127 * - PS_DEPTH_COUNT_UDW 2128 */ 2129 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2130 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2131 RING_FORCE_TO_NONPRIV_RANGE_4); 2132 } 2133 2134 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 2135 { 2136 struct i915_wa_list *w = &engine->whitelist; 2137 2138 if (engine->class != RENDER_CLASS) 2139 whitelist_reg_ext(w, 2140 RING_CTX_TIMESTAMP(engine->mmio_base), 2141 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2142 } 2143 2144 static void cml_whitelist_build(struct intel_engine_cs *engine) 2145 { 2146 allow_read_ctx_timestamp(engine); 2147 2148 cfl_whitelist_build(engine); 2149 } 2150 2151 static void icl_whitelist_build(struct intel_engine_cs *engine) 2152 { 2153 struct i915_wa_list *w = &engine->whitelist; 2154 2155 allow_read_ctx_timestamp(engine); 2156 2157 switch (engine->class) { 2158 case RENDER_CLASS: 2159 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 2160 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 2161 2162 /* WaAllowUMDToModifySamplerMode:icl */ 2163 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2164 2165 /* WaEnableStateCacheRedirectToCS:icl */ 2166 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2167 2168 /* 2169 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2170 * 2171 * This covers 4 register which are next to one another : 2172 * - PS_INVOCATION_COUNT 2173 * - PS_INVOCATION_COUNT_UDW 2174 * - PS_DEPTH_COUNT 2175 * - PS_DEPTH_COUNT_UDW 2176 */ 2177 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2178 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2179 RING_FORCE_TO_NONPRIV_RANGE_4); 2180 break; 2181 2182 case VIDEO_DECODE_CLASS: 2183 /* hucStatusRegOffset */ 2184 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2185 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2186 /* hucUKernelHdrInfoRegOffset */ 2187 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2188 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2189 /* hucStatus2RegOffset */ 2190 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2191 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2192 break; 2193 2194 default: 2195 break; 2196 } 2197 } 2198 2199 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2200 { 2201 struct i915_wa_list *w = &engine->whitelist; 2202 2203 allow_read_ctx_timestamp(engine); 2204 2205 switch (engine->class) { 2206 case RENDER_CLASS: 2207 /* 2208 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2209 * Wa_1408556865:tgl 2210 * 2211 * This covers 4 registers which are next to one another : 2212 * - PS_INVOCATION_COUNT 2213 * - PS_INVOCATION_COUNT_UDW 2214 * - PS_DEPTH_COUNT 2215 * - PS_DEPTH_COUNT_UDW 2216 */ 2217 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2218 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2219 RING_FORCE_TO_NONPRIV_RANGE_4); 2220 2221 /* 2222 * Wa_1808121037:tgl 2223 * Wa_14012131227:dg1 2224 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2225 */ 2226 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2227 2228 /* Wa_1806527549:tgl */ 2229 whitelist_reg(w, HIZ_CHICKEN); 2230 break; 2231 default: 2232 break; 2233 } 2234 } 2235 2236 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2237 { 2238 struct i915_wa_list *w = &engine->whitelist; 2239 2240 tgl_whitelist_build(engine); 2241 2242 /* GEN:BUG:1409280441:dg1 */ 2243 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2244 (engine->class == RENDER_CLASS || 2245 engine->class == COPY_ENGINE_CLASS)) 2246 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2247 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2248 } 2249 2250 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2251 { 2252 allow_read_ctx_timestamp(engine); 2253 } 2254 2255 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2256 { 2257 struct i915_wa_list *w = &engine->whitelist; 2258 2259 allow_read_ctx_timestamp(engine); 2260 2261 switch (engine->class) { 2262 case RENDER_CLASS: 2263 /* 2264 * Wa_1507100340:dg2_g10 2265 * 2266 * This covers 4 registers which are next to one another : 2267 * - PS_INVOCATION_COUNT 2268 * - PS_INVOCATION_COUNT_UDW 2269 * - PS_DEPTH_COUNT 2270 * - PS_DEPTH_COUNT_UDW 2271 */ 2272 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2273 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2274 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2275 RING_FORCE_TO_NONPRIV_RANGE_4); 2276 2277 break; 2278 case COMPUTE_CLASS: 2279 /* Wa_16011157294:dg2_g10 */ 2280 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2281 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2282 break; 2283 default: 2284 break; 2285 } 2286 } 2287 2288 static void blacklist_trtt(struct intel_engine_cs *engine) 2289 { 2290 struct i915_wa_list *w = &engine->whitelist; 2291 2292 /* 2293 * Prevent read/write access to [0x4400, 0x4600) which covers 2294 * the TRTT range across all engines. Note that normally userspace 2295 * cannot access the other engines' trtt control, but for simplicity 2296 * we cover the entire range on each engine. 2297 */ 2298 whitelist_reg_ext(w, _MMIO(0x4400), 2299 RING_FORCE_TO_NONPRIV_DENY | 2300 RING_FORCE_TO_NONPRIV_RANGE_64); 2301 whitelist_reg_ext(w, _MMIO(0x4500), 2302 RING_FORCE_TO_NONPRIV_DENY | 2303 RING_FORCE_TO_NONPRIV_RANGE_64); 2304 } 2305 2306 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2307 { 2308 allow_read_ctx_timestamp(engine); 2309 2310 /* Wa_16014440446:pvc */ 2311 blacklist_trtt(engine); 2312 } 2313 2314 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2315 { 2316 struct drm_i915_private *i915 = engine->i915; 2317 struct i915_wa_list *w = &engine->whitelist; 2318 2319 wa_init_start(w, engine->gt, "whitelist", engine->name); 2320 2321 if (IS_METEORLAKE(i915)) 2322 ; /* noop; none at this time */ 2323 else if (IS_PONTEVECCHIO(i915)) 2324 pvc_whitelist_build(engine); 2325 else if (IS_DG2(i915)) 2326 dg2_whitelist_build(engine); 2327 else if (IS_XEHPSDV(i915)) 2328 xehpsdv_whitelist_build(engine); 2329 else if (IS_DG1(i915)) 2330 dg1_whitelist_build(engine); 2331 else if (GRAPHICS_VER(i915) == 12) 2332 tgl_whitelist_build(engine); 2333 else if (GRAPHICS_VER(i915) == 11) 2334 icl_whitelist_build(engine); 2335 else if (IS_COMETLAKE(i915)) 2336 cml_whitelist_build(engine); 2337 else if (IS_COFFEELAKE(i915)) 2338 cfl_whitelist_build(engine); 2339 else if (IS_GEMINILAKE(i915)) 2340 glk_whitelist_build(engine); 2341 else if (IS_KABYLAKE(i915)) 2342 kbl_whitelist_build(engine); 2343 else if (IS_BROXTON(i915)) 2344 bxt_whitelist_build(engine); 2345 else if (IS_SKYLAKE(i915)) 2346 skl_whitelist_build(engine); 2347 else if (GRAPHICS_VER(i915) <= 8) 2348 ; 2349 else 2350 MISSING_CASE(GRAPHICS_VER(i915)); 2351 2352 wa_init_finish(w); 2353 } 2354 2355 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2356 { 2357 const struct i915_wa_list *wal = &engine->whitelist; 2358 struct intel_uncore *uncore = engine->uncore; 2359 const u32 base = engine->mmio_base; 2360 struct i915_wa *wa; 2361 unsigned int i; 2362 2363 if (!wal->count) 2364 return; 2365 2366 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2367 intel_uncore_write(uncore, 2368 RING_FORCE_TO_NONPRIV(base, i), 2369 i915_mmio_reg_offset(wa->reg)); 2370 2371 /* And clear the rest just in case of garbage */ 2372 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2373 intel_uncore_write(uncore, 2374 RING_FORCE_TO_NONPRIV(base, i), 2375 i915_mmio_reg_offset(RING_NOPID(base))); 2376 } 2377 2378 /* 2379 * engine_fake_wa_init(), a place holder to program the registers 2380 * which are not part of an official workaround defined by the 2381 * hardware team. 2382 * Adding programming of those register inside workaround will 2383 * allow utilizing wa framework to proper application and verification. 2384 */ 2385 static void 2386 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2387 { 2388 u8 mocs_w, mocs_r; 2389 2390 /* 2391 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2392 * by the command streamer when executing commands that don't have 2393 * a way to explicitly specify a MOCS setting. The default should 2394 * usually reference whichever MOCS entry corresponds to uncached 2395 * behavior, although use of a WB cached entry is recommended by the 2396 * spec in certain circumstances on specific platforms. 2397 */ 2398 if (GRAPHICS_VER(engine->i915) >= 12) { 2399 mocs_r = engine->gt->mocs.uc_index; 2400 mocs_w = engine->gt->mocs.uc_index; 2401 2402 if (HAS_L3_CCS_READ(engine->i915) && 2403 engine->class == COMPUTE_CLASS) { 2404 mocs_r = engine->gt->mocs.wb_index; 2405 2406 /* 2407 * Even on the few platforms where MOCS 0 is a 2408 * legitimate table entry, it's never the correct 2409 * setting to use here; we can assume the MOCS init 2410 * just forgot to initialize wb_index. 2411 */ 2412 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2413 } 2414 2415 wa_masked_field_set(wal, 2416 RING_CMD_CCTL(engine->mmio_base), 2417 CMD_CCTL_MOCS_MASK, 2418 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2419 } 2420 } 2421 2422 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2423 { 2424 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2425 GEN_DSS_PER_GSLICE; 2426 } 2427 2428 static void 2429 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2430 { 2431 struct drm_i915_private *i915 = engine->i915; 2432 2433 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2434 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 2435 /* Wa_22014600077 */ 2436 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2437 ENABLE_EU_COUNT_FOR_TDL_FLUSH); 2438 } 2439 2440 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2441 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 2442 IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2443 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2444 /* Wa_1509727124 */ 2445 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2446 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2447 } 2448 2449 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2450 IS_DG2_G11(i915) || IS_DG2_G12(i915) || 2451 IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) { 2452 /* Wa_22012856258 */ 2453 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2454 GEN12_DISABLE_READ_SUPPRESSION); 2455 } 2456 2457 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2458 /* Wa_14013392000:dg2_g11 */ 2459 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2460 } 2461 2462 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2463 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2464 /* Wa_14012419201:dg2 */ 2465 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2466 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2467 } 2468 2469 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2470 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2471 needs_wa_1308578152(engine)) { 2472 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2473 GEN12_REPLAY_MODE_GRANULARITY); 2474 } 2475 2476 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2477 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2478 /* 2479 * Wa_22010960976:dg2 2480 * Wa_14013347512:dg2 2481 */ 2482 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2483 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2484 } 2485 2486 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2487 /* 2488 * Wa_1608949956:dg2_g10 2489 * Wa_14010198302:dg2_g10 2490 */ 2491 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2492 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2493 } 2494 2495 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) 2496 /* Wa_22010430635:dg2 */ 2497 wa_mcr_masked_en(wal, 2498 GEN9_ROW_CHICKEN4, 2499 GEN12_DISABLE_GRF_CLEAR); 2500 2501 /* Wa_14013202645:dg2 */ 2502 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2503 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2504 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2505 2506 /* Wa_22012532006:dg2 */ 2507 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2508 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2509 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2510 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2511 2512 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2513 IS_DG2_G10(i915)) { 2514 /* Wa_22014600077:dg2 */ 2515 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2516 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2517 0 /* Wa_14012342262 write-only reg, so skip verification */, 2518 true); 2519 } 2520 2521 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2522 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2523 /* 2524 * Wa_1607138336:tgl[a0],dg1[a0] 2525 * Wa_1607063988:tgl[a0],dg1[a0] 2526 */ 2527 wa_write_or(wal, 2528 GEN9_CTX_PREEMPT_REG, 2529 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2530 } 2531 2532 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2533 /* 2534 * Wa_1606679103:tgl 2535 * (see also Wa_1606682166:icl) 2536 */ 2537 wa_write_or(wal, 2538 GEN7_SARCHKMD, 2539 GEN7_DISABLE_SAMPLER_PREFETCH); 2540 } 2541 2542 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2543 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2544 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2545 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2546 2547 /* 2548 * Wa_1407928979:tgl A* 2549 * Wa_18011464164:tgl[B0+],dg1[B0+] 2550 * Wa_22010931296:tgl[B0+],dg1[B0+] 2551 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2552 */ 2553 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2554 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2555 } 2556 2557 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2558 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2559 /* 2560 * Wa_1606700617:tgl,dg1,adl-p 2561 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2562 * Wa_14010826681:tgl,dg1,rkl,adl-p 2563 * Wa_18019627453:dg2 2564 */ 2565 wa_masked_en(wal, 2566 GEN9_CS_DEBUG_MODE1, 2567 FF_DOP_CLOCK_GATE_DISABLE); 2568 } 2569 2570 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2571 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2572 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2573 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2574 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2575 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2576 2577 /* 2578 * Wa_1409085225:tgl 2579 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2580 */ 2581 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2582 } 2583 2584 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2585 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2586 /* 2587 * Wa_1607030317:tgl 2588 * Wa_1607186500:tgl 2589 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2590 * 2591 * On TGL and RKL there are multiple entries for this WA in the 2592 * BSpec; some indicate this is an A0-only WA, others indicate 2593 * it applies to all steppings so we trust the "all steppings." 2594 * For DG1 this only applies to A0. 2595 */ 2596 wa_masked_en(wal, 2597 RING_PSMI_CTL(RENDER_RING_BASE), 2598 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2599 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2600 } 2601 2602 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2603 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2604 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2605 wa_mcr_masked_en(wal, 2606 GEN10_SAMPLER_MODE, 2607 ENABLE_SMALLPL); 2608 } 2609 2610 if (GRAPHICS_VER(i915) == 11) { 2611 /* This is not an Wa. Enable for better image quality */ 2612 wa_masked_en(wal, 2613 _3D_CHICKEN3, 2614 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2615 2616 /* 2617 * Wa_1405543622:icl 2618 * Formerly known as WaGAPZPriorityScheme 2619 */ 2620 wa_write_or(wal, 2621 GEN8_GARBCNTL, 2622 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2623 2624 /* 2625 * Wa_1604223664:icl 2626 * Formerly known as WaL3BankAddressHashing 2627 */ 2628 wa_write_clr_set(wal, 2629 GEN8_GARBCNTL, 2630 GEN11_HASH_CTRL_EXCL_MASK, 2631 GEN11_HASH_CTRL_EXCL_BIT0); 2632 wa_write_clr_set(wal, 2633 GEN11_GLBLINVL, 2634 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2635 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2636 2637 /* 2638 * Wa_1405733216:icl 2639 * Formerly known as WaDisableCleanEvicts 2640 */ 2641 wa_mcr_write_or(wal, 2642 GEN8_L3SQCREG4, 2643 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2644 2645 /* Wa_1606682166:icl */ 2646 wa_write_or(wal, 2647 GEN7_SARCHKMD, 2648 GEN7_DISABLE_SAMPLER_PREFETCH); 2649 2650 /* Wa_1409178092:icl */ 2651 wa_mcr_write_clr_set(wal, 2652 GEN11_SCRATCH2, 2653 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2654 0); 2655 2656 /* WaEnable32PlaneMode:icl */ 2657 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2658 GEN11_ENABLE_32_PLANE_MODE); 2659 2660 /* 2661 * Wa_1408767742:icl[a2..forever],ehl[all] 2662 * Wa_1605460711:icl[a0..c0] 2663 */ 2664 wa_write_or(wal, 2665 GEN7_FF_THREAD_MODE, 2666 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2667 2668 /* Wa_22010271021 */ 2669 wa_masked_en(wal, 2670 GEN9_CS_DEBUG_MODE1, 2671 FF_DOP_CLOCK_GATE_DISABLE); 2672 } 2673 2674 /* 2675 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2676 * beyond) allow the kernel-mode driver to choose between two different 2677 * options for controlling preemption granularity and behavior. 2678 * 2679 * Option 1 (hardware default): 2680 * Preemption settings are controlled in a global manner via 2681 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2682 * and settings chosen by the kernel-mode driver will apply to all 2683 * userspace clients. 2684 * 2685 * Option 2: 2686 * Preemption settings are controlled on a per-context basis via 2687 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2688 * context switch and is writable by userspace (e.g., via 2689 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2690 * which allows different userspace drivers/clients to select 2691 * different settings, or to change those settings on the fly in 2692 * response to runtime needs. This option was known by name 2693 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2694 * that name is somewhat misleading as other non-granularity 2695 * preemption settings are also impacted by this decision. 2696 * 2697 * On Linux, our policy has always been to let userspace drivers 2698 * control preemption granularity/settings (Option 2). This was 2699 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2700 * userspace developed before object-level preemption was enabled would 2701 * not behave well if i915 were to go with Option 1 and enable that 2702 * preemption in a global manner). On gen9 each context would have 2703 * object-level preemption disabled by default (see 2704 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2705 * userspace drivers could opt-in to object-level preemption as they 2706 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2707 * even though it is no longer necessary for ABI compatibility when 2708 * enabling a new platform, it does ensure that userspace will be able 2709 * to implement any workarounds that show up requiring temporary 2710 * adjustments to preemption behavior at runtime. 2711 * 2712 * Notes/Workarounds: 2713 * - Wa_14015141709: On DG2 and early steppings of MTL, 2714 * CS_CHICKEN1[0] does not disable object-level preemption as 2715 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2716 * using Option 1). Effectively this means userspace is unable 2717 * to disable object-level preemption on these platforms/steppings 2718 * despite the setting here. 2719 * 2720 * - Wa_16013994831: May require that userspace program 2721 * CS_CHICKEN1[10] when certain runtime conditions are true. 2722 * Userspace requires Option 2 to be in effect for their update of 2723 * CS_CHICKEN1[10] to be effective. 2724 * 2725 * Other workarounds may appear in the future that will also require 2726 * Option 2 behavior to allow proper userspace implementation. 2727 */ 2728 if (GRAPHICS_VER(i915) >= 9) 2729 wa_masked_en(wal, 2730 GEN7_FF_SLICE_CS_CHICKEN1, 2731 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2732 2733 if (IS_SKYLAKE(i915) || 2734 IS_KABYLAKE(i915) || 2735 IS_COFFEELAKE(i915) || 2736 IS_COMETLAKE(i915)) { 2737 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2738 wa_write_or(wal, 2739 GEN8_GARBCNTL, 2740 GEN9_GAPS_TSV_CREDIT_DISABLE); 2741 } 2742 2743 if (IS_BROXTON(i915)) { 2744 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2745 wa_masked_en(wal, 2746 FF_SLICE_CS_CHICKEN2, 2747 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2748 } 2749 2750 if (GRAPHICS_VER(i915) == 9) { 2751 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2752 wa_masked_en(wal, 2753 GEN9_CSFE_CHICKEN1_RCS, 2754 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2755 2756 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2757 wa_mcr_write_or(wal, 2758 BDW_SCRATCH1, 2759 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2760 2761 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2762 if (IS_GEN9_LP(i915)) 2763 wa_mcr_write_clr_set(wal, 2764 GEN8_L3SQCREG1, 2765 L3_PRIO_CREDITS_MASK, 2766 L3_GENERAL_PRIO_CREDITS(62) | 2767 L3_HIGH_PRIO_CREDITS(2)); 2768 2769 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2770 wa_mcr_write_or(wal, 2771 GEN8_L3SQCREG4, 2772 GEN8_LQSC_FLUSH_COHERENT_LINES); 2773 2774 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2775 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2776 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2777 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2778 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2779 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2780 EVICTION_PERF_FIX_ENABLE, 0); 2781 } 2782 2783 if (IS_HASWELL(i915)) { 2784 /* WaSampleCChickenBitEnable:hsw */ 2785 wa_masked_en(wal, 2786 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2787 2788 wa_masked_dis(wal, 2789 CACHE_MODE_0_GEN7, 2790 /* enable HiZ Raw Stall Optimization */ 2791 HIZ_RAW_STALL_OPT_DISABLE); 2792 } 2793 2794 if (IS_VALLEYVIEW(i915)) { 2795 /* WaDisableEarlyCull:vlv */ 2796 wa_masked_en(wal, 2797 _3D_CHICKEN3, 2798 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2799 2800 /* 2801 * WaVSThreadDispatchOverride:ivb,vlv 2802 * 2803 * This actually overrides the dispatch 2804 * mode for all thread types. 2805 */ 2806 wa_write_clr_set(wal, 2807 GEN7_FF_THREAD_MODE, 2808 GEN7_FF_SCHED_MASK, 2809 GEN7_FF_TS_SCHED_HW | 2810 GEN7_FF_VS_SCHED_HW | 2811 GEN7_FF_DS_SCHED_HW); 2812 2813 /* WaPsdDispatchEnable:vlv */ 2814 /* WaDisablePSDDualDispatchEnable:vlv */ 2815 wa_masked_en(wal, 2816 GEN7_HALF_SLICE_CHICKEN1, 2817 GEN7_MAX_PS_THREAD_DEP | 2818 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2819 } 2820 2821 if (IS_IVYBRIDGE(i915)) { 2822 /* WaDisableEarlyCull:ivb */ 2823 wa_masked_en(wal, 2824 _3D_CHICKEN3, 2825 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2826 2827 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2828 /* enable HiZ Raw Stall Optimization */ 2829 wa_masked_dis(wal, 2830 CACHE_MODE_0_GEN7, 2831 HIZ_RAW_STALL_OPT_DISABLE); 2832 } 2833 2834 /* 2835 * WaVSThreadDispatchOverride:ivb,vlv 2836 * 2837 * This actually overrides the dispatch 2838 * mode for all thread types. 2839 */ 2840 wa_write_clr_set(wal, 2841 GEN7_FF_THREAD_MODE, 2842 GEN7_FF_SCHED_MASK, 2843 GEN7_FF_TS_SCHED_HW | 2844 GEN7_FF_VS_SCHED_HW | 2845 GEN7_FF_DS_SCHED_HW); 2846 2847 /* WaDisablePSDDualDispatchEnable:ivb */ 2848 if (IS_IVB_GT1(i915)) 2849 wa_masked_en(wal, 2850 GEN7_HALF_SLICE_CHICKEN1, 2851 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2852 } 2853 2854 if (GRAPHICS_VER(i915) == 7) { 2855 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2856 wa_masked_en(wal, 2857 RING_MODE_GEN7(RENDER_RING_BASE), 2858 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2859 2860 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2861 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2862 2863 /* 2864 * BSpec says this must be set, even though 2865 * WaDisable4x2SubspanOptimization:ivb,hsw 2866 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2867 */ 2868 wa_masked_en(wal, 2869 CACHE_MODE_1, 2870 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2871 2872 /* 2873 * BSpec recommends 8x4 when MSAA is used, 2874 * however in practice 16x4 seems fastest. 2875 * 2876 * Note that PS/WM thread counts depend on the WIZ hashing 2877 * disable bit, which we don't touch here, but it's good 2878 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2879 */ 2880 wa_masked_field_set(wal, 2881 GEN7_GT_MODE, 2882 GEN6_WIZ_HASHING_MASK, 2883 GEN6_WIZ_HASHING_16x4); 2884 } 2885 2886 if (IS_GRAPHICS_VER(i915, 6, 7)) 2887 /* 2888 * We need to disable the AsyncFlip performance optimisations in 2889 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2890 * already be programmed to '1' on all products. 2891 * 2892 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2893 */ 2894 wa_masked_en(wal, 2895 RING_MI_MODE(RENDER_RING_BASE), 2896 ASYNC_FLIP_PERF_DISABLE); 2897 2898 if (GRAPHICS_VER(i915) == 6) { 2899 /* 2900 * Required for the hardware to program scanline values for 2901 * waiting 2902 * WaEnableFlushTlbInvalidationMode:snb 2903 */ 2904 wa_masked_en(wal, 2905 GFX_MODE, 2906 GFX_TLB_INVALIDATE_EXPLICIT); 2907 2908 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2909 wa_masked_en(wal, 2910 _3D_CHICKEN, 2911 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2912 2913 wa_masked_en(wal, 2914 _3D_CHICKEN3, 2915 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2916 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2917 /* 2918 * Bspec says: 2919 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2920 * to normal and 3DSTATE_SF number of SF output attributes 2921 * is more than 16." 2922 */ 2923 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2924 2925 /* 2926 * BSpec recommends 8x4 when MSAA is used, 2927 * however in practice 16x4 seems fastest. 2928 * 2929 * Note that PS/WM thread counts depend on the WIZ hashing 2930 * disable bit, which we don't touch here, but it's good 2931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2932 */ 2933 wa_masked_field_set(wal, 2934 GEN6_GT_MODE, 2935 GEN6_WIZ_HASHING_MASK, 2936 GEN6_WIZ_HASHING_16x4); 2937 2938 /* WaDisable_RenderCache_OperationalFlush:snb */ 2939 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2940 2941 /* 2942 * From the Sandybridge PRM, volume 1 part 3, page 24: 2943 * "If this bit is set, STCunit will have LRA as replacement 2944 * policy. [...] This bit must be reset. LRA replacement 2945 * policy is not supported." 2946 */ 2947 wa_masked_dis(wal, 2948 CACHE_MODE_0, 2949 CM0_STC_EVICT_DISABLE_LRA_SNB); 2950 } 2951 2952 if (IS_GRAPHICS_VER(i915, 4, 6)) 2953 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2954 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2955 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2956 /* XXX bit doesn't stick on Broadwater */ 2957 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2958 2959 if (GRAPHICS_VER(i915) == 4) 2960 /* 2961 * Disable CONSTANT_BUFFER before it is loaded from the context 2962 * image. For as it is loaded, it is executed and the stored 2963 * address may no longer be valid, leading to a GPU hang. 2964 * 2965 * This imposes the requirement that userspace reload their 2966 * CONSTANT_BUFFER on every batch, fortunately a requirement 2967 * they are already accustomed to from before contexts were 2968 * enabled. 2969 */ 2970 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2971 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2972 0 /* XXX bit doesn't stick on Broadwater */, 2973 true); 2974 } 2975 2976 static void 2977 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2978 { 2979 struct drm_i915_private *i915 = engine->i915; 2980 2981 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2982 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2983 wa_write(wal, 2984 RING_SEMA_WAIT_POLL(engine->mmio_base), 2985 1); 2986 } 2987 } 2988 2989 static void 2990 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2991 { 2992 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2993 /* Wa_14014999345:pvc */ 2994 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2995 } 2996 } 2997 2998 /* 2999 * The bspec performance guide has recommended MMIO tuning settings. These 3000 * aren't truly "workarounds" but we want to program them with the same 3001 * workaround infrastructure to ensure that they're automatically added to 3002 * the GuC save/restore lists, re-applied at the right times, and checked for 3003 * any conflicting programming requested by real workarounds. 3004 * 3005 * Programming settings should be added here only if their registers are not 3006 * part of an engine's register state context. If a register is part of a 3007 * context, then any tuning settings should be programmed in an appropriate 3008 * function invoked by __intel_engine_init_ctx_wa(). 3009 */ 3010 static void 3011 add_render_compute_tuning_settings(struct drm_i915_private *i915, 3012 struct i915_wa_list *wal) 3013 { 3014 if (IS_DG2(i915)) 3015 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 3016 3017 /* 3018 * This tuning setting proves beneficial only on ATS-M designs; the 3019 * default "age based" setting is optimal on regular DG2 and other 3020 * platforms. 3021 */ 3022 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 3023 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 3024 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 3025 3026 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 3027 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 3028 } 3029 3030 /* 3031 * The workarounds in this function apply to shared registers in 3032 * the general render reset domain that aren't tied to a 3033 * specific engine. Since all render+compute engines get reset 3034 * together, and the contents of these registers are lost during 3035 * the shared render domain reset, we'll define such workarounds 3036 * here and then add them to just a single RCS or CCS engine's 3037 * workaround list (whichever engine has the XXXX flag). 3038 */ 3039 static void 3040 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3041 { 3042 struct drm_i915_private *i915 = engine->i915; 3043 3044 add_render_compute_tuning_settings(i915, wal); 3045 3046 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3047 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3048 IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 3049 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 3050 /* Wa_22013037850 */ 3051 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 3052 DISABLE_128B_EVICTION_COMMAND_UDW); 3053 } 3054 3055 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3056 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3057 IS_PONTEVECCHIO(i915) || 3058 IS_DG2(i915)) { 3059 /* Wa_22014226127 */ 3060 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 3061 } 3062 3063 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3064 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3065 IS_DG2(i915)) { 3066 /* Wa_18017747507 */ 3067 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3068 } 3069 3070 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 3071 IS_DG2_G11(i915)) { 3072 /* 3073 * Wa_22012826095:dg2 3074 * Wa_22013059131:dg2 3075 */ 3076 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 3077 MAXREQS_PER_BANK, 3078 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 3079 3080 /* Wa_22013059131:dg2 */ 3081 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 3082 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 3083 } 3084 3085 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 3086 /* 3087 * Wa_14010918519:dg2_g10 3088 * 3089 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 3090 * so ignoring verification. 3091 */ 3092 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 3093 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 3094 0, false); 3095 } 3096 3097 if (IS_XEHPSDV(i915)) { 3098 /* Wa_1409954639 */ 3099 wa_mcr_masked_en(wal, 3100 GEN8_ROW_CHICKEN, 3101 SYSTOLIC_DOP_CLOCK_GATING_DIS); 3102 3103 /* Wa_1607196519 */ 3104 wa_mcr_masked_en(wal, 3105 GEN9_ROW_CHICKEN4, 3106 GEN12_DISABLE_GRF_CLEAR); 3107 3108 /* Wa_14010449647:xehpsdv */ 3109 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 3110 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 3111 } 3112 3113 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 3114 /* Wa_14015227452:dg2,pvc */ 3115 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 3116 3117 /* Wa_16015675438:dg2,pvc */ 3118 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 3119 } 3120 3121 if (IS_DG2(i915)) { 3122 /* 3123 * Wa_16011620976:dg2_g11 3124 * Wa_22015475538:dg2 3125 */ 3126 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3127 } 3128 3129 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915)) 3130 /* 3131 * Wa_22012654132 3132 * 3133 * Note that register 0xE420 is write-only and cannot be read 3134 * back for verification on DG2 (due to Wa_14012342262), so 3135 * we need to explicitly skip the readback. 3136 */ 3137 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 3138 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 3139 0 /* write-only, so skip validation */, 3140 true); 3141 } 3142 3143 static void 3144 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3145 { 3146 if (GRAPHICS_VER(engine->i915) < 4) 3147 return; 3148 3149 engine_fake_wa_init(engine, wal); 3150 3151 /* 3152 * These are common workarounds that just need to applied 3153 * to a single RCS/CCS engine's workaround list since 3154 * they're reset as part of the general render domain reset. 3155 */ 3156 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3157 general_render_compute_wa_init(engine, wal); 3158 3159 if (engine->class == COMPUTE_CLASS) 3160 ccs_engine_wa_init(engine, wal); 3161 else if (engine->class == RENDER_CLASS) 3162 rcs_engine_wa_init(engine, wal); 3163 else 3164 xcs_engine_wa_init(engine, wal); 3165 } 3166 3167 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3168 { 3169 struct i915_wa_list *wal = &engine->wa_list; 3170 3171 wa_init_start(wal, engine->gt, "engine", engine->name); 3172 engine_init_workarounds(engine, wal); 3173 wa_init_finish(wal); 3174 } 3175 3176 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3177 { 3178 wa_list_apply(&engine->wa_list); 3179 } 3180 3181 static const struct i915_range mcr_ranges_gen8[] = { 3182 { .start = 0x5500, .end = 0x55ff }, 3183 { .start = 0x7000, .end = 0x7fff }, 3184 { .start = 0x9400, .end = 0x97ff }, 3185 { .start = 0xb000, .end = 0xb3ff }, 3186 { .start = 0xe000, .end = 0xe7ff }, 3187 {}, 3188 }; 3189 3190 static const struct i915_range mcr_ranges_gen12[] = { 3191 { .start = 0x8150, .end = 0x815f }, 3192 { .start = 0x9520, .end = 0x955f }, 3193 { .start = 0xb100, .end = 0xb3ff }, 3194 { .start = 0xde80, .end = 0xe8ff }, 3195 { .start = 0x24a00, .end = 0x24a7f }, 3196 {}, 3197 }; 3198 3199 static const struct i915_range mcr_ranges_xehp[] = { 3200 { .start = 0x4000, .end = 0x4aff }, 3201 { .start = 0x5200, .end = 0x52ff }, 3202 { .start = 0x5400, .end = 0x7fff }, 3203 { .start = 0x8140, .end = 0x815f }, 3204 { .start = 0x8c80, .end = 0x8dff }, 3205 { .start = 0x94d0, .end = 0x955f }, 3206 { .start = 0x9680, .end = 0x96ff }, 3207 { .start = 0xb000, .end = 0xb3ff }, 3208 { .start = 0xc800, .end = 0xcfff }, 3209 { .start = 0xd800, .end = 0xd8ff }, 3210 { .start = 0xdc00, .end = 0xffff }, 3211 { .start = 0x17000, .end = 0x17fff }, 3212 { .start = 0x24a00, .end = 0x24a7f }, 3213 {}, 3214 }; 3215 3216 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3217 { 3218 const struct i915_range *mcr_ranges; 3219 int i; 3220 3221 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3222 mcr_ranges = mcr_ranges_xehp; 3223 else if (GRAPHICS_VER(i915) >= 12) 3224 mcr_ranges = mcr_ranges_gen12; 3225 else if (GRAPHICS_VER(i915) >= 8) 3226 mcr_ranges = mcr_ranges_gen8; 3227 else 3228 return false; 3229 3230 /* 3231 * Registers in these ranges are affected by the MCR selector 3232 * which only controls CPU initiated MMIO. Routing does not 3233 * work for CS access so we cannot verify them on this path. 3234 */ 3235 for (i = 0; mcr_ranges[i].start; i++) 3236 if (offset >= mcr_ranges[i].start && 3237 offset <= mcr_ranges[i].end) 3238 return true; 3239 3240 return false; 3241 } 3242 3243 static int 3244 wa_list_srm(struct i915_request *rq, 3245 const struct i915_wa_list *wal, 3246 struct i915_vma *vma) 3247 { 3248 struct drm_i915_private *i915 = rq->engine->i915; 3249 unsigned int i, count = 0; 3250 const struct i915_wa *wa; 3251 u32 srm, *cs; 3252 3253 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3254 if (GRAPHICS_VER(i915) >= 8) 3255 srm++; 3256 3257 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3258 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3259 count++; 3260 } 3261 3262 cs = intel_ring_begin(rq, 4 * count); 3263 if (IS_ERR(cs)) 3264 return PTR_ERR(cs); 3265 3266 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3267 u32 offset = i915_mmio_reg_offset(wa->reg); 3268 3269 if (mcr_range(i915, offset)) 3270 continue; 3271 3272 *cs++ = srm; 3273 *cs++ = offset; 3274 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3275 *cs++ = 0; 3276 } 3277 intel_ring_advance(rq, cs); 3278 3279 return 0; 3280 } 3281 3282 static int engine_wa_list_verify(struct intel_context *ce, 3283 const struct i915_wa_list * const wal, 3284 const char *from) 3285 { 3286 const struct i915_wa *wa; 3287 struct i915_request *rq; 3288 struct i915_vma *vma; 3289 struct i915_gem_ww_ctx ww; 3290 unsigned int i; 3291 u32 *results; 3292 int err; 3293 3294 if (!wal->count) 3295 return 0; 3296 3297 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3298 wal->count * sizeof(u32)); 3299 if (IS_ERR(vma)) 3300 return PTR_ERR(vma); 3301 3302 intel_engine_pm_get(ce->engine); 3303 i915_gem_ww_ctx_init(&ww, false); 3304 retry: 3305 err = i915_gem_object_lock(vma->obj, &ww); 3306 if (err == 0) 3307 err = intel_context_pin_ww(ce, &ww); 3308 if (err) 3309 goto err_pm; 3310 3311 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3312 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3313 if (err) 3314 goto err_unpin; 3315 3316 rq = i915_request_create(ce); 3317 if (IS_ERR(rq)) { 3318 err = PTR_ERR(rq); 3319 goto err_vma; 3320 } 3321 3322 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3323 if (err == 0) 3324 err = wa_list_srm(rq, wal, vma); 3325 3326 i915_request_get(rq); 3327 if (err) 3328 i915_request_set_error_once(rq, err); 3329 i915_request_add(rq); 3330 3331 if (err) 3332 goto err_rq; 3333 3334 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3335 err = -ETIME; 3336 goto err_rq; 3337 } 3338 3339 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3340 if (IS_ERR(results)) { 3341 err = PTR_ERR(results); 3342 goto err_rq; 3343 } 3344 3345 err = 0; 3346 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3347 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3348 continue; 3349 3350 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3351 err = -ENXIO; 3352 } 3353 3354 i915_gem_object_unpin_map(vma->obj); 3355 3356 err_rq: 3357 i915_request_put(rq); 3358 err_vma: 3359 i915_vma_unpin(vma); 3360 err_unpin: 3361 intel_context_unpin(ce); 3362 err_pm: 3363 if (err == -EDEADLK) { 3364 err = i915_gem_ww_ctx_backoff(&ww); 3365 if (!err) 3366 goto retry; 3367 } 3368 i915_gem_ww_ctx_fini(&ww); 3369 intel_engine_pm_put(ce->engine); 3370 i915_vma_put(vma); 3371 return err; 3372 } 3373 3374 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3375 const char *from) 3376 { 3377 return engine_wa_list_verify(engine->kernel_context, 3378 &engine->wa_list, 3379 from); 3380 } 3381 3382 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3383 #include "selftest_workarounds.c" 3384 #endif 3385