1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_engine_regs.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_gt_regs.h" 13 #include "intel_ring.h" 14 #include "intel_workarounds.h" 15 16 /** 17 * DOC: Hardware workarounds 18 * 19 * This file is intended as a central place to implement most [1]_ of the 20 * required workarounds for hardware to work as originally intended. They fall 21 * in five basic categories depending on how/when they are applied: 22 * 23 * - Workarounds that touch registers that are saved/restored to/from the HW 24 * context image. The list is emitted (via Load Register Immediate commands) 25 * everytime a new context is created. 26 * - GT workarounds. The list of these WAs is applied whenever these registers 27 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 28 * - Display workarounds. The list is applied during display clock-gating 29 * initialization. 30 * - Workarounds that whitelist a privileged register, so that UMDs can manage 31 * them directly. This is just a special case of a MMMIO workaround (as we 32 * write the list of these to/be-whitelisted registers to some special HW 33 * registers). 34 * - Workaround batchbuffers, that get executed automatically by the hardware 35 * on every HW context restore. 36 * 37 * .. [1] Please notice that there are other WAs that, due to their nature, 38 * cannot be applied from a central place. Those are peppered around the rest 39 * of the code, as needed. 40 * 41 * .. [2] Technically, some registers are powercontext saved & restored, so they 42 * survive a suspend/resume. In practice, writing them again is not too 43 * costly and simplifies things. We can revisit this in the future. 44 * 45 * Layout 46 * ~~~~~~ 47 * 48 * Keep things in this file ordered by WA type, as per the above (context, GT, 49 * display, register whitelist, batchbuffer). Then, inside each type, keep the 50 * following order: 51 * 52 * - Infrastructure functions and macros 53 * - WAs per platform in standard gen/chrono order 54 * - Public functions to init or apply the given workaround type. 55 */ 56 57 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 58 { 59 wal->name = name; 60 wal->engine_name = engine_name; 61 } 62 63 #define WA_LIST_CHUNK (1 << 4) 64 65 static void wa_init_finish(struct i915_wa_list *wal) 66 { 67 /* Trim unused entries. */ 68 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 69 struct i915_wa *list = kmemdup(wal->list, 70 wal->count * sizeof(*list), 71 GFP_KERNEL); 72 73 if (list) { 74 kfree(wal->list); 75 wal->list = list; 76 } 77 } 78 79 if (!wal->count) 80 return; 81 82 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 83 wal->wa_count, wal->name, wal->engine_name); 84 } 85 86 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 87 { 88 unsigned int addr = i915_mmio_reg_offset(wa->reg); 89 unsigned int start = 0, end = wal->count; 90 const unsigned int grow = WA_LIST_CHUNK; 91 struct i915_wa *wa_; 92 93 GEM_BUG_ON(!is_power_of_2(grow)); 94 95 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 96 struct i915_wa *list; 97 98 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 99 GFP_KERNEL); 100 if (!list) { 101 DRM_ERROR("No space for workaround init!\n"); 102 return; 103 } 104 105 if (wal->list) { 106 memcpy(list, wal->list, sizeof(*wa) * wal->count); 107 kfree(wal->list); 108 } 109 110 wal->list = list; 111 } 112 113 while (start < end) { 114 unsigned int mid = start + (end - start) / 2; 115 116 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 117 start = mid + 1; 118 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 119 end = mid; 120 } else { 121 wa_ = &wal->list[mid]; 122 123 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 124 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 125 i915_mmio_reg_offset(wa_->reg), 126 wa_->clr, wa_->set); 127 128 wa_->set &= ~wa->clr; 129 } 130 131 wal->wa_count++; 132 wa_->set |= wa->set; 133 wa_->clr |= wa->clr; 134 wa_->read |= wa->read; 135 return; 136 } 137 } 138 139 wal->wa_count++; 140 wa_ = &wal->list[wal->count++]; 141 *wa_ = *wa; 142 143 while (wa_-- > wal->list) { 144 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 145 i915_mmio_reg_offset(wa_[1].reg)); 146 if (i915_mmio_reg_offset(wa_[1].reg) > 147 i915_mmio_reg_offset(wa_[0].reg)) 148 break; 149 150 swap(wa_[1], wa_[0]); 151 } 152 } 153 154 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 155 u32 clear, u32 set, u32 read_mask, bool masked_reg) 156 { 157 struct i915_wa wa = { 158 .reg = reg, 159 .clr = clear, 160 .set = set, 161 .read = read_mask, 162 .masked_reg = masked_reg, 163 }; 164 165 _wa_add(wal, &wa); 166 } 167 168 static void 169 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 170 { 171 wa_add(wal, reg, clear, set, clear, false); 172 } 173 174 static void 175 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 176 { 177 wa_write_clr_set(wal, reg, ~0, set); 178 } 179 180 static void 181 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 182 { 183 wa_write_clr_set(wal, reg, set, set); 184 } 185 186 static void 187 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 188 { 189 wa_write_clr_set(wal, reg, clr, 0); 190 } 191 192 /* 193 * WA operations on "masked register". A masked register has the upper 16 bits 194 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 195 * portion of the register without a rmw: you simply write in the upper 16 bits 196 * the mask of bits you are going to modify. 197 * 198 * The wa_masked_* family of functions already does the necessary operations to 199 * calculate the mask based on the parameters passed, so user only has to 200 * provide the lower 16 bits of that register. 201 */ 202 203 static void 204 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 205 { 206 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 207 } 208 209 static void 210 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 211 { 212 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 213 } 214 215 static void 216 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 217 u32 mask, u32 val) 218 { 219 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 220 } 221 222 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 223 struct i915_wa_list *wal) 224 { 225 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 226 } 227 228 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 229 struct i915_wa_list *wal) 230 { 231 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 232 } 233 234 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 235 struct i915_wa_list *wal) 236 { 237 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 238 239 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 240 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 241 242 /* WaDisablePartialInstShootdown:bdw,chv */ 243 wa_masked_en(wal, GEN8_ROW_CHICKEN, 244 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 245 246 /* Use Force Non-Coherent whenever executing a 3D context. This is a 247 * workaround for a possible hang in the unlikely event a TLB 248 * invalidation occurs during a PSD flush. 249 */ 250 /* WaForceEnableNonCoherent:bdw,chv */ 251 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 252 wa_masked_en(wal, HDC_CHICKEN0, 253 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 254 HDC_FORCE_NON_COHERENT); 255 256 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 257 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 258 * polygons in the same 8x4 pixel/sample area to be processed without 259 * stalling waiting for the earlier ones to write to Hierarchical Z 260 * buffer." 261 * 262 * This optimization is off by default for BDW and CHV; turn it on. 263 */ 264 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 265 266 /* Wa4x4STCOptimizationDisable:bdw,chv */ 267 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 268 269 /* 270 * BSpec recommends 8x4 when MSAA is used, 271 * however in practice 16x4 seems fastest. 272 * 273 * Note that PS/WM thread counts depend on the WIZ hashing 274 * disable bit, which we don't touch here, but it's good 275 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 276 */ 277 wa_masked_field_set(wal, GEN7_GT_MODE, 278 GEN6_WIZ_HASHING_MASK, 279 GEN6_WIZ_HASHING_16x4); 280 } 281 282 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 283 struct i915_wa_list *wal) 284 { 285 struct drm_i915_private *i915 = engine->i915; 286 287 gen8_ctx_workarounds_init(engine, wal); 288 289 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 290 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 291 292 /* WaDisableDopClockGating:bdw 293 * 294 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 295 * to disable EUTC clock gating. 296 */ 297 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 298 DOP_CLOCK_GATING_DISABLE); 299 300 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 301 GEN8_SAMPLER_POWER_BYPASS_DIS); 302 303 wa_masked_en(wal, HDC_CHICKEN0, 304 /* WaForceContextSaveRestoreNonCoherent:bdw */ 305 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 306 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 307 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 308 } 309 310 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 311 struct i915_wa_list *wal) 312 { 313 gen8_ctx_workarounds_init(engine, wal); 314 315 /* WaDisableThreadStallDopClockGating:chv */ 316 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 317 318 /* Improve HiZ throughput on CHV. */ 319 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 320 } 321 322 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 323 struct i915_wa_list *wal) 324 { 325 struct drm_i915_private *i915 = engine->i915; 326 327 if (HAS_LLC(i915)) { 328 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 329 * 330 * Must match Display Engine. See 331 * WaCompressedResourceDisplayNewHashMode. 332 */ 333 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 334 GEN9_PBE_COMPRESSED_HASH_SELECTION); 335 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 336 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 337 } 338 339 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 340 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 341 wa_masked_en(wal, GEN8_ROW_CHICKEN, 342 FLOW_CONTROL_ENABLE | 343 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 344 345 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 346 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 347 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 348 GEN9_ENABLE_YV12_BUGFIX | 349 GEN9_ENABLE_GPGPU_PREEMPTION); 350 351 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 352 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 353 wa_masked_en(wal, CACHE_MODE_1, 354 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 355 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 356 357 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 358 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 359 GEN9_CCS_TLB_PREFETCH_ENABLE); 360 361 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 362 wa_masked_en(wal, HDC_CHICKEN0, 363 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 364 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 365 366 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 367 * both tied to WaForceContextSaveRestoreNonCoherent 368 * in some hsds for skl. We keep the tie for all gen9. The 369 * documentation is a bit hazy and so we want to get common behaviour, 370 * even though there is no clear evidence we would need both on kbl/bxt. 371 * This area has been source of system hangs so we play it safe 372 * and mimic the skl regardless of what bspec says. 373 * 374 * Use Force Non-Coherent whenever executing a 3D context. This 375 * is a workaround for a possible hang in the unlikely event 376 * a TLB invalidation occurs during a PSD flush. 377 */ 378 379 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 380 wa_masked_en(wal, HDC_CHICKEN0, 381 HDC_FORCE_NON_COHERENT); 382 383 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 384 if (IS_SKYLAKE(i915) || 385 IS_KABYLAKE(i915) || 386 IS_COFFEELAKE(i915) || 387 IS_COMETLAKE(i915)) 388 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 389 GEN8_SAMPLER_POWER_BYPASS_DIS); 390 391 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 392 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 393 394 /* 395 * Supporting preemption with fine-granularity requires changes in the 396 * batch buffer programming. Since we can't break old userspace, we 397 * need to set our default preemption level to safe value. Userspace is 398 * still able to use more fine-grained preemption levels, since in 399 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 400 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 401 * not real HW workarounds, but merely a way to start using preemption 402 * while maintaining old contract with userspace. 403 */ 404 405 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 406 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 407 408 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 409 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 410 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 411 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 412 413 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 414 if (IS_GEN9_LP(i915)) 415 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 416 } 417 418 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 419 struct i915_wa_list *wal) 420 { 421 struct intel_gt *gt = engine->gt; 422 u8 vals[3] = { 0, 0, 0 }; 423 unsigned int i; 424 425 for (i = 0; i < 3; i++) { 426 u8 ss; 427 428 /* 429 * Only consider slices where one, and only one, subslice has 7 430 * EUs 431 */ 432 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 433 continue; 434 435 /* 436 * subslice_7eu[i] != 0 (because of the check above) and 437 * ss_max == 4 (maximum number of subslices possible per slice) 438 * 439 * -> 0 <= ss <= 3; 440 */ 441 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 442 vals[i] = 3 - ss; 443 } 444 445 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 446 return; 447 448 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 449 wa_masked_field_set(wal, GEN7_GT_MODE, 450 GEN9_IZ_HASHING_MASK(2) | 451 GEN9_IZ_HASHING_MASK(1) | 452 GEN9_IZ_HASHING_MASK(0), 453 GEN9_IZ_HASHING(2, vals[2]) | 454 GEN9_IZ_HASHING(1, vals[1]) | 455 GEN9_IZ_HASHING(0, vals[0])); 456 } 457 458 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 459 struct i915_wa_list *wal) 460 { 461 gen9_ctx_workarounds_init(engine, wal); 462 skl_tune_iz_hashing(engine, wal); 463 } 464 465 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 466 struct i915_wa_list *wal) 467 { 468 gen9_ctx_workarounds_init(engine, wal); 469 470 /* WaDisableThreadStallDopClockGating:bxt */ 471 wa_masked_en(wal, GEN8_ROW_CHICKEN, 472 STALL_DOP_GATING_DISABLE); 473 474 /* WaToEnableHwFixForPushConstHWBug:bxt */ 475 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 476 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 477 } 478 479 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 480 struct i915_wa_list *wal) 481 { 482 struct drm_i915_private *i915 = engine->i915; 483 484 gen9_ctx_workarounds_init(engine, wal); 485 486 /* WaToEnableHwFixForPushConstHWBug:kbl */ 487 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 488 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 489 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 490 491 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 492 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 493 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 494 } 495 496 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 497 struct i915_wa_list *wal) 498 { 499 gen9_ctx_workarounds_init(engine, wal); 500 501 /* WaToEnableHwFixForPushConstHWBug:glk */ 502 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 503 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 504 } 505 506 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 507 struct i915_wa_list *wal) 508 { 509 gen9_ctx_workarounds_init(engine, wal); 510 511 /* WaToEnableHwFixForPushConstHWBug:cfl */ 512 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 513 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 514 515 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 516 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 517 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 518 } 519 520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 521 struct i915_wa_list *wal) 522 { 523 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 524 wa_write(wal, 525 GEN8_L3CNTLREG, 526 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 527 GEN8_ERRDETBCTRL); 528 529 /* WaForceEnableNonCoherent:icl 530 * This is not the same workaround as in early Gen9 platforms, where 531 * lacking this could cause system hangs, but coherency performance 532 * overhead is high and only a few compute workloads really need it 533 * (the register is whitelisted in hardware now, so UMDs can opt in 534 * for coherency if they have a good reason). 535 */ 536 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 537 538 /* WaEnableFloatBlendOptimization:icl */ 539 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 540 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 541 0 /* write-only, so skip validation */, 542 true); 543 544 /* WaDisableGPGPUMidThreadPreemption:icl */ 545 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 546 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 547 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 548 549 /* allow headerless messages for preemptible GPGPU context */ 550 wa_masked_en(wal, GEN10_SAMPLER_MODE, 551 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 552 553 /* Wa_1604278689:icl,ehl */ 554 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 555 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 556 0, /* write-only register; skip validation */ 557 0xFFFFFFFF); 558 559 /* Wa_1406306137:icl,ehl */ 560 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 561 } 562 563 /* 564 * These settings aren't actually workarounds, but general tuning settings that 565 * need to be programmed on dg2 platform. 566 */ 567 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 568 struct i915_wa_list *wal) 569 { 570 wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 571 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 572 wa_add(wal, 573 FF_MODE2, 574 FF_MODE2_TDS_TIMER_MASK, 575 FF_MODE2_TDS_TIMER_128, 576 0, false); 577 } 578 579 /* 580 * These settings aren't actually workarounds, but general tuning settings that 581 * need to be programmed on several platforms. 582 */ 583 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 584 struct i915_wa_list *wal) 585 { 586 /* 587 * Although some platforms refer to it as Wa_1604555607, we need to 588 * program it even on those that don't explicitly list that 589 * workaround. 590 * 591 * Note that the programming of this register is further modified 592 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 593 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 594 * value when read. The default value for this register is zero for all 595 * fields and there are no bit masks. So instead of doing a RMW we 596 * should just write TDS timer value. For the same reason read 597 * verification is ignored. 598 */ 599 wa_add(wal, 600 FF_MODE2, 601 FF_MODE2_TDS_TIMER_MASK, 602 FF_MODE2_TDS_TIMER_128, 603 0, false); 604 } 605 606 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 607 struct i915_wa_list *wal) 608 { 609 gen12_ctx_gt_tuning_init(engine, wal); 610 611 /* 612 * Wa_1409142259:tgl,dg1,adl-p 613 * Wa_1409347922:tgl,dg1,adl-p 614 * Wa_1409252684:tgl,dg1,adl-p 615 * Wa_1409217633:tgl,dg1,adl-p 616 * Wa_1409207793:tgl,dg1,adl-p 617 * Wa_1409178076:tgl,dg1,adl-p 618 * Wa_1408979724:tgl,dg1,adl-p 619 * Wa_14010443199:tgl,rkl,dg1,adl-p 620 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 621 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 622 */ 623 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 624 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 625 626 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 627 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 628 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 629 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 630 631 /* 632 * Wa_16011163337 633 * 634 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 635 * to Wa_1608008084. 636 */ 637 wa_add(wal, 638 FF_MODE2, 639 FF_MODE2_GS_TIMER_MASK, 640 FF_MODE2_GS_TIMER_224, 641 0, false); 642 } 643 644 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 645 struct i915_wa_list *wal) 646 { 647 gen12_ctx_workarounds_init(engine, wal); 648 649 /* Wa_1409044764 */ 650 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 651 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 652 653 /* Wa_22010493298 */ 654 wa_masked_en(wal, HIZ_CHICKEN, 655 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 656 } 657 658 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 659 struct i915_wa_list *wal) 660 { 661 dg2_ctx_gt_tuning_init(engine, wal); 662 663 /* Wa_16011186671:dg2_g11 */ 664 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 665 wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 666 wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 667 } 668 669 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 670 /* Wa_14010469329:dg2_g10 */ 671 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 672 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 673 674 /* 675 * Wa_22010465075:dg2_g10 676 * Wa_22010613112:dg2_g10 677 * Wa_14010698770:dg2_g10 678 */ 679 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 680 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 681 } 682 683 /* Wa_16013271637:dg2 */ 684 wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1, 685 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 686 687 /* Wa_14014947963:dg2 */ 688 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 689 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 690 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 691 } 692 693 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 694 struct i915_wa_list *wal) 695 { 696 /* 697 * This is a "fake" workaround defined by software to ensure we 698 * maintain reliable, backward-compatible behavior for userspace with 699 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 700 * 701 * The per-context setting of MI_MODE[12] determines whether the bits 702 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 703 * in the traditional manner or whether they should instead use a new 704 * tgl+ meaning that breaks backward compatibility, but allows nesting 705 * into 3rd-level batchbuffers. When this new capability was first 706 * added in TGL, it remained off by default unless a context 707 * intentionally opted in to the new behavior. However Xe_HPG now 708 * flips this on by default and requires that we explicitly opt out if 709 * we don't want the new behavior. 710 * 711 * From a SW perspective, we want to maintain the backward-compatible 712 * behavior for userspace, so we'll apply a fake workaround to set it 713 * back to the legacy behavior on platforms where the hardware default 714 * is to break compatibility. At the moment there is no Linux 715 * userspace that utilizes third-level batchbuffers, so this will avoid 716 * userspace from needing to make any changes. using the legacy 717 * meaning is the correct thing to do. If/when we have userspace 718 * consumers that want to utilize third-level batch nesting, we can 719 * provide a context parameter to allow them to opt-in. 720 */ 721 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 722 } 723 724 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 725 struct i915_wa_list *wal) 726 { 727 u8 mocs; 728 729 /* 730 * Some blitter commands do not have a field for MOCS, those 731 * commands will use MOCS index pointed by BLIT_CCTL. 732 * BLIT_CCTL registers are needed to be programmed to un-cached. 733 */ 734 if (engine->class == COPY_ENGINE_CLASS) { 735 mocs = engine->gt->mocs.uc_index; 736 wa_write_clr_set(wal, 737 BLIT_CCTL(engine->mmio_base), 738 BLIT_CCTL_MASK, 739 BLIT_CCTL_MOCS(mocs, mocs)); 740 } 741 } 742 743 /* 744 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 745 * defined by the hardware team, but it programming general context registers. 746 * Adding those context register programming in context workaround 747 * allow us to use the wa framework for proper application and validation. 748 */ 749 static void 750 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 751 struct i915_wa_list *wal) 752 { 753 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 754 fakewa_disable_nestedbb_mode(engine, wal); 755 756 gen12_ctx_gt_mocs_init(engine, wal); 757 } 758 759 static void 760 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 761 struct i915_wa_list *wal, 762 const char *name) 763 { 764 struct drm_i915_private *i915 = engine->i915; 765 766 wa_init_start(wal, name, engine->name); 767 768 /* Applies to all engines */ 769 /* 770 * Fake workarounds are not the actual workaround but 771 * programming of context registers using workaround framework. 772 */ 773 if (GRAPHICS_VER(i915) >= 12) 774 gen12_ctx_gt_fake_wa_init(engine, wal); 775 776 if (engine->class != RENDER_CLASS) 777 goto done; 778 779 if (IS_DG2(i915)) 780 dg2_ctx_workarounds_init(engine, wal); 781 else if (IS_XEHPSDV(i915)) 782 ; /* noop; none at this time */ 783 else if (IS_DG1(i915)) 784 dg1_ctx_workarounds_init(engine, wal); 785 else if (GRAPHICS_VER(i915) == 12) 786 gen12_ctx_workarounds_init(engine, wal); 787 else if (GRAPHICS_VER(i915) == 11) 788 icl_ctx_workarounds_init(engine, wal); 789 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 790 cfl_ctx_workarounds_init(engine, wal); 791 else if (IS_GEMINILAKE(i915)) 792 glk_ctx_workarounds_init(engine, wal); 793 else if (IS_KABYLAKE(i915)) 794 kbl_ctx_workarounds_init(engine, wal); 795 else if (IS_BROXTON(i915)) 796 bxt_ctx_workarounds_init(engine, wal); 797 else if (IS_SKYLAKE(i915)) 798 skl_ctx_workarounds_init(engine, wal); 799 else if (IS_CHERRYVIEW(i915)) 800 chv_ctx_workarounds_init(engine, wal); 801 else if (IS_BROADWELL(i915)) 802 bdw_ctx_workarounds_init(engine, wal); 803 else if (GRAPHICS_VER(i915) == 7) 804 gen7_ctx_workarounds_init(engine, wal); 805 else if (GRAPHICS_VER(i915) == 6) 806 gen6_ctx_workarounds_init(engine, wal); 807 else if (GRAPHICS_VER(i915) < 8) 808 ; 809 else 810 MISSING_CASE(GRAPHICS_VER(i915)); 811 812 done: 813 wa_init_finish(wal); 814 } 815 816 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 817 { 818 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 819 } 820 821 int intel_engine_emit_ctx_wa(struct i915_request *rq) 822 { 823 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 824 struct i915_wa *wa; 825 unsigned int i; 826 u32 *cs; 827 int ret; 828 829 if (wal->count == 0) 830 return 0; 831 832 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 833 if (ret) 834 return ret; 835 836 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 837 if (IS_ERR(cs)) 838 return PTR_ERR(cs); 839 840 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 841 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 842 *cs++ = i915_mmio_reg_offset(wa->reg); 843 *cs++ = wa->set; 844 } 845 *cs++ = MI_NOOP; 846 847 intel_ring_advance(rq, cs); 848 849 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 850 if (ret) 851 return ret; 852 853 return 0; 854 } 855 856 static void 857 gen4_gt_workarounds_init(struct intel_gt *gt, 858 struct i915_wa_list *wal) 859 { 860 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 861 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 862 } 863 864 static void 865 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 866 { 867 gen4_gt_workarounds_init(gt, wal); 868 869 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 870 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 871 } 872 873 static void 874 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 875 { 876 g4x_gt_workarounds_init(gt, wal); 877 878 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 879 } 880 881 static void 882 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 883 { 884 } 885 886 static void 887 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 888 { 889 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 890 wa_masked_dis(wal, 891 GEN7_COMMON_SLICE_CHICKEN1, 892 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 893 894 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 895 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 896 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 897 898 /* WaForceL3Serialization:ivb */ 899 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 900 } 901 902 static void 903 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 904 { 905 /* WaForceL3Serialization:vlv */ 906 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 907 908 /* 909 * WaIncreaseL3CreditsForVLVB0:vlv 910 * This is the hardware default actually. 911 */ 912 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 913 } 914 915 static void 916 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 917 { 918 /* L3 caching of data atomics doesn't work -- disable it. */ 919 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 920 921 wa_add(wal, 922 HSW_ROW_CHICKEN3, 0, 923 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 924 0 /* XXX does this reg exist? */, true); 925 926 /* WaVSRefCountFullforceMissDisable:hsw */ 927 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 928 } 929 930 static void 931 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 932 { 933 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 934 unsigned int slice, subslice; 935 u32 mcr, mcr_mask; 936 937 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 938 939 /* 940 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 941 * Before any MMIO read into slice/subslice specific registers, MCR 942 * packet control register needs to be programmed to point to any 943 * enabled s/ss pair. Otherwise, incorrect values will be returned. 944 * This means each subsequent MMIO read will be forwarded to an 945 * specific s/ss combination, but this is OK since these registers 946 * are consistent across s/ss in almost all cases. In the rare 947 * occasions, such as INSTDONE, where this value is dependent 948 * on s/ss combo, the read should be done with read_subslice_reg. 949 */ 950 slice = ffs(sseu->slice_mask) - 1; 951 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); 952 subslice = ffs(intel_sseu_get_subslices(sseu, slice)); 953 GEM_BUG_ON(!subslice); 954 subslice--; 955 956 /* 957 * We use GEN8_MCR..() macros to calculate the |mcr| value for 958 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 959 */ 960 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 961 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 962 963 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 964 965 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 966 } 967 968 static void 969 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 970 { 971 struct drm_i915_private *i915 = gt->i915; 972 973 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 974 gen9_wa_init_mcr(i915, wal); 975 976 /* WaDisableKillLogic:bxt,skl,kbl */ 977 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 978 wa_write_or(wal, 979 GAM_ECOCHK, 980 ECOCHK_DIS_TLB); 981 982 if (HAS_LLC(i915)) { 983 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 984 * 985 * Must match Display Engine. See 986 * WaCompressedResourceDisplayNewHashMode. 987 */ 988 wa_write_or(wal, 989 MMCD_MISC_CTRL, 990 MMCD_PCLA | MMCD_HOTSPOT_EN); 991 } 992 993 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 994 wa_write_or(wal, 995 GAM_ECOCHK, 996 BDW_DISABLE_HDC_INVALIDATION); 997 } 998 999 static void 1000 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1001 { 1002 gen9_gt_workarounds_init(gt, wal); 1003 1004 /* WaDisableGafsUnitClkGating:skl */ 1005 wa_write_or(wal, 1006 GEN7_UCGCTL4, 1007 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1008 1009 /* WaInPlaceDecompressionHang:skl */ 1010 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1011 wa_write_or(wal, 1012 GEN9_GAMT_ECO_REG_RW_IA, 1013 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1014 } 1015 1016 static void 1017 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1018 { 1019 gen9_gt_workarounds_init(gt, wal); 1020 1021 /* WaDisableDynamicCreditSharing:kbl */ 1022 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1023 wa_write_or(wal, 1024 GAMT_CHKN_BIT_REG, 1025 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1026 1027 /* WaDisableGafsUnitClkGating:kbl */ 1028 wa_write_or(wal, 1029 GEN7_UCGCTL4, 1030 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1031 1032 /* WaInPlaceDecompressionHang:kbl */ 1033 wa_write_or(wal, 1034 GEN9_GAMT_ECO_REG_RW_IA, 1035 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1036 } 1037 1038 static void 1039 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1040 { 1041 gen9_gt_workarounds_init(gt, wal); 1042 } 1043 1044 static void 1045 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1046 { 1047 gen9_gt_workarounds_init(gt, wal); 1048 1049 /* WaDisableGafsUnitClkGating:cfl */ 1050 wa_write_or(wal, 1051 GEN7_UCGCTL4, 1052 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1053 1054 /* WaInPlaceDecompressionHang:cfl */ 1055 wa_write_or(wal, 1056 GEN9_GAMT_ECO_REG_RW_IA, 1057 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1058 } 1059 1060 static void __set_mcr_steering(struct i915_wa_list *wal, 1061 i915_reg_t steering_reg, 1062 unsigned int slice, unsigned int subslice) 1063 { 1064 u32 mcr, mcr_mask; 1065 1066 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1067 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1068 1069 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1070 } 1071 1072 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1073 unsigned int slice, unsigned int subslice) 1074 { 1075 drm_dbg(>->i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); 1076 1077 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1078 } 1079 1080 static void 1081 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1082 { 1083 const struct sseu_dev_info *sseu = >->info.sseu; 1084 unsigned int slice, subslice; 1085 1086 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1087 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1088 slice = 0; 1089 1090 /* 1091 * Although a platform may have subslices, we need to always steer 1092 * reads to the lowest instance that isn't fused off. When Render 1093 * Power Gating is enabled, grabbing forcewake will only power up a 1094 * single subslice (the "minconfig") if there isn't a real workload 1095 * that needs to be run; this means that if we steer register reads to 1096 * one of the higher subslices, we run the risk of reading back 0's or 1097 * random garbage. 1098 */ 1099 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); 1100 1101 /* 1102 * If the subslice we picked above also steers us to a valid L3 bank, 1103 * then we can just rely on the default steering and won't need to 1104 * worry about explicitly re-steering L3BANK reads later. 1105 */ 1106 if (gt->info.l3bank_mask & BIT(subslice)) 1107 gt->steering_table[L3BANK] = NULL; 1108 1109 __add_mcr_wa(gt, wal, slice, subslice); 1110 } 1111 1112 static void 1113 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1114 { 1115 const struct sseu_dev_info *sseu = >->info.sseu; 1116 unsigned long slice, subslice = 0, slice_mask = 0; 1117 u64 dss_mask = 0; 1118 u32 lncf_mask = 0; 1119 int i; 1120 1121 /* 1122 * On Xe_HP the steering increases in complexity. There are now several 1123 * more units that require steering and we're not guaranteed to be able 1124 * to find a common setting for all of them. These are: 1125 * - GSLICE (fusable) 1126 * - DSS (sub-unit within gslice; fusable) 1127 * - L3 Bank (fusable) 1128 * - MSLICE (fusable) 1129 * - LNCF (sub-unit within mslice; always present if mslice is present) 1130 * 1131 * We'll do our default/implicit steering based on GSLICE (in the 1132 * sliceid field) and DSS (in the subsliceid field). If we can 1133 * find overlap between the valid MSLICE and/or LNCF values with 1134 * a suitable GSLICE, then we can just re-use the default value and 1135 * skip and explicit steering at runtime. 1136 * 1137 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1138 * a valid sliceid value. DSS steering is the only type of steering 1139 * that utilizes the 'subsliceid' bits. 1140 * 1141 * Also note that, even though the steering domain is called "GSlice" 1142 * and it is encoded in the register using the gslice format, the spec 1143 * says that the combined (geometry | compute) fuse should be used to 1144 * select the steering. 1145 */ 1146 1147 /* Find the potential gslice candidates */ 1148 dss_mask = intel_sseu_get_subslices(sseu, 0); 1149 slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE); 1150 1151 /* 1152 * Find the potential LNCF candidates. Either LNCF within a valid 1153 * mslice is fine. 1154 */ 1155 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1156 lncf_mask |= (0x3 << (i * 2)); 1157 1158 /* 1159 * Are there any sliceid values that work for both GSLICE and LNCF 1160 * steering? 1161 */ 1162 if (slice_mask & lncf_mask) { 1163 slice_mask &= lncf_mask; 1164 gt->steering_table[LNCF] = NULL; 1165 } 1166 1167 /* How about sliceid values that also work for MSLICE steering? */ 1168 if (slice_mask & gt->info.mslice_mask) { 1169 slice_mask &= gt->info.mslice_mask; 1170 gt->steering_table[MSLICE] = NULL; 1171 } 1172 1173 slice = __ffs(slice_mask); 1174 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); 1175 WARN_ON(subslice > GEN_DSS_PER_GSLICE); 1176 WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); 1177 1178 __add_mcr_wa(gt, wal, slice, subslice); 1179 1180 /* 1181 * SQIDI ranges are special because they use different steering 1182 * registers than everything else we work with. On XeHP SDV and 1183 * DG2-G10, any value in the steering registers will work fine since 1184 * all instances are present, but DG2-G11 only has SQIDI instances at 1185 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1186 * we'll just steer to a hardcoded "2" since that value will work 1187 * everywhere. 1188 */ 1189 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1190 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1191 } 1192 1193 static void 1194 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1195 { 1196 struct drm_i915_private *i915 = gt->i915; 1197 1198 icl_wa_init_mcr(gt, wal); 1199 1200 /* WaModifyGamTlbPartitioning:icl */ 1201 wa_write_clr_set(wal, 1202 GEN11_GACB_PERF_CTRL, 1203 GEN11_HASH_CTRL_MASK, 1204 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1205 1206 /* Wa_1405766107:icl 1207 * Formerly known as WaCL2SFHalfMaxAlloc 1208 */ 1209 wa_write_or(wal, 1210 GEN11_LSN_UNSLCVC, 1211 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1212 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1213 1214 /* Wa_220166154:icl 1215 * Formerly known as WaDisCtxReload 1216 */ 1217 wa_write_or(wal, 1218 GEN8_GAMW_ECO_DEV_RW_IA, 1219 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1220 1221 /* Wa_1406463099:icl 1222 * Formerly known as WaGamTlbPendError 1223 */ 1224 wa_write_or(wal, 1225 GAMT_CHKN_BIT_REG, 1226 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1227 1228 /* Wa_1407352427:icl,ehl */ 1229 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1230 PSDUNIT_CLKGATE_DIS); 1231 1232 /* Wa_1406680159:icl,ehl */ 1233 wa_write_or(wal, 1234 SUBSLICE_UNIT_LEVEL_CLKGATE, 1235 GWUNIT_CLKGATE_DIS); 1236 1237 /* Wa_1607087056:icl,ehl,jsl */ 1238 if (IS_ICELAKE(i915) || 1239 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1240 wa_write_or(wal, 1241 SLICE_UNIT_LEVEL_CLKGATE, 1242 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1243 1244 /* 1245 * This is not a documented workaround, but rather an optimization 1246 * to reduce sampler power. 1247 */ 1248 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1249 } 1250 1251 /* 1252 * Though there are per-engine instances of these registers, 1253 * they retain their value through engine resets and should 1254 * only be provided on the GT workaround list rather than 1255 * the engine-specific workaround list. 1256 */ 1257 static void 1258 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1259 { 1260 struct intel_engine_cs *engine; 1261 int id; 1262 1263 for_each_engine(engine, gt, id) { 1264 if (engine->class != VIDEO_DECODE_CLASS || 1265 (engine->instance % 2)) 1266 continue; 1267 1268 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1269 IECPUNIT_CLKGATE_DIS); 1270 } 1271 } 1272 1273 static void 1274 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1275 { 1276 icl_wa_init_mcr(gt, wal); 1277 1278 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1279 wa_14011060649(gt, wal); 1280 1281 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1282 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1283 } 1284 1285 static void 1286 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1287 { 1288 struct drm_i915_private *i915 = gt->i915; 1289 1290 gen12_gt_workarounds_init(gt, wal); 1291 1292 /* Wa_1409420604:tgl */ 1293 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1294 wa_write_or(wal, 1295 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1296 CPSSUNIT_CLKGATE_DIS); 1297 1298 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1299 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1300 wa_write_or(wal, 1301 SLICE_UNIT_LEVEL_CLKGATE, 1302 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1303 1304 /* Wa_1408615072:tgl[a0] */ 1305 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1306 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1307 VSUNIT_CLKGATE_DIS_TGL); 1308 } 1309 1310 static void 1311 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1312 { 1313 struct drm_i915_private *i915 = gt->i915; 1314 1315 gen12_gt_workarounds_init(gt, wal); 1316 1317 /* Wa_1607087056:dg1 */ 1318 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1319 wa_write_or(wal, 1320 SLICE_UNIT_LEVEL_CLKGATE, 1321 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1322 1323 /* Wa_1409420604:dg1 */ 1324 if (IS_DG1(i915)) 1325 wa_write_or(wal, 1326 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1327 CPSSUNIT_CLKGATE_DIS); 1328 1329 /* Wa_1408615072:dg1 */ 1330 /* Empirical testing shows this register is unaffected by engine reset. */ 1331 if (IS_DG1(i915)) 1332 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1333 VSUNIT_CLKGATE_DIS_TGL); 1334 } 1335 1336 static void 1337 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1338 { 1339 struct drm_i915_private *i915 = gt->i915; 1340 1341 xehp_init_mcr(gt, wal); 1342 1343 /* Wa_1409757795:xehpsdv */ 1344 wa_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1345 1346 /* Wa_16011155590:xehpsdv */ 1347 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1348 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1349 TSGUNIT_CLKGATE_DIS); 1350 1351 /* Wa_14011780169:xehpsdv */ 1352 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1353 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1354 GAMTLBVDBOX7_CLKGATE_DIS | 1355 GAMTLBVDBOX6_CLKGATE_DIS | 1356 GAMTLBVDBOX5_CLKGATE_DIS | 1357 GAMTLBVDBOX4_CLKGATE_DIS | 1358 GAMTLBVDBOX3_CLKGATE_DIS | 1359 GAMTLBVDBOX2_CLKGATE_DIS | 1360 GAMTLBVDBOX1_CLKGATE_DIS | 1361 GAMTLBVDBOX0_CLKGATE_DIS | 1362 GAMTLBKCR_CLKGATE_DIS | 1363 GAMTLBGUC_CLKGATE_DIS | 1364 GAMTLBBLT_CLKGATE_DIS); 1365 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1366 GAMTLBGFXA1_CLKGATE_DIS | 1367 GAMTLBCOMPA0_CLKGATE_DIS | 1368 GAMTLBCOMPA1_CLKGATE_DIS | 1369 GAMTLBCOMPB0_CLKGATE_DIS | 1370 GAMTLBCOMPB1_CLKGATE_DIS | 1371 GAMTLBCOMPC0_CLKGATE_DIS | 1372 GAMTLBCOMPC1_CLKGATE_DIS | 1373 GAMTLBCOMPD0_CLKGATE_DIS | 1374 GAMTLBCOMPD1_CLKGATE_DIS | 1375 GAMTLBMERT_CLKGATE_DIS | 1376 GAMTLBVEBOX3_CLKGATE_DIS | 1377 GAMTLBVEBOX2_CLKGATE_DIS | 1378 GAMTLBVEBOX1_CLKGATE_DIS | 1379 GAMTLBVEBOX0_CLKGATE_DIS); 1380 } 1381 1382 /* Wa_16012725990:xehpsdv */ 1383 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1384 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1385 1386 /* Wa_14011060649:xehpsdv */ 1387 wa_14011060649(gt, wal); 1388 } 1389 1390 static void 1391 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1392 { 1393 struct intel_engine_cs *engine; 1394 int id; 1395 1396 xehp_init_mcr(gt, wal); 1397 1398 /* Wa_14011060649:dg2 */ 1399 wa_14011060649(gt, wal); 1400 1401 /* 1402 * Although there are per-engine instances of these registers, 1403 * they technically exist outside the engine itself and are not 1404 * impacted by engine resets. Furthermore, they're part of the 1405 * GuC blacklist so trying to treat them as engine workarounds 1406 * will result in GuC initialization failure and a wedged GPU. 1407 */ 1408 for_each_engine(engine, gt, id) { 1409 if (engine->class != VIDEO_DECODE_CLASS) 1410 continue; 1411 1412 /* Wa_16010515920:dg2_g10 */ 1413 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1414 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1415 ALNUNIT_CLKGATE_DIS); 1416 } 1417 1418 if (IS_DG2_G10(gt->i915)) { 1419 /* Wa_22010523718:dg2 */ 1420 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1421 CG3DDISCFEG_CLKGATE_DIS); 1422 1423 /* Wa_14011006942:dg2 */ 1424 wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE, 1425 DSS_ROUTER_CLKGATE_DIS); 1426 } 1427 1428 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1429 /* Wa_14010948348:dg2_g10 */ 1430 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1431 1432 /* Wa_14011037102:dg2_g10 */ 1433 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1434 1435 /* Wa_14011371254:dg2_g10 */ 1436 wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1437 1438 /* Wa_14011431319:dg2_g10 */ 1439 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1440 GAMTLBVDBOX7_CLKGATE_DIS | 1441 GAMTLBVDBOX6_CLKGATE_DIS | 1442 GAMTLBVDBOX5_CLKGATE_DIS | 1443 GAMTLBVDBOX4_CLKGATE_DIS | 1444 GAMTLBVDBOX3_CLKGATE_DIS | 1445 GAMTLBVDBOX2_CLKGATE_DIS | 1446 GAMTLBVDBOX1_CLKGATE_DIS | 1447 GAMTLBVDBOX0_CLKGATE_DIS | 1448 GAMTLBKCR_CLKGATE_DIS | 1449 GAMTLBGUC_CLKGATE_DIS | 1450 GAMTLBBLT_CLKGATE_DIS); 1451 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1452 GAMTLBGFXA1_CLKGATE_DIS | 1453 GAMTLBCOMPA0_CLKGATE_DIS | 1454 GAMTLBCOMPA1_CLKGATE_DIS | 1455 GAMTLBCOMPB0_CLKGATE_DIS | 1456 GAMTLBCOMPB1_CLKGATE_DIS | 1457 GAMTLBCOMPC0_CLKGATE_DIS | 1458 GAMTLBCOMPC1_CLKGATE_DIS | 1459 GAMTLBCOMPD0_CLKGATE_DIS | 1460 GAMTLBCOMPD1_CLKGATE_DIS | 1461 GAMTLBMERT_CLKGATE_DIS | 1462 GAMTLBVEBOX3_CLKGATE_DIS | 1463 GAMTLBVEBOX2_CLKGATE_DIS | 1464 GAMTLBVEBOX1_CLKGATE_DIS | 1465 GAMTLBVEBOX0_CLKGATE_DIS); 1466 1467 /* Wa_14010569222:dg2_g10 */ 1468 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1469 GAMEDIA_CLKGATE_DIS); 1470 1471 /* Wa_14011028019:dg2_g10 */ 1472 wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1473 } 1474 1475 /* Wa_14014830051:dg2 */ 1476 wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1477 1478 /* 1479 * The following are not actually "workarounds" but rather 1480 * recommended tuning settings documented in the bspec's 1481 * performance guide section. 1482 */ 1483 wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); 1484 } 1485 1486 static void 1487 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1488 { 1489 struct drm_i915_private *i915 = gt->i915; 1490 1491 if (IS_DG2(i915)) 1492 dg2_gt_workarounds_init(gt, wal); 1493 else if (IS_XEHPSDV(i915)) 1494 xehpsdv_gt_workarounds_init(gt, wal); 1495 else if (IS_DG1(i915)) 1496 dg1_gt_workarounds_init(gt, wal); 1497 else if (IS_TIGERLAKE(i915)) 1498 tgl_gt_workarounds_init(gt, wal); 1499 else if (GRAPHICS_VER(i915) == 12) 1500 gen12_gt_workarounds_init(gt, wal); 1501 else if (GRAPHICS_VER(i915) == 11) 1502 icl_gt_workarounds_init(gt, wal); 1503 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1504 cfl_gt_workarounds_init(gt, wal); 1505 else if (IS_GEMINILAKE(i915)) 1506 glk_gt_workarounds_init(gt, wal); 1507 else if (IS_KABYLAKE(i915)) 1508 kbl_gt_workarounds_init(gt, wal); 1509 else if (IS_BROXTON(i915)) 1510 gen9_gt_workarounds_init(gt, wal); 1511 else if (IS_SKYLAKE(i915)) 1512 skl_gt_workarounds_init(gt, wal); 1513 else if (IS_HASWELL(i915)) 1514 hsw_gt_workarounds_init(gt, wal); 1515 else if (IS_VALLEYVIEW(i915)) 1516 vlv_gt_workarounds_init(gt, wal); 1517 else if (IS_IVYBRIDGE(i915)) 1518 ivb_gt_workarounds_init(gt, wal); 1519 else if (GRAPHICS_VER(i915) == 6) 1520 snb_gt_workarounds_init(gt, wal); 1521 else if (GRAPHICS_VER(i915) == 5) 1522 ilk_gt_workarounds_init(gt, wal); 1523 else if (IS_G4X(i915)) 1524 g4x_gt_workarounds_init(gt, wal); 1525 else if (GRAPHICS_VER(i915) == 4) 1526 gen4_gt_workarounds_init(gt, wal); 1527 else if (GRAPHICS_VER(i915) <= 8) 1528 ; 1529 else 1530 MISSING_CASE(GRAPHICS_VER(i915)); 1531 } 1532 1533 void intel_gt_init_workarounds(struct intel_gt *gt) 1534 { 1535 struct i915_wa_list *wal = >->wa_list; 1536 1537 wa_init_start(wal, "GT", "global"); 1538 gt_init_workarounds(gt, wal); 1539 wa_init_finish(wal); 1540 } 1541 1542 static enum forcewake_domains 1543 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1544 { 1545 enum forcewake_domains fw = 0; 1546 struct i915_wa *wa; 1547 unsigned int i; 1548 1549 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1550 fw |= intel_uncore_forcewake_for_reg(uncore, 1551 wa->reg, 1552 FW_REG_READ | 1553 FW_REG_WRITE); 1554 1555 return fw; 1556 } 1557 1558 static bool 1559 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1560 { 1561 if ((cur ^ wa->set) & wa->read) { 1562 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1563 name, from, i915_mmio_reg_offset(wa->reg), 1564 cur, cur & wa->read, wa->set & wa->read); 1565 1566 return false; 1567 } 1568 1569 return true; 1570 } 1571 1572 static void 1573 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1574 { 1575 struct intel_uncore *uncore = gt->uncore; 1576 enum forcewake_domains fw; 1577 unsigned long flags; 1578 struct i915_wa *wa; 1579 unsigned int i; 1580 1581 if (!wal->count) 1582 return; 1583 1584 fw = wal_get_fw_for_rmw(uncore, wal); 1585 1586 spin_lock_irqsave(&uncore->lock, flags); 1587 intel_uncore_forcewake_get__locked(uncore, fw); 1588 1589 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1590 u32 val, old = 0; 1591 1592 /* open-coded rmw due to steering */ 1593 old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; 1594 val = (old & ~wa->clr) | wa->set; 1595 if (val != old || !wa->clr) 1596 intel_uncore_write_fw(uncore, wa->reg, val); 1597 1598 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1599 wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), 1600 wal->name, "application"); 1601 } 1602 1603 intel_uncore_forcewake_put__locked(uncore, fw); 1604 spin_unlock_irqrestore(&uncore->lock, flags); 1605 } 1606 1607 void intel_gt_apply_workarounds(struct intel_gt *gt) 1608 { 1609 wa_list_apply(gt, >->wa_list); 1610 } 1611 1612 static bool wa_list_verify(struct intel_gt *gt, 1613 const struct i915_wa_list *wal, 1614 const char *from) 1615 { 1616 struct intel_uncore *uncore = gt->uncore; 1617 struct i915_wa *wa; 1618 enum forcewake_domains fw; 1619 unsigned long flags; 1620 unsigned int i; 1621 bool ok = true; 1622 1623 fw = wal_get_fw_for_rmw(uncore, wal); 1624 1625 spin_lock_irqsave(&uncore->lock, flags); 1626 intel_uncore_forcewake_get__locked(uncore, fw); 1627 1628 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1629 ok &= wa_verify(wa, 1630 intel_gt_read_register_fw(gt, wa->reg), 1631 wal->name, from); 1632 1633 intel_uncore_forcewake_put__locked(uncore, fw); 1634 spin_unlock_irqrestore(&uncore->lock, flags); 1635 1636 return ok; 1637 } 1638 1639 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1640 { 1641 return wa_list_verify(gt, >->wa_list, from); 1642 } 1643 1644 __maybe_unused 1645 static bool is_nonpriv_flags_valid(u32 flags) 1646 { 1647 /* Check only valid flag bits are set */ 1648 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1649 return false; 1650 1651 /* NB: Only 3 out of 4 enum values are valid for access field */ 1652 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1653 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1654 return false; 1655 1656 return true; 1657 } 1658 1659 static void 1660 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1661 { 1662 struct i915_wa wa = { 1663 .reg = reg 1664 }; 1665 1666 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1667 return; 1668 1669 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1670 return; 1671 1672 wa.reg.reg |= flags; 1673 _wa_add(wal, &wa); 1674 } 1675 1676 static void 1677 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1678 { 1679 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1680 } 1681 1682 static void gen9_whitelist_build(struct i915_wa_list *w) 1683 { 1684 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1685 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1686 1687 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1688 whitelist_reg(w, GEN8_CS_CHICKEN1); 1689 1690 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1691 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1692 1693 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1694 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1695 } 1696 1697 static void skl_whitelist_build(struct intel_engine_cs *engine) 1698 { 1699 struct i915_wa_list *w = &engine->whitelist; 1700 1701 if (engine->class != RENDER_CLASS) 1702 return; 1703 1704 gen9_whitelist_build(w); 1705 1706 /* WaDisableLSQCROPERFforOCL:skl */ 1707 whitelist_reg(w, GEN8_L3SQCREG4); 1708 } 1709 1710 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1711 { 1712 if (engine->class != RENDER_CLASS) 1713 return; 1714 1715 gen9_whitelist_build(&engine->whitelist); 1716 } 1717 1718 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1719 { 1720 struct i915_wa_list *w = &engine->whitelist; 1721 1722 if (engine->class != RENDER_CLASS) 1723 return; 1724 1725 gen9_whitelist_build(w); 1726 1727 /* WaDisableLSQCROPERFforOCL:kbl */ 1728 whitelist_reg(w, GEN8_L3SQCREG4); 1729 } 1730 1731 static void glk_whitelist_build(struct intel_engine_cs *engine) 1732 { 1733 struct i915_wa_list *w = &engine->whitelist; 1734 1735 if (engine->class != RENDER_CLASS) 1736 return; 1737 1738 gen9_whitelist_build(w); 1739 1740 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1741 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1742 } 1743 1744 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1745 { 1746 struct i915_wa_list *w = &engine->whitelist; 1747 1748 if (engine->class != RENDER_CLASS) 1749 return; 1750 1751 gen9_whitelist_build(w); 1752 1753 /* 1754 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1755 * 1756 * This covers 4 register which are next to one another : 1757 * - PS_INVOCATION_COUNT 1758 * - PS_INVOCATION_COUNT_UDW 1759 * - PS_DEPTH_COUNT 1760 * - PS_DEPTH_COUNT_UDW 1761 */ 1762 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1763 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1764 RING_FORCE_TO_NONPRIV_RANGE_4); 1765 } 1766 1767 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1768 { 1769 struct i915_wa_list *w = &engine->whitelist; 1770 1771 if (engine->class != RENDER_CLASS) 1772 whitelist_reg_ext(w, 1773 RING_CTX_TIMESTAMP(engine->mmio_base), 1774 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1775 } 1776 1777 static void cml_whitelist_build(struct intel_engine_cs *engine) 1778 { 1779 allow_read_ctx_timestamp(engine); 1780 1781 cfl_whitelist_build(engine); 1782 } 1783 1784 static void icl_whitelist_build(struct intel_engine_cs *engine) 1785 { 1786 struct i915_wa_list *w = &engine->whitelist; 1787 1788 allow_read_ctx_timestamp(engine); 1789 1790 switch (engine->class) { 1791 case RENDER_CLASS: 1792 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1793 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1794 1795 /* WaAllowUMDToModifySamplerMode:icl */ 1796 whitelist_reg(w, GEN10_SAMPLER_MODE); 1797 1798 /* WaEnableStateCacheRedirectToCS:icl */ 1799 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1800 1801 /* 1802 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1803 * 1804 * This covers 4 register which are next to one another : 1805 * - PS_INVOCATION_COUNT 1806 * - PS_INVOCATION_COUNT_UDW 1807 * - PS_DEPTH_COUNT 1808 * - PS_DEPTH_COUNT_UDW 1809 */ 1810 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1811 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1812 RING_FORCE_TO_NONPRIV_RANGE_4); 1813 break; 1814 1815 case VIDEO_DECODE_CLASS: 1816 /* hucStatusRegOffset */ 1817 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1818 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1819 /* hucUKernelHdrInfoRegOffset */ 1820 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1821 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1822 /* hucStatus2RegOffset */ 1823 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1824 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1825 break; 1826 1827 default: 1828 break; 1829 } 1830 } 1831 1832 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1833 { 1834 struct i915_wa_list *w = &engine->whitelist; 1835 1836 allow_read_ctx_timestamp(engine); 1837 1838 switch (engine->class) { 1839 case RENDER_CLASS: 1840 /* 1841 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1842 * Wa_1408556865:tgl 1843 * 1844 * This covers 4 registers which are next to one another : 1845 * - PS_INVOCATION_COUNT 1846 * - PS_INVOCATION_COUNT_UDW 1847 * - PS_DEPTH_COUNT 1848 * - PS_DEPTH_COUNT_UDW 1849 */ 1850 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1851 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1852 RING_FORCE_TO_NONPRIV_RANGE_4); 1853 1854 /* 1855 * Wa_1808121037:tgl 1856 * Wa_14012131227:dg1 1857 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 1858 */ 1859 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1860 1861 /* Wa_1806527549:tgl */ 1862 whitelist_reg(w, HIZ_CHICKEN); 1863 break; 1864 default: 1865 break; 1866 } 1867 } 1868 1869 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1870 { 1871 struct i915_wa_list *w = &engine->whitelist; 1872 1873 tgl_whitelist_build(engine); 1874 1875 /* GEN:BUG:1409280441:dg1 */ 1876 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 1877 (engine->class == RENDER_CLASS || 1878 engine->class == COPY_ENGINE_CLASS)) 1879 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1880 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1881 } 1882 1883 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 1884 { 1885 allow_read_ctx_timestamp(engine); 1886 } 1887 1888 static void dg2_whitelist_build(struct intel_engine_cs *engine) 1889 { 1890 struct i915_wa_list *w = &engine->whitelist; 1891 1892 allow_read_ctx_timestamp(engine); 1893 1894 switch (engine->class) { 1895 case RENDER_CLASS: 1896 /* 1897 * Wa_1507100340:dg2_g10 1898 * 1899 * This covers 4 registers which are next to one another : 1900 * - PS_INVOCATION_COUNT 1901 * - PS_INVOCATION_COUNT_UDW 1902 * - PS_DEPTH_COUNT 1903 * - PS_DEPTH_COUNT_UDW 1904 */ 1905 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1906 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1907 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1908 RING_FORCE_TO_NONPRIV_RANGE_4); 1909 1910 break; 1911 case COMPUTE_CLASS: 1912 /* Wa_16011157294:dg2_g10 */ 1913 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1914 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1915 break; 1916 default: 1917 break; 1918 } 1919 } 1920 1921 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1922 { 1923 struct drm_i915_private *i915 = engine->i915; 1924 struct i915_wa_list *w = &engine->whitelist; 1925 1926 wa_init_start(w, "whitelist", engine->name); 1927 1928 if (IS_DG2(i915)) 1929 dg2_whitelist_build(engine); 1930 else if (IS_XEHPSDV(i915)) 1931 xehpsdv_whitelist_build(engine); 1932 else if (IS_DG1(i915)) 1933 dg1_whitelist_build(engine); 1934 else if (GRAPHICS_VER(i915) == 12) 1935 tgl_whitelist_build(engine); 1936 else if (GRAPHICS_VER(i915) == 11) 1937 icl_whitelist_build(engine); 1938 else if (IS_COMETLAKE(i915)) 1939 cml_whitelist_build(engine); 1940 else if (IS_COFFEELAKE(i915)) 1941 cfl_whitelist_build(engine); 1942 else if (IS_GEMINILAKE(i915)) 1943 glk_whitelist_build(engine); 1944 else if (IS_KABYLAKE(i915)) 1945 kbl_whitelist_build(engine); 1946 else if (IS_BROXTON(i915)) 1947 bxt_whitelist_build(engine); 1948 else if (IS_SKYLAKE(i915)) 1949 skl_whitelist_build(engine); 1950 else if (GRAPHICS_VER(i915) <= 8) 1951 ; 1952 else 1953 MISSING_CASE(GRAPHICS_VER(i915)); 1954 1955 wa_init_finish(w); 1956 } 1957 1958 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1959 { 1960 const struct i915_wa_list *wal = &engine->whitelist; 1961 struct intel_uncore *uncore = engine->uncore; 1962 const u32 base = engine->mmio_base; 1963 struct i915_wa *wa; 1964 unsigned int i; 1965 1966 if (!wal->count) 1967 return; 1968 1969 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1970 intel_uncore_write(uncore, 1971 RING_FORCE_TO_NONPRIV(base, i), 1972 i915_mmio_reg_offset(wa->reg)); 1973 1974 /* And clear the rest just in case of garbage */ 1975 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1976 intel_uncore_write(uncore, 1977 RING_FORCE_TO_NONPRIV(base, i), 1978 i915_mmio_reg_offset(RING_NOPID(base))); 1979 } 1980 1981 /* 1982 * engine_fake_wa_init(), a place holder to program the registers 1983 * which are not part of an official workaround defined by the 1984 * hardware team. 1985 * Adding programming of those register inside workaround will 1986 * allow utilizing wa framework to proper application and verification. 1987 */ 1988 static void 1989 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1990 { 1991 u8 mocs; 1992 1993 /* 1994 * RING_CMD_CCTL are need to be programed to un-cached 1995 * for memory writes and reads outputted by Command 1996 * Streamers on Gen12 onward platforms. 1997 */ 1998 if (GRAPHICS_VER(engine->i915) >= 12) { 1999 mocs = engine->gt->mocs.uc_index; 2000 wa_masked_field_set(wal, 2001 RING_CMD_CCTL(engine->mmio_base), 2002 CMD_CCTL_MOCS_MASK, 2003 CMD_CCTL_MOCS_OVERRIDE(mocs, mocs)); 2004 } 2005 } 2006 2007 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2008 { 2009 u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0); 2010 2011 return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0; 2012 } 2013 2014 static void 2015 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2016 { 2017 struct drm_i915_private *i915 = engine->i915; 2018 2019 if (IS_DG2(i915)) { 2020 /* Wa_14015227452:dg2 */ 2021 wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2022 2023 /* Wa_1509235366:dg2 */ 2024 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2025 GLOBAL_INVALIDATION_MODE); 2026 2027 /* 2028 * The following are not actually "workarounds" but rather 2029 * recommended tuning settings documented in the bspec's 2030 * performance guide section. 2031 */ 2032 wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2033 2034 /* Wa_18018781329:dg2 */ 2035 wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2036 wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2037 wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2038 wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2039 } 2040 2041 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2042 /* Wa_14013392000:dg2_g11 */ 2043 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2044 2045 /* Wa_16011620976:dg2_g11 */ 2046 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2047 } 2048 2049 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2050 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2051 /* Wa_14012419201:dg2 */ 2052 wa_masked_en(wal, GEN9_ROW_CHICKEN4, 2053 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2054 } 2055 2056 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2057 IS_DG2_G11(i915)) { 2058 /* 2059 * Wa_22012826095:dg2 2060 * Wa_22013059131:dg2 2061 */ 2062 wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2063 MAXREQS_PER_BANK, 2064 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2065 2066 /* Wa_22013059131:dg2 */ 2067 wa_write_or(wal, LSC_CHICKEN_BIT_0, 2068 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2069 } 2070 2071 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2072 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2073 needs_wa_1308578152(engine)) { 2074 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2075 GEN12_REPLAY_MODE_GRANULARITY); 2076 } 2077 2078 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2079 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2080 /* Wa_22013037850:dg2 */ 2081 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2082 DISABLE_128B_EVICTION_COMMAND_UDW); 2083 2084 /* Wa_22012856258:dg2 */ 2085 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2086 GEN12_DISABLE_READ_SUPPRESSION); 2087 2088 /* 2089 * Wa_22010960976:dg2 2090 * Wa_14013347512:dg2 2091 */ 2092 wa_masked_dis(wal, GEN12_HDC_CHICKEN0, 2093 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2094 } 2095 2096 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2097 /* 2098 * Wa_1608949956:dg2_g10 2099 * Wa_14010198302:dg2_g10 2100 */ 2101 wa_masked_en(wal, GEN8_ROW_CHICKEN, 2102 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2103 2104 /* 2105 * Wa_14010918519:dg2_g10 2106 * 2107 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2108 * so ignoring verification. 2109 */ 2110 wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2111 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2112 0, false); 2113 } 2114 2115 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2116 /* Wa_22010430635:dg2 */ 2117 wa_masked_en(wal, 2118 GEN9_ROW_CHICKEN4, 2119 GEN12_DISABLE_GRF_CLEAR); 2120 2121 /* Wa_14010648519:dg2 */ 2122 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2123 } 2124 2125 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || 2126 IS_DG2_G11(i915)) { 2127 /* Wa_22012654132:dg2 */ 2128 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 2129 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2130 0 /* write-only, so skip validation */, 2131 true); 2132 } 2133 2134 /* Wa_14013202645:dg2 */ 2135 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2136 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2137 wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2138 2139 /* Wa_22012532006:dg2 */ 2140 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2141 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2142 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2143 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2144 2145 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2146 /* Wa_14010680813:dg2_g10 */ 2147 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2148 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2149 } 2150 2151 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2152 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2153 /* Wa_14012362059:dg2 */ 2154 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2155 } 2156 2157 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2158 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2159 /* 2160 * Wa_1607138336:tgl[a0],dg1[a0] 2161 * Wa_1607063988:tgl[a0],dg1[a0] 2162 */ 2163 wa_write_or(wal, 2164 GEN9_CTX_PREEMPT_REG, 2165 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2166 } 2167 2168 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2169 /* 2170 * Wa_1606679103:tgl 2171 * (see also Wa_1606682166:icl) 2172 */ 2173 wa_write_or(wal, 2174 GEN7_SARCHKMD, 2175 GEN7_DISABLE_SAMPLER_PREFETCH); 2176 } 2177 2178 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2179 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2180 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2181 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2182 2183 /* 2184 * Wa_1407928979:tgl A* 2185 * Wa_18011464164:tgl[B0+],dg1[B0+] 2186 * Wa_22010931296:tgl[B0+],dg1[B0+] 2187 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2188 */ 2189 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2190 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2191 2192 /* 2193 * Wa_1606700617:tgl,dg1,adl-p 2194 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2195 * Wa_14010826681:tgl,dg1,rkl,adl-p 2196 */ 2197 wa_masked_en(wal, 2198 GEN9_CS_DEBUG_MODE1, 2199 FF_DOP_CLOCK_GATE_DISABLE); 2200 } 2201 2202 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2203 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2204 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2205 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2206 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2207 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2208 2209 /* 2210 * Wa_1409085225:tgl 2211 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2212 */ 2213 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2214 } 2215 2216 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2217 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2218 /* 2219 * Wa_1607030317:tgl 2220 * Wa_1607186500:tgl 2221 * Wa_1607297627:tgl,rkl,dg1[a0] 2222 * 2223 * On TGL and RKL there are multiple entries for this WA in the 2224 * BSpec; some indicate this is an A0-only WA, others indicate 2225 * it applies to all steppings so we trust the "all steppings." 2226 * For DG1 this only applies to A0. 2227 */ 2228 wa_masked_en(wal, 2229 RING_PSMI_CTL(RENDER_RING_BASE), 2230 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2231 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2232 } 2233 2234 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2235 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2236 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2237 wa_masked_en(wal, 2238 GEN10_SAMPLER_MODE, 2239 ENABLE_SMALLPL); 2240 } 2241 2242 if (GRAPHICS_VER(i915) == 11) { 2243 /* This is not an Wa. Enable for better image quality */ 2244 wa_masked_en(wal, 2245 _3D_CHICKEN3, 2246 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2247 2248 /* 2249 * Wa_1405543622:icl 2250 * Formerly known as WaGAPZPriorityScheme 2251 */ 2252 wa_write_or(wal, 2253 GEN8_GARBCNTL, 2254 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2255 2256 /* 2257 * Wa_1604223664:icl 2258 * Formerly known as WaL3BankAddressHashing 2259 */ 2260 wa_write_clr_set(wal, 2261 GEN8_GARBCNTL, 2262 GEN11_HASH_CTRL_EXCL_MASK, 2263 GEN11_HASH_CTRL_EXCL_BIT0); 2264 wa_write_clr_set(wal, 2265 GEN11_GLBLINVL, 2266 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2267 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2268 2269 /* 2270 * Wa_1405733216:icl 2271 * Formerly known as WaDisableCleanEvicts 2272 */ 2273 wa_write_or(wal, 2274 GEN8_L3SQCREG4, 2275 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2276 2277 /* Wa_1606682166:icl */ 2278 wa_write_or(wal, 2279 GEN7_SARCHKMD, 2280 GEN7_DISABLE_SAMPLER_PREFETCH); 2281 2282 /* Wa_1409178092:icl */ 2283 wa_write_clr_set(wal, 2284 GEN11_SCRATCH2, 2285 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2286 0); 2287 2288 /* WaEnable32PlaneMode:icl */ 2289 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2290 GEN11_ENABLE_32_PLANE_MODE); 2291 2292 /* 2293 * Wa_1408615072:icl,ehl (vsunit) 2294 * Wa_1407596294:icl,ehl (hsunit) 2295 */ 2296 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2297 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2298 2299 /* 2300 * Wa_1408767742:icl[a2..forever],ehl[all] 2301 * Wa_1605460711:icl[a0..c0] 2302 */ 2303 wa_write_or(wal, 2304 GEN7_FF_THREAD_MODE, 2305 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2306 2307 /* Wa_22010271021 */ 2308 wa_masked_en(wal, 2309 GEN9_CS_DEBUG_MODE1, 2310 FF_DOP_CLOCK_GATE_DISABLE); 2311 } 2312 2313 if (IS_GRAPHICS_VER(i915, 9, 12)) { 2314 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 2315 wa_masked_en(wal, 2316 GEN7_FF_SLICE_CS_CHICKEN1, 2317 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2318 } 2319 2320 if (IS_SKYLAKE(i915) || 2321 IS_KABYLAKE(i915) || 2322 IS_COFFEELAKE(i915) || 2323 IS_COMETLAKE(i915)) { 2324 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2325 wa_write_or(wal, 2326 GEN8_GARBCNTL, 2327 GEN9_GAPS_TSV_CREDIT_DISABLE); 2328 } 2329 2330 if (IS_BROXTON(i915)) { 2331 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2332 wa_masked_en(wal, 2333 FF_SLICE_CS_CHICKEN2, 2334 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2335 } 2336 2337 if (GRAPHICS_VER(i915) == 9) { 2338 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2339 wa_masked_en(wal, 2340 GEN9_CSFE_CHICKEN1_RCS, 2341 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2342 2343 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2344 wa_write_or(wal, 2345 BDW_SCRATCH1, 2346 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2347 2348 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2349 if (IS_GEN9_LP(i915)) 2350 wa_write_clr_set(wal, 2351 GEN8_L3SQCREG1, 2352 L3_PRIO_CREDITS_MASK, 2353 L3_GENERAL_PRIO_CREDITS(62) | 2354 L3_HIGH_PRIO_CREDITS(2)); 2355 2356 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2357 wa_write_or(wal, 2358 GEN8_L3SQCREG4, 2359 GEN8_LQSC_FLUSH_COHERENT_LINES); 2360 2361 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2362 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2363 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2364 wa_write_clr_set(wal, GEN8_L3SQCREG4, 2365 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2366 wa_write_clr_set(wal, GEN9_SCRATCH1, 2367 EVICTION_PERF_FIX_ENABLE, 0); 2368 } 2369 2370 if (IS_HASWELL(i915)) { 2371 /* WaSampleCChickenBitEnable:hsw */ 2372 wa_masked_en(wal, 2373 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2374 2375 wa_masked_dis(wal, 2376 CACHE_MODE_0_GEN7, 2377 /* enable HiZ Raw Stall Optimization */ 2378 HIZ_RAW_STALL_OPT_DISABLE); 2379 } 2380 2381 if (IS_VALLEYVIEW(i915)) { 2382 /* WaDisableEarlyCull:vlv */ 2383 wa_masked_en(wal, 2384 _3D_CHICKEN3, 2385 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2386 2387 /* 2388 * WaVSThreadDispatchOverride:ivb,vlv 2389 * 2390 * This actually overrides the dispatch 2391 * mode for all thread types. 2392 */ 2393 wa_write_clr_set(wal, 2394 GEN7_FF_THREAD_MODE, 2395 GEN7_FF_SCHED_MASK, 2396 GEN7_FF_TS_SCHED_HW | 2397 GEN7_FF_VS_SCHED_HW | 2398 GEN7_FF_DS_SCHED_HW); 2399 2400 /* WaPsdDispatchEnable:vlv */ 2401 /* WaDisablePSDDualDispatchEnable:vlv */ 2402 wa_masked_en(wal, 2403 GEN7_HALF_SLICE_CHICKEN1, 2404 GEN7_MAX_PS_THREAD_DEP | 2405 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2406 } 2407 2408 if (IS_IVYBRIDGE(i915)) { 2409 /* WaDisableEarlyCull:ivb */ 2410 wa_masked_en(wal, 2411 _3D_CHICKEN3, 2412 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2413 2414 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2415 /* enable HiZ Raw Stall Optimization */ 2416 wa_masked_dis(wal, 2417 CACHE_MODE_0_GEN7, 2418 HIZ_RAW_STALL_OPT_DISABLE); 2419 } 2420 2421 /* 2422 * WaVSThreadDispatchOverride:ivb,vlv 2423 * 2424 * This actually overrides the dispatch 2425 * mode for all thread types. 2426 */ 2427 wa_write_clr_set(wal, 2428 GEN7_FF_THREAD_MODE, 2429 GEN7_FF_SCHED_MASK, 2430 GEN7_FF_TS_SCHED_HW | 2431 GEN7_FF_VS_SCHED_HW | 2432 GEN7_FF_DS_SCHED_HW); 2433 2434 /* WaDisablePSDDualDispatchEnable:ivb */ 2435 if (IS_IVB_GT1(i915)) 2436 wa_masked_en(wal, 2437 GEN7_HALF_SLICE_CHICKEN1, 2438 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2439 } 2440 2441 if (GRAPHICS_VER(i915) == 7) { 2442 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2443 wa_masked_en(wal, 2444 RING_MODE_GEN7(RENDER_RING_BASE), 2445 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2446 2447 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2448 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2449 2450 /* 2451 * BSpec says this must be set, even though 2452 * WaDisable4x2SubspanOptimization:ivb,hsw 2453 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2454 */ 2455 wa_masked_en(wal, 2456 CACHE_MODE_1, 2457 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2458 2459 /* 2460 * BSpec recommends 8x4 when MSAA is used, 2461 * however in practice 16x4 seems fastest. 2462 * 2463 * Note that PS/WM thread counts depend on the WIZ hashing 2464 * disable bit, which we don't touch here, but it's good 2465 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2466 */ 2467 wa_masked_field_set(wal, 2468 GEN7_GT_MODE, 2469 GEN6_WIZ_HASHING_MASK, 2470 GEN6_WIZ_HASHING_16x4); 2471 } 2472 2473 if (IS_GRAPHICS_VER(i915, 6, 7)) 2474 /* 2475 * We need to disable the AsyncFlip performance optimisations in 2476 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2477 * already be programmed to '1' on all products. 2478 * 2479 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2480 */ 2481 wa_masked_en(wal, 2482 RING_MI_MODE(RENDER_RING_BASE), 2483 ASYNC_FLIP_PERF_DISABLE); 2484 2485 if (GRAPHICS_VER(i915) == 6) { 2486 /* 2487 * Required for the hardware to program scanline values for 2488 * waiting 2489 * WaEnableFlushTlbInvalidationMode:snb 2490 */ 2491 wa_masked_en(wal, 2492 GFX_MODE, 2493 GFX_TLB_INVALIDATE_EXPLICIT); 2494 2495 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2496 wa_masked_en(wal, 2497 _3D_CHICKEN, 2498 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2499 2500 wa_masked_en(wal, 2501 _3D_CHICKEN3, 2502 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2503 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2504 /* 2505 * Bspec says: 2506 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2507 * to normal and 3DSTATE_SF number of SF output attributes 2508 * is more than 16." 2509 */ 2510 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2511 2512 /* 2513 * BSpec recommends 8x4 when MSAA is used, 2514 * however in practice 16x4 seems fastest. 2515 * 2516 * Note that PS/WM thread counts depend on the WIZ hashing 2517 * disable bit, which we don't touch here, but it's good 2518 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2519 */ 2520 wa_masked_field_set(wal, 2521 GEN6_GT_MODE, 2522 GEN6_WIZ_HASHING_MASK, 2523 GEN6_WIZ_HASHING_16x4); 2524 2525 /* WaDisable_RenderCache_OperationalFlush:snb */ 2526 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2527 2528 /* 2529 * From the Sandybridge PRM, volume 1 part 3, page 24: 2530 * "If this bit is set, STCunit will have LRA as replacement 2531 * policy. [...] This bit must be reset. LRA replacement 2532 * policy is not supported." 2533 */ 2534 wa_masked_dis(wal, 2535 CACHE_MODE_0, 2536 CM0_STC_EVICT_DISABLE_LRA_SNB); 2537 } 2538 2539 if (IS_GRAPHICS_VER(i915, 4, 6)) 2540 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2541 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2542 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2543 /* XXX bit doesn't stick on Broadwater */ 2544 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2545 2546 if (GRAPHICS_VER(i915) == 4) 2547 /* 2548 * Disable CONSTANT_BUFFER before it is loaded from the context 2549 * image. For as it is loaded, it is executed and the stored 2550 * address may no longer be valid, leading to a GPU hang. 2551 * 2552 * This imposes the requirement that userspace reload their 2553 * CONSTANT_BUFFER on every batch, fortunately a requirement 2554 * they are already accustomed to from before contexts were 2555 * enabled. 2556 */ 2557 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2558 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2559 0 /* XXX bit doesn't stick on Broadwater */, 2560 true); 2561 } 2562 2563 static void 2564 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2565 { 2566 struct drm_i915_private *i915 = engine->i915; 2567 2568 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2569 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2570 wa_write(wal, 2571 RING_SEMA_WAIT_POLL(engine->mmio_base), 2572 1); 2573 } 2574 } 2575 2576 /* 2577 * The workarounds in this function apply to shared registers in 2578 * the general render reset domain that aren't tied to a 2579 * specific engine. Since all render+compute engines get reset 2580 * together, and the contents of these registers are lost during 2581 * the shared render domain reset, we'll define such workarounds 2582 * here and then add them to just a single RCS or CCS engine's 2583 * workaround list (whichever engine has the XXXX flag). 2584 */ 2585 static void 2586 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2587 { 2588 struct drm_i915_private *i915 = engine->i915; 2589 2590 if (IS_XEHPSDV(i915)) { 2591 /* Wa_1409954639 */ 2592 wa_masked_en(wal, 2593 GEN8_ROW_CHICKEN, 2594 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2595 2596 /* Wa_1607196519 */ 2597 wa_masked_en(wal, 2598 GEN9_ROW_CHICKEN4, 2599 GEN12_DISABLE_GRF_CLEAR); 2600 2601 /* Wa_14010670810:xehpsdv */ 2602 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2603 2604 /* Wa_14010449647:xehpsdv */ 2605 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 2606 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2607 2608 /* Wa_18011725039:xehpsdv */ 2609 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2610 wa_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2611 wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2612 } 2613 2614 /* Wa_14012362059:xehpsdv */ 2615 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2616 2617 /* Wa_14014368820:xehpsdv */ 2618 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2619 GLOBAL_INVALIDATION_MODE); 2620 } 2621 } 2622 2623 static void 2624 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2625 { 2626 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2627 return; 2628 2629 engine_fake_wa_init(engine, wal); 2630 2631 /* 2632 * These are common workarounds that just need to applied 2633 * to a single RCS/CCS engine's workaround list since 2634 * they're reset as part of the general render domain reset. 2635 */ 2636 if (engine->class == RENDER_CLASS) 2637 general_render_compute_wa_init(engine, wal); 2638 2639 if (engine->class == RENDER_CLASS) 2640 rcs_engine_wa_init(engine, wal); 2641 else 2642 xcs_engine_wa_init(engine, wal); 2643 } 2644 2645 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2646 { 2647 struct i915_wa_list *wal = &engine->wa_list; 2648 2649 if (GRAPHICS_VER(engine->i915) < 4) 2650 return; 2651 2652 wa_init_start(wal, "engine", engine->name); 2653 engine_init_workarounds(engine, wal); 2654 wa_init_finish(wal); 2655 } 2656 2657 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2658 { 2659 wa_list_apply(engine->gt, &engine->wa_list); 2660 } 2661 2662 static const struct i915_range mcr_ranges_gen8[] = { 2663 { .start = 0x5500, .end = 0x55ff }, 2664 { .start = 0x7000, .end = 0x7fff }, 2665 { .start = 0x9400, .end = 0x97ff }, 2666 { .start = 0xb000, .end = 0xb3ff }, 2667 { .start = 0xe000, .end = 0xe7ff }, 2668 {}, 2669 }; 2670 2671 static const struct i915_range mcr_ranges_gen12[] = { 2672 { .start = 0x8150, .end = 0x815f }, 2673 { .start = 0x9520, .end = 0x955f }, 2674 { .start = 0xb100, .end = 0xb3ff }, 2675 { .start = 0xde80, .end = 0xe8ff }, 2676 { .start = 0x24a00, .end = 0x24a7f }, 2677 {}, 2678 }; 2679 2680 static const struct i915_range mcr_ranges_xehp[] = { 2681 { .start = 0x4000, .end = 0x4aff }, 2682 { .start = 0x5200, .end = 0x52ff }, 2683 { .start = 0x5400, .end = 0x7fff }, 2684 { .start = 0x8140, .end = 0x815f }, 2685 { .start = 0x8c80, .end = 0x8dff }, 2686 { .start = 0x94d0, .end = 0x955f }, 2687 { .start = 0x9680, .end = 0x96ff }, 2688 { .start = 0xb000, .end = 0xb3ff }, 2689 { .start = 0xc800, .end = 0xcfff }, 2690 { .start = 0xd800, .end = 0xd8ff }, 2691 { .start = 0xdc00, .end = 0xffff }, 2692 { .start = 0x17000, .end = 0x17fff }, 2693 { .start = 0x24a00, .end = 0x24a7f }, 2694 {}, 2695 }; 2696 2697 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2698 { 2699 const struct i915_range *mcr_ranges; 2700 int i; 2701 2702 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2703 mcr_ranges = mcr_ranges_xehp; 2704 else if (GRAPHICS_VER(i915) >= 12) 2705 mcr_ranges = mcr_ranges_gen12; 2706 else if (GRAPHICS_VER(i915) >= 8) 2707 mcr_ranges = mcr_ranges_gen8; 2708 else 2709 return false; 2710 2711 /* 2712 * Registers in these ranges are affected by the MCR selector 2713 * which only controls CPU initiated MMIO. Routing does not 2714 * work for CS access so we cannot verify them on this path. 2715 */ 2716 for (i = 0; mcr_ranges[i].start; i++) 2717 if (offset >= mcr_ranges[i].start && 2718 offset <= mcr_ranges[i].end) 2719 return true; 2720 2721 return false; 2722 } 2723 2724 static int 2725 wa_list_srm(struct i915_request *rq, 2726 const struct i915_wa_list *wal, 2727 struct i915_vma *vma) 2728 { 2729 struct drm_i915_private *i915 = rq->engine->i915; 2730 unsigned int i, count = 0; 2731 const struct i915_wa *wa; 2732 u32 srm, *cs; 2733 2734 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2735 if (GRAPHICS_VER(i915) >= 8) 2736 srm++; 2737 2738 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2739 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2740 count++; 2741 } 2742 2743 cs = intel_ring_begin(rq, 4 * count); 2744 if (IS_ERR(cs)) 2745 return PTR_ERR(cs); 2746 2747 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2748 u32 offset = i915_mmio_reg_offset(wa->reg); 2749 2750 if (mcr_range(i915, offset)) 2751 continue; 2752 2753 *cs++ = srm; 2754 *cs++ = offset; 2755 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2756 *cs++ = 0; 2757 } 2758 intel_ring_advance(rq, cs); 2759 2760 return 0; 2761 } 2762 2763 static int engine_wa_list_verify(struct intel_context *ce, 2764 const struct i915_wa_list * const wal, 2765 const char *from) 2766 { 2767 const struct i915_wa *wa; 2768 struct i915_request *rq; 2769 struct i915_vma *vma; 2770 struct i915_gem_ww_ctx ww; 2771 unsigned int i; 2772 u32 *results; 2773 int err; 2774 2775 if (!wal->count) 2776 return 0; 2777 2778 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2779 wal->count * sizeof(u32)); 2780 if (IS_ERR(vma)) 2781 return PTR_ERR(vma); 2782 2783 intel_engine_pm_get(ce->engine); 2784 i915_gem_ww_ctx_init(&ww, false); 2785 retry: 2786 err = i915_gem_object_lock(vma->obj, &ww); 2787 if (err == 0) 2788 err = intel_context_pin_ww(ce, &ww); 2789 if (err) 2790 goto err_pm; 2791 2792 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2793 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2794 if (err) 2795 goto err_unpin; 2796 2797 rq = i915_request_create(ce); 2798 if (IS_ERR(rq)) { 2799 err = PTR_ERR(rq); 2800 goto err_vma; 2801 } 2802 2803 err = i915_request_await_object(rq, vma->obj, true); 2804 if (err == 0) 2805 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2806 if (err == 0) 2807 err = wa_list_srm(rq, wal, vma); 2808 2809 i915_request_get(rq); 2810 if (err) 2811 i915_request_set_error_once(rq, err); 2812 i915_request_add(rq); 2813 2814 if (err) 2815 goto err_rq; 2816 2817 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2818 err = -ETIME; 2819 goto err_rq; 2820 } 2821 2822 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2823 if (IS_ERR(results)) { 2824 err = PTR_ERR(results); 2825 goto err_rq; 2826 } 2827 2828 err = 0; 2829 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2830 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2831 continue; 2832 2833 if (!wa_verify(wa, results[i], wal->name, from)) 2834 err = -ENXIO; 2835 } 2836 2837 i915_gem_object_unpin_map(vma->obj); 2838 2839 err_rq: 2840 i915_request_put(rq); 2841 err_vma: 2842 i915_vma_unpin(vma); 2843 err_unpin: 2844 intel_context_unpin(ce); 2845 err_pm: 2846 if (err == -EDEADLK) { 2847 err = i915_gem_ww_ctx_backoff(&ww); 2848 if (!err) 2849 goto retry; 2850 } 2851 i915_gem_ww_ctx_fini(&ww); 2852 intel_engine_pm_put(ce->engine); 2853 i915_vma_put(vma); 2854 return err; 2855 } 2856 2857 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2858 const char *from) 2859 { 2860 return engine_wa_list_verify(engine->kernel_context, 2861 &engine->wa_list, 2862 from); 2863 } 2864 2865 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2866 #include "selftest_workarounds.c" 2867 #endif 2868