1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * Hardware workarounds are register programming documented to be executed in 22 * the driver that fall outside of the normal programming sequences for a 23 * platform. There are some basic categories of workarounds, depending on 24 * how/when they are applied: 25 * 26 * - Context workarounds: workarounds that touch registers that are 27 * saved/restored to/from the HW context image. The list is emitted (via Load 28 * Register Immediate commands) once when initializing the device and saved in 29 * the default context. That default context is then used on every context 30 * creation to have a "primed golden context", i.e. a context image that 31 * already contains the changes needed to all the registers. 32 * 33 * - Engine workarounds: the list of these WAs is applied whenever the specific 34 * engine is reset. It's also possible that a set of engine classes share a 35 * common power domain and they are reset together. This happens on some 36 * platforms with render and compute engines. In this case (at least) one of 37 * them need to keeep the workaround programming: the approach taken in the 38 * driver is to tie those workarounds to the first compute/render engine that 39 * is registered. When executing with GuC submission, engine resets are 40 * outside of kernel driver control, hence the list of registers involved in 41 * written once, on engine initialization, and then passed to GuC, that 42 * saves/restores their values before/after the reset takes place. See 43 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 44 * 45 * - GT workarounds: the list of these WAs is applied whenever these registers 46 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 47 * 48 * - Register whitelist: some workarounds need to be implemented in userspace, 49 * but need to touch privileged registers. The whitelist in the kernel 50 * instructs the hardware to allow the access to happen. From the kernel side, 51 * this is just a special case of a MMIO workaround (as we write the list of 52 * these to/be-whitelisted registers to some special HW registers). 53 * 54 * - Workaround batchbuffers: buffers that get executed automatically by the 55 * hardware on every HW context restore. These buffers are created and 56 * programmed in the default context so the hardware always go through those 57 * programming sequences when switching contexts. The support for workaround 58 * batchbuffers is enabled these hardware mechanisms: 59 * 60 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 61 * context, pointing the hardware to jump to that location when that offset 62 * is reached in the context restore. Workaround batchbuffer in the driver 63 * currently uses this mechanism for all platforms. 64 * 65 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 66 * pointing the hardware to a buffer to continue executing after the 67 * engine registers are restored in a context restore sequence. This is 68 * currently not used in the driver. 69 * 70 * - Other: There are WAs that, due to their nature, cannot be applied from a 71 * central place. Those are peppered around the rest of the code, as needed. 72 * Workarounds related to the display IP are the main example. 73 * 74 * .. [1] Technically, some registers are powercontext saved & restored, so they 75 * survive a suspend/resume. In practice, writing them again is not too 76 * costly and simplifies things, so it's the approach taken in the driver. 77 */ 78 79 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 80 const char *name, const char *engine_name) 81 { 82 wal->gt = gt; 83 wal->name = name; 84 wal->engine_name = engine_name; 85 } 86 87 #define WA_LIST_CHUNK (1 << 4) 88 89 static void wa_init_finish(struct i915_wa_list *wal) 90 { 91 /* Trim unused entries. */ 92 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 93 struct i915_wa *list = kmemdup(wal->list, 94 wal->count * sizeof(*list), 95 GFP_KERNEL); 96 97 if (list) { 98 kfree(wal->list); 99 wal->list = list; 100 } 101 } 102 103 if (!wal->count) 104 return; 105 106 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 107 wal->wa_count, wal->name, wal->engine_name); 108 } 109 110 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 111 { 112 unsigned int addr = i915_mmio_reg_offset(wa->reg); 113 struct drm_i915_private *i915 = wal->gt->i915; 114 unsigned int start = 0, end = wal->count; 115 const unsigned int grow = WA_LIST_CHUNK; 116 struct i915_wa *wa_; 117 118 GEM_BUG_ON(!is_power_of_2(grow)); 119 120 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 121 struct i915_wa *list; 122 123 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 124 GFP_KERNEL); 125 if (!list) { 126 drm_err(&i915->drm, "No space for workaround init!\n"); 127 return; 128 } 129 130 if (wal->list) { 131 memcpy(list, wal->list, sizeof(*wa) * wal->count); 132 kfree(wal->list); 133 } 134 135 wal->list = list; 136 } 137 138 while (start < end) { 139 unsigned int mid = start + (end - start) / 2; 140 141 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 142 start = mid + 1; 143 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 144 end = mid; 145 } else { 146 wa_ = &wal->list[mid]; 147 148 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 149 drm_err(&i915->drm, 150 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 151 i915_mmio_reg_offset(wa_->reg), 152 wa_->clr, wa_->set); 153 154 wa_->set &= ~wa->clr; 155 } 156 157 wal->wa_count++; 158 wa_->set |= wa->set; 159 wa_->clr |= wa->clr; 160 wa_->read |= wa->read; 161 return; 162 } 163 } 164 165 wal->wa_count++; 166 wa_ = &wal->list[wal->count++]; 167 *wa_ = *wa; 168 169 while (wa_-- > wal->list) { 170 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 171 i915_mmio_reg_offset(wa_[1].reg)); 172 if (i915_mmio_reg_offset(wa_[1].reg) > 173 i915_mmio_reg_offset(wa_[0].reg)) 174 break; 175 176 swap(wa_[1], wa_[0]); 177 } 178 } 179 180 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 181 u32 clear, u32 set, u32 read_mask, bool masked_reg) 182 { 183 struct i915_wa wa = { 184 .reg = reg, 185 .clr = clear, 186 .set = set, 187 .read = read_mask, 188 .masked_reg = masked_reg, 189 }; 190 191 _wa_add(wal, &wa); 192 } 193 194 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 195 u32 clear, u32 set, u32 read_mask, bool masked_reg) 196 { 197 struct i915_wa wa = { 198 .mcr_reg = reg, 199 .clr = clear, 200 .set = set, 201 .read = read_mask, 202 .masked_reg = masked_reg, 203 .is_mcr = 1, 204 }; 205 206 _wa_add(wal, &wa); 207 } 208 209 static void 210 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 211 { 212 wa_add(wal, reg, clear, set, clear, false); 213 } 214 215 static void 216 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 217 { 218 wa_mcr_add(wal, reg, clear, set, clear, false); 219 } 220 221 static void 222 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 223 { 224 wa_write_clr_set(wal, reg, ~0, set); 225 } 226 227 static void 228 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 229 { 230 wa_write_clr_set(wal, reg, set, set); 231 } 232 233 static void 234 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 235 { 236 wa_mcr_write_clr_set(wal, reg, set, set); 237 } 238 239 static void 240 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 241 { 242 wa_write_clr_set(wal, reg, clr, 0); 243 } 244 245 static void 246 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 247 { 248 wa_mcr_write_clr_set(wal, reg, clr, 0); 249 } 250 251 /* 252 * WA operations on "masked register". A masked register has the upper 16 bits 253 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 254 * portion of the register without a rmw: you simply write in the upper 16 bits 255 * the mask of bits you are going to modify. 256 * 257 * The wa_masked_* family of functions already does the necessary operations to 258 * calculate the mask based on the parameters passed, so user only has to 259 * provide the lower 16 bits of that register. 260 */ 261 262 static void 263 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 264 { 265 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 266 } 267 268 static void 269 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 270 { 271 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 272 } 273 274 static void 275 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 276 { 277 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 278 } 279 280 static void 281 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 282 { 283 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 284 } 285 286 static void 287 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 288 u32 mask, u32 val) 289 { 290 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 291 } 292 293 static void 294 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 295 u32 mask, u32 val) 296 { 297 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 298 } 299 300 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 301 struct i915_wa_list *wal) 302 { 303 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 304 } 305 306 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 307 struct i915_wa_list *wal) 308 { 309 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 310 } 311 312 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 313 struct i915_wa_list *wal) 314 { 315 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 316 317 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 318 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 319 320 /* WaDisablePartialInstShootdown:bdw,chv */ 321 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 322 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 323 324 /* Use Force Non-Coherent whenever executing a 3D context. This is a 325 * workaround for a possible hang in the unlikely event a TLB 326 * invalidation occurs during a PSD flush. 327 */ 328 /* WaForceEnableNonCoherent:bdw,chv */ 329 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 330 wa_masked_en(wal, HDC_CHICKEN0, 331 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 332 HDC_FORCE_NON_COHERENT); 333 334 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 335 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 336 * polygons in the same 8x4 pixel/sample area to be processed without 337 * stalling waiting for the earlier ones to write to Hierarchical Z 338 * buffer." 339 * 340 * This optimization is off by default for BDW and CHV; turn it on. 341 */ 342 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 343 344 /* Wa4x4STCOptimizationDisable:bdw,chv */ 345 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 346 347 /* 348 * BSpec recommends 8x4 when MSAA is used, 349 * however in practice 16x4 seems fastest. 350 * 351 * Note that PS/WM thread counts depend on the WIZ hashing 352 * disable bit, which we don't touch here, but it's good 353 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 354 */ 355 wa_masked_field_set(wal, GEN7_GT_MODE, 356 GEN6_WIZ_HASHING_MASK, 357 GEN6_WIZ_HASHING_16x4); 358 } 359 360 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 361 struct i915_wa_list *wal) 362 { 363 struct drm_i915_private *i915 = engine->i915; 364 365 gen8_ctx_workarounds_init(engine, wal); 366 367 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 368 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 369 370 /* WaDisableDopClockGating:bdw 371 * 372 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 373 * to disable EUTC clock gating. 374 */ 375 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 376 DOP_CLOCK_GATING_DISABLE); 377 378 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 379 GEN8_SAMPLER_POWER_BYPASS_DIS); 380 381 wa_masked_en(wal, HDC_CHICKEN0, 382 /* WaForceContextSaveRestoreNonCoherent:bdw */ 383 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 384 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 385 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 386 } 387 388 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 389 struct i915_wa_list *wal) 390 { 391 gen8_ctx_workarounds_init(engine, wal); 392 393 /* WaDisableThreadStallDopClockGating:chv */ 394 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 395 396 /* Improve HiZ throughput on CHV. */ 397 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 398 } 399 400 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 401 struct i915_wa_list *wal) 402 { 403 struct drm_i915_private *i915 = engine->i915; 404 405 if (HAS_LLC(i915)) { 406 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 407 * 408 * Must match Display Engine. See 409 * WaCompressedResourceDisplayNewHashMode. 410 */ 411 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 412 GEN9_PBE_COMPRESSED_HASH_SELECTION); 413 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 414 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 415 } 416 417 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 418 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 419 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 420 FLOW_CONTROL_ENABLE | 421 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 422 423 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 424 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 425 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 426 GEN9_ENABLE_YV12_BUGFIX | 427 GEN9_ENABLE_GPGPU_PREEMPTION); 428 429 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 430 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 431 wa_masked_en(wal, CACHE_MODE_1, 432 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 433 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 434 435 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 436 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 437 GEN9_CCS_TLB_PREFETCH_ENABLE); 438 439 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 440 wa_masked_en(wal, HDC_CHICKEN0, 441 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 442 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 443 444 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 445 * both tied to WaForceContextSaveRestoreNonCoherent 446 * in some hsds for skl. We keep the tie for all gen9. The 447 * documentation is a bit hazy and so we want to get common behaviour, 448 * even though there is no clear evidence we would need both on kbl/bxt. 449 * This area has been source of system hangs so we play it safe 450 * and mimic the skl regardless of what bspec says. 451 * 452 * Use Force Non-Coherent whenever executing a 3D context. This 453 * is a workaround for a possible hang in the unlikely event 454 * a TLB invalidation occurs during a PSD flush. 455 */ 456 457 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 458 wa_masked_en(wal, HDC_CHICKEN0, 459 HDC_FORCE_NON_COHERENT); 460 461 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 462 if (IS_SKYLAKE(i915) || 463 IS_KABYLAKE(i915) || 464 IS_COFFEELAKE(i915) || 465 IS_COMETLAKE(i915)) 466 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 467 GEN8_SAMPLER_POWER_BYPASS_DIS); 468 469 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 470 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 471 472 /* 473 * Supporting preemption with fine-granularity requires changes in the 474 * batch buffer programming. Since we can't break old userspace, we 475 * need to set our default preemption level to safe value. Userspace is 476 * still able to use more fine-grained preemption levels, since in 477 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 478 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 479 * not real HW workarounds, but merely a way to start using preemption 480 * while maintaining old contract with userspace. 481 */ 482 483 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 484 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 485 486 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 487 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 488 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 489 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 490 491 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 492 if (IS_GEN9_LP(i915)) 493 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 494 } 495 496 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 497 struct i915_wa_list *wal) 498 { 499 struct intel_gt *gt = engine->gt; 500 u8 vals[3] = { 0, 0, 0 }; 501 unsigned int i; 502 503 for (i = 0; i < 3; i++) { 504 u8 ss; 505 506 /* 507 * Only consider slices where one, and only one, subslice has 7 508 * EUs 509 */ 510 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 511 continue; 512 513 /* 514 * subslice_7eu[i] != 0 (because of the check above) and 515 * ss_max == 4 (maximum number of subslices possible per slice) 516 * 517 * -> 0 <= ss <= 3; 518 */ 519 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 520 vals[i] = 3 - ss; 521 } 522 523 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 524 return; 525 526 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 527 wa_masked_field_set(wal, GEN7_GT_MODE, 528 GEN9_IZ_HASHING_MASK(2) | 529 GEN9_IZ_HASHING_MASK(1) | 530 GEN9_IZ_HASHING_MASK(0), 531 GEN9_IZ_HASHING(2, vals[2]) | 532 GEN9_IZ_HASHING(1, vals[1]) | 533 GEN9_IZ_HASHING(0, vals[0])); 534 } 535 536 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 537 struct i915_wa_list *wal) 538 { 539 gen9_ctx_workarounds_init(engine, wal); 540 skl_tune_iz_hashing(engine, wal); 541 } 542 543 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 544 struct i915_wa_list *wal) 545 { 546 gen9_ctx_workarounds_init(engine, wal); 547 548 /* WaDisableThreadStallDopClockGating:bxt */ 549 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 550 STALL_DOP_GATING_DISABLE); 551 552 /* WaToEnableHwFixForPushConstHWBug:bxt */ 553 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 554 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 555 } 556 557 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 558 struct i915_wa_list *wal) 559 { 560 struct drm_i915_private *i915 = engine->i915; 561 562 gen9_ctx_workarounds_init(engine, wal); 563 564 /* WaToEnableHwFixForPushConstHWBug:kbl */ 565 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 566 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 567 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 568 569 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 570 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 571 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 572 } 573 574 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 575 struct i915_wa_list *wal) 576 { 577 gen9_ctx_workarounds_init(engine, wal); 578 579 /* WaToEnableHwFixForPushConstHWBug:glk */ 580 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 581 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 582 } 583 584 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 585 struct i915_wa_list *wal) 586 { 587 gen9_ctx_workarounds_init(engine, wal); 588 589 /* WaToEnableHwFixForPushConstHWBug:cfl */ 590 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 591 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 592 593 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 594 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 595 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 596 } 597 598 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 599 struct i915_wa_list *wal) 600 { 601 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 602 wa_write(wal, 603 GEN8_L3CNTLREG, 604 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 605 GEN8_ERRDETBCTRL); 606 607 /* WaForceEnableNonCoherent:icl 608 * This is not the same workaround as in early Gen9 platforms, where 609 * lacking this could cause system hangs, but coherency performance 610 * overhead is high and only a few compute workloads really need it 611 * (the register is whitelisted in hardware now, so UMDs can opt in 612 * for coherency if they have a good reason). 613 */ 614 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 615 616 /* WaEnableFloatBlendOptimization:icl */ 617 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 618 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 619 0 /* write-only, so skip validation */, 620 true); 621 622 /* WaDisableGPGPUMidThreadPreemption:icl */ 623 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 624 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 625 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 626 627 /* allow headerless messages for preemptible GPGPU context */ 628 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 629 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 630 631 /* Wa_1604278689:icl,ehl */ 632 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 633 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 634 0, /* write-only register; skip validation */ 635 0xFFFFFFFF); 636 637 /* Wa_1406306137:icl,ehl */ 638 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 639 } 640 641 /* 642 * These settings aren't actually workarounds, but general tuning settings that 643 * need to be programmed on dg2 platform. 644 */ 645 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 646 struct i915_wa_list *wal) 647 { 648 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 649 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 650 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 651 wa_mcr_add(wal, 652 XEHP_FF_MODE2, 653 FF_MODE2_TDS_TIMER_MASK, 654 FF_MODE2_TDS_TIMER_128, 655 0, false); 656 } 657 658 /* 659 * These settings aren't actually workarounds, but general tuning settings that 660 * need to be programmed on several platforms. 661 */ 662 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 663 struct i915_wa_list *wal) 664 { 665 /* 666 * Although some platforms refer to it as Wa_1604555607, we need to 667 * program it even on those that don't explicitly list that 668 * workaround. 669 * 670 * Note that the programming of this register is further modified 671 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 672 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 673 * value when read. The default value for this register is zero for all 674 * fields and there are no bit masks. So instead of doing a RMW we 675 * should just write TDS timer value. For the same reason read 676 * verification is ignored. 677 */ 678 wa_add(wal, 679 GEN12_FF_MODE2, 680 FF_MODE2_TDS_TIMER_MASK, 681 FF_MODE2_TDS_TIMER_128, 682 0, false); 683 } 684 685 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 686 struct i915_wa_list *wal) 687 { 688 struct drm_i915_private *i915 = engine->i915; 689 690 gen12_ctx_gt_tuning_init(engine, wal); 691 692 /* 693 * Wa_1409142259:tgl,dg1,adl-p 694 * Wa_1409347922:tgl,dg1,adl-p 695 * Wa_1409252684:tgl,dg1,adl-p 696 * Wa_1409217633:tgl,dg1,adl-p 697 * Wa_1409207793:tgl,dg1,adl-p 698 * Wa_1409178076:tgl,dg1,adl-p 699 * Wa_1408979724:tgl,dg1,adl-p 700 * Wa_14010443199:tgl,rkl,dg1,adl-p 701 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 702 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 703 */ 704 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 705 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 706 707 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 708 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 709 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 710 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 711 712 /* 713 * Wa_16011163337 714 * 715 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 716 * to Wa_1608008084. 717 */ 718 wa_add(wal, 719 GEN12_FF_MODE2, 720 FF_MODE2_GS_TIMER_MASK, 721 FF_MODE2_GS_TIMER_224, 722 0, false); 723 724 if (!IS_DG1(i915)) 725 /* Wa_1806527549 */ 726 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 727 } 728 729 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 730 struct i915_wa_list *wal) 731 { 732 gen12_ctx_workarounds_init(engine, wal); 733 734 /* Wa_1409044764 */ 735 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 736 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 737 738 /* Wa_22010493298 */ 739 wa_masked_en(wal, HIZ_CHICKEN, 740 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 741 } 742 743 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 744 struct i915_wa_list *wal) 745 { 746 dg2_ctx_gt_tuning_init(engine, wal); 747 748 /* Wa_16011186671:dg2_g11 */ 749 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 750 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 751 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 752 } 753 754 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 755 /* Wa_14010469329:dg2_g10 */ 756 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 757 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 758 759 /* 760 * Wa_22010465075:dg2_g10 761 * Wa_22010613112:dg2_g10 762 * Wa_14010698770:dg2_g10 763 */ 764 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 765 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 766 } 767 768 /* Wa_16013271637:dg2 */ 769 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 770 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 771 772 /* Wa_14014947963:dg2 */ 773 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 774 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 775 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 776 777 /* Wa_18018764978:dg2 */ 778 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || 779 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 780 wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 781 782 /* Wa_15010599737:dg2 */ 783 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 784 785 /* Wa_18019271663:dg2 */ 786 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 787 } 788 789 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, 790 struct i915_wa_list *wal) 791 { 792 struct drm_i915_private *i915 = engine->i915; 793 794 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 795 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 796 /* Wa_14014947963 */ 797 wa_masked_field_set(wal, VF_PREEMPTION, 798 PREEMPTION_VERTEX_COUNT, 0x4000); 799 800 /* Wa_16013271637 */ 801 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 802 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 803 804 /* Wa_18019627453 */ 805 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); 806 807 /* Wa_18018764978 */ 808 wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 809 } 810 811 /* Wa_18019271663 */ 812 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 813 } 814 815 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 816 struct i915_wa_list *wal) 817 { 818 /* 819 * This is a "fake" workaround defined by software to ensure we 820 * maintain reliable, backward-compatible behavior for userspace with 821 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 822 * 823 * The per-context setting of MI_MODE[12] determines whether the bits 824 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 825 * in the traditional manner or whether they should instead use a new 826 * tgl+ meaning that breaks backward compatibility, but allows nesting 827 * into 3rd-level batchbuffers. When this new capability was first 828 * added in TGL, it remained off by default unless a context 829 * intentionally opted in to the new behavior. However Xe_HPG now 830 * flips this on by default and requires that we explicitly opt out if 831 * we don't want the new behavior. 832 * 833 * From a SW perspective, we want to maintain the backward-compatible 834 * behavior for userspace, so we'll apply a fake workaround to set it 835 * back to the legacy behavior on platforms where the hardware default 836 * is to break compatibility. At the moment there is no Linux 837 * userspace that utilizes third-level batchbuffers, so this will avoid 838 * userspace from needing to make any changes. using the legacy 839 * meaning is the correct thing to do. If/when we have userspace 840 * consumers that want to utilize third-level batch nesting, we can 841 * provide a context parameter to allow them to opt-in. 842 */ 843 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 844 } 845 846 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 847 struct i915_wa_list *wal) 848 { 849 u8 mocs; 850 851 /* 852 * Some blitter commands do not have a field for MOCS, those 853 * commands will use MOCS index pointed by BLIT_CCTL. 854 * BLIT_CCTL registers are needed to be programmed to un-cached. 855 */ 856 if (engine->class == COPY_ENGINE_CLASS) { 857 mocs = engine->gt->mocs.uc_index; 858 wa_write_clr_set(wal, 859 BLIT_CCTL(engine->mmio_base), 860 BLIT_CCTL_MASK, 861 BLIT_CCTL_MOCS(mocs, mocs)); 862 } 863 } 864 865 /* 866 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 867 * defined by the hardware team, but it programming general context registers. 868 * Adding those context register programming in context workaround 869 * allow us to use the wa framework for proper application and validation. 870 */ 871 static void 872 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 873 struct i915_wa_list *wal) 874 { 875 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 876 fakewa_disable_nestedbb_mode(engine, wal); 877 878 gen12_ctx_gt_mocs_init(engine, wal); 879 } 880 881 static void 882 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 883 struct i915_wa_list *wal, 884 const char *name) 885 { 886 struct drm_i915_private *i915 = engine->i915; 887 888 wa_init_start(wal, engine->gt, name, engine->name); 889 890 /* Applies to all engines */ 891 /* 892 * Fake workarounds are not the actual workaround but 893 * programming of context registers using workaround framework. 894 */ 895 if (GRAPHICS_VER(i915) >= 12) 896 gen12_ctx_gt_fake_wa_init(engine, wal); 897 898 if (engine->class != RENDER_CLASS) 899 goto done; 900 901 if (IS_METEORLAKE(i915)) 902 mtl_ctx_workarounds_init(engine, wal); 903 else if (IS_PONTEVECCHIO(i915)) 904 ; /* noop; none at this time */ 905 else if (IS_DG2(i915)) 906 dg2_ctx_workarounds_init(engine, wal); 907 else if (IS_XEHPSDV(i915)) 908 ; /* noop; none at this time */ 909 else if (IS_DG1(i915)) 910 dg1_ctx_workarounds_init(engine, wal); 911 else if (GRAPHICS_VER(i915) == 12) 912 gen12_ctx_workarounds_init(engine, wal); 913 else if (GRAPHICS_VER(i915) == 11) 914 icl_ctx_workarounds_init(engine, wal); 915 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 916 cfl_ctx_workarounds_init(engine, wal); 917 else if (IS_GEMINILAKE(i915)) 918 glk_ctx_workarounds_init(engine, wal); 919 else if (IS_KABYLAKE(i915)) 920 kbl_ctx_workarounds_init(engine, wal); 921 else if (IS_BROXTON(i915)) 922 bxt_ctx_workarounds_init(engine, wal); 923 else if (IS_SKYLAKE(i915)) 924 skl_ctx_workarounds_init(engine, wal); 925 else if (IS_CHERRYVIEW(i915)) 926 chv_ctx_workarounds_init(engine, wal); 927 else if (IS_BROADWELL(i915)) 928 bdw_ctx_workarounds_init(engine, wal); 929 else if (GRAPHICS_VER(i915) == 7) 930 gen7_ctx_workarounds_init(engine, wal); 931 else if (GRAPHICS_VER(i915) == 6) 932 gen6_ctx_workarounds_init(engine, wal); 933 else if (GRAPHICS_VER(i915) < 8) 934 ; 935 else 936 MISSING_CASE(GRAPHICS_VER(i915)); 937 938 done: 939 wa_init_finish(wal); 940 } 941 942 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 943 { 944 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 945 } 946 947 int intel_engine_emit_ctx_wa(struct i915_request *rq) 948 { 949 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 950 struct i915_wa *wa; 951 unsigned int i; 952 u32 *cs; 953 int ret; 954 955 if (wal->count == 0) 956 return 0; 957 958 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 959 if (ret) 960 return ret; 961 962 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 963 if (IS_ERR(cs)) 964 return PTR_ERR(cs); 965 966 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 967 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 968 *cs++ = i915_mmio_reg_offset(wa->reg); 969 *cs++ = wa->set; 970 } 971 *cs++ = MI_NOOP; 972 973 intel_ring_advance(rq, cs); 974 975 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 976 if (ret) 977 return ret; 978 979 return 0; 980 } 981 982 static void 983 gen4_gt_workarounds_init(struct intel_gt *gt, 984 struct i915_wa_list *wal) 985 { 986 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 987 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 988 } 989 990 static void 991 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 992 { 993 gen4_gt_workarounds_init(gt, wal); 994 995 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 996 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 997 } 998 999 static void 1000 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1001 { 1002 g4x_gt_workarounds_init(gt, wal); 1003 1004 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 1005 } 1006 1007 static void 1008 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1009 { 1010 } 1011 1012 static void 1013 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1014 { 1015 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 1016 wa_masked_dis(wal, 1017 GEN7_COMMON_SLICE_CHICKEN1, 1018 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 1019 1020 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 1021 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 1022 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 1023 1024 /* WaForceL3Serialization:ivb */ 1025 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1026 } 1027 1028 static void 1029 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1030 { 1031 /* WaForceL3Serialization:vlv */ 1032 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1033 1034 /* 1035 * WaIncreaseL3CreditsForVLVB0:vlv 1036 * This is the hardware default actually. 1037 */ 1038 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1039 } 1040 1041 static void 1042 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1043 { 1044 /* L3 caching of data atomics doesn't work -- disable it. */ 1045 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1046 1047 wa_add(wal, 1048 HSW_ROW_CHICKEN3, 0, 1049 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1050 0 /* XXX does this reg exist? */, true); 1051 1052 /* WaVSRefCountFullforceMissDisable:hsw */ 1053 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1054 } 1055 1056 static void 1057 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1058 { 1059 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1060 unsigned int slice, subslice; 1061 u32 mcr, mcr_mask; 1062 1063 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1064 1065 /* 1066 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1067 * Before any MMIO read into slice/subslice specific registers, MCR 1068 * packet control register needs to be programmed to point to any 1069 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1070 * This means each subsequent MMIO read will be forwarded to an 1071 * specific s/ss combination, but this is OK since these registers 1072 * are consistent across s/ss in almost all cases. In the rare 1073 * occasions, such as INSTDONE, where this value is dependent 1074 * on s/ss combo, the read should be done with read_subslice_reg. 1075 */ 1076 slice = ffs(sseu->slice_mask) - 1; 1077 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1078 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1079 GEM_BUG_ON(!subslice); 1080 subslice--; 1081 1082 /* 1083 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1084 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1085 */ 1086 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1087 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1088 1089 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1090 1091 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1092 } 1093 1094 static void 1095 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1096 { 1097 struct drm_i915_private *i915 = gt->i915; 1098 1099 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1100 gen9_wa_init_mcr(i915, wal); 1101 1102 /* WaDisableKillLogic:bxt,skl,kbl */ 1103 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1104 wa_write_or(wal, 1105 GAM_ECOCHK, 1106 ECOCHK_DIS_TLB); 1107 1108 if (HAS_LLC(i915)) { 1109 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1110 * 1111 * Must match Display Engine. See 1112 * WaCompressedResourceDisplayNewHashMode. 1113 */ 1114 wa_write_or(wal, 1115 MMCD_MISC_CTRL, 1116 MMCD_PCLA | MMCD_HOTSPOT_EN); 1117 } 1118 1119 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1120 wa_write_or(wal, 1121 GAM_ECOCHK, 1122 BDW_DISABLE_HDC_INVALIDATION); 1123 } 1124 1125 static void 1126 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1127 { 1128 gen9_gt_workarounds_init(gt, wal); 1129 1130 /* WaDisableGafsUnitClkGating:skl */ 1131 wa_write_or(wal, 1132 GEN7_UCGCTL4, 1133 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1134 1135 /* WaInPlaceDecompressionHang:skl */ 1136 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1137 wa_write_or(wal, 1138 GEN9_GAMT_ECO_REG_RW_IA, 1139 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1140 } 1141 1142 static void 1143 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1144 { 1145 gen9_gt_workarounds_init(gt, wal); 1146 1147 /* WaDisableDynamicCreditSharing:kbl */ 1148 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1149 wa_write_or(wal, 1150 GAMT_CHKN_BIT_REG, 1151 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1152 1153 /* WaDisableGafsUnitClkGating:kbl */ 1154 wa_write_or(wal, 1155 GEN7_UCGCTL4, 1156 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1157 1158 /* WaInPlaceDecompressionHang:kbl */ 1159 wa_write_or(wal, 1160 GEN9_GAMT_ECO_REG_RW_IA, 1161 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1162 } 1163 1164 static void 1165 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1166 { 1167 gen9_gt_workarounds_init(gt, wal); 1168 } 1169 1170 static void 1171 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1172 { 1173 gen9_gt_workarounds_init(gt, wal); 1174 1175 /* WaDisableGafsUnitClkGating:cfl */ 1176 wa_write_or(wal, 1177 GEN7_UCGCTL4, 1178 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1179 1180 /* WaInPlaceDecompressionHang:cfl */ 1181 wa_write_or(wal, 1182 GEN9_GAMT_ECO_REG_RW_IA, 1183 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1184 } 1185 1186 static void __set_mcr_steering(struct i915_wa_list *wal, 1187 i915_reg_t steering_reg, 1188 unsigned int slice, unsigned int subslice) 1189 { 1190 u32 mcr, mcr_mask; 1191 1192 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1193 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1194 1195 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1196 } 1197 1198 static void debug_dump_steering(struct intel_gt *gt) 1199 { 1200 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1201 1202 if (drm_debug_enabled(DRM_UT_DRIVER)) 1203 intel_gt_mcr_report_steering(&p, gt, false); 1204 } 1205 1206 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1207 unsigned int slice, unsigned int subslice) 1208 { 1209 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1210 1211 gt->default_steering.groupid = slice; 1212 gt->default_steering.instanceid = subslice; 1213 1214 debug_dump_steering(gt); 1215 } 1216 1217 static void 1218 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1219 { 1220 const struct sseu_dev_info *sseu = >->info.sseu; 1221 unsigned int subslice; 1222 1223 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1224 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1225 1226 /* 1227 * Although a platform may have subslices, we need to always steer 1228 * reads to the lowest instance that isn't fused off. When Render 1229 * Power Gating is enabled, grabbing forcewake will only power up a 1230 * single subslice (the "minconfig") if there isn't a real workload 1231 * that needs to be run; this means that if we steer register reads to 1232 * one of the higher subslices, we run the risk of reading back 0's or 1233 * random garbage. 1234 */ 1235 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1236 1237 /* 1238 * If the subslice we picked above also steers us to a valid L3 bank, 1239 * then we can just rely on the default steering and won't need to 1240 * worry about explicitly re-steering L3BANK reads later. 1241 */ 1242 if (gt->info.l3bank_mask & BIT(subslice)) 1243 gt->steering_table[L3BANK] = NULL; 1244 1245 __add_mcr_wa(gt, wal, 0, subslice); 1246 } 1247 1248 static void 1249 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1250 { 1251 const struct sseu_dev_info *sseu = >->info.sseu; 1252 unsigned long slice, subslice = 0, slice_mask = 0; 1253 u32 lncf_mask = 0; 1254 int i; 1255 1256 /* 1257 * On Xe_HP the steering increases in complexity. There are now several 1258 * more units that require steering and we're not guaranteed to be able 1259 * to find a common setting for all of them. These are: 1260 * - GSLICE (fusable) 1261 * - DSS (sub-unit within gslice; fusable) 1262 * - L3 Bank (fusable) 1263 * - MSLICE (fusable) 1264 * - LNCF (sub-unit within mslice; always present if mslice is present) 1265 * 1266 * We'll do our default/implicit steering based on GSLICE (in the 1267 * sliceid field) and DSS (in the subsliceid field). If we can 1268 * find overlap between the valid MSLICE and/or LNCF values with 1269 * a suitable GSLICE, then we can just re-use the default value and 1270 * skip and explicit steering at runtime. 1271 * 1272 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1273 * a valid sliceid value. DSS steering is the only type of steering 1274 * that utilizes the 'subsliceid' bits. 1275 * 1276 * Also note that, even though the steering domain is called "GSlice" 1277 * and it is encoded in the register using the gslice format, the spec 1278 * says that the combined (geometry | compute) fuse should be used to 1279 * select the steering. 1280 */ 1281 1282 /* Find the potential gslice candidates */ 1283 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1284 GEN_DSS_PER_GSLICE); 1285 1286 /* 1287 * Find the potential LNCF candidates. Either LNCF within a valid 1288 * mslice is fine. 1289 */ 1290 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1291 lncf_mask |= (0x3 << (i * 2)); 1292 1293 /* 1294 * Are there any sliceid values that work for both GSLICE and LNCF 1295 * steering? 1296 */ 1297 if (slice_mask & lncf_mask) { 1298 slice_mask &= lncf_mask; 1299 gt->steering_table[LNCF] = NULL; 1300 } 1301 1302 /* How about sliceid values that also work for MSLICE steering? */ 1303 if (slice_mask & gt->info.mslice_mask) { 1304 slice_mask &= gt->info.mslice_mask; 1305 gt->steering_table[MSLICE] = NULL; 1306 } 1307 1308 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1309 gt->steering_table[GAM] = NULL; 1310 1311 slice = __ffs(slice_mask); 1312 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1313 GEN_DSS_PER_GSLICE; 1314 1315 __add_mcr_wa(gt, wal, slice, subslice); 1316 1317 /* 1318 * SQIDI ranges are special because they use different steering 1319 * registers than everything else we work with. On XeHP SDV and 1320 * DG2-G10, any value in the steering registers will work fine since 1321 * all instances are present, but DG2-G11 only has SQIDI instances at 1322 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1323 * we'll just steer to a hardcoded "2" since that value will work 1324 * everywhere. 1325 */ 1326 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1327 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1328 1329 /* 1330 * On DG2, GAM registers have a dedicated steering control register 1331 * and must always be programmed to a hardcoded groupid of "1." 1332 */ 1333 if (IS_DG2(gt->i915)) 1334 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1335 } 1336 1337 static void 1338 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1339 { 1340 unsigned int dss; 1341 1342 /* 1343 * Setup implicit steering for COMPUTE and DSS ranges to the first 1344 * non-fused-off DSS. All other types of MCR registers will be 1345 * explicitly steered. 1346 */ 1347 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1348 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1349 } 1350 1351 static void 1352 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1353 { 1354 struct drm_i915_private *i915 = gt->i915; 1355 1356 icl_wa_init_mcr(gt, wal); 1357 1358 /* WaModifyGamTlbPartitioning:icl */ 1359 wa_write_clr_set(wal, 1360 GEN11_GACB_PERF_CTRL, 1361 GEN11_HASH_CTRL_MASK, 1362 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1363 1364 /* Wa_1405766107:icl 1365 * Formerly known as WaCL2SFHalfMaxAlloc 1366 */ 1367 wa_write_or(wal, 1368 GEN11_LSN_UNSLCVC, 1369 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1370 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1371 1372 /* Wa_220166154:icl 1373 * Formerly known as WaDisCtxReload 1374 */ 1375 wa_write_or(wal, 1376 GEN8_GAMW_ECO_DEV_RW_IA, 1377 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1378 1379 /* Wa_1406463099:icl 1380 * Formerly known as WaGamTlbPendError 1381 */ 1382 wa_write_or(wal, 1383 GAMT_CHKN_BIT_REG, 1384 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1385 1386 /* Wa_1407352427:icl,ehl */ 1387 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1388 PSDUNIT_CLKGATE_DIS); 1389 1390 /* Wa_1406680159:icl,ehl */ 1391 wa_mcr_write_or(wal, 1392 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1393 GWUNIT_CLKGATE_DIS); 1394 1395 /* Wa_1607087056:icl,ehl,jsl */ 1396 if (IS_ICELAKE(i915) || 1397 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1398 wa_write_or(wal, 1399 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1400 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1401 1402 /* 1403 * This is not a documented workaround, but rather an optimization 1404 * to reduce sampler power. 1405 */ 1406 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1407 } 1408 1409 /* 1410 * Though there are per-engine instances of these registers, 1411 * they retain their value through engine resets and should 1412 * only be provided on the GT workaround list rather than 1413 * the engine-specific workaround list. 1414 */ 1415 static void 1416 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1417 { 1418 struct intel_engine_cs *engine; 1419 int id; 1420 1421 for_each_engine(engine, gt, id) { 1422 if (engine->class != VIDEO_DECODE_CLASS || 1423 (engine->instance % 2)) 1424 continue; 1425 1426 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1427 IECPUNIT_CLKGATE_DIS); 1428 } 1429 } 1430 1431 static void 1432 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1433 { 1434 icl_wa_init_mcr(gt, wal); 1435 1436 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1437 wa_14011060649(gt, wal); 1438 1439 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1440 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1441 } 1442 1443 static void 1444 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1445 { 1446 struct drm_i915_private *i915 = gt->i915; 1447 1448 gen12_gt_workarounds_init(gt, wal); 1449 1450 /* Wa_1409420604:tgl */ 1451 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1452 wa_mcr_write_or(wal, 1453 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1454 CPSSUNIT_CLKGATE_DIS); 1455 1456 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1457 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1458 wa_write_or(wal, 1459 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1460 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1461 1462 /* Wa_1408615072:tgl[a0] */ 1463 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1464 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1465 VSUNIT_CLKGATE_DIS_TGL); 1466 } 1467 1468 static void 1469 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1470 { 1471 struct drm_i915_private *i915 = gt->i915; 1472 1473 gen12_gt_workarounds_init(gt, wal); 1474 1475 /* Wa_1607087056:dg1 */ 1476 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1477 wa_write_or(wal, 1478 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1479 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1480 1481 /* Wa_1409420604:dg1 */ 1482 if (IS_DG1(i915)) 1483 wa_mcr_write_or(wal, 1484 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1485 CPSSUNIT_CLKGATE_DIS); 1486 1487 /* Wa_1408615072:dg1 */ 1488 /* Empirical testing shows this register is unaffected by engine reset. */ 1489 if (IS_DG1(i915)) 1490 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1491 VSUNIT_CLKGATE_DIS_TGL); 1492 } 1493 1494 static void 1495 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1496 { 1497 struct drm_i915_private *i915 = gt->i915; 1498 1499 xehp_init_mcr(gt, wal); 1500 1501 /* Wa_1409757795:xehpsdv */ 1502 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1503 1504 /* Wa_16011155590:xehpsdv */ 1505 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1506 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1507 TSGUNIT_CLKGATE_DIS); 1508 1509 /* Wa_14011780169:xehpsdv */ 1510 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1511 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1512 GAMTLBVDBOX7_CLKGATE_DIS | 1513 GAMTLBVDBOX6_CLKGATE_DIS | 1514 GAMTLBVDBOX5_CLKGATE_DIS | 1515 GAMTLBVDBOX4_CLKGATE_DIS | 1516 GAMTLBVDBOX3_CLKGATE_DIS | 1517 GAMTLBVDBOX2_CLKGATE_DIS | 1518 GAMTLBVDBOX1_CLKGATE_DIS | 1519 GAMTLBVDBOX0_CLKGATE_DIS | 1520 GAMTLBKCR_CLKGATE_DIS | 1521 GAMTLBGUC_CLKGATE_DIS | 1522 GAMTLBBLT_CLKGATE_DIS); 1523 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1524 GAMTLBGFXA1_CLKGATE_DIS | 1525 GAMTLBCOMPA0_CLKGATE_DIS | 1526 GAMTLBCOMPA1_CLKGATE_DIS | 1527 GAMTLBCOMPB0_CLKGATE_DIS | 1528 GAMTLBCOMPB1_CLKGATE_DIS | 1529 GAMTLBCOMPC0_CLKGATE_DIS | 1530 GAMTLBCOMPC1_CLKGATE_DIS | 1531 GAMTLBCOMPD0_CLKGATE_DIS | 1532 GAMTLBCOMPD1_CLKGATE_DIS | 1533 GAMTLBMERT_CLKGATE_DIS | 1534 GAMTLBVEBOX3_CLKGATE_DIS | 1535 GAMTLBVEBOX2_CLKGATE_DIS | 1536 GAMTLBVEBOX1_CLKGATE_DIS | 1537 GAMTLBVEBOX0_CLKGATE_DIS); 1538 } 1539 1540 /* Wa_16012725990:xehpsdv */ 1541 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1542 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1543 1544 /* Wa_14011060649:xehpsdv */ 1545 wa_14011060649(gt, wal); 1546 } 1547 1548 static void 1549 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1550 { 1551 struct intel_engine_cs *engine; 1552 int id; 1553 1554 xehp_init_mcr(gt, wal); 1555 1556 /* Wa_14011060649:dg2 */ 1557 wa_14011060649(gt, wal); 1558 1559 /* 1560 * Although there are per-engine instances of these registers, 1561 * they technically exist outside the engine itself and are not 1562 * impacted by engine resets. Furthermore, they're part of the 1563 * GuC blacklist so trying to treat them as engine workarounds 1564 * will result in GuC initialization failure and a wedged GPU. 1565 */ 1566 for_each_engine(engine, gt, id) { 1567 if (engine->class != VIDEO_DECODE_CLASS) 1568 continue; 1569 1570 /* Wa_16010515920:dg2_g10 */ 1571 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1572 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1573 ALNUNIT_CLKGATE_DIS); 1574 } 1575 1576 if (IS_DG2_G10(gt->i915)) { 1577 /* Wa_22010523718:dg2 */ 1578 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1579 CG3DDISCFEG_CLKGATE_DIS); 1580 1581 /* Wa_14011006942:dg2 */ 1582 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1583 DSS_ROUTER_CLKGATE_DIS); 1584 } 1585 1586 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1587 /* Wa_14010948348:dg2_g10 */ 1588 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1589 1590 /* Wa_14011037102:dg2_g10 */ 1591 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1592 1593 /* Wa_14011371254:dg2_g10 */ 1594 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1595 1596 /* Wa_14011431319:dg2_g10 */ 1597 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1598 GAMTLBVDBOX7_CLKGATE_DIS | 1599 GAMTLBVDBOX6_CLKGATE_DIS | 1600 GAMTLBVDBOX5_CLKGATE_DIS | 1601 GAMTLBVDBOX4_CLKGATE_DIS | 1602 GAMTLBVDBOX3_CLKGATE_DIS | 1603 GAMTLBVDBOX2_CLKGATE_DIS | 1604 GAMTLBVDBOX1_CLKGATE_DIS | 1605 GAMTLBVDBOX0_CLKGATE_DIS | 1606 GAMTLBKCR_CLKGATE_DIS | 1607 GAMTLBGUC_CLKGATE_DIS | 1608 GAMTLBBLT_CLKGATE_DIS); 1609 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1610 GAMTLBGFXA1_CLKGATE_DIS | 1611 GAMTLBCOMPA0_CLKGATE_DIS | 1612 GAMTLBCOMPA1_CLKGATE_DIS | 1613 GAMTLBCOMPB0_CLKGATE_DIS | 1614 GAMTLBCOMPB1_CLKGATE_DIS | 1615 GAMTLBCOMPC0_CLKGATE_DIS | 1616 GAMTLBCOMPC1_CLKGATE_DIS | 1617 GAMTLBCOMPD0_CLKGATE_DIS | 1618 GAMTLBCOMPD1_CLKGATE_DIS | 1619 GAMTLBMERT_CLKGATE_DIS | 1620 GAMTLBVEBOX3_CLKGATE_DIS | 1621 GAMTLBVEBOX2_CLKGATE_DIS | 1622 GAMTLBVEBOX1_CLKGATE_DIS | 1623 GAMTLBVEBOX0_CLKGATE_DIS); 1624 1625 /* Wa_14010569222:dg2_g10 */ 1626 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1627 GAMEDIA_CLKGATE_DIS); 1628 1629 /* Wa_14011028019:dg2_g10 */ 1630 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1631 } 1632 1633 /* Wa_14014830051:dg2 */ 1634 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1635 1636 /* 1637 * The following are not actually "workarounds" but rather 1638 * recommended tuning settings documented in the bspec's 1639 * performance guide section. 1640 */ 1641 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1642 1643 /* Wa_14015795083 */ 1644 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1645 } 1646 1647 static void 1648 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1649 { 1650 pvc_init_mcr(gt, wal); 1651 1652 /* Wa_14015795083 */ 1653 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1654 } 1655 1656 static void 1657 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1658 { 1659 /* Wa_14014830051 */ 1660 if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) || 1661 IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) 1662 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1663 1664 /* 1665 * Unlike older platforms, we no longer setup implicit steering here; 1666 * all MCR accesses are explicitly steered. 1667 */ 1668 debug_dump_steering(gt); 1669 } 1670 1671 static void 1672 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1673 { 1674 /* FIXME: Actual workarounds will be added in future patch(es) */ 1675 1676 debug_dump_steering(gt); 1677 } 1678 1679 static void 1680 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1681 { 1682 struct drm_i915_private *i915 = gt->i915; 1683 1684 if (gt->type == GT_MEDIA) { 1685 if (MEDIA_VER(i915) >= 13) 1686 xelpmp_gt_workarounds_init(gt, wal); 1687 else 1688 MISSING_CASE(MEDIA_VER(i915)); 1689 1690 return; 1691 } 1692 1693 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1694 xelpg_gt_workarounds_init(gt, wal); 1695 else if (IS_PONTEVECCHIO(i915)) 1696 pvc_gt_workarounds_init(gt, wal); 1697 else if (IS_DG2(i915)) 1698 dg2_gt_workarounds_init(gt, wal); 1699 else if (IS_XEHPSDV(i915)) 1700 xehpsdv_gt_workarounds_init(gt, wal); 1701 else if (IS_DG1(i915)) 1702 dg1_gt_workarounds_init(gt, wal); 1703 else if (IS_TIGERLAKE(i915)) 1704 tgl_gt_workarounds_init(gt, wal); 1705 else if (GRAPHICS_VER(i915) == 12) 1706 gen12_gt_workarounds_init(gt, wal); 1707 else if (GRAPHICS_VER(i915) == 11) 1708 icl_gt_workarounds_init(gt, wal); 1709 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1710 cfl_gt_workarounds_init(gt, wal); 1711 else if (IS_GEMINILAKE(i915)) 1712 glk_gt_workarounds_init(gt, wal); 1713 else if (IS_KABYLAKE(i915)) 1714 kbl_gt_workarounds_init(gt, wal); 1715 else if (IS_BROXTON(i915)) 1716 gen9_gt_workarounds_init(gt, wal); 1717 else if (IS_SKYLAKE(i915)) 1718 skl_gt_workarounds_init(gt, wal); 1719 else if (IS_HASWELL(i915)) 1720 hsw_gt_workarounds_init(gt, wal); 1721 else if (IS_VALLEYVIEW(i915)) 1722 vlv_gt_workarounds_init(gt, wal); 1723 else if (IS_IVYBRIDGE(i915)) 1724 ivb_gt_workarounds_init(gt, wal); 1725 else if (GRAPHICS_VER(i915) == 6) 1726 snb_gt_workarounds_init(gt, wal); 1727 else if (GRAPHICS_VER(i915) == 5) 1728 ilk_gt_workarounds_init(gt, wal); 1729 else if (IS_G4X(i915)) 1730 g4x_gt_workarounds_init(gt, wal); 1731 else if (GRAPHICS_VER(i915) == 4) 1732 gen4_gt_workarounds_init(gt, wal); 1733 else if (GRAPHICS_VER(i915) <= 8) 1734 ; 1735 else 1736 MISSING_CASE(GRAPHICS_VER(i915)); 1737 } 1738 1739 void intel_gt_init_workarounds(struct intel_gt *gt) 1740 { 1741 struct i915_wa_list *wal = >->wa_list; 1742 1743 wa_init_start(wal, gt, "GT", "global"); 1744 gt_init_workarounds(gt, wal); 1745 wa_init_finish(wal); 1746 } 1747 1748 static enum forcewake_domains 1749 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1750 { 1751 enum forcewake_domains fw = 0; 1752 struct i915_wa *wa; 1753 unsigned int i; 1754 1755 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1756 fw |= intel_uncore_forcewake_for_reg(uncore, 1757 wa->reg, 1758 FW_REG_READ | 1759 FW_REG_WRITE); 1760 1761 return fw; 1762 } 1763 1764 static bool 1765 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1766 const char *name, const char *from) 1767 { 1768 if ((cur ^ wa->set) & wa->read) { 1769 drm_err(>->i915->drm, 1770 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1771 name, from, i915_mmio_reg_offset(wa->reg), 1772 cur, cur & wa->read, wa->set & wa->read); 1773 1774 return false; 1775 } 1776 1777 return true; 1778 } 1779 1780 static void wa_list_apply(const struct i915_wa_list *wal) 1781 { 1782 struct intel_gt *gt = wal->gt; 1783 struct intel_uncore *uncore = gt->uncore; 1784 enum forcewake_domains fw; 1785 unsigned long flags; 1786 struct i915_wa *wa; 1787 unsigned int i; 1788 1789 if (!wal->count) 1790 return; 1791 1792 fw = wal_get_fw_for_rmw(uncore, wal); 1793 1794 intel_gt_mcr_lock(gt, &flags); 1795 spin_lock(&uncore->lock); 1796 intel_uncore_forcewake_get__locked(uncore, fw); 1797 1798 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1799 u32 val, old = 0; 1800 1801 /* open-coded rmw due to steering */ 1802 if (wa->clr) 1803 old = wa->is_mcr ? 1804 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1805 intel_uncore_read_fw(uncore, wa->reg); 1806 val = (old & ~wa->clr) | wa->set; 1807 if (val != old || !wa->clr) { 1808 if (wa->is_mcr) 1809 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1810 else 1811 intel_uncore_write_fw(uncore, wa->reg, val); 1812 } 1813 1814 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1815 u32 val = wa->is_mcr ? 1816 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1817 intel_uncore_read_fw(uncore, wa->reg); 1818 1819 wa_verify(gt, wa, val, wal->name, "application"); 1820 } 1821 } 1822 1823 intel_uncore_forcewake_put__locked(uncore, fw); 1824 spin_unlock(&uncore->lock); 1825 intel_gt_mcr_unlock(gt, flags); 1826 } 1827 1828 void intel_gt_apply_workarounds(struct intel_gt *gt) 1829 { 1830 wa_list_apply(>->wa_list); 1831 } 1832 1833 static bool wa_list_verify(struct intel_gt *gt, 1834 const struct i915_wa_list *wal, 1835 const char *from) 1836 { 1837 struct intel_uncore *uncore = gt->uncore; 1838 struct i915_wa *wa; 1839 enum forcewake_domains fw; 1840 unsigned long flags; 1841 unsigned int i; 1842 bool ok = true; 1843 1844 fw = wal_get_fw_for_rmw(uncore, wal); 1845 1846 intel_gt_mcr_lock(gt, &flags); 1847 spin_lock(&uncore->lock); 1848 intel_uncore_forcewake_get__locked(uncore, fw); 1849 1850 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1851 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1852 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1853 intel_uncore_read_fw(uncore, wa->reg), 1854 wal->name, from); 1855 1856 intel_uncore_forcewake_put__locked(uncore, fw); 1857 spin_unlock(&uncore->lock); 1858 intel_gt_mcr_unlock(gt, flags); 1859 1860 return ok; 1861 } 1862 1863 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1864 { 1865 return wa_list_verify(gt, >->wa_list, from); 1866 } 1867 1868 __maybe_unused 1869 static bool is_nonpriv_flags_valid(u32 flags) 1870 { 1871 /* Check only valid flag bits are set */ 1872 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1873 return false; 1874 1875 /* NB: Only 3 out of 4 enum values are valid for access field */ 1876 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1877 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1878 return false; 1879 1880 return true; 1881 } 1882 1883 static void 1884 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1885 { 1886 struct i915_wa wa = { 1887 .reg = reg 1888 }; 1889 1890 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1891 return; 1892 1893 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1894 return; 1895 1896 wa.reg.reg |= flags; 1897 _wa_add(wal, &wa); 1898 } 1899 1900 static void 1901 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1902 { 1903 struct i915_wa wa = { 1904 .mcr_reg = reg, 1905 .is_mcr = 1, 1906 }; 1907 1908 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1909 return; 1910 1911 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1912 return; 1913 1914 wa.mcr_reg.reg |= flags; 1915 _wa_add(wal, &wa); 1916 } 1917 1918 static void 1919 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1920 { 1921 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1922 } 1923 1924 static void 1925 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1926 { 1927 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1928 } 1929 1930 static void gen9_whitelist_build(struct i915_wa_list *w) 1931 { 1932 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1933 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1934 1935 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1936 whitelist_reg(w, GEN8_CS_CHICKEN1); 1937 1938 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1939 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1940 1941 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1942 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1943 } 1944 1945 static void skl_whitelist_build(struct intel_engine_cs *engine) 1946 { 1947 struct i915_wa_list *w = &engine->whitelist; 1948 1949 if (engine->class != RENDER_CLASS) 1950 return; 1951 1952 gen9_whitelist_build(w); 1953 1954 /* WaDisableLSQCROPERFforOCL:skl */ 1955 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1956 } 1957 1958 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1959 { 1960 if (engine->class != RENDER_CLASS) 1961 return; 1962 1963 gen9_whitelist_build(&engine->whitelist); 1964 } 1965 1966 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1967 { 1968 struct i915_wa_list *w = &engine->whitelist; 1969 1970 if (engine->class != RENDER_CLASS) 1971 return; 1972 1973 gen9_whitelist_build(w); 1974 1975 /* WaDisableLSQCROPERFforOCL:kbl */ 1976 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1977 } 1978 1979 static void glk_whitelist_build(struct intel_engine_cs *engine) 1980 { 1981 struct i915_wa_list *w = &engine->whitelist; 1982 1983 if (engine->class != RENDER_CLASS) 1984 return; 1985 1986 gen9_whitelist_build(w); 1987 1988 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1989 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1990 } 1991 1992 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1993 { 1994 struct i915_wa_list *w = &engine->whitelist; 1995 1996 if (engine->class != RENDER_CLASS) 1997 return; 1998 1999 gen9_whitelist_build(w); 2000 2001 /* 2002 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 2003 * 2004 * This covers 4 register which are next to one another : 2005 * - PS_INVOCATION_COUNT 2006 * - PS_INVOCATION_COUNT_UDW 2007 * - PS_DEPTH_COUNT 2008 * - PS_DEPTH_COUNT_UDW 2009 */ 2010 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2011 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2012 RING_FORCE_TO_NONPRIV_RANGE_4); 2013 } 2014 2015 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 2016 { 2017 struct i915_wa_list *w = &engine->whitelist; 2018 2019 if (engine->class != RENDER_CLASS) 2020 whitelist_reg_ext(w, 2021 RING_CTX_TIMESTAMP(engine->mmio_base), 2022 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2023 } 2024 2025 static void cml_whitelist_build(struct intel_engine_cs *engine) 2026 { 2027 allow_read_ctx_timestamp(engine); 2028 2029 cfl_whitelist_build(engine); 2030 } 2031 2032 static void icl_whitelist_build(struct intel_engine_cs *engine) 2033 { 2034 struct i915_wa_list *w = &engine->whitelist; 2035 2036 allow_read_ctx_timestamp(engine); 2037 2038 switch (engine->class) { 2039 case RENDER_CLASS: 2040 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 2041 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 2042 2043 /* WaAllowUMDToModifySamplerMode:icl */ 2044 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2045 2046 /* WaEnableStateCacheRedirectToCS:icl */ 2047 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2048 2049 /* 2050 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2051 * 2052 * This covers 4 register which are next to one another : 2053 * - PS_INVOCATION_COUNT 2054 * - PS_INVOCATION_COUNT_UDW 2055 * - PS_DEPTH_COUNT 2056 * - PS_DEPTH_COUNT_UDW 2057 */ 2058 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2059 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2060 RING_FORCE_TO_NONPRIV_RANGE_4); 2061 break; 2062 2063 case VIDEO_DECODE_CLASS: 2064 /* hucStatusRegOffset */ 2065 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2066 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2067 /* hucUKernelHdrInfoRegOffset */ 2068 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2069 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2070 /* hucStatus2RegOffset */ 2071 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2072 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2073 break; 2074 2075 default: 2076 break; 2077 } 2078 } 2079 2080 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2081 { 2082 struct i915_wa_list *w = &engine->whitelist; 2083 2084 allow_read_ctx_timestamp(engine); 2085 2086 switch (engine->class) { 2087 case RENDER_CLASS: 2088 /* 2089 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2090 * Wa_1408556865:tgl 2091 * 2092 * This covers 4 registers which are next to one another : 2093 * - PS_INVOCATION_COUNT 2094 * - PS_INVOCATION_COUNT_UDW 2095 * - PS_DEPTH_COUNT 2096 * - PS_DEPTH_COUNT_UDW 2097 */ 2098 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2099 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2100 RING_FORCE_TO_NONPRIV_RANGE_4); 2101 2102 /* 2103 * Wa_1808121037:tgl 2104 * Wa_14012131227:dg1 2105 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2106 */ 2107 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2108 2109 /* Wa_1806527549:tgl */ 2110 whitelist_reg(w, HIZ_CHICKEN); 2111 break; 2112 default: 2113 break; 2114 } 2115 } 2116 2117 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2118 { 2119 struct i915_wa_list *w = &engine->whitelist; 2120 2121 tgl_whitelist_build(engine); 2122 2123 /* GEN:BUG:1409280441:dg1 */ 2124 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2125 (engine->class == RENDER_CLASS || 2126 engine->class == COPY_ENGINE_CLASS)) 2127 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2128 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2129 } 2130 2131 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2132 { 2133 allow_read_ctx_timestamp(engine); 2134 } 2135 2136 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2137 { 2138 struct i915_wa_list *w = &engine->whitelist; 2139 2140 allow_read_ctx_timestamp(engine); 2141 2142 switch (engine->class) { 2143 case RENDER_CLASS: 2144 /* 2145 * Wa_1507100340:dg2_g10 2146 * 2147 * This covers 4 registers which are next to one another : 2148 * - PS_INVOCATION_COUNT 2149 * - PS_INVOCATION_COUNT_UDW 2150 * - PS_DEPTH_COUNT 2151 * - PS_DEPTH_COUNT_UDW 2152 */ 2153 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2154 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2155 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2156 RING_FORCE_TO_NONPRIV_RANGE_4); 2157 2158 break; 2159 case COMPUTE_CLASS: 2160 /* Wa_16011157294:dg2_g10 */ 2161 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2162 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2163 break; 2164 default: 2165 break; 2166 } 2167 } 2168 2169 static void blacklist_trtt(struct intel_engine_cs *engine) 2170 { 2171 struct i915_wa_list *w = &engine->whitelist; 2172 2173 /* 2174 * Prevent read/write access to [0x4400, 0x4600) which covers 2175 * the TRTT range across all engines. Note that normally userspace 2176 * cannot access the other engines' trtt control, but for simplicity 2177 * we cover the entire range on each engine. 2178 */ 2179 whitelist_reg_ext(w, _MMIO(0x4400), 2180 RING_FORCE_TO_NONPRIV_DENY | 2181 RING_FORCE_TO_NONPRIV_RANGE_64); 2182 whitelist_reg_ext(w, _MMIO(0x4500), 2183 RING_FORCE_TO_NONPRIV_DENY | 2184 RING_FORCE_TO_NONPRIV_RANGE_64); 2185 } 2186 2187 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2188 { 2189 allow_read_ctx_timestamp(engine); 2190 2191 /* Wa_16014440446:pvc */ 2192 blacklist_trtt(engine); 2193 } 2194 2195 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2196 { 2197 struct drm_i915_private *i915 = engine->i915; 2198 struct i915_wa_list *w = &engine->whitelist; 2199 2200 wa_init_start(w, engine->gt, "whitelist", engine->name); 2201 2202 if (IS_METEORLAKE(i915)) 2203 ; /* noop; none at this time */ 2204 else if (IS_PONTEVECCHIO(i915)) 2205 pvc_whitelist_build(engine); 2206 else if (IS_DG2(i915)) 2207 dg2_whitelist_build(engine); 2208 else if (IS_XEHPSDV(i915)) 2209 xehpsdv_whitelist_build(engine); 2210 else if (IS_DG1(i915)) 2211 dg1_whitelist_build(engine); 2212 else if (GRAPHICS_VER(i915) == 12) 2213 tgl_whitelist_build(engine); 2214 else if (GRAPHICS_VER(i915) == 11) 2215 icl_whitelist_build(engine); 2216 else if (IS_COMETLAKE(i915)) 2217 cml_whitelist_build(engine); 2218 else if (IS_COFFEELAKE(i915)) 2219 cfl_whitelist_build(engine); 2220 else if (IS_GEMINILAKE(i915)) 2221 glk_whitelist_build(engine); 2222 else if (IS_KABYLAKE(i915)) 2223 kbl_whitelist_build(engine); 2224 else if (IS_BROXTON(i915)) 2225 bxt_whitelist_build(engine); 2226 else if (IS_SKYLAKE(i915)) 2227 skl_whitelist_build(engine); 2228 else if (GRAPHICS_VER(i915) <= 8) 2229 ; 2230 else 2231 MISSING_CASE(GRAPHICS_VER(i915)); 2232 2233 wa_init_finish(w); 2234 } 2235 2236 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2237 { 2238 const struct i915_wa_list *wal = &engine->whitelist; 2239 struct intel_uncore *uncore = engine->uncore; 2240 const u32 base = engine->mmio_base; 2241 struct i915_wa *wa; 2242 unsigned int i; 2243 2244 if (!wal->count) 2245 return; 2246 2247 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2248 intel_uncore_write(uncore, 2249 RING_FORCE_TO_NONPRIV(base, i), 2250 i915_mmio_reg_offset(wa->reg)); 2251 2252 /* And clear the rest just in case of garbage */ 2253 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2254 intel_uncore_write(uncore, 2255 RING_FORCE_TO_NONPRIV(base, i), 2256 i915_mmio_reg_offset(RING_NOPID(base))); 2257 } 2258 2259 /* 2260 * engine_fake_wa_init(), a place holder to program the registers 2261 * which are not part of an official workaround defined by the 2262 * hardware team. 2263 * Adding programming of those register inside workaround will 2264 * allow utilizing wa framework to proper application and verification. 2265 */ 2266 static void 2267 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2268 { 2269 u8 mocs_w, mocs_r; 2270 2271 /* 2272 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2273 * by the command streamer when executing commands that don't have 2274 * a way to explicitly specify a MOCS setting. The default should 2275 * usually reference whichever MOCS entry corresponds to uncached 2276 * behavior, although use of a WB cached entry is recommended by the 2277 * spec in certain circumstances on specific platforms. 2278 */ 2279 if (GRAPHICS_VER(engine->i915) >= 12) { 2280 mocs_r = engine->gt->mocs.uc_index; 2281 mocs_w = engine->gt->mocs.uc_index; 2282 2283 if (HAS_L3_CCS_READ(engine->i915) && 2284 engine->class == COMPUTE_CLASS) { 2285 mocs_r = engine->gt->mocs.wb_index; 2286 2287 /* 2288 * Even on the few platforms where MOCS 0 is a 2289 * legitimate table entry, it's never the correct 2290 * setting to use here; we can assume the MOCS init 2291 * just forgot to initialize wb_index. 2292 */ 2293 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2294 } 2295 2296 wa_masked_field_set(wal, 2297 RING_CMD_CCTL(engine->mmio_base), 2298 CMD_CCTL_MOCS_MASK, 2299 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2300 } 2301 } 2302 2303 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2304 { 2305 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2306 GEN_DSS_PER_GSLICE; 2307 } 2308 2309 static void 2310 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2311 { 2312 struct drm_i915_private *i915 = engine->i915; 2313 2314 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2315 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 2316 /* Wa_22014600077 */ 2317 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2318 ENABLE_EU_COUNT_FOR_TDL_FLUSH); 2319 } 2320 2321 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2322 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 2323 IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2324 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2325 /* Wa_1509727124 */ 2326 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2327 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2328 2329 /* Wa_22013037850 */ 2330 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2331 DISABLE_128B_EVICTION_COMMAND_UDW); 2332 } 2333 2334 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2335 IS_DG2_G11(i915) || IS_DG2_G12(i915) || 2336 IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) { 2337 /* Wa_22012856258 */ 2338 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2339 GEN12_DISABLE_READ_SUPPRESSION); 2340 } 2341 2342 if (IS_DG2(i915)) { 2343 /* Wa_1509235366:dg2 */ 2344 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2345 GLOBAL_INVALIDATION_MODE); 2346 } 2347 2348 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2349 /* Wa_14013392000:dg2_g11 */ 2350 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2351 } 2352 2353 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2354 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2355 /* Wa_14012419201:dg2 */ 2356 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2357 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2358 } 2359 2360 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2361 IS_DG2_G11(i915)) { 2362 /* 2363 * Wa_22012826095:dg2 2364 * Wa_22013059131:dg2 2365 */ 2366 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2367 MAXREQS_PER_BANK, 2368 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2369 2370 /* Wa_22013059131:dg2 */ 2371 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2372 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2373 } 2374 2375 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2376 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2377 needs_wa_1308578152(engine)) { 2378 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2379 GEN12_REPLAY_MODE_GRANULARITY); 2380 } 2381 2382 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2383 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2384 /* 2385 * Wa_22010960976:dg2 2386 * Wa_14013347512:dg2 2387 */ 2388 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2389 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2390 } 2391 2392 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2393 /* 2394 * Wa_1608949956:dg2_g10 2395 * Wa_14010198302:dg2_g10 2396 */ 2397 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2398 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2399 2400 /* 2401 * Wa_14010918519:dg2_g10 2402 * 2403 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2404 * so ignoring verification. 2405 */ 2406 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2407 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2408 0, false); 2409 } 2410 2411 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2412 /* Wa_22010430635:dg2 */ 2413 wa_mcr_masked_en(wal, 2414 GEN9_ROW_CHICKEN4, 2415 GEN12_DISABLE_GRF_CLEAR); 2416 2417 /* Wa_14010648519:dg2 */ 2418 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2419 } 2420 2421 /* Wa_14013202645:dg2 */ 2422 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2423 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2424 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2425 2426 /* Wa_22012532006:dg2 */ 2427 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2428 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2429 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2430 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2431 2432 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2433 /* Wa_14010680813:dg2_g10 */ 2434 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2435 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2436 } 2437 2438 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2439 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2440 /* Wa_14012362059:dg2 */ 2441 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2442 } 2443 2444 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2445 IS_DG2_G10(i915)) { 2446 /* Wa_22014600077:dg2 */ 2447 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2448 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2449 0 /* Wa_14012342262 write-only reg, so skip verification */, 2450 true); 2451 } 2452 2453 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2454 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2455 /* 2456 * Wa_1607138336:tgl[a0],dg1[a0] 2457 * Wa_1607063988:tgl[a0],dg1[a0] 2458 */ 2459 wa_write_or(wal, 2460 GEN9_CTX_PREEMPT_REG, 2461 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2462 } 2463 2464 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2465 /* 2466 * Wa_1606679103:tgl 2467 * (see also Wa_1606682166:icl) 2468 */ 2469 wa_write_or(wal, 2470 GEN7_SARCHKMD, 2471 GEN7_DISABLE_SAMPLER_PREFETCH); 2472 } 2473 2474 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2475 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2476 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2477 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2478 2479 /* 2480 * Wa_1407928979:tgl A* 2481 * Wa_18011464164:tgl[B0+],dg1[B0+] 2482 * Wa_22010931296:tgl[B0+],dg1[B0+] 2483 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2484 */ 2485 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2486 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2487 } 2488 2489 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2490 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2491 /* 2492 * Wa_1606700617:tgl,dg1,adl-p 2493 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2494 * Wa_14010826681:tgl,dg1,rkl,adl-p 2495 * Wa_18019627453:dg2 2496 */ 2497 wa_masked_en(wal, 2498 GEN9_CS_DEBUG_MODE1, 2499 FF_DOP_CLOCK_GATE_DISABLE); 2500 } 2501 2502 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2503 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2504 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2505 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2506 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2507 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2508 2509 /* 2510 * Wa_1409085225:tgl 2511 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2512 */ 2513 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2514 } 2515 2516 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2517 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2518 /* 2519 * Wa_1607030317:tgl 2520 * Wa_1607186500:tgl 2521 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2522 * 2523 * On TGL and RKL there are multiple entries for this WA in the 2524 * BSpec; some indicate this is an A0-only WA, others indicate 2525 * it applies to all steppings so we trust the "all steppings." 2526 * For DG1 this only applies to A0. 2527 */ 2528 wa_masked_en(wal, 2529 RING_PSMI_CTL(RENDER_RING_BASE), 2530 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2531 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2532 } 2533 2534 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2535 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2536 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2537 wa_mcr_masked_en(wal, 2538 GEN10_SAMPLER_MODE, 2539 ENABLE_SMALLPL); 2540 } 2541 2542 if (GRAPHICS_VER(i915) == 11) { 2543 /* This is not an Wa. Enable for better image quality */ 2544 wa_masked_en(wal, 2545 _3D_CHICKEN3, 2546 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2547 2548 /* 2549 * Wa_1405543622:icl 2550 * Formerly known as WaGAPZPriorityScheme 2551 */ 2552 wa_write_or(wal, 2553 GEN8_GARBCNTL, 2554 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2555 2556 /* 2557 * Wa_1604223664:icl 2558 * Formerly known as WaL3BankAddressHashing 2559 */ 2560 wa_write_clr_set(wal, 2561 GEN8_GARBCNTL, 2562 GEN11_HASH_CTRL_EXCL_MASK, 2563 GEN11_HASH_CTRL_EXCL_BIT0); 2564 wa_write_clr_set(wal, 2565 GEN11_GLBLINVL, 2566 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2567 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2568 2569 /* 2570 * Wa_1405733216:icl 2571 * Formerly known as WaDisableCleanEvicts 2572 */ 2573 wa_mcr_write_or(wal, 2574 GEN8_L3SQCREG4, 2575 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2576 2577 /* Wa_1606682166:icl */ 2578 wa_write_or(wal, 2579 GEN7_SARCHKMD, 2580 GEN7_DISABLE_SAMPLER_PREFETCH); 2581 2582 /* Wa_1409178092:icl */ 2583 wa_mcr_write_clr_set(wal, 2584 GEN11_SCRATCH2, 2585 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2586 0); 2587 2588 /* WaEnable32PlaneMode:icl */ 2589 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2590 GEN11_ENABLE_32_PLANE_MODE); 2591 2592 /* 2593 * Wa_1408615072:icl,ehl (vsunit) 2594 * Wa_1407596294:icl,ehl (hsunit) 2595 */ 2596 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2597 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2598 2599 /* 2600 * Wa_1408767742:icl[a2..forever],ehl[all] 2601 * Wa_1605460711:icl[a0..c0] 2602 */ 2603 wa_write_or(wal, 2604 GEN7_FF_THREAD_MODE, 2605 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2606 2607 /* Wa_22010271021 */ 2608 wa_masked_en(wal, 2609 GEN9_CS_DEBUG_MODE1, 2610 FF_DOP_CLOCK_GATE_DISABLE); 2611 } 2612 2613 /* 2614 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2615 * beyond) allow the kernel-mode driver to choose between two different 2616 * options for controlling preemption granularity and behavior. 2617 * 2618 * Option 1 (hardware default): 2619 * Preemption settings are controlled in a global manner via 2620 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2621 * and settings chosen by the kernel-mode driver will apply to all 2622 * userspace clients. 2623 * 2624 * Option 2: 2625 * Preemption settings are controlled on a per-context basis via 2626 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2627 * context switch and is writable by userspace (e.g., via 2628 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2629 * which allows different userspace drivers/clients to select 2630 * different settings, or to change those settings on the fly in 2631 * response to runtime needs. This option was known by name 2632 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2633 * that name is somewhat misleading as other non-granularity 2634 * preemption settings are also impacted by this decision. 2635 * 2636 * On Linux, our policy has always been to let userspace drivers 2637 * control preemption granularity/settings (Option 2). This was 2638 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2639 * userspace developed before object-level preemption was enabled would 2640 * not behave well if i915 were to go with Option 1 and enable that 2641 * preemption in a global manner). On gen9 each context would have 2642 * object-level preemption disabled by default (see 2643 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2644 * userspace drivers could opt-in to object-level preemption as they 2645 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2646 * even though it is no longer necessary for ABI compatibility when 2647 * enabling a new platform, it does ensure that userspace will be able 2648 * to implement any workarounds that show up requiring temporary 2649 * adjustments to preemption behavior at runtime. 2650 * 2651 * Notes/Workarounds: 2652 * - Wa_14015141709: On DG2 and early steppings of MTL, 2653 * CS_CHICKEN1[0] does not disable object-level preemption as 2654 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2655 * using Option 1). Effectively this means userspace is unable 2656 * to disable object-level preemption on these platforms/steppings 2657 * despite the setting here. 2658 * 2659 * - Wa_16013994831: May require that userspace program 2660 * CS_CHICKEN1[10] when certain runtime conditions are true. 2661 * Userspace requires Option 2 to be in effect for their update of 2662 * CS_CHICKEN1[10] to be effective. 2663 * 2664 * Other workarounds may appear in the future that will also require 2665 * Option 2 behavior to allow proper userspace implementation. 2666 */ 2667 if (GRAPHICS_VER(i915) >= 9) 2668 wa_masked_en(wal, 2669 GEN7_FF_SLICE_CS_CHICKEN1, 2670 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2671 2672 if (IS_SKYLAKE(i915) || 2673 IS_KABYLAKE(i915) || 2674 IS_COFFEELAKE(i915) || 2675 IS_COMETLAKE(i915)) { 2676 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2677 wa_write_or(wal, 2678 GEN8_GARBCNTL, 2679 GEN9_GAPS_TSV_CREDIT_DISABLE); 2680 } 2681 2682 if (IS_BROXTON(i915)) { 2683 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2684 wa_masked_en(wal, 2685 FF_SLICE_CS_CHICKEN2, 2686 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2687 } 2688 2689 if (GRAPHICS_VER(i915) == 9) { 2690 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2691 wa_masked_en(wal, 2692 GEN9_CSFE_CHICKEN1_RCS, 2693 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2694 2695 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2696 wa_mcr_write_or(wal, 2697 BDW_SCRATCH1, 2698 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2699 2700 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2701 if (IS_GEN9_LP(i915)) 2702 wa_mcr_write_clr_set(wal, 2703 GEN8_L3SQCREG1, 2704 L3_PRIO_CREDITS_MASK, 2705 L3_GENERAL_PRIO_CREDITS(62) | 2706 L3_HIGH_PRIO_CREDITS(2)); 2707 2708 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2709 wa_mcr_write_or(wal, 2710 GEN8_L3SQCREG4, 2711 GEN8_LQSC_FLUSH_COHERENT_LINES); 2712 2713 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2714 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2715 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2716 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2717 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2718 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2719 EVICTION_PERF_FIX_ENABLE, 0); 2720 } 2721 2722 if (IS_HASWELL(i915)) { 2723 /* WaSampleCChickenBitEnable:hsw */ 2724 wa_masked_en(wal, 2725 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2726 2727 wa_masked_dis(wal, 2728 CACHE_MODE_0_GEN7, 2729 /* enable HiZ Raw Stall Optimization */ 2730 HIZ_RAW_STALL_OPT_DISABLE); 2731 } 2732 2733 if (IS_VALLEYVIEW(i915)) { 2734 /* WaDisableEarlyCull:vlv */ 2735 wa_masked_en(wal, 2736 _3D_CHICKEN3, 2737 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2738 2739 /* 2740 * WaVSThreadDispatchOverride:ivb,vlv 2741 * 2742 * This actually overrides the dispatch 2743 * mode for all thread types. 2744 */ 2745 wa_write_clr_set(wal, 2746 GEN7_FF_THREAD_MODE, 2747 GEN7_FF_SCHED_MASK, 2748 GEN7_FF_TS_SCHED_HW | 2749 GEN7_FF_VS_SCHED_HW | 2750 GEN7_FF_DS_SCHED_HW); 2751 2752 /* WaPsdDispatchEnable:vlv */ 2753 /* WaDisablePSDDualDispatchEnable:vlv */ 2754 wa_masked_en(wal, 2755 GEN7_HALF_SLICE_CHICKEN1, 2756 GEN7_MAX_PS_THREAD_DEP | 2757 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2758 } 2759 2760 if (IS_IVYBRIDGE(i915)) { 2761 /* WaDisableEarlyCull:ivb */ 2762 wa_masked_en(wal, 2763 _3D_CHICKEN3, 2764 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2765 2766 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2767 /* enable HiZ Raw Stall Optimization */ 2768 wa_masked_dis(wal, 2769 CACHE_MODE_0_GEN7, 2770 HIZ_RAW_STALL_OPT_DISABLE); 2771 } 2772 2773 /* 2774 * WaVSThreadDispatchOverride:ivb,vlv 2775 * 2776 * This actually overrides the dispatch 2777 * mode for all thread types. 2778 */ 2779 wa_write_clr_set(wal, 2780 GEN7_FF_THREAD_MODE, 2781 GEN7_FF_SCHED_MASK, 2782 GEN7_FF_TS_SCHED_HW | 2783 GEN7_FF_VS_SCHED_HW | 2784 GEN7_FF_DS_SCHED_HW); 2785 2786 /* WaDisablePSDDualDispatchEnable:ivb */ 2787 if (IS_IVB_GT1(i915)) 2788 wa_masked_en(wal, 2789 GEN7_HALF_SLICE_CHICKEN1, 2790 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2791 } 2792 2793 if (GRAPHICS_VER(i915) == 7) { 2794 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2795 wa_masked_en(wal, 2796 RING_MODE_GEN7(RENDER_RING_BASE), 2797 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2798 2799 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2800 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2801 2802 /* 2803 * BSpec says this must be set, even though 2804 * WaDisable4x2SubspanOptimization:ivb,hsw 2805 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2806 */ 2807 wa_masked_en(wal, 2808 CACHE_MODE_1, 2809 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2810 2811 /* 2812 * BSpec recommends 8x4 when MSAA is used, 2813 * however in practice 16x4 seems fastest. 2814 * 2815 * Note that PS/WM thread counts depend on the WIZ hashing 2816 * disable bit, which we don't touch here, but it's good 2817 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2818 */ 2819 wa_masked_field_set(wal, 2820 GEN7_GT_MODE, 2821 GEN6_WIZ_HASHING_MASK, 2822 GEN6_WIZ_HASHING_16x4); 2823 } 2824 2825 if (IS_GRAPHICS_VER(i915, 6, 7)) 2826 /* 2827 * We need to disable the AsyncFlip performance optimisations in 2828 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2829 * already be programmed to '1' on all products. 2830 * 2831 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2832 */ 2833 wa_masked_en(wal, 2834 RING_MI_MODE(RENDER_RING_BASE), 2835 ASYNC_FLIP_PERF_DISABLE); 2836 2837 if (GRAPHICS_VER(i915) == 6) { 2838 /* 2839 * Required for the hardware to program scanline values for 2840 * waiting 2841 * WaEnableFlushTlbInvalidationMode:snb 2842 */ 2843 wa_masked_en(wal, 2844 GFX_MODE, 2845 GFX_TLB_INVALIDATE_EXPLICIT); 2846 2847 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2848 wa_masked_en(wal, 2849 _3D_CHICKEN, 2850 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2851 2852 wa_masked_en(wal, 2853 _3D_CHICKEN3, 2854 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2855 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2856 /* 2857 * Bspec says: 2858 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2859 * to normal and 3DSTATE_SF number of SF output attributes 2860 * is more than 16." 2861 */ 2862 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2863 2864 /* 2865 * BSpec recommends 8x4 when MSAA is used, 2866 * however in practice 16x4 seems fastest. 2867 * 2868 * Note that PS/WM thread counts depend on the WIZ hashing 2869 * disable bit, which we don't touch here, but it's good 2870 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2871 */ 2872 wa_masked_field_set(wal, 2873 GEN6_GT_MODE, 2874 GEN6_WIZ_HASHING_MASK, 2875 GEN6_WIZ_HASHING_16x4); 2876 2877 /* WaDisable_RenderCache_OperationalFlush:snb */ 2878 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2879 2880 /* 2881 * From the Sandybridge PRM, volume 1 part 3, page 24: 2882 * "If this bit is set, STCunit will have LRA as replacement 2883 * policy. [...] This bit must be reset. LRA replacement 2884 * policy is not supported." 2885 */ 2886 wa_masked_dis(wal, 2887 CACHE_MODE_0, 2888 CM0_STC_EVICT_DISABLE_LRA_SNB); 2889 } 2890 2891 if (IS_GRAPHICS_VER(i915, 4, 6)) 2892 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2893 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2894 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2895 /* XXX bit doesn't stick on Broadwater */ 2896 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2897 2898 if (GRAPHICS_VER(i915) == 4) 2899 /* 2900 * Disable CONSTANT_BUFFER before it is loaded from the context 2901 * image. For as it is loaded, it is executed and the stored 2902 * address may no longer be valid, leading to a GPU hang. 2903 * 2904 * This imposes the requirement that userspace reload their 2905 * CONSTANT_BUFFER on every batch, fortunately a requirement 2906 * they are already accustomed to from before contexts were 2907 * enabled. 2908 */ 2909 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2910 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2911 0 /* XXX bit doesn't stick on Broadwater */, 2912 true); 2913 } 2914 2915 static void 2916 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2917 { 2918 struct drm_i915_private *i915 = engine->i915; 2919 2920 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2921 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2922 wa_write(wal, 2923 RING_SEMA_WAIT_POLL(engine->mmio_base), 2924 1); 2925 } 2926 } 2927 2928 static void 2929 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2930 { 2931 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2932 /* Wa_14014999345:pvc */ 2933 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2934 } 2935 } 2936 2937 /* 2938 * The bspec performance guide has recommended MMIO tuning settings. These 2939 * aren't truly "workarounds" but we want to program them with the same 2940 * workaround infrastructure to ensure that they're automatically added to 2941 * the GuC save/restore lists, re-applied at the right times, and checked for 2942 * any conflicting programming requested by real workarounds. 2943 * 2944 * Programming settings should be added here only if their registers are not 2945 * part of an engine's register state context. If a register is part of a 2946 * context, then any tuning settings should be programmed in an appropriate 2947 * function invoked by __intel_engine_init_ctx_wa(). 2948 */ 2949 static void 2950 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2951 struct i915_wa_list *wal) 2952 { 2953 if (IS_PONTEVECCHIO(i915)) { 2954 wa_write(wal, XEHPC_L3SCRUB, 2955 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2956 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); 2957 } 2958 2959 if (IS_DG2(i915)) { 2960 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2961 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2962 } 2963 2964 /* 2965 * This tuning setting proves beneficial only on ATS-M designs; the 2966 * default "age based" setting is optimal on regular DG2 and other 2967 * platforms. 2968 */ 2969 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2970 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2971 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2972 2973 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 2974 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 2975 } 2976 2977 /* 2978 * The workarounds in this function apply to shared registers in 2979 * the general render reset domain that aren't tied to a 2980 * specific engine. Since all render+compute engines get reset 2981 * together, and the contents of these registers are lost during 2982 * the shared render domain reset, we'll define such workarounds 2983 * here and then add them to just a single RCS or CCS engine's 2984 * workaround list (whichever engine has the XXXX flag). 2985 */ 2986 static void 2987 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2988 { 2989 struct drm_i915_private *i915 = engine->i915; 2990 2991 add_render_compute_tuning_settings(i915, wal); 2992 2993 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2994 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 2995 IS_PONTEVECCHIO(i915) || 2996 IS_DG2(i915)) { 2997 /* Wa_18018781329 */ 2998 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2999 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 3000 wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 3001 wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 3002 3003 /* Wa_22014226127 */ 3004 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 3005 } 3006 3007 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3008 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3009 IS_DG2(i915)) { 3010 /* Wa_18017747507 */ 3011 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3012 } 3013 3014 if (IS_PONTEVECCHIO(i915)) { 3015 /* Wa_16016694945 */ 3016 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 3017 } 3018 3019 if (IS_XEHPSDV(i915)) { 3020 /* Wa_1409954639 */ 3021 wa_mcr_masked_en(wal, 3022 GEN8_ROW_CHICKEN, 3023 SYSTOLIC_DOP_CLOCK_GATING_DIS); 3024 3025 /* Wa_1607196519 */ 3026 wa_mcr_masked_en(wal, 3027 GEN9_ROW_CHICKEN4, 3028 GEN12_DISABLE_GRF_CLEAR); 3029 3030 /* Wa_14010670810:xehpsdv */ 3031 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 3032 3033 /* Wa_14010449647:xehpsdv */ 3034 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 3035 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 3036 3037 /* Wa_18011725039:xehpsdv */ 3038 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 3039 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 3040 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 3041 } 3042 3043 /* Wa_14012362059:xehpsdv */ 3044 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 3045 3046 /* Wa_14014368820:xehpsdv */ 3047 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 3048 GLOBAL_INVALIDATION_MODE); 3049 } 3050 3051 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 3052 /* Wa_14015227452:dg2,pvc */ 3053 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 3054 3055 /* Wa_16015675438:dg2,pvc */ 3056 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 3057 } 3058 3059 if (IS_DG2(i915)) { 3060 /* 3061 * Wa_16011620976:dg2_g11 3062 * Wa_22015475538:dg2 3063 */ 3064 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3065 } 3066 3067 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915)) 3068 /* 3069 * Wa_22012654132 3070 * 3071 * Note that register 0xE420 is write-only and cannot be read 3072 * back for verification on DG2 (due to Wa_14012342262), so 3073 * we need to explicitly skip the readback. 3074 */ 3075 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 3076 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 3077 0 /* write-only, so skip validation */, 3078 true); 3079 } 3080 3081 static void 3082 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3083 { 3084 if (GRAPHICS_VER(engine->i915) < 4) 3085 return; 3086 3087 engine_fake_wa_init(engine, wal); 3088 3089 /* 3090 * These are common workarounds that just need to applied 3091 * to a single RCS/CCS engine's workaround list since 3092 * they're reset as part of the general render domain reset. 3093 */ 3094 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3095 general_render_compute_wa_init(engine, wal); 3096 3097 if (engine->class == COMPUTE_CLASS) 3098 ccs_engine_wa_init(engine, wal); 3099 else if (engine->class == RENDER_CLASS) 3100 rcs_engine_wa_init(engine, wal); 3101 else 3102 xcs_engine_wa_init(engine, wal); 3103 } 3104 3105 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3106 { 3107 struct i915_wa_list *wal = &engine->wa_list; 3108 3109 wa_init_start(wal, engine->gt, "engine", engine->name); 3110 engine_init_workarounds(engine, wal); 3111 wa_init_finish(wal); 3112 } 3113 3114 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3115 { 3116 wa_list_apply(&engine->wa_list); 3117 } 3118 3119 static const struct i915_range mcr_ranges_gen8[] = { 3120 { .start = 0x5500, .end = 0x55ff }, 3121 { .start = 0x7000, .end = 0x7fff }, 3122 { .start = 0x9400, .end = 0x97ff }, 3123 { .start = 0xb000, .end = 0xb3ff }, 3124 { .start = 0xe000, .end = 0xe7ff }, 3125 {}, 3126 }; 3127 3128 static const struct i915_range mcr_ranges_gen12[] = { 3129 { .start = 0x8150, .end = 0x815f }, 3130 { .start = 0x9520, .end = 0x955f }, 3131 { .start = 0xb100, .end = 0xb3ff }, 3132 { .start = 0xde80, .end = 0xe8ff }, 3133 { .start = 0x24a00, .end = 0x24a7f }, 3134 {}, 3135 }; 3136 3137 static const struct i915_range mcr_ranges_xehp[] = { 3138 { .start = 0x4000, .end = 0x4aff }, 3139 { .start = 0x5200, .end = 0x52ff }, 3140 { .start = 0x5400, .end = 0x7fff }, 3141 { .start = 0x8140, .end = 0x815f }, 3142 { .start = 0x8c80, .end = 0x8dff }, 3143 { .start = 0x94d0, .end = 0x955f }, 3144 { .start = 0x9680, .end = 0x96ff }, 3145 { .start = 0xb000, .end = 0xb3ff }, 3146 { .start = 0xc800, .end = 0xcfff }, 3147 { .start = 0xd800, .end = 0xd8ff }, 3148 { .start = 0xdc00, .end = 0xffff }, 3149 { .start = 0x17000, .end = 0x17fff }, 3150 { .start = 0x24a00, .end = 0x24a7f }, 3151 {}, 3152 }; 3153 3154 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3155 { 3156 const struct i915_range *mcr_ranges; 3157 int i; 3158 3159 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3160 mcr_ranges = mcr_ranges_xehp; 3161 else if (GRAPHICS_VER(i915) >= 12) 3162 mcr_ranges = mcr_ranges_gen12; 3163 else if (GRAPHICS_VER(i915) >= 8) 3164 mcr_ranges = mcr_ranges_gen8; 3165 else 3166 return false; 3167 3168 /* 3169 * Registers in these ranges are affected by the MCR selector 3170 * which only controls CPU initiated MMIO. Routing does not 3171 * work for CS access so we cannot verify them on this path. 3172 */ 3173 for (i = 0; mcr_ranges[i].start; i++) 3174 if (offset >= mcr_ranges[i].start && 3175 offset <= mcr_ranges[i].end) 3176 return true; 3177 3178 return false; 3179 } 3180 3181 static int 3182 wa_list_srm(struct i915_request *rq, 3183 const struct i915_wa_list *wal, 3184 struct i915_vma *vma) 3185 { 3186 struct drm_i915_private *i915 = rq->engine->i915; 3187 unsigned int i, count = 0; 3188 const struct i915_wa *wa; 3189 u32 srm, *cs; 3190 3191 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3192 if (GRAPHICS_VER(i915) >= 8) 3193 srm++; 3194 3195 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3196 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3197 count++; 3198 } 3199 3200 cs = intel_ring_begin(rq, 4 * count); 3201 if (IS_ERR(cs)) 3202 return PTR_ERR(cs); 3203 3204 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3205 u32 offset = i915_mmio_reg_offset(wa->reg); 3206 3207 if (mcr_range(i915, offset)) 3208 continue; 3209 3210 *cs++ = srm; 3211 *cs++ = offset; 3212 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3213 *cs++ = 0; 3214 } 3215 intel_ring_advance(rq, cs); 3216 3217 return 0; 3218 } 3219 3220 static int engine_wa_list_verify(struct intel_context *ce, 3221 const struct i915_wa_list * const wal, 3222 const char *from) 3223 { 3224 const struct i915_wa *wa; 3225 struct i915_request *rq; 3226 struct i915_vma *vma; 3227 struct i915_gem_ww_ctx ww; 3228 unsigned int i; 3229 u32 *results; 3230 int err; 3231 3232 if (!wal->count) 3233 return 0; 3234 3235 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3236 wal->count * sizeof(u32)); 3237 if (IS_ERR(vma)) 3238 return PTR_ERR(vma); 3239 3240 intel_engine_pm_get(ce->engine); 3241 i915_gem_ww_ctx_init(&ww, false); 3242 retry: 3243 err = i915_gem_object_lock(vma->obj, &ww); 3244 if (err == 0) 3245 err = intel_context_pin_ww(ce, &ww); 3246 if (err) 3247 goto err_pm; 3248 3249 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3250 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3251 if (err) 3252 goto err_unpin; 3253 3254 rq = i915_request_create(ce); 3255 if (IS_ERR(rq)) { 3256 err = PTR_ERR(rq); 3257 goto err_vma; 3258 } 3259 3260 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3261 if (err == 0) 3262 err = wa_list_srm(rq, wal, vma); 3263 3264 i915_request_get(rq); 3265 if (err) 3266 i915_request_set_error_once(rq, err); 3267 i915_request_add(rq); 3268 3269 if (err) 3270 goto err_rq; 3271 3272 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3273 err = -ETIME; 3274 goto err_rq; 3275 } 3276 3277 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3278 if (IS_ERR(results)) { 3279 err = PTR_ERR(results); 3280 goto err_rq; 3281 } 3282 3283 err = 0; 3284 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3285 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3286 continue; 3287 3288 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3289 err = -ENXIO; 3290 } 3291 3292 i915_gem_object_unpin_map(vma->obj); 3293 3294 err_rq: 3295 i915_request_put(rq); 3296 err_vma: 3297 i915_vma_unpin(vma); 3298 err_unpin: 3299 intel_context_unpin(ce); 3300 err_pm: 3301 if (err == -EDEADLK) { 3302 err = i915_gem_ww_ctx_backoff(&ww); 3303 if (!err) 3304 goto retry; 3305 } 3306 i915_gem_ww_ctx_fini(&ww); 3307 intel_engine_pm_put(ce->engine); 3308 i915_vma_put(vma); 3309 return err; 3310 } 3311 3312 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3313 const char *from) 3314 { 3315 return engine_wa_list_verify(engine->kernel_context, 3316 &engine->wa_list, 3317 from); 3318 } 3319 3320 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3321 #include "selftest_workarounds.c" 3322 #endif 3323