1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 /* 56 * KBL revision ID ordering is bizarre; higher revision ID's map to lower 57 * steppings in some cases. So rather than test against the revision ID 58 * directly, let's map that into our own range of increasing ID's that we 59 * can test against in a regular manner. 60 */ 61 62 const struct i915_rev_steppings kbl_revids[] = { 63 [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, 64 [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, 65 [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, 66 [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, 67 [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, 68 [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, 69 [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, 70 [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, 71 }; 72 73 const struct i915_rev_steppings tgl_uy_revids[] = { 74 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 }, 75 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 }, 76 [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 }, 77 [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 }, 78 }; 79 80 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 81 const struct i915_rev_steppings tgl_revids[] = { 82 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 }, 83 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 }, 84 }; 85 86 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 87 { 88 wal->name = name; 89 wal->engine_name = engine_name; 90 } 91 92 #define WA_LIST_CHUNK (1 << 4) 93 94 static void wa_init_finish(struct i915_wa_list *wal) 95 { 96 /* Trim unused entries. */ 97 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 98 struct i915_wa *list = kmemdup(wal->list, 99 wal->count * sizeof(*list), 100 GFP_KERNEL); 101 102 if (list) { 103 kfree(wal->list); 104 wal->list = list; 105 } 106 } 107 108 if (!wal->count) 109 return; 110 111 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 112 wal->wa_count, wal->name, wal->engine_name); 113 } 114 115 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 116 { 117 unsigned int addr = i915_mmio_reg_offset(wa->reg); 118 unsigned int start = 0, end = wal->count; 119 const unsigned int grow = WA_LIST_CHUNK; 120 struct i915_wa *wa_; 121 122 GEM_BUG_ON(!is_power_of_2(grow)); 123 124 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 125 struct i915_wa *list; 126 127 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 128 GFP_KERNEL); 129 if (!list) { 130 DRM_ERROR("No space for workaround init!\n"); 131 return; 132 } 133 134 if (wal->list) { 135 memcpy(list, wal->list, sizeof(*wa) * wal->count); 136 kfree(wal->list); 137 } 138 139 wal->list = list; 140 } 141 142 while (start < end) { 143 unsigned int mid = start + (end - start) / 2; 144 145 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 146 start = mid + 1; 147 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 148 end = mid; 149 } else { 150 wa_ = &wal->list[mid]; 151 152 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 153 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 154 i915_mmio_reg_offset(wa_->reg), 155 wa_->clr, wa_->set); 156 157 wa_->set &= ~wa->clr; 158 } 159 160 wal->wa_count++; 161 wa_->set |= wa->set; 162 wa_->clr |= wa->clr; 163 wa_->read |= wa->read; 164 return; 165 } 166 } 167 168 wal->wa_count++; 169 wa_ = &wal->list[wal->count++]; 170 *wa_ = *wa; 171 172 while (wa_-- > wal->list) { 173 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 174 i915_mmio_reg_offset(wa_[1].reg)); 175 if (i915_mmio_reg_offset(wa_[1].reg) > 176 i915_mmio_reg_offset(wa_[0].reg)) 177 break; 178 179 swap(wa_[1], wa_[0]); 180 } 181 } 182 183 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 184 u32 clear, u32 set, u32 read_mask) 185 { 186 struct i915_wa wa = { 187 .reg = reg, 188 .clr = clear, 189 .set = set, 190 .read = read_mask, 191 }; 192 193 _wa_add(wal, &wa); 194 } 195 196 static void 197 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 198 { 199 wa_add(wal, reg, clear, set, clear); 200 } 201 202 static void 203 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 204 { 205 wa_write_masked_or(wal, reg, ~0, set); 206 } 207 208 static void 209 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 210 { 211 wa_write_masked_or(wal, reg, set, set); 212 } 213 214 static void 215 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 216 { 217 wa_write_masked_or(wal, reg, clr, 0); 218 } 219 220 static void 221 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 222 { 223 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 224 } 225 226 static void 227 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 228 { 229 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 230 } 231 232 #define WA_SET_BIT_MASKED(addr, mask) \ 233 wa_masked_en(wal, (addr), (mask)) 234 235 #define WA_CLR_BIT_MASKED(addr, mask) \ 236 wa_masked_dis(wal, (addr), (mask)) 237 238 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 239 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 240 241 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 242 struct i915_wa_list *wal) 243 { 244 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 245 } 246 247 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 248 struct i915_wa_list *wal) 249 { 250 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 251 } 252 253 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 254 struct i915_wa_list *wal) 255 { 256 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 257 258 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 259 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 260 261 /* WaDisablePartialInstShootdown:bdw,chv */ 262 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 263 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 264 265 /* Use Force Non-Coherent whenever executing a 3D context. This is a 266 * workaround for for a possible hang in the unlikely event a TLB 267 * invalidation occurs during a PSD flush. 268 */ 269 /* WaForceEnableNonCoherent:bdw,chv */ 270 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 271 WA_SET_BIT_MASKED(HDC_CHICKEN0, 272 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 273 HDC_FORCE_NON_COHERENT); 274 275 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 276 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 277 * polygons in the same 8x4 pixel/sample area to be processed without 278 * stalling waiting for the earlier ones to write to Hierarchical Z 279 * buffer." 280 * 281 * This optimization is off by default for BDW and CHV; turn it on. 282 */ 283 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 284 285 /* Wa4x4STCOptimizationDisable:bdw,chv */ 286 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 287 288 /* 289 * BSpec recommends 8x4 when MSAA is used, 290 * however in practice 16x4 seems fastest. 291 * 292 * Note that PS/WM thread counts depend on the WIZ hashing 293 * disable bit, which we don't touch here, but it's good 294 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 295 */ 296 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 297 GEN6_WIZ_HASHING_MASK, 298 GEN6_WIZ_HASHING_16x4); 299 } 300 301 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 302 struct i915_wa_list *wal) 303 { 304 struct drm_i915_private *i915 = engine->i915; 305 306 gen8_ctx_workarounds_init(engine, wal); 307 308 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 309 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 310 311 /* WaDisableDopClockGating:bdw 312 * 313 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 314 * to disable EUTC clock gating. 315 */ 316 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 317 DOP_CLOCK_GATING_DISABLE); 318 319 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 320 GEN8_SAMPLER_POWER_BYPASS_DIS); 321 322 WA_SET_BIT_MASKED(HDC_CHICKEN0, 323 /* WaForceContextSaveRestoreNonCoherent:bdw */ 324 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 325 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 326 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 327 } 328 329 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 330 struct i915_wa_list *wal) 331 { 332 gen8_ctx_workarounds_init(engine, wal); 333 334 /* WaDisableThreadStallDopClockGating:chv */ 335 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 336 337 /* Improve HiZ throughput on CHV. */ 338 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 339 } 340 341 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 342 struct i915_wa_list *wal) 343 { 344 struct drm_i915_private *i915 = engine->i915; 345 346 if (HAS_LLC(i915)) { 347 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 348 * 349 * Must match Display Engine. See 350 * WaCompressedResourceDisplayNewHashMode. 351 */ 352 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 353 GEN9_PBE_COMPRESSED_HASH_SELECTION); 354 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 355 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 356 } 357 358 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 359 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 360 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 361 FLOW_CONTROL_ENABLE | 362 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 363 364 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 365 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 366 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 367 GEN9_ENABLE_YV12_BUGFIX | 368 GEN9_ENABLE_GPGPU_PREEMPTION); 369 370 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 371 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 372 WA_SET_BIT_MASKED(CACHE_MODE_1, 373 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 374 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 375 376 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 377 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 378 GEN9_CCS_TLB_PREFETCH_ENABLE); 379 380 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 381 WA_SET_BIT_MASKED(HDC_CHICKEN0, 382 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 383 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 384 385 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 386 * both tied to WaForceContextSaveRestoreNonCoherent 387 * in some hsds for skl. We keep the tie for all gen9. The 388 * documentation is a bit hazy and so we want to get common behaviour, 389 * even though there is no clear evidence we would need both on kbl/bxt. 390 * This area has been source of system hangs so we play it safe 391 * and mimic the skl regardless of what bspec says. 392 * 393 * Use Force Non-Coherent whenever executing a 3D context. This 394 * is a workaround for a possible hang in the unlikely event 395 * a TLB invalidation occurs during a PSD flush. 396 */ 397 398 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 399 WA_SET_BIT_MASKED(HDC_CHICKEN0, 400 HDC_FORCE_NON_COHERENT); 401 402 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 403 if (IS_SKYLAKE(i915) || 404 IS_KABYLAKE(i915) || 405 IS_COFFEELAKE(i915) || 406 IS_COMETLAKE(i915)) 407 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 408 GEN8_SAMPLER_POWER_BYPASS_DIS); 409 410 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 411 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 412 413 /* 414 * Supporting preemption with fine-granularity requires changes in the 415 * batch buffer programming. Since we can't break old userspace, we 416 * need to set our default preemption level to safe value. Userspace is 417 * still able to use more fine-grained preemption levels, since in 418 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 419 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 420 * not real HW workarounds, but merely a way to start using preemption 421 * while maintaining old contract with userspace. 422 */ 423 424 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 425 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 426 427 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 428 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 429 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 430 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 431 432 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 433 if (IS_GEN9_LP(i915)) 434 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 435 } 436 437 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 438 struct i915_wa_list *wal) 439 { 440 struct intel_gt *gt = engine->gt; 441 u8 vals[3] = { 0, 0, 0 }; 442 unsigned int i; 443 444 for (i = 0; i < 3; i++) { 445 u8 ss; 446 447 /* 448 * Only consider slices where one, and only one, subslice has 7 449 * EUs 450 */ 451 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 452 continue; 453 454 /* 455 * subslice_7eu[i] != 0 (because of the check above) and 456 * ss_max == 4 (maximum number of subslices possible per slice) 457 * 458 * -> 0 <= ss <= 3; 459 */ 460 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 461 vals[i] = 3 - ss; 462 } 463 464 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 465 return; 466 467 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 468 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 469 GEN9_IZ_HASHING_MASK(2) | 470 GEN9_IZ_HASHING_MASK(1) | 471 GEN9_IZ_HASHING_MASK(0), 472 GEN9_IZ_HASHING(2, vals[2]) | 473 GEN9_IZ_HASHING(1, vals[1]) | 474 GEN9_IZ_HASHING(0, vals[0])); 475 } 476 477 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 478 struct i915_wa_list *wal) 479 { 480 gen9_ctx_workarounds_init(engine, wal); 481 skl_tune_iz_hashing(engine, wal); 482 } 483 484 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 485 struct i915_wa_list *wal) 486 { 487 gen9_ctx_workarounds_init(engine, wal); 488 489 /* WaDisableThreadStallDopClockGating:bxt */ 490 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 491 STALL_DOP_GATING_DISABLE); 492 493 /* WaToEnableHwFixForPushConstHWBug:bxt */ 494 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 495 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 496 } 497 498 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 499 struct i915_wa_list *wal) 500 { 501 struct drm_i915_private *i915 = engine->i915; 502 503 gen9_ctx_workarounds_init(engine, wal); 504 505 /* WaToEnableHwFixForPushConstHWBug:kbl */ 506 if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 507 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 508 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 509 510 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 511 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 512 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 513 } 514 515 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 516 struct i915_wa_list *wal) 517 { 518 gen9_ctx_workarounds_init(engine, wal); 519 520 /* WaToEnableHwFixForPushConstHWBug:glk */ 521 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 522 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 523 } 524 525 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 526 struct i915_wa_list *wal) 527 { 528 gen9_ctx_workarounds_init(engine, wal); 529 530 /* WaToEnableHwFixForPushConstHWBug:cfl */ 531 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 532 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 533 534 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 535 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 536 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 537 } 538 539 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 540 struct i915_wa_list *wal) 541 { 542 /* WaForceContextSaveRestoreNonCoherent:cnl */ 543 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 544 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 545 546 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 547 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 548 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 549 550 /* WaPushConstantDereferenceHoldDisable:cnl */ 551 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 552 553 /* FtrEnableFastAnisoL1BankingFix:cnl */ 554 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 555 556 /* WaDisable3DMidCmdPreemption:cnl */ 557 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 558 559 /* WaDisableGPGPUMidCmdPreemption:cnl */ 560 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 561 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 562 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 563 564 /* WaDisableEarlyEOT:cnl */ 565 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 566 } 567 568 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 569 struct i915_wa_list *wal) 570 { 571 struct drm_i915_private *i915 = engine->i915; 572 573 /* WaDisableBankHangMode:icl */ 574 wa_write(wal, 575 GEN8_L3CNTLREG, 576 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 577 GEN8_ERRDETBCTRL); 578 579 /* Wa_1604370585:icl (pre-prod) 580 * Formerly known as WaPushConstantDereferenceHoldDisable 581 */ 582 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 583 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 584 PUSH_CONSTANT_DEREF_DISABLE); 585 586 /* WaForceEnableNonCoherent:icl 587 * This is not the same workaround as in early Gen9 platforms, where 588 * lacking this could cause system hangs, but coherency performance 589 * overhead is high and only a few compute workloads really need it 590 * (the register is whitelisted in hardware now, so UMDs can opt in 591 * for coherency if they have a good reason). 592 */ 593 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 594 595 /* Wa_2006611047:icl (pre-prod) 596 * Formerly known as WaDisableImprovedTdlClkGating 597 */ 598 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 599 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 600 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 601 602 /* Wa_2006665173:icl (pre-prod) */ 603 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 604 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 605 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 606 607 /* WaEnableFloatBlendOptimization:icl */ 608 wa_write_masked_or(wal, 609 GEN10_CACHE_MODE_SS, 610 0, /* write-only, so skip validation */ 611 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 612 613 /* WaDisableGPGPUMidThreadPreemption:icl */ 614 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 615 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 616 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 617 618 /* allow headerless messages for preemptible GPGPU context */ 619 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 620 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 621 622 /* Wa_1604278689:icl,ehl */ 623 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 624 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 625 0, /* write-only register; skip validation */ 626 0xFFFFFFFF); 627 628 /* Wa_1406306137:icl,ehl */ 629 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 630 } 631 632 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 633 struct i915_wa_list *wal) 634 { 635 /* 636 * Wa_1409142259:tgl 637 * Wa_1409347922:tgl 638 * Wa_1409252684:tgl 639 * Wa_1409217633:tgl 640 * Wa_1409207793:tgl 641 * Wa_1409178076:tgl 642 * Wa_1408979724:tgl 643 * Wa_14010443199:rkl 644 * Wa_14010698770:rkl 645 */ 646 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 647 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 648 649 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 650 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 651 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 652 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 653 } 654 655 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 656 struct i915_wa_list *wal) 657 { 658 gen12_ctx_workarounds_init(engine, wal); 659 660 /* 661 * Wa_1604555607:tgl,rkl 662 * 663 * Note that the implementation of this workaround is further modified 664 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 665 * FF_MODE2 register will return the wrong value when read. The default 666 * value for this register is zero for all fields and there are no bit 667 * masks. So instead of doing a RMW we should just write the GS Timer 668 * and TDS timer values for Wa_1604555607 and Wa_16011163337. 669 */ 670 wa_add(wal, 671 FF_MODE2, 672 FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, 673 FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 674 0); 675 } 676 677 static void 678 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 679 struct i915_wa_list *wal, 680 const char *name) 681 { 682 struct drm_i915_private *i915 = engine->i915; 683 684 if (engine->class != RENDER_CLASS) 685 return; 686 687 wa_init_start(wal, name, engine->name); 688 689 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) 690 tgl_ctx_workarounds_init(engine, wal); 691 else if (IS_GEN(i915, 12)) 692 gen12_ctx_workarounds_init(engine, wal); 693 else if (IS_GEN(i915, 11)) 694 icl_ctx_workarounds_init(engine, wal); 695 else if (IS_CANNONLAKE(i915)) 696 cnl_ctx_workarounds_init(engine, wal); 697 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 698 cfl_ctx_workarounds_init(engine, wal); 699 else if (IS_GEMINILAKE(i915)) 700 glk_ctx_workarounds_init(engine, wal); 701 else if (IS_KABYLAKE(i915)) 702 kbl_ctx_workarounds_init(engine, wal); 703 else if (IS_BROXTON(i915)) 704 bxt_ctx_workarounds_init(engine, wal); 705 else if (IS_SKYLAKE(i915)) 706 skl_ctx_workarounds_init(engine, wal); 707 else if (IS_CHERRYVIEW(i915)) 708 chv_ctx_workarounds_init(engine, wal); 709 else if (IS_BROADWELL(i915)) 710 bdw_ctx_workarounds_init(engine, wal); 711 else if (IS_GEN(i915, 7)) 712 gen7_ctx_workarounds_init(engine, wal); 713 else if (IS_GEN(i915, 6)) 714 gen6_ctx_workarounds_init(engine, wal); 715 else if (INTEL_GEN(i915) < 8) 716 return; 717 else 718 MISSING_CASE(INTEL_GEN(i915)); 719 720 wa_init_finish(wal); 721 } 722 723 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 724 { 725 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 726 } 727 728 int intel_engine_emit_ctx_wa(struct i915_request *rq) 729 { 730 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 731 struct i915_wa *wa; 732 unsigned int i; 733 u32 *cs; 734 int ret; 735 736 if (wal->count == 0) 737 return 0; 738 739 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 740 if (ret) 741 return ret; 742 743 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 744 if (IS_ERR(cs)) 745 return PTR_ERR(cs); 746 747 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 748 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 749 *cs++ = i915_mmio_reg_offset(wa->reg); 750 *cs++ = wa->set; 751 } 752 *cs++ = MI_NOOP; 753 754 intel_ring_advance(rq, cs); 755 756 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 757 if (ret) 758 return ret; 759 760 return 0; 761 } 762 763 static void 764 gen4_gt_workarounds_init(struct drm_i915_private *i915, 765 struct i915_wa_list *wal) 766 { 767 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 768 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 769 } 770 771 static void 772 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 773 { 774 gen4_gt_workarounds_init(i915, wal); 775 776 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 777 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 778 } 779 780 static void 781 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 782 { 783 g4x_gt_workarounds_init(i915, wal); 784 785 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 786 } 787 788 static void 789 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 790 { 791 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 792 wa_masked_en(wal, 793 _3D_CHICKEN, 794 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 795 796 /* WaDisable_RenderCache_OperationalFlush:snb */ 797 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 798 799 /* 800 * BSpec recommends 8x4 when MSAA is used, 801 * however in practice 16x4 seems fastest. 802 * 803 * Note that PS/WM thread counts depend on the WIZ hashing 804 * disable bit, which we don't touch here, but it's good 805 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 806 */ 807 wa_add(wal, 808 GEN6_GT_MODE, 0, 809 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 810 GEN6_WIZ_HASHING_16x4); 811 812 wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); 813 814 wa_masked_en(wal, 815 _3D_CHICKEN3, 816 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 817 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 818 /* 819 * Bspec says: 820 * "This bit must be set if 3DSTATE_CLIP clip mode is set 821 * to normal and 3DSTATE_SF number of SF output attributes 822 * is more than 16." 823 */ 824 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 825 } 826 827 static void 828 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 829 { 830 /* WaDisableEarlyCull:ivb */ 831 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 832 833 /* WaDisablePSDDualDispatchEnable:ivb */ 834 if (IS_IVB_GT1(i915)) 835 wa_masked_en(wal, 836 GEN7_HALF_SLICE_CHICKEN1, 837 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 838 839 /* WaDisable_RenderCache_OperationalFlush:ivb */ 840 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 841 842 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 843 wa_masked_dis(wal, 844 GEN7_COMMON_SLICE_CHICKEN1, 845 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 846 847 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 848 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 849 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 850 851 /* WaForceL3Serialization:ivb */ 852 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 853 854 /* 855 * WaVSThreadDispatchOverride:ivb,vlv 856 * 857 * This actually overrides the dispatch 858 * mode for all thread types. 859 */ 860 wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, 861 GEN7_FF_SCHED_MASK, 862 GEN7_FF_TS_SCHED_HW | 863 GEN7_FF_VS_SCHED_HW | 864 GEN7_FF_DS_SCHED_HW); 865 866 if (0) { /* causes HiZ corruption on ivb:gt1 */ 867 /* enable HiZ Raw Stall Optimization */ 868 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 869 } 870 871 /* WaDisable4x2SubspanOptimization:ivb */ 872 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 873 874 /* 875 * BSpec recommends 8x4 when MSAA is used, 876 * however in practice 16x4 seems fastest. 877 * 878 * Note that PS/WM thread counts depend on the WIZ hashing 879 * disable bit, which we don't touch here, but it's good 880 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 881 */ 882 wa_add(wal, GEN7_GT_MODE, 0, 883 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 884 GEN6_WIZ_HASHING_16x4); 885 } 886 887 static void 888 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 889 { 890 /* WaDisableEarlyCull:vlv */ 891 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 892 893 /* WaPsdDispatchEnable:vlv */ 894 /* WaDisablePSDDualDispatchEnable:vlv */ 895 wa_masked_en(wal, 896 GEN7_HALF_SLICE_CHICKEN1, 897 GEN7_MAX_PS_THREAD_DEP | 898 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 899 900 /* WaDisable_RenderCache_OperationalFlush:vlv */ 901 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 902 903 /* WaForceL3Serialization:vlv */ 904 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 905 906 /* 907 * WaVSThreadDispatchOverride:ivb,vlv 908 * 909 * This actually overrides the dispatch 910 * mode for all thread types. 911 */ 912 wa_write_masked_or(wal, 913 GEN7_FF_THREAD_MODE, 914 GEN7_FF_SCHED_MASK, 915 GEN7_FF_TS_SCHED_HW | 916 GEN7_FF_VS_SCHED_HW | 917 GEN7_FF_DS_SCHED_HW); 918 919 /* 920 * BSpec says this must be set, even though 921 * WaDisable4x2SubspanOptimization isn't listed for VLV. 922 */ 923 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 924 925 /* 926 * BSpec recommends 8x4 when MSAA is used, 927 * however in practice 16x4 seems fastest. 928 * 929 * Note that PS/WM thread counts depend on the WIZ hashing 930 * disable bit, which we don't touch here, but it's good 931 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 932 */ 933 wa_add(wal, GEN7_GT_MODE, 0, 934 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 935 GEN6_WIZ_HASHING_16x4); 936 937 /* 938 * WaIncreaseL3CreditsForVLVB0:vlv 939 * This is the hardware default actually. 940 */ 941 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 942 } 943 944 static void 945 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 946 { 947 /* L3 caching of data atomics doesn't work -- disable it. */ 948 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 949 950 wa_add(wal, 951 HSW_ROW_CHICKEN3, 0, 952 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 953 0 /* XXX does this reg exist? */); 954 955 /* WaVSRefCountFullforceMissDisable:hsw */ 956 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 957 958 wa_masked_dis(wal, 959 CACHE_MODE_0_GEN7, 960 /* WaDisable_RenderCache_OperationalFlush:hsw */ 961 RC_OP_FLUSH_ENABLE | 962 /* enable HiZ Raw Stall Optimization */ 963 HIZ_RAW_STALL_OPT_DISABLE); 964 965 /* WaDisable4x2SubspanOptimization:hsw */ 966 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 967 968 /* 969 * BSpec recommends 8x4 when MSAA is used, 970 * however in practice 16x4 seems fastest. 971 * 972 * Note that PS/WM thread counts depend on the WIZ hashing 973 * disable bit, which we don't touch here, but it's good 974 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 975 */ 976 wa_add(wal, GEN7_GT_MODE, 0, 977 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 978 GEN6_WIZ_HASHING_16x4); 979 980 /* WaSampleCChickenBitEnable:hsw */ 981 wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 982 } 983 984 static void 985 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 986 { 987 /* WaDisableKillLogic:bxt,skl,kbl */ 988 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 989 wa_write_or(wal, 990 GAM_ECOCHK, 991 ECOCHK_DIS_TLB); 992 993 if (HAS_LLC(i915)) { 994 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 995 * 996 * Must match Display Engine. See 997 * WaCompressedResourceDisplayNewHashMode. 998 */ 999 wa_write_or(wal, 1000 MMCD_MISC_CTRL, 1001 MMCD_PCLA | MMCD_HOTSPOT_EN); 1002 } 1003 1004 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1005 wa_write_or(wal, 1006 GAM_ECOCHK, 1007 BDW_DISABLE_HDC_INVALIDATION); 1008 } 1009 1010 static void 1011 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1012 { 1013 gen9_gt_workarounds_init(i915, wal); 1014 1015 /* WaDisableGafsUnitClkGating:skl */ 1016 wa_write_or(wal, 1017 GEN7_UCGCTL4, 1018 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1019 1020 /* WaInPlaceDecompressionHang:skl */ 1021 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 1022 wa_write_or(wal, 1023 GEN9_GAMT_ECO_REG_RW_IA, 1024 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1025 } 1026 1027 static void 1028 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1029 { 1030 gen9_gt_workarounds_init(i915, wal); 1031 1032 /* WaInPlaceDecompressionHang:bxt */ 1033 wa_write_or(wal, 1034 GEN9_GAMT_ECO_REG_RW_IA, 1035 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1036 } 1037 1038 static void 1039 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1040 { 1041 gen9_gt_workarounds_init(i915, wal); 1042 1043 /* WaDisableDynamicCreditSharing:kbl */ 1044 if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)) 1045 wa_write_or(wal, 1046 GAMT_CHKN_BIT_REG, 1047 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1048 1049 /* WaDisableGafsUnitClkGating:kbl */ 1050 wa_write_or(wal, 1051 GEN7_UCGCTL4, 1052 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1053 1054 /* WaInPlaceDecompressionHang:kbl */ 1055 wa_write_or(wal, 1056 GEN9_GAMT_ECO_REG_RW_IA, 1057 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1058 } 1059 1060 static void 1061 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1062 { 1063 gen9_gt_workarounds_init(i915, wal); 1064 } 1065 1066 static void 1067 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1068 { 1069 gen9_gt_workarounds_init(i915, wal); 1070 1071 /* WaDisableGafsUnitClkGating:cfl */ 1072 wa_write_or(wal, 1073 GEN7_UCGCTL4, 1074 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1075 1076 /* WaInPlaceDecompressionHang:cfl */ 1077 wa_write_or(wal, 1078 GEN9_GAMT_ECO_REG_RW_IA, 1079 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1080 } 1081 1082 static void 1083 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1084 { 1085 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; 1086 unsigned int slice, subslice; 1087 u32 l3_en, mcr, mcr_mask; 1088 1089 GEM_BUG_ON(INTEL_GEN(i915) < 10); 1090 1091 /* 1092 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 1093 * L3Banks could be fused off in single slice scenario. If that is 1094 * the case, we might need to program MCR select to a valid L3Bank 1095 * by default, to make sure we correctly read certain registers 1096 * later on (in the range 0xB100 - 0xB3FF). 1097 * 1098 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 1099 * Before any MMIO read into slice/subslice specific registers, MCR 1100 * packet control register needs to be programmed to point to any 1101 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1102 * This means each subsequent MMIO read will be forwarded to an 1103 * specific s/ss combination, but this is OK since these registers 1104 * are consistent across s/ss in almost all cases. In the rare 1105 * occasions, such as INSTDONE, where this value is dependent 1106 * on s/ss combo, the read should be done with read_subslice_reg. 1107 * 1108 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 1109 * to which subslice, or to which L3 bank, the respective mmio reads 1110 * will go, we have to find a common index which works for both 1111 * accesses. 1112 * 1113 * Case where we cannot find a common index fortunately should not 1114 * happen in production hardware, so we only emit a warning instead of 1115 * implementing something more complex that requires checking the range 1116 * of every MMIO read. 1117 */ 1118 1119 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 1120 u32 l3_fuse = 1121 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 1122 GEN10_L3BANK_MASK; 1123 1124 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 1125 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 1126 } else { 1127 l3_en = ~0; 1128 } 1129 1130 slice = fls(sseu->slice_mask) - 1; 1131 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 1132 if (!subslice) { 1133 drm_warn(&i915->drm, 1134 "No common index found between subslice mask %x and L3 bank mask %x!\n", 1135 intel_sseu_get_subslices(sseu, slice), l3_en); 1136 subslice = fls(l3_en); 1137 drm_WARN_ON(&i915->drm, !subslice); 1138 } 1139 subslice--; 1140 1141 if (INTEL_GEN(i915) >= 11) { 1142 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1143 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1144 } else { 1145 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1146 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1147 } 1148 1149 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 1150 1151 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1152 } 1153 1154 static void 1155 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1156 { 1157 wa_init_mcr(i915, wal); 1158 1159 /* WaInPlaceDecompressionHang:cnl */ 1160 wa_write_or(wal, 1161 GEN9_GAMT_ECO_REG_RW_IA, 1162 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1163 } 1164 1165 static void 1166 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1167 { 1168 wa_init_mcr(i915, wal); 1169 1170 /* WaInPlaceDecompressionHang:icl */ 1171 wa_write_or(wal, 1172 GEN9_GAMT_ECO_REG_RW_IA, 1173 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1174 1175 /* WaModifyGamTlbPartitioning:icl */ 1176 wa_write_masked_or(wal, 1177 GEN11_GACB_PERF_CTRL, 1178 GEN11_HASH_CTRL_MASK, 1179 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1180 1181 /* Wa_1405766107:icl 1182 * Formerly known as WaCL2SFHalfMaxAlloc 1183 */ 1184 wa_write_or(wal, 1185 GEN11_LSN_UNSLCVC, 1186 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1187 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1188 1189 /* Wa_220166154:icl 1190 * Formerly known as WaDisCtxReload 1191 */ 1192 wa_write_or(wal, 1193 GEN8_GAMW_ECO_DEV_RW_IA, 1194 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1195 1196 /* Wa_1405779004:icl (pre-prod) */ 1197 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 1198 wa_write_or(wal, 1199 SLICE_UNIT_LEVEL_CLKGATE, 1200 MSCUNIT_CLKGATE_DIS); 1201 1202 /* Wa_1406838659:icl (pre-prod) */ 1203 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1204 wa_write_or(wal, 1205 INF_UNIT_LEVEL_CLKGATE, 1206 CGPSF_CLKGATE_DIS); 1207 1208 /* Wa_1406463099:icl 1209 * Formerly known as WaGamTlbPendError 1210 */ 1211 wa_write_or(wal, 1212 GAMT_CHKN_BIT_REG, 1213 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1214 1215 /* Wa_1607087056:icl,ehl,jsl */ 1216 if (IS_ICELAKE(i915) || 1217 IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 1218 wa_write_or(wal, 1219 SLICE_UNIT_LEVEL_CLKGATE, 1220 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1221 } 1222 } 1223 1224 static void 1225 gen12_gt_workarounds_init(struct drm_i915_private *i915, 1226 struct i915_wa_list *wal) 1227 { 1228 wa_init_mcr(i915, wal); 1229 } 1230 1231 static void 1232 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1233 { 1234 gen12_gt_workarounds_init(i915, wal); 1235 1236 /* Wa_1409420604:tgl */ 1237 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1238 wa_write_or(wal, 1239 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1240 CPSSUNIT_CLKGATE_DIS); 1241 1242 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1243 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1244 wa_write_or(wal, 1245 SLICE_UNIT_LEVEL_CLKGATE, 1246 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1247 } 1248 1249 static void 1250 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1251 { 1252 if (IS_TIGERLAKE(i915)) 1253 tgl_gt_workarounds_init(i915, wal); 1254 else if (IS_GEN(i915, 12)) 1255 gen12_gt_workarounds_init(i915, wal); 1256 else if (IS_GEN(i915, 11)) 1257 icl_gt_workarounds_init(i915, wal); 1258 else if (IS_CANNONLAKE(i915)) 1259 cnl_gt_workarounds_init(i915, wal); 1260 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1261 cfl_gt_workarounds_init(i915, wal); 1262 else if (IS_GEMINILAKE(i915)) 1263 glk_gt_workarounds_init(i915, wal); 1264 else if (IS_KABYLAKE(i915)) 1265 kbl_gt_workarounds_init(i915, wal); 1266 else if (IS_BROXTON(i915)) 1267 bxt_gt_workarounds_init(i915, wal); 1268 else if (IS_SKYLAKE(i915)) 1269 skl_gt_workarounds_init(i915, wal); 1270 else if (IS_HASWELL(i915)) 1271 hsw_gt_workarounds_init(i915, wal); 1272 else if (IS_VALLEYVIEW(i915)) 1273 vlv_gt_workarounds_init(i915, wal); 1274 else if (IS_IVYBRIDGE(i915)) 1275 ivb_gt_workarounds_init(i915, wal); 1276 else if (IS_GEN(i915, 6)) 1277 snb_gt_workarounds_init(i915, wal); 1278 else if (IS_GEN(i915, 5)) 1279 ilk_gt_workarounds_init(i915, wal); 1280 else if (IS_G4X(i915)) 1281 g4x_gt_workarounds_init(i915, wal); 1282 else if (IS_GEN(i915, 4)) 1283 gen4_gt_workarounds_init(i915, wal); 1284 else if (INTEL_GEN(i915) <= 8) 1285 return; 1286 else 1287 MISSING_CASE(INTEL_GEN(i915)); 1288 } 1289 1290 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1291 { 1292 struct i915_wa_list *wal = &i915->gt_wa_list; 1293 1294 wa_init_start(wal, "GT", "global"); 1295 gt_init_workarounds(i915, wal); 1296 wa_init_finish(wal); 1297 } 1298 1299 static enum forcewake_domains 1300 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1301 { 1302 enum forcewake_domains fw = 0; 1303 struct i915_wa *wa; 1304 unsigned int i; 1305 1306 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1307 fw |= intel_uncore_forcewake_for_reg(uncore, 1308 wa->reg, 1309 FW_REG_READ | 1310 FW_REG_WRITE); 1311 1312 return fw; 1313 } 1314 1315 static bool 1316 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1317 { 1318 if ((cur ^ wa->set) & wa->read) { 1319 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1320 name, from, i915_mmio_reg_offset(wa->reg), 1321 cur, cur & wa->read, wa->set); 1322 1323 return false; 1324 } 1325 1326 return true; 1327 } 1328 1329 static void 1330 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1331 { 1332 enum forcewake_domains fw; 1333 unsigned long flags; 1334 struct i915_wa *wa; 1335 unsigned int i; 1336 1337 if (!wal->count) 1338 return; 1339 1340 fw = wal_get_fw_for_rmw(uncore, wal); 1341 1342 spin_lock_irqsave(&uncore->lock, flags); 1343 intel_uncore_forcewake_get__locked(uncore, fw); 1344 1345 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1346 if (wa->clr) 1347 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1348 else 1349 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1350 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1351 wa_verify(wa, 1352 intel_uncore_read_fw(uncore, wa->reg), 1353 wal->name, "application"); 1354 } 1355 1356 intel_uncore_forcewake_put__locked(uncore, fw); 1357 spin_unlock_irqrestore(&uncore->lock, flags); 1358 } 1359 1360 void intel_gt_apply_workarounds(struct intel_gt *gt) 1361 { 1362 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1363 } 1364 1365 static bool wa_list_verify(struct intel_uncore *uncore, 1366 const struct i915_wa_list *wal, 1367 const char *from) 1368 { 1369 struct i915_wa *wa; 1370 unsigned int i; 1371 bool ok = true; 1372 1373 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1374 ok &= wa_verify(wa, 1375 intel_uncore_read(uncore, wa->reg), 1376 wal->name, from); 1377 1378 return ok; 1379 } 1380 1381 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1382 { 1383 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1384 } 1385 1386 static inline bool is_nonpriv_flags_valid(u32 flags) 1387 { 1388 /* Check only valid flag bits are set */ 1389 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1390 return false; 1391 1392 /* NB: Only 3 out of 4 enum values are valid for access field */ 1393 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1394 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1395 return false; 1396 1397 return true; 1398 } 1399 1400 static void 1401 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1402 { 1403 struct i915_wa wa = { 1404 .reg = reg 1405 }; 1406 1407 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1408 return; 1409 1410 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1411 return; 1412 1413 wa.reg.reg |= flags; 1414 _wa_add(wal, &wa); 1415 } 1416 1417 static void 1418 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1419 { 1420 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1421 } 1422 1423 static void gen9_whitelist_build(struct i915_wa_list *w) 1424 { 1425 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1426 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1427 1428 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1429 whitelist_reg(w, GEN8_CS_CHICKEN1); 1430 1431 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1432 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1433 1434 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1435 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1436 } 1437 1438 static void skl_whitelist_build(struct intel_engine_cs *engine) 1439 { 1440 struct i915_wa_list *w = &engine->whitelist; 1441 1442 if (engine->class != RENDER_CLASS) 1443 return; 1444 1445 gen9_whitelist_build(w); 1446 1447 /* WaDisableLSQCROPERFforOCL:skl */ 1448 whitelist_reg(w, GEN8_L3SQCREG4); 1449 } 1450 1451 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1452 { 1453 if (engine->class != RENDER_CLASS) 1454 return; 1455 1456 gen9_whitelist_build(&engine->whitelist); 1457 } 1458 1459 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1460 { 1461 struct i915_wa_list *w = &engine->whitelist; 1462 1463 if (engine->class != RENDER_CLASS) 1464 return; 1465 1466 gen9_whitelist_build(w); 1467 1468 /* WaDisableLSQCROPERFforOCL:kbl */ 1469 whitelist_reg(w, GEN8_L3SQCREG4); 1470 } 1471 1472 static void glk_whitelist_build(struct intel_engine_cs *engine) 1473 { 1474 struct i915_wa_list *w = &engine->whitelist; 1475 1476 if (engine->class != RENDER_CLASS) 1477 return; 1478 1479 gen9_whitelist_build(w); 1480 1481 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1482 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1483 } 1484 1485 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1486 { 1487 struct i915_wa_list *w = &engine->whitelist; 1488 1489 if (engine->class != RENDER_CLASS) 1490 return; 1491 1492 gen9_whitelist_build(w); 1493 1494 /* 1495 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1496 * 1497 * This covers 4 register which are next to one another : 1498 * - PS_INVOCATION_COUNT 1499 * - PS_INVOCATION_COUNT_UDW 1500 * - PS_DEPTH_COUNT 1501 * - PS_DEPTH_COUNT_UDW 1502 */ 1503 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1504 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1505 RING_FORCE_TO_NONPRIV_RANGE_4); 1506 } 1507 1508 static void cml_whitelist_build(struct intel_engine_cs *engine) 1509 { 1510 struct i915_wa_list *w = &engine->whitelist; 1511 1512 if (engine->class != RENDER_CLASS) 1513 whitelist_reg_ext(w, 1514 RING_CTX_TIMESTAMP(engine->mmio_base), 1515 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1516 1517 cfl_whitelist_build(engine); 1518 } 1519 1520 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1521 { 1522 struct i915_wa_list *w = &engine->whitelist; 1523 1524 if (engine->class != RENDER_CLASS) 1525 return; 1526 1527 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1528 whitelist_reg(w, GEN8_CS_CHICKEN1); 1529 } 1530 1531 static void icl_whitelist_build(struct intel_engine_cs *engine) 1532 { 1533 struct i915_wa_list *w = &engine->whitelist; 1534 1535 switch (engine->class) { 1536 case RENDER_CLASS: 1537 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1538 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1539 1540 /* WaAllowUMDToModifySamplerMode:icl */ 1541 whitelist_reg(w, GEN10_SAMPLER_MODE); 1542 1543 /* WaEnableStateCacheRedirectToCS:icl */ 1544 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1545 1546 /* 1547 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1548 * 1549 * This covers 4 register which are next to one another : 1550 * - PS_INVOCATION_COUNT 1551 * - PS_INVOCATION_COUNT_UDW 1552 * - PS_DEPTH_COUNT 1553 * - PS_DEPTH_COUNT_UDW 1554 */ 1555 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1556 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1557 RING_FORCE_TO_NONPRIV_RANGE_4); 1558 break; 1559 1560 case VIDEO_DECODE_CLASS: 1561 /* hucStatusRegOffset */ 1562 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1563 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1564 /* hucUKernelHdrInfoRegOffset */ 1565 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1566 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1567 /* hucStatus2RegOffset */ 1568 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1569 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1570 whitelist_reg_ext(w, 1571 RING_CTX_TIMESTAMP(engine->mmio_base), 1572 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1573 break; 1574 1575 default: 1576 whitelist_reg_ext(w, 1577 RING_CTX_TIMESTAMP(engine->mmio_base), 1578 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1579 break; 1580 } 1581 } 1582 1583 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1584 { 1585 struct i915_wa_list *w = &engine->whitelist; 1586 1587 switch (engine->class) { 1588 case RENDER_CLASS: 1589 /* 1590 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1591 * Wa_1408556865:tgl 1592 * 1593 * This covers 4 registers which are next to one another : 1594 * - PS_INVOCATION_COUNT 1595 * - PS_INVOCATION_COUNT_UDW 1596 * - PS_DEPTH_COUNT 1597 * - PS_DEPTH_COUNT_UDW 1598 */ 1599 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1600 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1601 RING_FORCE_TO_NONPRIV_RANGE_4); 1602 1603 /* Wa_1808121037:tgl */ 1604 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1605 1606 /* Wa_1806527549:tgl */ 1607 whitelist_reg(w, HIZ_CHICKEN); 1608 break; 1609 default: 1610 whitelist_reg_ext(w, 1611 RING_CTX_TIMESTAMP(engine->mmio_base), 1612 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1613 break; 1614 } 1615 } 1616 1617 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1618 { 1619 struct drm_i915_private *i915 = engine->i915; 1620 struct i915_wa_list *w = &engine->whitelist; 1621 1622 wa_init_start(w, "whitelist", engine->name); 1623 1624 if (IS_GEN(i915, 12)) 1625 tgl_whitelist_build(engine); 1626 else if (IS_GEN(i915, 11)) 1627 icl_whitelist_build(engine); 1628 else if (IS_CANNONLAKE(i915)) 1629 cnl_whitelist_build(engine); 1630 else if (IS_COMETLAKE(i915)) 1631 cml_whitelist_build(engine); 1632 else if (IS_COFFEELAKE(i915)) 1633 cfl_whitelist_build(engine); 1634 else if (IS_GEMINILAKE(i915)) 1635 glk_whitelist_build(engine); 1636 else if (IS_KABYLAKE(i915)) 1637 kbl_whitelist_build(engine); 1638 else if (IS_BROXTON(i915)) 1639 bxt_whitelist_build(engine); 1640 else if (IS_SKYLAKE(i915)) 1641 skl_whitelist_build(engine); 1642 else if (INTEL_GEN(i915) <= 8) 1643 return; 1644 else 1645 MISSING_CASE(INTEL_GEN(i915)); 1646 1647 wa_init_finish(w); 1648 } 1649 1650 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1651 { 1652 const struct i915_wa_list *wal = &engine->whitelist; 1653 struct intel_uncore *uncore = engine->uncore; 1654 const u32 base = engine->mmio_base; 1655 struct i915_wa *wa; 1656 unsigned int i; 1657 1658 if (!wal->count) 1659 return; 1660 1661 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1662 intel_uncore_write(uncore, 1663 RING_FORCE_TO_NONPRIV(base, i), 1664 i915_mmio_reg_offset(wa->reg)); 1665 1666 /* And clear the rest just in case of garbage */ 1667 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1668 intel_uncore_write(uncore, 1669 RING_FORCE_TO_NONPRIV(base, i), 1670 i915_mmio_reg_offset(RING_NOPID(base))); 1671 } 1672 1673 static void 1674 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1675 { 1676 struct drm_i915_private *i915 = engine->i915; 1677 1678 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1679 /* 1680 * Wa_1607138336:tgl 1681 * Wa_1607063988:tgl 1682 */ 1683 wa_write_or(wal, 1684 GEN9_CTX_PREEMPT_REG, 1685 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1686 1687 /* 1688 * Wa_1606679103:tgl 1689 * (see also Wa_1606682166:icl) 1690 */ 1691 wa_write_or(wal, 1692 GEN7_SARCHKMD, 1693 GEN7_DISABLE_SAMPLER_PREFETCH); 1694 1695 /* Wa_1408615072:tgl */ 1696 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1697 VSUNIT_CLKGATE_DIS_TGL); 1698 } 1699 1700 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1701 /* Wa_1606931601:tgl,rkl */ 1702 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1703 1704 /* Wa_1409804808:tgl,rkl */ 1705 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1706 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1707 1708 /* 1709 * Wa_1409085225:tgl 1710 * Wa_14010229206:tgl,rkl 1711 */ 1712 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1713 1714 /* 1715 * Wa_1407928979:tgl A* 1716 * Wa_18011464164:tgl B0+ 1717 * Wa_22010931296:tgl B0+ 1718 * Wa_14010919138:rkl,tgl 1719 */ 1720 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1721 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1722 1723 /* 1724 * Wa_1607030317:tgl 1725 * Wa_1607186500:tgl 1726 * Wa_1607297627:tgl,rkl there are multiple entries for this 1727 * WA in the BSpec; some indicate this is an A0-only WA, 1728 * others indicate it applies to all steppings. 1729 */ 1730 wa_masked_en(wal, 1731 GEN6_RC_SLEEP_PSMI_CONTROL, 1732 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1733 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1734 1735 /* 1736 * Wa_1606700617:tgl 1737 * Wa_22010271021:tgl,rkl 1738 */ 1739 wa_masked_en(wal, 1740 GEN9_CS_DEBUG_MODE1, 1741 FF_DOP_CLOCK_GATE_DISABLE); 1742 } 1743 1744 if (IS_GEN(i915, 12)) { 1745 /* Wa_1406941453:gen12 */ 1746 wa_masked_en(wal, 1747 GEN10_SAMPLER_MODE, 1748 ENABLE_SMALLPL); 1749 } 1750 1751 if (IS_GEN(i915, 11)) { 1752 /* This is not an Wa. Enable for better image quality */ 1753 wa_masked_en(wal, 1754 _3D_CHICKEN3, 1755 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1756 1757 /* WaPipelineFlushCoherentLines:icl */ 1758 wa_write_or(wal, 1759 GEN8_L3SQCREG4, 1760 GEN8_LQSC_FLUSH_COHERENT_LINES); 1761 1762 /* 1763 * Wa_1405543622:icl 1764 * Formerly known as WaGAPZPriorityScheme 1765 */ 1766 wa_write_or(wal, 1767 GEN8_GARBCNTL, 1768 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1769 1770 /* 1771 * Wa_1604223664:icl 1772 * Formerly known as WaL3BankAddressHashing 1773 */ 1774 wa_write_masked_or(wal, 1775 GEN8_GARBCNTL, 1776 GEN11_HASH_CTRL_EXCL_MASK, 1777 GEN11_HASH_CTRL_EXCL_BIT0); 1778 wa_write_masked_or(wal, 1779 GEN11_GLBLINVL, 1780 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1781 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1782 1783 /* 1784 * Wa_1405733216:icl 1785 * Formerly known as WaDisableCleanEvicts 1786 */ 1787 wa_write_or(wal, 1788 GEN8_L3SQCREG4, 1789 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1790 1791 /* WaForwardProgressSoftReset:icl */ 1792 wa_write_or(wal, 1793 GEN10_SCRATCH_LNCF2, 1794 PMFLUSHDONE_LNICRSDROP | 1795 PMFLUSH_GAPL3UNBLOCK | 1796 PMFLUSHDONE_LNEBLK); 1797 1798 /* Wa_1406609255:icl (pre-prod) */ 1799 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1800 wa_write_or(wal, 1801 GEN7_SARCHKMD, 1802 GEN7_DISABLE_DEMAND_PREFETCH); 1803 1804 /* Wa_1606682166:icl */ 1805 wa_write_or(wal, 1806 GEN7_SARCHKMD, 1807 GEN7_DISABLE_SAMPLER_PREFETCH); 1808 1809 /* Wa_1409178092:icl */ 1810 wa_write_masked_or(wal, 1811 GEN11_SCRATCH2, 1812 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1813 0); 1814 1815 /* WaEnable32PlaneMode:icl */ 1816 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1817 GEN11_ENABLE_32_PLANE_MODE); 1818 1819 /* 1820 * Wa_1408615072:icl,ehl (vsunit) 1821 * Wa_1407596294:icl,ehl (hsunit) 1822 */ 1823 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1824 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1825 1826 /* Wa_1407352427:icl,ehl */ 1827 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1828 PSDUNIT_CLKGATE_DIS); 1829 1830 /* Wa_1406680159:icl,ehl */ 1831 wa_write_or(wal, 1832 SUBSLICE_UNIT_LEVEL_CLKGATE, 1833 GWUNIT_CLKGATE_DIS); 1834 1835 /* 1836 * Wa_1408767742:icl[a2..forever],ehl[all] 1837 * Wa_1605460711:icl[a0..c0] 1838 */ 1839 wa_write_or(wal, 1840 GEN7_FF_THREAD_MODE, 1841 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1842 1843 /* Wa_22010271021:ehl */ 1844 if (IS_ELKHARTLAKE(i915)) 1845 wa_masked_en(wal, 1846 GEN9_CS_DEBUG_MODE1, 1847 FF_DOP_CLOCK_GATE_DISABLE); 1848 } 1849 1850 if (IS_GEN_RANGE(i915, 9, 12)) { 1851 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1852 wa_masked_en(wal, 1853 GEN7_FF_SLICE_CS_CHICKEN1, 1854 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1855 } 1856 1857 if (IS_SKYLAKE(i915) || 1858 IS_KABYLAKE(i915) || 1859 IS_COFFEELAKE(i915) || 1860 IS_COMETLAKE(i915)) { 1861 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1862 wa_write_or(wal, 1863 GEN8_GARBCNTL, 1864 GEN9_GAPS_TSV_CREDIT_DISABLE); 1865 } 1866 1867 if (IS_BROXTON(i915)) { 1868 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1869 wa_masked_en(wal, 1870 FF_SLICE_CS_CHICKEN2, 1871 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1872 } 1873 1874 if (IS_GEN(i915, 9)) { 1875 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1876 wa_masked_en(wal, 1877 GEN9_CSFE_CHICKEN1_RCS, 1878 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1879 1880 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1881 wa_write_or(wal, 1882 BDW_SCRATCH1, 1883 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1884 1885 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1886 if (IS_GEN9_LP(i915)) 1887 wa_write_masked_or(wal, 1888 GEN8_L3SQCREG1, 1889 L3_PRIO_CREDITS_MASK, 1890 L3_GENERAL_PRIO_CREDITS(62) | 1891 L3_HIGH_PRIO_CREDITS(2)); 1892 1893 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1894 wa_write_or(wal, 1895 GEN8_L3SQCREG4, 1896 GEN8_LQSC_FLUSH_COHERENT_LINES); 1897 } 1898 1899 if (IS_GEN(i915, 7)) 1900 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1901 wa_masked_en(wal, 1902 GFX_MODE_GEN7, 1903 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1904 1905 if (IS_GEN_RANGE(i915, 6, 7)) 1906 /* 1907 * We need to disable the AsyncFlip performance optimisations in 1908 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1909 * already be programmed to '1' on all products. 1910 * 1911 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1912 */ 1913 wa_masked_en(wal, 1914 MI_MODE, 1915 ASYNC_FLIP_PERF_DISABLE); 1916 1917 if (IS_GEN(i915, 6)) { 1918 /* 1919 * Required for the hardware to program scanline values for 1920 * waiting 1921 * WaEnableFlushTlbInvalidationMode:snb 1922 */ 1923 wa_masked_en(wal, 1924 GFX_MODE, 1925 GFX_TLB_INVALIDATE_EXPLICIT); 1926 1927 /* 1928 * From the Sandybridge PRM, volume 1 part 3, page 24: 1929 * "If this bit is set, STCunit will have LRA as replacement 1930 * policy. [...] This bit must be reset. LRA replacement 1931 * policy is not supported." 1932 */ 1933 wa_masked_dis(wal, 1934 CACHE_MODE_0, 1935 CM0_STC_EVICT_DISABLE_LRA_SNB); 1936 } 1937 1938 if (IS_GEN_RANGE(i915, 4, 6)) 1939 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1940 wa_add(wal, MI_MODE, 1941 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1942 /* XXX bit doesn't stick on Broadwater */ 1943 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1944 1945 if (IS_GEN(i915, 4)) 1946 /* 1947 * Disable CONSTANT_BUFFER before it is loaded from the context 1948 * image. For as it is loaded, it is executed and the stored 1949 * address may no longer be valid, leading to a GPU hang. 1950 * 1951 * This imposes the requirement that userspace reload their 1952 * CONSTANT_BUFFER on every batch, fortunately a requirement 1953 * they are already accustomed to from before contexts were 1954 * enabled. 1955 */ 1956 wa_add(wal, ECOSKPD, 1957 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 1958 0 /* XXX bit doesn't stick on Broadwater */); 1959 } 1960 1961 static void 1962 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1963 { 1964 struct drm_i915_private *i915 = engine->i915; 1965 1966 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1967 if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1968 wa_write(wal, 1969 RING_SEMA_WAIT_POLL(engine->mmio_base), 1970 1); 1971 } 1972 } 1973 1974 static void 1975 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1976 { 1977 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1978 return; 1979 1980 if (engine->class == RENDER_CLASS) 1981 rcs_engine_wa_init(engine, wal); 1982 else 1983 xcs_engine_wa_init(engine, wal); 1984 } 1985 1986 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1987 { 1988 struct i915_wa_list *wal = &engine->wa_list; 1989 1990 if (INTEL_GEN(engine->i915) < 4) 1991 return; 1992 1993 wa_init_start(wal, "engine", engine->name); 1994 engine_init_workarounds(engine, wal); 1995 wa_init_finish(wal); 1996 } 1997 1998 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1999 { 2000 wa_list_apply(engine->uncore, &engine->wa_list); 2001 } 2002 2003 static struct i915_vma * 2004 create_scratch(struct i915_address_space *vm, int count) 2005 { 2006 struct drm_i915_gem_object *obj; 2007 struct i915_vma *vma; 2008 unsigned int size; 2009 int err; 2010 2011 size = round_up(count * sizeof(u32), PAGE_SIZE); 2012 obj = i915_gem_object_create_internal(vm->i915, size); 2013 if (IS_ERR(obj)) 2014 return ERR_CAST(obj); 2015 2016 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 2017 2018 vma = i915_vma_instance(obj, vm, NULL); 2019 if (IS_ERR(vma)) { 2020 err = PTR_ERR(vma); 2021 goto err_obj; 2022 } 2023 2024 err = i915_vma_pin(vma, 0, 0, 2025 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2026 if (err) 2027 goto err_obj; 2028 2029 return vma; 2030 2031 err_obj: 2032 i915_gem_object_put(obj); 2033 return ERR_PTR(err); 2034 } 2035 2036 static const struct { 2037 u32 start; 2038 u32 end; 2039 } mcr_ranges_gen8[] = { 2040 { .start = 0x5500, .end = 0x55ff }, 2041 { .start = 0x7000, .end = 0x7fff }, 2042 { .start = 0x9400, .end = 0x97ff }, 2043 { .start = 0xb000, .end = 0xb3ff }, 2044 { .start = 0xe000, .end = 0xe7ff }, 2045 {}, 2046 }; 2047 2048 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2049 { 2050 int i; 2051 2052 if (INTEL_GEN(i915) < 8) 2053 return false; 2054 2055 /* 2056 * Registers in these ranges are affected by the MCR selector 2057 * which only controls CPU initiated MMIO. Routing does not 2058 * work for CS access so we cannot verify them on this path. 2059 */ 2060 for (i = 0; mcr_ranges_gen8[i].start; i++) 2061 if (offset >= mcr_ranges_gen8[i].start && 2062 offset <= mcr_ranges_gen8[i].end) 2063 return true; 2064 2065 return false; 2066 } 2067 2068 static int 2069 wa_list_srm(struct i915_request *rq, 2070 const struct i915_wa_list *wal, 2071 struct i915_vma *vma) 2072 { 2073 struct drm_i915_private *i915 = rq->engine->i915; 2074 unsigned int i, count = 0; 2075 const struct i915_wa *wa; 2076 u32 srm, *cs; 2077 2078 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2079 if (INTEL_GEN(i915) >= 8) 2080 srm++; 2081 2082 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2083 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2084 count++; 2085 } 2086 2087 cs = intel_ring_begin(rq, 4 * count); 2088 if (IS_ERR(cs)) 2089 return PTR_ERR(cs); 2090 2091 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2092 u32 offset = i915_mmio_reg_offset(wa->reg); 2093 2094 if (mcr_range(i915, offset)) 2095 continue; 2096 2097 *cs++ = srm; 2098 *cs++ = offset; 2099 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2100 *cs++ = 0; 2101 } 2102 intel_ring_advance(rq, cs); 2103 2104 return 0; 2105 } 2106 2107 static int engine_wa_list_verify(struct intel_context *ce, 2108 const struct i915_wa_list * const wal, 2109 const char *from) 2110 { 2111 const struct i915_wa *wa; 2112 struct i915_request *rq; 2113 struct i915_vma *vma; 2114 struct i915_gem_ww_ctx ww; 2115 unsigned int i; 2116 u32 *results; 2117 int err; 2118 2119 if (!wal->count) 2120 return 0; 2121 2122 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 2123 if (IS_ERR(vma)) 2124 return PTR_ERR(vma); 2125 2126 intel_engine_pm_get(ce->engine); 2127 i915_gem_ww_ctx_init(&ww, false); 2128 retry: 2129 err = i915_gem_object_lock(vma->obj, &ww); 2130 if (err == 0) 2131 err = intel_context_pin_ww(ce, &ww); 2132 if (err) 2133 goto err_pm; 2134 2135 rq = i915_request_create(ce); 2136 if (IS_ERR(rq)) { 2137 err = PTR_ERR(rq); 2138 goto err_unpin; 2139 } 2140 2141 err = i915_request_await_object(rq, vma->obj, true); 2142 if (err == 0) 2143 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2144 if (err == 0) 2145 err = wa_list_srm(rq, wal, vma); 2146 2147 i915_request_get(rq); 2148 if (err) 2149 i915_request_set_error_once(rq, err); 2150 i915_request_add(rq); 2151 2152 if (err) 2153 goto err_rq; 2154 2155 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2156 err = -ETIME; 2157 goto err_rq; 2158 } 2159 2160 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2161 if (IS_ERR(results)) { 2162 err = PTR_ERR(results); 2163 goto err_rq; 2164 } 2165 2166 err = 0; 2167 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2168 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2169 continue; 2170 2171 if (!wa_verify(wa, results[i], wal->name, from)) 2172 err = -ENXIO; 2173 } 2174 2175 i915_gem_object_unpin_map(vma->obj); 2176 2177 err_rq: 2178 i915_request_put(rq); 2179 err_unpin: 2180 intel_context_unpin(ce); 2181 err_pm: 2182 if (err == -EDEADLK) { 2183 err = i915_gem_ww_ctx_backoff(&ww); 2184 if (!err) 2185 goto retry; 2186 } 2187 i915_gem_ww_ctx_fini(&ww); 2188 intel_engine_pm_put(ce->engine); 2189 i915_vma_unpin(vma); 2190 i915_vma_put(vma); 2191 return err; 2192 } 2193 2194 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2195 const char *from) 2196 { 2197 return engine_wa_list_verify(engine->kernel_context, 2198 &engine->wa_list, 2199 from); 2200 } 2201 2202 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2203 #include "selftest_workarounds.c" 2204 #endif 2205