1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * This file is intended as a central place to implement most [1]_ of the 22 * required workarounds for hardware to work as originally intended. They fall 23 * in five basic categories depending on how/when they are applied: 24 * 25 * - Workarounds that touch registers that are saved/restored to/from the HW 26 * context image. The list is emitted (via Load Register Immediate commands) 27 * everytime a new context is created. 28 * - GT workarounds. The list of these WAs is applied whenever these registers 29 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 30 * - Display workarounds. The list is applied during display clock-gating 31 * initialization. 32 * - Workarounds that whitelist a privileged register, so that UMDs can manage 33 * them directly. This is just a special case of a MMMIO workaround (as we 34 * write the list of these to/be-whitelisted registers to some special HW 35 * registers). 36 * - Workaround batchbuffers, that get executed automatically by the hardware 37 * on every HW context restore. 38 * 39 * .. [1] Please notice that there are other WAs that, due to their nature, 40 * cannot be applied from a central place. Those are peppered around the rest 41 * of the code, as needed. 42 * 43 * .. [2] Technically, some registers are powercontext saved & restored, so they 44 * survive a suspend/resume. In practice, writing them again is not too 45 * costly and simplifies things. We can revisit this in the future. 46 * 47 * Layout 48 * ~~~~~~ 49 * 50 * Keep things in this file ordered by WA type, as per the above (context, GT, 51 * display, register whitelist, batchbuffer). Then, inside each type, keep the 52 * following order: 53 * 54 * - Infrastructure functions and macros 55 * - WAs per platform in standard gen/chrono order 56 * - Public functions to init or apply the given workaround type. 57 */ 58 59 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 60 { 61 wal->name = name; 62 wal->engine_name = engine_name; 63 } 64 65 #define WA_LIST_CHUNK (1 << 4) 66 67 static void wa_init_finish(struct i915_wa_list *wal) 68 { 69 /* Trim unused entries. */ 70 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 71 struct i915_wa *list = kmemdup(wal->list, 72 wal->count * sizeof(*list), 73 GFP_KERNEL); 74 75 if (list) { 76 kfree(wal->list); 77 wal->list = list; 78 } 79 } 80 81 if (!wal->count) 82 return; 83 84 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 85 wal->wa_count, wal->name, wal->engine_name); 86 } 87 88 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 89 { 90 unsigned int addr = i915_mmio_reg_offset(wa->reg); 91 unsigned int start = 0, end = wal->count; 92 const unsigned int grow = WA_LIST_CHUNK; 93 struct i915_wa *wa_; 94 95 GEM_BUG_ON(!is_power_of_2(grow)); 96 97 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 98 struct i915_wa *list; 99 100 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 101 GFP_KERNEL); 102 if (!list) { 103 DRM_ERROR("No space for workaround init!\n"); 104 return; 105 } 106 107 if (wal->list) { 108 memcpy(list, wal->list, sizeof(*wa) * wal->count); 109 kfree(wal->list); 110 } 111 112 wal->list = list; 113 } 114 115 while (start < end) { 116 unsigned int mid = start + (end - start) / 2; 117 118 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 119 start = mid + 1; 120 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 121 end = mid; 122 } else { 123 wa_ = &wal->list[mid]; 124 125 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 126 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 127 i915_mmio_reg_offset(wa_->reg), 128 wa_->clr, wa_->set); 129 130 wa_->set &= ~wa->clr; 131 } 132 133 wal->wa_count++; 134 wa_->set |= wa->set; 135 wa_->clr |= wa->clr; 136 wa_->read |= wa->read; 137 return; 138 } 139 } 140 141 wal->wa_count++; 142 wa_ = &wal->list[wal->count++]; 143 *wa_ = *wa; 144 145 while (wa_-- > wal->list) { 146 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 147 i915_mmio_reg_offset(wa_[1].reg)); 148 if (i915_mmio_reg_offset(wa_[1].reg) > 149 i915_mmio_reg_offset(wa_[0].reg)) 150 break; 151 152 swap(wa_[1], wa_[0]); 153 } 154 } 155 156 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 157 u32 clear, u32 set, u32 read_mask, bool masked_reg) 158 { 159 struct i915_wa wa = { 160 .reg = reg, 161 .clr = clear, 162 .set = set, 163 .read = read_mask, 164 .masked_reg = masked_reg, 165 }; 166 167 _wa_add(wal, &wa); 168 } 169 170 static void 171 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 172 { 173 wa_add(wal, reg, clear, set, clear, false); 174 } 175 176 static void 177 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 178 { 179 wa_write_clr_set(wal, reg, ~0, set); 180 } 181 182 static void 183 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 184 { 185 wa_write_clr_set(wal, reg, set, set); 186 } 187 188 static void 189 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 190 { 191 wa_write_clr_set(wal, reg, clr, 0); 192 } 193 194 /* 195 * WA operations on "masked register". A masked register has the upper 16 bits 196 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 197 * portion of the register without a rmw: you simply write in the upper 16 bits 198 * the mask of bits you are going to modify. 199 * 200 * The wa_masked_* family of functions already does the necessary operations to 201 * calculate the mask based on the parameters passed, so user only has to 202 * provide the lower 16 bits of that register. 203 */ 204 205 static void 206 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 207 { 208 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 209 } 210 211 static void 212 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 213 { 214 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 215 } 216 217 static void 218 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 219 u32 mask, u32 val) 220 { 221 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 222 } 223 224 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 225 struct i915_wa_list *wal) 226 { 227 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 228 } 229 230 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 231 struct i915_wa_list *wal) 232 { 233 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 234 } 235 236 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 237 struct i915_wa_list *wal) 238 { 239 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 240 241 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 242 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 243 244 /* WaDisablePartialInstShootdown:bdw,chv */ 245 wa_masked_en(wal, GEN8_ROW_CHICKEN, 246 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 247 248 /* Use Force Non-Coherent whenever executing a 3D context. This is a 249 * workaround for a possible hang in the unlikely event a TLB 250 * invalidation occurs during a PSD flush. 251 */ 252 /* WaForceEnableNonCoherent:bdw,chv */ 253 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 254 wa_masked_en(wal, HDC_CHICKEN0, 255 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 256 HDC_FORCE_NON_COHERENT); 257 258 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 259 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 260 * polygons in the same 8x4 pixel/sample area to be processed without 261 * stalling waiting for the earlier ones to write to Hierarchical Z 262 * buffer." 263 * 264 * This optimization is off by default for BDW and CHV; turn it on. 265 */ 266 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 267 268 /* Wa4x4STCOptimizationDisable:bdw,chv */ 269 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 270 271 /* 272 * BSpec recommends 8x4 when MSAA is used, 273 * however in practice 16x4 seems fastest. 274 * 275 * Note that PS/WM thread counts depend on the WIZ hashing 276 * disable bit, which we don't touch here, but it's good 277 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 278 */ 279 wa_masked_field_set(wal, GEN7_GT_MODE, 280 GEN6_WIZ_HASHING_MASK, 281 GEN6_WIZ_HASHING_16x4); 282 } 283 284 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 285 struct i915_wa_list *wal) 286 { 287 struct drm_i915_private *i915 = engine->i915; 288 289 gen8_ctx_workarounds_init(engine, wal); 290 291 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 292 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 293 294 /* WaDisableDopClockGating:bdw 295 * 296 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 297 * to disable EUTC clock gating. 298 */ 299 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 300 DOP_CLOCK_GATING_DISABLE); 301 302 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 303 GEN8_SAMPLER_POWER_BYPASS_DIS); 304 305 wa_masked_en(wal, HDC_CHICKEN0, 306 /* WaForceContextSaveRestoreNonCoherent:bdw */ 307 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 308 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 309 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 310 } 311 312 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 313 struct i915_wa_list *wal) 314 { 315 gen8_ctx_workarounds_init(engine, wal); 316 317 /* WaDisableThreadStallDopClockGating:chv */ 318 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 319 320 /* Improve HiZ throughput on CHV. */ 321 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 322 } 323 324 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 325 struct i915_wa_list *wal) 326 { 327 struct drm_i915_private *i915 = engine->i915; 328 329 if (HAS_LLC(i915)) { 330 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 331 * 332 * Must match Display Engine. See 333 * WaCompressedResourceDisplayNewHashMode. 334 */ 335 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 336 GEN9_PBE_COMPRESSED_HASH_SELECTION); 337 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 338 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 339 } 340 341 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 342 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 343 wa_masked_en(wal, GEN8_ROW_CHICKEN, 344 FLOW_CONTROL_ENABLE | 345 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 346 347 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 348 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 349 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 350 GEN9_ENABLE_YV12_BUGFIX | 351 GEN9_ENABLE_GPGPU_PREEMPTION); 352 353 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 354 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 355 wa_masked_en(wal, CACHE_MODE_1, 356 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 357 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 358 359 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 360 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 361 GEN9_CCS_TLB_PREFETCH_ENABLE); 362 363 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 364 wa_masked_en(wal, HDC_CHICKEN0, 365 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 366 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 367 368 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 369 * both tied to WaForceContextSaveRestoreNonCoherent 370 * in some hsds for skl. We keep the tie for all gen9. The 371 * documentation is a bit hazy and so we want to get common behaviour, 372 * even though there is no clear evidence we would need both on kbl/bxt. 373 * This area has been source of system hangs so we play it safe 374 * and mimic the skl regardless of what bspec says. 375 * 376 * Use Force Non-Coherent whenever executing a 3D context. This 377 * is a workaround for a possible hang in the unlikely event 378 * a TLB invalidation occurs during a PSD flush. 379 */ 380 381 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 382 wa_masked_en(wal, HDC_CHICKEN0, 383 HDC_FORCE_NON_COHERENT); 384 385 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 386 if (IS_SKYLAKE(i915) || 387 IS_KABYLAKE(i915) || 388 IS_COFFEELAKE(i915) || 389 IS_COMETLAKE(i915)) 390 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 391 GEN8_SAMPLER_POWER_BYPASS_DIS); 392 393 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 394 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 395 396 /* 397 * Supporting preemption with fine-granularity requires changes in the 398 * batch buffer programming. Since we can't break old userspace, we 399 * need to set our default preemption level to safe value. Userspace is 400 * still able to use more fine-grained preemption levels, since in 401 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 402 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 403 * not real HW workarounds, but merely a way to start using preemption 404 * while maintaining old contract with userspace. 405 */ 406 407 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 408 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 409 410 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 411 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 412 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 413 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 414 415 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 416 if (IS_GEN9_LP(i915)) 417 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 418 } 419 420 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 421 struct i915_wa_list *wal) 422 { 423 struct intel_gt *gt = engine->gt; 424 u8 vals[3] = { 0, 0, 0 }; 425 unsigned int i; 426 427 for (i = 0; i < 3; i++) { 428 u8 ss; 429 430 /* 431 * Only consider slices where one, and only one, subslice has 7 432 * EUs 433 */ 434 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 435 continue; 436 437 /* 438 * subslice_7eu[i] != 0 (because of the check above) and 439 * ss_max == 4 (maximum number of subslices possible per slice) 440 * 441 * -> 0 <= ss <= 3; 442 */ 443 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 444 vals[i] = 3 - ss; 445 } 446 447 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 448 return; 449 450 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 451 wa_masked_field_set(wal, GEN7_GT_MODE, 452 GEN9_IZ_HASHING_MASK(2) | 453 GEN9_IZ_HASHING_MASK(1) | 454 GEN9_IZ_HASHING_MASK(0), 455 GEN9_IZ_HASHING(2, vals[2]) | 456 GEN9_IZ_HASHING(1, vals[1]) | 457 GEN9_IZ_HASHING(0, vals[0])); 458 } 459 460 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 461 struct i915_wa_list *wal) 462 { 463 gen9_ctx_workarounds_init(engine, wal); 464 skl_tune_iz_hashing(engine, wal); 465 } 466 467 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 468 struct i915_wa_list *wal) 469 { 470 gen9_ctx_workarounds_init(engine, wal); 471 472 /* WaDisableThreadStallDopClockGating:bxt */ 473 wa_masked_en(wal, GEN8_ROW_CHICKEN, 474 STALL_DOP_GATING_DISABLE); 475 476 /* WaToEnableHwFixForPushConstHWBug:bxt */ 477 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 478 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 479 } 480 481 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 482 struct i915_wa_list *wal) 483 { 484 struct drm_i915_private *i915 = engine->i915; 485 486 gen9_ctx_workarounds_init(engine, wal); 487 488 /* WaToEnableHwFixForPushConstHWBug:kbl */ 489 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 490 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 491 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 492 493 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 494 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 495 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 496 } 497 498 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 499 struct i915_wa_list *wal) 500 { 501 gen9_ctx_workarounds_init(engine, wal); 502 503 /* WaToEnableHwFixForPushConstHWBug:glk */ 504 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 505 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 506 } 507 508 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 509 struct i915_wa_list *wal) 510 { 511 gen9_ctx_workarounds_init(engine, wal); 512 513 /* WaToEnableHwFixForPushConstHWBug:cfl */ 514 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 515 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 516 517 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 518 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 519 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 520 } 521 522 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 523 struct i915_wa_list *wal) 524 { 525 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 526 wa_write(wal, 527 GEN8_L3CNTLREG, 528 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 529 GEN8_ERRDETBCTRL); 530 531 /* WaForceEnableNonCoherent:icl 532 * This is not the same workaround as in early Gen9 platforms, where 533 * lacking this could cause system hangs, but coherency performance 534 * overhead is high and only a few compute workloads really need it 535 * (the register is whitelisted in hardware now, so UMDs can opt in 536 * for coherency if they have a good reason). 537 */ 538 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 539 540 /* WaEnableFloatBlendOptimization:icl */ 541 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 542 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 543 0 /* write-only, so skip validation */, 544 true); 545 546 /* WaDisableGPGPUMidThreadPreemption:icl */ 547 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 548 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 549 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 550 551 /* allow headerless messages for preemptible GPGPU context */ 552 wa_masked_en(wal, GEN10_SAMPLER_MODE, 553 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 554 555 /* Wa_1604278689:icl,ehl */ 556 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 557 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 558 0, /* write-only register; skip validation */ 559 0xFFFFFFFF); 560 561 /* Wa_1406306137:icl,ehl */ 562 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 563 } 564 565 /* 566 * These settings aren't actually workarounds, but general tuning settings that 567 * need to be programmed on dg2 platform. 568 */ 569 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 570 struct i915_wa_list *wal) 571 { 572 wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 573 wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 574 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 575 wa_add(wal, 576 FF_MODE2, 577 FF_MODE2_TDS_TIMER_MASK, 578 FF_MODE2_TDS_TIMER_128, 579 0, false); 580 } 581 582 /* 583 * These settings aren't actually workarounds, but general tuning settings that 584 * need to be programmed on several platforms. 585 */ 586 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 587 struct i915_wa_list *wal) 588 { 589 /* 590 * Although some platforms refer to it as Wa_1604555607, we need to 591 * program it even on those that don't explicitly list that 592 * workaround. 593 * 594 * Note that the programming of this register is further modified 595 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 596 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 597 * value when read. The default value for this register is zero for all 598 * fields and there are no bit masks. So instead of doing a RMW we 599 * should just write TDS timer value. For the same reason read 600 * verification is ignored. 601 */ 602 wa_add(wal, 603 FF_MODE2, 604 FF_MODE2_TDS_TIMER_MASK, 605 FF_MODE2_TDS_TIMER_128, 606 0, false); 607 } 608 609 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 610 struct i915_wa_list *wal) 611 { 612 gen12_ctx_gt_tuning_init(engine, wal); 613 614 /* 615 * Wa_1409142259:tgl,dg1,adl-p 616 * Wa_1409347922:tgl,dg1,adl-p 617 * Wa_1409252684:tgl,dg1,adl-p 618 * Wa_1409217633:tgl,dg1,adl-p 619 * Wa_1409207793:tgl,dg1,adl-p 620 * Wa_1409178076:tgl,dg1,adl-p 621 * Wa_1408979724:tgl,dg1,adl-p 622 * Wa_14010443199:tgl,rkl,dg1,adl-p 623 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 624 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 625 */ 626 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 627 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 628 629 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 630 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 631 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 632 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 633 634 /* 635 * Wa_16011163337 636 * 637 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 638 * to Wa_1608008084. 639 */ 640 wa_add(wal, 641 FF_MODE2, 642 FF_MODE2_GS_TIMER_MASK, 643 FF_MODE2_GS_TIMER_224, 644 0, false); 645 } 646 647 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 648 struct i915_wa_list *wal) 649 { 650 gen12_ctx_workarounds_init(engine, wal); 651 652 /* Wa_1409044764 */ 653 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 654 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 655 656 /* Wa_22010493298 */ 657 wa_masked_en(wal, HIZ_CHICKEN, 658 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 659 } 660 661 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 662 struct i915_wa_list *wal) 663 { 664 dg2_ctx_gt_tuning_init(engine, wal); 665 666 /* Wa_16011186671:dg2_g11 */ 667 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 668 wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 669 wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 670 } 671 672 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 673 /* Wa_14010469329:dg2_g10 */ 674 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 675 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 676 677 /* 678 * Wa_22010465075:dg2_g10 679 * Wa_22010613112:dg2_g10 680 * Wa_14010698770:dg2_g10 681 */ 682 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 683 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 684 } 685 686 /* Wa_16013271637:dg2 */ 687 wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1, 688 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 689 690 /* Wa_14014947963:dg2 */ 691 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 692 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 693 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 694 695 /* Wa_15010599737:dg2 */ 696 wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 697 } 698 699 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 700 struct i915_wa_list *wal) 701 { 702 /* 703 * This is a "fake" workaround defined by software to ensure we 704 * maintain reliable, backward-compatible behavior for userspace with 705 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 706 * 707 * The per-context setting of MI_MODE[12] determines whether the bits 708 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 709 * in the traditional manner or whether they should instead use a new 710 * tgl+ meaning that breaks backward compatibility, but allows nesting 711 * into 3rd-level batchbuffers. When this new capability was first 712 * added in TGL, it remained off by default unless a context 713 * intentionally opted in to the new behavior. However Xe_HPG now 714 * flips this on by default and requires that we explicitly opt out if 715 * we don't want the new behavior. 716 * 717 * From a SW perspective, we want to maintain the backward-compatible 718 * behavior for userspace, so we'll apply a fake workaround to set it 719 * back to the legacy behavior on platforms where the hardware default 720 * is to break compatibility. At the moment there is no Linux 721 * userspace that utilizes third-level batchbuffers, so this will avoid 722 * userspace from needing to make any changes. using the legacy 723 * meaning is the correct thing to do. If/when we have userspace 724 * consumers that want to utilize third-level batch nesting, we can 725 * provide a context parameter to allow them to opt-in. 726 */ 727 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 728 } 729 730 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 731 struct i915_wa_list *wal) 732 { 733 u8 mocs; 734 735 /* 736 * Some blitter commands do not have a field for MOCS, those 737 * commands will use MOCS index pointed by BLIT_CCTL. 738 * BLIT_CCTL registers are needed to be programmed to un-cached. 739 */ 740 if (engine->class == COPY_ENGINE_CLASS) { 741 mocs = engine->gt->mocs.uc_index; 742 wa_write_clr_set(wal, 743 BLIT_CCTL(engine->mmio_base), 744 BLIT_CCTL_MASK, 745 BLIT_CCTL_MOCS(mocs, mocs)); 746 } 747 } 748 749 /* 750 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 751 * defined by the hardware team, but it programming general context registers. 752 * Adding those context register programming in context workaround 753 * allow us to use the wa framework for proper application and validation. 754 */ 755 static void 756 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 757 struct i915_wa_list *wal) 758 { 759 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 760 fakewa_disable_nestedbb_mode(engine, wal); 761 762 gen12_ctx_gt_mocs_init(engine, wal); 763 } 764 765 static void 766 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 767 struct i915_wa_list *wal, 768 const char *name) 769 { 770 struct drm_i915_private *i915 = engine->i915; 771 772 wa_init_start(wal, name, engine->name); 773 774 /* Applies to all engines */ 775 /* 776 * Fake workarounds are not the actual workaround but 777 * programming of context registers using workaround framework. 778 */ 779 if (GRAPHICS_VER(i915) >= 12) 780 gen12_ctx_gt_fake_wa_init(engine, wal); 781 782 if (engine->class != RENDER_CLASS) 783 goto done; 784 785 if (IS_PONTEVECCHIO(i915)) 786 ; /* noop; none at this time */ 787 else if (IS_DG2(i915)) 788 dg2_ctx_workarounds_init(engine, wal); 789 else if (IS_XEHPSDV(i915)) 790 ; /* noop; none at this time */ 791 else if (IS_DG1(i915)) 792 dg1_ctx_workarounds_init(engine, wal); 793 else if (GRAPHICS_VER(i915) == 12) 794 gen12_ctx_workarounds_init(engine, wal); 795 else if (GRAPHICS_VER(i915) == 11) 796 icl_ctx_workarounds_init(engine, wal); 797 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 798 cfl_ctx_workarounds_init(engine, wal); 799 else if (IS_GEMINILAKE(i915)) 800 glk_ctx_workarounds_init(engine, wal); 801 else if (IS_KABYLAKE(i915)) 802 kbl_ctx_workarounds_init(engine, wal); 803 else if (IS_BROXTON(i915)) 804 bxt_ctx_workarounds_init(engine, wal); 805 else if (IS_SKYLAKE(i915)) 806 skl_ctx_workarounds_init(engine, wal); 807 else if (IS_CHERRYVIEW(i915)) 808 chv_ctx_workarounds_init(engine, wal); 809 else if (IS_BROADWELL(i915)) 810 bdw_ctx_workarounds_init(engine, wal); 811 else if (GRAPHICS_VER(i915) == 7) 812 gen7_ctx_workarounds_init(engine, wal); 813 else if (GRAPHICS_VER(i915) == 6) 814 gen6_ctx_workarounds_init(engine, wal); 815 else if (GRAPHICS_VER(i915) < 8) 816 ; 817 else 818 MISSING_CASE(GRAPHICS_VER(i915)); 819 820 done: 821 wa_init_finish(wal); 822 } 823 824 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 825 { 826 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 827 } 828 829 int intel_engine_emit_ctx_wa(struct i915_request *rq) 830 { 831 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 832 struct i915_wa *wa; 833 unsigned int i; 834 u32 *cs; 835 int ret; 836 837 if (wal->count == 0) 838 return 0; 839 840 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 841 if (ret) 842 return ret; 843 844 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 845 if (IS_ERR(cs)) 846 return PTR_ERR(cs); 847 848 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 849 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 850 *cs++ = i915_mmio_reg_offset(wa->reg); 851 *cs++ = wa->set; 852 } 853 *cs++ = MI_NOOP; 854 855 intel_ring_advance(rq, cs); 856 857 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 858 if (ret) 859 return ret; 860 861 return 0; 862 } 863 864 static void 865 gen4_gt_workarounds_init(struct intel_gt *gt, 866 struct i915_wa_list *wal) 867 { 868 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 869 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 870 } 871 872 static void 873 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 874 { 875 gen4_gt_workarounds_init(gt, wal); 876 877 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 878 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 879 } 880 881 static void 882 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 883 { 884 g4x_gt_workarounds_init(gt, wal); 885 886 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 887 } 888 889 static void 890 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 891 { 892 } 893 894 static void 895 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 896 { 897 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 898 wa_masked_dis(wal, 899 GEN7_COMMON_SLICE_CHICKEN1, 900 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 901 902 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 903 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 904 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 905 906 /* WaForceL3Serialization:ivb */ 907 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 908 } 909 910 static void 911 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 912 { 913 /* WaForceL3Serialization:vlv */ 914 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 915 916 /* 917 * WaIncreaseL3CreditsForVLVB0:vlv 918 * This is the hardware default actually. 919 */ 920 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 921 } 922 923 static void 924 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 925 { 926 /* L3 caching of data atomics doesn't work -- disable it. */ 927 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 928 929 wa_add(wal, 930 HSW_ROW_CHICKEN3, 0, 931 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 932 0 /* XXX does this reg exist? */, true); 933 934 /* WaVSRefCountFullforceMissDisable:hsw */ 935 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 936 } 937 938 static void 939 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 940 { 941 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 942 unsigned int slice, subslice; 943 u32 mcr, mcr_mask; 944 945 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 946 947 /* 948 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 949 * Before any MMIO read into slice/subslice specific registers, MCR 950 * packet control register needs to be programmed to point to any 951 * enabled s/ss pair. Otherwise, incorrect values will be returned. 952 * This means each subsequent MMIO read will be forwarded to an 953 * specific s/ss combination, but this is OK since these registers 954 * are consistent across s/ss in almost all cases. In the rare 955 * occasions, such as INSTDONE, where this value is dependent 956 * on s/ss combo, the read should be done with read_subslice_reg. 957 */ 958 slice = ffs(sseu->slice_mask) - 1; 959 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 960 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 961 GEM_BUG_ON(!subslice); 962 subslice--; 963 964 /* 965 * We use GEN8_MCR..() macros to calculate the |mcr| value for 966 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 967 */ 968 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 969 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 970 971 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 972 973 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 974 } 975 976 static void 977 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 978 { 979 struct drm_i915_private *i915 = gt->i915; 980 981 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 982 gen9_wa_init_mcr(i915, wal); 983 984 /* WaDisableKillLogic:bxt,skl,kbl */ 985 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 986 wa_write_or(wal, 987 GAM_ECOCHK, 988 ECOCHK_DIS_TLB); 989 990 if (HAS_LLC(i915)) { 991 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 992 * 993 * Must match Display Engine. See 994 * WaCompressedResourceDisplayNewHashMode. 995 */ 996 wa_write_or(wal, 997 MMCD_MISC_CTRL, 998 MMCD_PCLA | MMCD_HOTSPOT_EN); 999 } 1000 1001 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1002 wa_write_or(wal, 1003 GAM_ECOCHK, 1004 BDW_DISABLE_HDC_INVALIDATION); 1005 } 1006 1007 static void 1008 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1009 { 1010 gen9_gt_workarounds_init(gt, wal); 1011 1012 /* WaDisableGafsUnitClkGating:skl */ 1013 wa_write_or(wal, 1014 GEN7_UCGCTL4, 1015 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1016 1017 /* WaInPlaceDecompressionHang:skl */ 1018 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1019 wa_write_or(wal, 1020 GEN9_GAMT_ECO_REG_RW_IA, 1021 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1022 } 1023 1024 static void 1025 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1026 { 1027 gen9_gt_workarounds_init(gt, wal); 1028 1029 /* WaDisableDynamicCreditSharing:kbl */ 1030 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1031 wa_write_or(wal, 1032 GAMT_CHKN_BIT_REG, 1033 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1034 1035 /* WaDisableGafsUnitClkGating:kbl */ 1036 wa_write_or(wal, 1037 GEN7_UCGCTL4, 1038 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1039 1040 /* WaInPlaceDecompressionHang:kbl */ 1041 wa_write_or(wal, 1042 GEN9_GAMT_ECO_REG_RW_IA, 1043 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1044 } 1045 1046 static void 1047 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1048 { 1049 gen9_gt_workarounds_init(gt, wal); 1050 } 1051 1052 static void 1053 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1054 { 1055 gen9_gt_workarounds_init(gt, wal); 1056 1057 /* WaDisableGafsUnitClkGating:cfl */ 1058 wa_write_or(wal, 1059 GEN7_UCGCTL4, 1060 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1061 1062 /* WaInPlaceDecompressionHang:cfl */ 1063 wa_write_or(wal, 1064 GEN9_GAMT_ECO_REG_RW_IA, 1065 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1066 } 1067 1068 static void __set_mcr_steering(struct i915_wa_list *wal, 1069 i915_reg_t steering_reg, 1070 unsigned int slice, unsigned int subslice) 1071 { 1072 u32 mcr, mcr_mask; 1073 1074 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1075 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1076 1077 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1078 } 1079 1080 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1081 unsigned int slice, unsigned int subslice) 1082 { 1083 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1084 1085 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1086 1087 gt->default_steering.groupid = slice; 1088 gt->default_steering.instanceid = subslice; 1089 1090 if (drm_debug_enabled(DRM_UT_DRIVER)) 1091 intel_gt_mcr_report_steering(&p, gt, false); 1092 } 1093 1094 static void 1095 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1096 { 1097 const struct sseu_dev_info *sseu = >->info.sseu; 1098 unsigned int subslice; 1099 1100 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1101 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1102 1103 /* 1104 * Although a platform may have subslices, we need to always steer 1105 * reads to the lowest instance that isn't fused off. When Render 1106 * Power Gating is enabled, grabbing forcewake will only power up a 1107 * single subslice (the "minconfig") if there isn't a real workload 1108 * that needs to be run; this means that if we steer register reads to 1109 * one of the higher subslices, we run the risk of reading back 0's or 1110 * random garbage. 1111 */ 1112 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1113 1114 /* 1115 * If the subslice we picked above also steers us to a valid L3 bank, 1116 * then we can just rely on the default steering and won't need to 1117 * worry about explicitly re-steering L3BANK reads later. 1118 */ 1119 if (gt->info.l3bank_mask & BIT(subslice)) 1120 gt->steering_table[L3BANK] = NULL; 1121 1122 __add_mcr_wa(gt, wal, 0, subslice); 1123 } 1124 1125 static void 1126 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1127 { 1128 const struct sseu_dev_info *sseu = >->info.sseu; 1129 unsigned long slice, subslice = 0, slice_mask = 0; 1130 u32 lncf_mask = 0; 1131 int i; 1132 1133 /* 1134 * On Xe_HP the steering increases in complexity. There are now several 1135 * more units that require steering and we're not guaranteed to be able 1136 * to find a common setting for all of them. These are: 1137 * - GSLICE (fusable) 1138 * - DSS (sub-unit within gslice; fusable) 1139 * - L3 Bank (fusable) 1140 * - MSLICE (fusable) 1141 * - LNCF (sub-unit within mslice; always present if mslice is present) 1142 * 1143 * We'll do our default/implicit steering based on GSLICE (in the 1144 * sliceid field) and DSS (in the subsliceid field). If we can 1145 * find overlap between the valid MSLICE and/or LNCF values with 1146 * a suitable GSLICE, then we can just re-use the default value and 1147 * skip and explicit steering at runtime. 1148 * 1149 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1150 * a valid sliceid value. DSS steering is the only type of steering 1151 * that utilizes the 'subsliceid' bits. 1152 * 1153 * Also note that, even though the steering domain is called "GSlice" 1154 * and it is encoded in the register using the gslice format, the spec 1155 * says that the combined (geometry | compute) fuse should be used to 1156 * select the steering. 1157 */ 1158 1159 /* Find the potential gslice candidates */ 1160 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1161 GEN_DSS_PER_GSLICE); 1162 1163 /* 1164 * Find the potential LNCF candidates. Either LNCF within a valid 1165 * mslice is fine. 1166 */ 1167 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1168 lncf_mask |= (0x3 << (i * 2)); 1169 1170 /* 1171 * Are there any sliceid values that work for both GSLICE and LNCF 1172 * steering? 1173 */ 1174 if (slice_mask & lncf_mask) { 1175 slice_mask &= lncf_mask; 1176 gt->steering_table[LNCF] = NULL; 1177 } 1178 1179 /* How about sliceid values that also work for MSLICE steering? */ 1180 if (slice_mask & gt->info.mslice_mask) { 1181 slice_mask &= gt->info.mslice_mask; 1182 gt->steering_table[MSLICE] = NULL; 1183 } 1184 1185 slice = __ffs(slice_mask); 1186 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1187 GEN_DSS_PER_GSLICE; 1188 1189 __add_mcr_wa(gt, wal, slice, subslice); 1190 1191 /* 1192 * SQIDI ranges are special because they use different steering 1193 * registers than everything else we work with. On XeHP SDV and 1194 * DG2-G10, any value in the steering registers will work fine since 1195 * all instances are present, but DG2-G11 only has SQIDI instances at 1196 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1197 * we'll just steer to a hardcoded "2" since that value will work 1198 * everywhere. 1199 */ 1200 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1201 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1202 } 1203 1204 static void 1205 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1206 { 1207 unsigned int dss; 1208 1209 /* 1210 * Setup implicit steering for COMPUTE and DSS ranges to the first 1211 * non-fused-off DSS. All other types of MCR registers will be 1212 * explicitly steered. 1213 */ 1214 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1215 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1216 } 1217 1218 static void 1219 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1220 { 1221 struct drm_i915_private *i915 = gt->i915; 1222 1223 icl_wa_init_mcr(gt, wal); 1224 1225 /* WaModifyGamTlbPartitioning:icl */ 1226 wa_write_clr_set(wal, 1227 GEN11_GACB_PERF_CTRL, 1228 GEN11_HASH_CTRL_MASK, 1229 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1230 1231 /* Wa_1405766107:icl 1232 * Formerly known as WaCL2SFHalfMaxAlloc 1233 */ 1234 wa_write_or(wal, 1235 GEN11_LSN_UNSLCVC, 1236 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1237 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1238 1239 /* Wa_220166154:icl 1240 * Formerly known as WaDisCtxReload 1241 */ 1242 wa_write_or(wal, 1243 GEN8_GAMW_ECO_DEV_RW_IA, 1244 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1245 1246 /* Wa_1406463099:icl 1247 * Formerly known as WaGamTlbPendError 1248 */ 1249 wa_write_or(wal, 1250 GAMT_CHKN_BIT_REG, 1251 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1252 1253 /* Wa_1407352427:icl,ehl */ 1254 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1255 PSDUNIT_CLKGATE_DIS); 1256 1257 /* Wa_1406680159:icl,ehl */ 1258 wa_write_or(wal, 1259 SUBSLICE_UNIT_LEVEL_CLKGATE, 1260 GWUNIT_CLKGATE_DIS); 1261 1262 /* Wa_1607087056:icl,ehl,jsl */ 1263 if (IS_ICELAKE(i915) || 1264 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1265 wa_write_or(wal, 1266 SLICE_UNIT_LEVEL_CLKGATE, 1267 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1268 1269 /* 1270 * This is not a documented workaround, but rather an optimization 1271 * to reduce sampler power. 1272 */ 1273 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1274 } 1275 1276 /* 1277 * Though there are per-engine instances of these registers, 1278 * they retain their value through engine resets and should 1279 * only be provided on the GT workaround list rather than 1280 * the engine-specific workaround list. 1281 */ 1282 static void 1283 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1284 { 1285 struct intel_engine_cs *engine; 1286 int id; 1287 1288 for_each_engine(engine, gt, id) { 1289 if (engine->class != VIDEO_DECODE_CLASS || 1290 (engine->instance % 2)) 1291 continue; 1292 1293 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1294 IECPUNIT_CLKGATE_DIS); 1295 } 1296 } 1297 1298 static void 1299 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1300 { 1301 icl_wa_init_mcr(gt, wal); 1302 1303 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1304 wa_14011060649(gt, wal); 1305 1306 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1307 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1308 } 1309 1310 static void 1311 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1312 { 1313 struct drm_i915_private *i915 = gt->i915; 1314 1315 gen12_gt_workarounds_init(gt, wal); 1316 1317 /* Wa_1409420604:tgl */ 1318 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1319 wa_write_or(wal, 1320 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1321 CPSSUNIT_CLKGATE_DIS); 1322 1323 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1324 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1325 wa_write_or(wal, 1326 SLICE_UNIT_LEVEL_CLKGATE, 1327 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1328 1329 /* Wa_1408615072:tgl[a0] */ 1330 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1331 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1332 VSUNIT_CLKGATE_DIS_TGL); 1333 } 1334 1335 static void 1336 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1337 { 1338 struct drm_i915_private *i915 = gt->i915; 1339 1340 gen12_gt_workarounds_init(gt, wal); 1341 1342 /* Wa_1607087056:dg1 */ 1343 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1344 wa_write_or(wal, 1345 SLICE_UNIT_LEVEL_CLKGATE, 1346 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1347 1348 /* Wa_1409420604:dg1 */ 1349 if (IS_DG1(i915)) 1350 wa_write_or(wal, 1351 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1352 CPSSUNIT_CLKGATE_DIS); 1353 1354 /* Wa_1408615072:dg1 */ 1355 /* Empirical testing shows this register is unaffected by engine reset. */ 1356 if (IS_DG1(i915)) 1357 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1358 VSUNIT_CLKGATE_DIS_TGL); 1359 } 1360 1361 static void 1362 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1363 { 1364 struct drm_i915_private *i915 = gt->i915; 1365 1366 xehp_init_mcr(gt, wal); 1367 1368 /* Wa_1409757795:xehpsdv */ 1369 wa_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1370 1371 /* Wa_16011155590:xehpsdv */ 1372 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1373 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1374 TSGUNIT_CLKGATE_DIS); 1375 1376 /* Wa_14011780169:xehpsdv */ 1377 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1378 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1379 GAMTLBVDBOX7_CLKGATE_DIS | 1380 GAMTLBVDBOX6_CLKGATE_DIS | 1381 GAMTLBVDBOX5_CLKGATE_DIS | 1382 GAMTLBVDBOX4_CLKGATE_DIS | 1383 GAMTLBVDBOX3_CLKGATE_DIS | 1384 GAMTLBVDBOX2_CLKGATE_DIS | 1385 GAMTLBVDBOX1_CLKGATE_DIS | 1386 GAMTLBVDBOX0_CLKGATE_DIS | 1387 GAMTLBKCR_CLKGATE_DIS | 1388 GAMTLBGUC_CLKGATE_DIS | 1389 GAMTLBBLT_CLKGATE_DIS); 1390 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1391 GAMTLBGFXA1_CLKGATE_DIS | 1392 GAMTLBCOMPA0_CLKGATE_DIS | 1393 GAMTLBCOMPA1_CLKGATE_DIS | 1394 GAMTLBCOMPB0_CLKGATE_DIS | 1395 GAMTLBCOMPB1_CLKGATE_DIS | 1396 GAMTLBCOMPC0_CLKGATE_DIS | 1397 GAMTLBCOMPC1_CLKGATE_DIS | 1398 GAMTLBCOMPD0_CLKGATE_DIS | 1399 GAMTLBCOMPD1_CLKGATE_DIS | 1400 GAMTLBMERT_CLKGATE_DIS | 1401 GAMTLBVEBOX3_CLKGATE_DIS | 1402 GAMTLBVEBOX2_CLKGATE_DIS | 1403 GAMTLBVEBOX1_CLKGATE_DIS | 1404 GAMTLBVEBOX0_CLKGATE_DIS); 1405 } 1406 1407 /* Wa_16012725990:xehpsdv */ 1408 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1409 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1410 1411 /* Wa_14011060649:xehpsdv */ 1412 wa_14011060649(gt, wal); 1413 } 1414 1415 static void 1416 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1417 { 1418 struct intel_engine_cs *engine; 1419 int id; 1420 1421 xehp_init_mcr(gt, wal); 1422 1423 /* Wa_14011060649:dg2 */ 1424 wa_14011060649(gt, wal); 1425 1426 /* 1427 * Although there are per-engine instances of these registers, 1428 * they technically exist outside the engine itself and are not 1429 * impacted by engine resets. Furthermore, they're part of the 1430 * GuC blacklist so trying to treat them as engine workarounds 1431 * will result in GuC initialization failure and a wedged GPU. 1432 */ 1433 for_each_engine(engine, gt, id) { 1434 if (engine->class != VIDEO_DECODE_CLASS) 1435 continue; 1436 1437 /* Wa_16010515920:dg2_g10 */ 1438 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1439 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1440 ALNUNIT_CLKGATE_DIS); 1441 } 1442 1443 if (IS_DG2_G10(gt->i915)) { 1444 /* Wa_22010523718:dg2 */ 1445 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1446 CG3DDISCFEG_CLKGATE_DIS); 1447 1448 /* Wa_14011006942:dg2 */ 1449 wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE, 1450 DSS_ROUTER_CLKGATE_DIS); 1451 } 1452 1453 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1454 /* Wa_14010948348:dg2_g10 */ 1455 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1456 1457 /* Wa_14011037102:dg2_g10 */ 1458 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1459 1460 /* Wa_14011371254:dg2_g10 */ 1461 wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1462 1463 /* Wa_14011431319:dg2_g10 */ 1464 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1465 GAMTLBVDBOX7_CLKGATE_DIS | 1466 GAMTLBVDBOX6_CLKGATE_DIS | 1467 GAMTLBVDBOX5_CLKGATE_DIS | 1468 GAMTLBVDBOX4_CLKGATE_DIS | 1469 GAMTLBVDBOX3_CLKGATE_DIS | 1470 GAMTLBVDBOX2_CLKGATE_DIS | 1471 GAMTLBVDBOX1_CLKGATE_DIS | 1472 GAMTLBVDBOX0_CLKGATE_DIS | 1473 GAMTLBKCR_CLKGATE_DIS | 1474 GAMTLBGUC_CLKGATE_DIS | 1475 GAMTLBBLT_CLKGATE_DIS); 1476 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1477 GAMTLBGFXA1_CLKGATE_DIS | 1478 GAMTLBCOMPA0_CLKGATE_DIS | 1479 GAMTLBCOMPA1_CLKGATE_DIS | 1480 GAMTLBCOMPB0_CLKGATE_DIS | 1481 GAMTLBCOMPB1_CLKGATE_DIS | 1482 GAMTLBCOMPC0_CLKGATE_DIS | 1483 GAMTLBCOMPC1_CLKGATE_DIS | 1484 GAMTLBCOMPD0_CLKGATE_DIS | 1485 GAMTLBCOMPD1_CLKGATE_DIS | 1486 GAMTLBMERT_CLKGATE_DIS | 1487 GAMTLBVEBOX3_CLKGATE_DIS | 1488 GAMTLBVEBOX2_CLKGATE_DIS | 1489 GAMTLBVEBOX1_CLKGATE_DIS | 1490 GAMTLBVEBOX0_CLKGATE_DIS); 1491 1492 /* Wa_14010569222:dg2_g10 */ 1493 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1494 GAMEDIA_CLKGATE_DIS); 1495 1496 /* Wa_14011028019:dg2_g10 */ 1497 wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1498 } 1499 1500 /* Wa_14014830051:dg2 */ 1501 wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1502 1503 /* 1504 * The following are not actually "workarounds" but rather 1505 * recommended tuning settings documented in the bspec's 1506 * performance guide section. 1507 */ 1508 wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); 1509 1510 /* Wa_14015795083 */ 1511 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1512 } 1513 1514 static void 1515 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1516 { 1517 pvc_init_mcr(gt, wal); 1518 1519 /* Wa_14015795083 */ 1520 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1521 } 1522 1523 static void 1524 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1525 { 1526 struct drm_i915_private *i915 = gt->i915; 1527 1528 if (IS_PONTEVECCHIO(i915)) 1529 pvc_gt_workarounds_init(gt, wal); 1530 else if (IS_DG2(i915)) 1531 dg2_gt_workarounds_init(gt, wal); 1532 else if (IS_XEHPSDV(i915)) 1533 xehpsdv_gt_workarounds_init(gt, wal); 1534 else if (IS_DG1(i915)) 1535 dg1_gt_workarounds_init(gt, wal); 1536 else if (IS_TIGERLAKE(i915)) 1537 tgl_gt_workarounds_init(gt, wal); 1538 else if (GRAPHICS_VER(i915) == 12) 1539 gen12_gt_workarounds_init(gt, wal); 1540 else if (GRAPHICS_VER(i915) == 11) 1541 icl_gt_workarounds_init(gt, wal); 1542 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1543 cfl_gt_workarounds_init(gt, wal); 1544 else if (IS_GEMINILAKE(i915)) 1545 glk_gt_workarounds_init(gt, wal); 1546 else if (IS_KABYLAKE(i915)) 1547 kbl_gt_workarounds_init(gt, wal); 1548 else if (IS_BROXTON(i915)) 1549 gen9_gt_workarounds_init(gt, wal); 1550 else if (IS_SKYLAKE(i915)) 1551 skl_gt_workarounds_init(gt, wal); 1552 else if (IS_HASWELL(i915)) 1553 hsw_gt_workarounds_init(gt, wal); 1554 else if (IS_VALLEYVIEW(i915)) 1555 vlv_gt_workarounds_init(gt, wal); 1556 else if (IS_IVYBRIDGE(i915)) 1557 ivb_gt_workarounds_init(gt, wal); 1558 else if (GRAPHICS_VER(i915) == 6) 1559 snb_gt_workarounds_init(gt, wal); 1560 else if (GRAPHICS_VER(i915) == 5) 1561 ilk_gt_workarounds_init(gt, wal); 1562 else if (IS_G4X(i915)) 1563 g4x_gt_workarounds_init(gt, wal); 1564 else if (GRAPHICS_VER(i915) == 4) 1565 gen4_gt_workarounds_init(gt, wal); 1566 else if (GRAPHICS_VER(i915) <= 8) 1567 ; 1568 else 1569 MISSING_CASE(GRAPHICS_VER(i915)); 1570 } 1571 1572 void intel_gt_init_workarounds(struct intel_gt *gt) 1573 { 1574 struct i915_wa_list *wal = >->wa_list; 1575 1576 wa_init_start(wal, "GT", "global"); 1577 gt_init_workarounds(gt, wal); 1578 wa_init_finish(wal); 1579 } 1580 1581 static enum forcewake_domains 1582 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1583 { 1584 enum forcewake_domains fw = 0; 1585 struct i915_wa *wa; 1586 unsigned int i; 1587 1588 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1589 fw |= intel_uncore_forcewake_for_reg(uncore, 1590 wa->reg, 1591 FW_REG_READ | 1592 FW_REG_WRITE); 1593 1594 return fw; 1595 } 1596 1597 static bool 1598 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1599 { 1600 if ((cur ^ wa->set) & wa->read) { 1601 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1602 name, from, i915_mmio_reg_offset(wa->reg), 1603 cur, cur & wa->read, wa->set & wa->read); 1604 1605 return false; 1606 } 1607 1608 return true; 1609 } 1610 1611 static void 1612 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1613 { 1614 struct intel_uncore *uncore = gt->uncore; 1615 enum forcewake_domains fw; 1616 unsigned long flags; 1617 struct i915_wa *wa; 1618 unsigned int i; 1619 1620 if (!wal->count) 1621 return; 1622 1623 fw = wal_get_fw_for_rmw(uncore, wal); 1624 1625 spin_lock_irqsave(&uncore->lock, flags); 1626 intel_uncore_forcewake_get__locked(uncore, fw); 1627 1628 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1629 u32 val, old = 0; 1630 1631 /* open-coded rmw due to steering */ 1632 old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0; 1633 val = (old & ~wa->clr) | wa->set; 1634 if (val != old || !wa->clr) 1635 intel_uncore_write_fw(uncore, wa->reg, val); 1636 1637 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1638 wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg), 1639 wal->name, "application"); 1640 } 1641 1642 intel_uncore_forcewake_put__locked(uncore, fw); 1643 spin_unlock_irqrestore(&uncore->lock, flags); 1644 } 1645 1646 void intel_gt_apply_workarounds(struct intel_gt *gt) 1647 { 1648 wa_list_apply(gt, >->wa_list); 1649 } 1650 1651 static bool wa_list_verify(struct intel_gt *gt, 1652 const struct i915_wa_list *wal, 1653 const char *from) 1654 { 1655 struct intel_uncore *uncore = gt->uncore; 1656 struct i915_wa *wa; 1657 enum forcewake_domains fw; 1658 unsigned long flags; 1659 unsigned int i; 1660 bool ok = true; 1661 1662 fw = wal_get_fw_for_rmw(uncore, wal); 1663 1664 spin_lock_irqsave(&uncore->lock, flags); 1665 intel_uncore_forcewake_get__locked(uncore, fw); 1666 1667 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1668 ok &= wa_verify(wa, 1669 intel_gt_mcr_read_any_fw(gt, wa->reg), 1670 wal->name, from); 1671 1672 intel_uncore_forcewake_put__locked(uncore, fw); 1673 spin_unlock_irqrestore(&uncore->lock, flags); 1674 1675 return ok; 1676 } 1677 1678 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1679 { 1680 return wa_list_verify(gt, >->wa_list, from); 1681 } 1682 1683 __maybe_unused 1684 static bool is_nonpriv_flags_valid(u32 flags) 1685 { 1686 /* Check only valid flag bits are set */ 1687 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1688 return false; 1689 1690 /* NB: Only 3 out of 4 enum values are valid for access field */ 1691 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1692 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1693 return false; 1694 1695 return true; 1696 } 1697 1698 static void 1699 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1700 { 1701 struct i915_wa wa = { 1702 .reg = reg 1703 }; 1704 1705 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1706 return; 1707 1708 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1709 return; 1710 1711 wa.reg.reg |= flags; 1712 _wa_add(wal, &wa); 1713 } 1714 1715 static void 1716 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1717 { 1718 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1719 } 1720 1721 static void gen9_whitelist_build(struct i915_wa_list *w) 1722 { 1723 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1724 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1725 1726 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1727 whitelist_reg(w, GEN8_CS_CHICKEN1); 1728 1729 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1730 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1731 1732 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1733 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1734 } 1735 1736 static void skl_whitelist_build(struct intel_engine_cs *engine) 1737 { 1738 struct i915_wa_list *w = &engine->whitelist; 1739 1740 if (engine->class != RENDER_CLASS) 1741 return; 1742 1743 gen9_whitelist_build(w); 1744 1745 /* WaDisableLSQCROPERFforOCL:skl */ 1746 whitelist_reg(w, GEN8_L3SQCREG4); 1747 } 1748 1749 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1750 { 1751 if (engine->class != RENDER_CLASS) 1752 return; 1753 1754 gen9_whitelist_build(&engine->whitelist); 1755 } 1756 1757 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1758 { 1759 struct i915_wa_list *w = &engine->whitelist; 1760 1761 if (engine->class != RENDER_CLASS) 1762 return; 1763 1764 gen9_whitelist_build(w); 1765 1766 /* WaDisableLSQCROPERFforOCL:kbl */ 1767 whitelist_reg(w, GEN8_L3SQCREG4); 1768 } 1769 1770 static void glk_whitelist_build(struct intel_engine_cs *engine) 1771 { 1772 struct i915_wa_list *w = &engine->whitelist; 1773 1774 if (engine->class != RENDER_CLASS) 1775 return; 1776 1777 gen9_whitelist_build(w); 1778 1779 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1780 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1781 } 1782 1783 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1784 { 1785 struct i915_wa_list *w = &engine->whitelist; 1786 1787 if (engine->class != RENDER_CLASS) 1788 return; 1789 1790 gen9_whitelist_build(w); 1791 1792 /* 1793 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1794 * 1795 * This covers 4 register which are next to one another : 1796 * - PS_INVOCATION_COUNT 1797 * - PS_INVOCATION_COUNT_UDW 1798 * - PS_DEPTH_COUNT 1799 * - PS_DEPTH_COUNT_UDW 1800 */ 1801 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1802 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1803 RING_FORCE_TO_NONPRIV_RANGE_4); 1804 } 1805 1806 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1807 { 1808 struct i915_wa_list *w = &engine->whitelist; 1809 1810 if (engine->class != RENDER_CLASS) 1811 whitelist_reg_ext(w, 1812 RING_CTX_TIMESTAMP(engine->mmio_base), 1813 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1814 } 1815 1816 static void cml_whitelist_build(struct intel_engine_cs *engine) 1817 { 1818 allow_read_ctx_timestamp(engine); 1819 1820 cfl_whitelist_build(engine); 1821 } 1822 1823 static void icl_whitelist_build(struct intel_engine_cs *engine) 1824 { 1825 struct i915_wa_list *w = &engine->whitelist; 1826 1827 allow_read_ctx_timestamp(engine); 1828 1829 switch (engine->class) { 1830 case RENDER_CLASS: 1831 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1832 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1833 1834 /* WaAllowUMDToModifySamplerMode:icl */ 1835 whitelist_reg(w, GEN10_SAMPLER_MODE); 1836 1837 /* WaEnableStateCacheRedirectToCS:icl */ 1838 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1839 1840 /* 1841 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1842 * 1843 * This covers 4 register which are next to one another : 1844 * - PS_INVOCATION_COUNT 1845 * - PS_INVOCATION_COUNT_UDW 1846 * - PS_DEPTH_COUNT 1847 * - PS_DEPTH_COUNT_UDW 1848 */ 1849 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1850 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1851 RING_FORCE_TO_NONPRIV_RANGE_4); 1852 break; 1853 1854 case VIDEO_DECODE_CLASS: 1855 /* hucStatusRegOffset */ 1856 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1857 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1858 /* hucUKernelHdrInfoRegOffset */ 1859 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1860 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1861 /* hucStatus2RegOffset */ 1862 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1863 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1864 break; 1865 1866 default: 1867 break; 1868 } 1869 } 1870 1871 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1872 { 1873 struct i915_wa_list *w = &engine->whitelist; 1874 1875 allow_read_ctx_timestamp(engine); 1876 1877 switch (engine->class) { 1878 case RENDER_CLASS: 1879 /* 1880 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1881 * Wa_1408556865:tgl 1882 * 1883 * This covers 4 registers which are next to one another : 1884 * - PS_INVOCATION_COUNT 1885 * - PS_INVOCATION_COUNT_UDW 1886 * - PS_DEPTH_COUNT 1887 * - PS_DEPTH_COUNT_UDW 1888 */ 1889 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1890 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1891 RING_FORCE_TO_NONPRIV_RANGE_4); 1892 1893 /* 1894 * Wa_1808121037:tgl 1895 * Wa_14012131227:dg1 1896 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 1897 */ 1898 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1899 1900 /* Wa_1806527549:tgl */ 1901 whitelist_reg(w, HIZ_CHICKEN); 1902 break; 1903 default: 1904 break; 1905 } 1906 } 1907 1908 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1909 { 1910 struct i915_wa_list *w = &engine->whitelist; 1911 1912 tgl_whitelist_build(engine); 1913 1914 /* GEN:BUG:1409280441:dg1 */ 1915 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 1916 (engine->class == RENDER_CLASS || 1917 engine->class == COPY_ENGINE_CLASS)) 1918 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1919 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1920 } 1921 1922 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 1923 { 1924 allow_read_ctx_timestamp(engine); 1925 } 1926 1927 static void dg2_whitelist_build(struct intel_engine_cs *engine) 1928 { 1929 struct i915_wa_list *w = &engine->whitelist; 1930 1931 allow_read_ctx_timestamp(engine); 1932 1933 switch (engine->class) { 1934 case RENDER_CLASS: 1935 /* 1936 * Wa_1507100340:dg2_g10 1937 * 1938 * This covers 4 registers which are next to one another : 1939 * - PS_INVOCATION_COUNT 1940 * - PS_INVOCATION_COUNT_UDW 1941 * - PS_DEPTH_COUNT 1942 * - PS_DEPTH_COUNT_UDW 1943 */ 1944 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1945 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1946 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1947 RING_FORCE_TO_NONPRIV_RANGE_4); 1948 1949 break; 1950 case COMPUTE_CLASS: 1951 /* Wa_16011157294:dg2_g10 */ 1952 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1953 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1954 break; 1955 default: 1956 break; 1957 } 1958 } 1959 1960 static void blacklist_trtt(struct intel_engine_cs *engine) 1961 { 1962 struct i915_wa_list *w = &engine->whitelist; 1963 1964 /* 1965 * Prevent read/write access to [0x4400, 0x4600) which covers 1966 * the TRTT range across all engines. Note that normally userspace 1967 * cannot access the other engines' trtt control, but for simplicity 1968 * we cover the entire range on each engine. 1969 */ 1970 whitelist_reg_ext(w, _MMIO(0x4400), 1971 RING_FORCE_TO_NONPRIV_DENY | 1972 RING_FORCE_TO_NONPRIV_RANGE_64); 1973 whitelist_reg_ext(w, _MMIO(0x4500), 1974 RING_FORCE_TO_NONPRIV_DENY | 1975 RING_FORCE_TO_NONPRIV_RANGE_64); 1976 } 1977 1978 static void pvc_whitelist_build(struct intel_engine_cs *engine) 1979 { 1980 allow_read_ctx_timestamp(engine); 1981 1982 /* Wa_16014440446:pvc */ 1983 blacklist_trtt(engine); 1984 } 1985 1986 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1987 { 1988 struct drm_i915_private *i915 = engine->i915; 1989 struct i915_wa_list *w = &engine->whitelist; 1990 1991 wa_init_start(w, "whitelist", engine->name); 1992 1993 if (IS_PONTEVECCHIO(i915)) 1994 pvc_whitelist_build(engine); 1995 else if (IS_DG2(i915)) 1996 dg2_whitelist_build(engine); 1997 else if (IS_XEHPSDV(i915)) 1998 xehpsdv_whitelist_build(engine); 1999 else if (IS_DG1(i915)) 2000 dg1_whitelist_build(engine); 2001 else if (GRAPHICS_VER(i915) == 12) 2002 tgl_whitelist_build(engine); 2003 else if (GRAPHICS_VER(i915) == 11) 2004 icl_whitelist_build(engine); 2005 else if (IS_COMETLAKE(i915)) 2006 cml_whitelist_build(engine); 2007 else if (IS_COFFEELAKE(i915)) 2008 cfl_whitelist_build(engine); 2009 else if (IS_GEMINILAKE(i915)) 2010 glk_whitelist_build(engine); 2011 else if (IS_KABYLAKE(i915)) 2012 kbl_whitelist_build(engine); 2013 else if (IS_BROXTON(i915)) 2014 bxt_whitelist_build(engine); 2015 else if (IS_SKYLAKE(i915)) 2016 skl_whitelist_build(engine); 2017 else if (GRAPHICS_VER(i915) <= 8) 2018 ; 2019 else 2020 MISSING_CASE(GRAPHICS_VER(i915)); 2021 2022 wa_init_finish(w); 2023 } 2024 2025 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2026 { 2027 const struct i915_wa_list *wal = &engine->whitelist; 2028 struct intel_uncore *uncore = engine->uncore; 2029 const u32 base = engine->mmio_base; 2030 struct i915_wa *wa; 2031 unsigned int i; 2032 2033 if (!wal->count) 2034 return; 2035 2036 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2037 intel_uncore_write(uncore, 2038 RING_FORCE_TO_NONPRIV(base, i), 2039 i915_mmio_reg_offset(wa->reg)); 2040 2041 /* And clear the rest just in case of garbage */ 2042 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2043 intel_uncore_write(uncore, 2044 RING_FORCE_TO_NONPRIV(base, i), 2045 i915_mmio_reg_offset(RING_NOPID(base))); 2046 } 2047 2048 /* 2049 * engine_fake_wa_init(), a place holder to program the registers 2050 * which are not part of an official workaround defined by the 2051 * hardware team. 2052 * Adding programming of those register inside workaround will 2053 * allow utilizing wa framework to proper application and verification. 2054 */ 2055 static void 2056 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2057 { 2058 u8 mocs_w, mocs_r; 2059 2060 /* 2061 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2062 * by the command streamer when executing commands that don't have 2063 * a way to explicitly specify a MOCS setting. The default should 2064 * usually reference whichever MOCS entry corresponds to uncached 2065 * behavior, although use of a WB cached entry is recommended by the 2066 * spec in certain circumstances on specific platforms. 2067 */ 2068 if (GRAPHICS_VER(engine->i915) >= 12) { 2069 mocs_r = engine->gt->mocs.uc_index; 2070 mocs_w = engine->gt->mocs.uc_index; 2071 2072 if (HAS_L3_CCS_READ(engine->i915) && 2073 engine->class == COMPUTE_CLASS) { 2074 mocs_r = engine->gt->mocs.wb_index; 2075 2076 /* 2077 * Even on the few platforms where MOCS 0 is a 2078 * legitimate table entry, it's never the correct 2079 * setting to use here; we can assume the MOCS init 2080 * just forgot to initialize wb_index. 2081 */ 2082 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2083 } 2084 2085 wa_masked_field_set(wal, 2086 RING_CMD_CCTL(engine->mmio_base), 2087 CMD_CCTL_MOCS_MASK, 2088 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2089 } 2090 } 2091 2092 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2093 { 2094 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2095 GEN_DSS_PER_GSLICE; 2096 } 2097 2098 static void 2099 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2100 { 2101 struct drm_i915_private *i915 = engine->i915; 2102 2103 if (IS_DG2(i915)) { 2104 /* Wa_1509235366:dg2 */ 2105 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2106 GLOBAL_INVALIDATION_MODE); 2107 } 2108 2109 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2110 /* Wa_14013392000:dg2_g11 */ 2111 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2112 2113 /* Wa_16011620976:dg2_g11 */ 2114 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2115 } 2116 2117 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2118 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2119 /* Wa_1509727124:dg2 */ 2120 wa_masked_en(wal, GEN10_SAMPLER_MODE, 2121 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2122 } 2123 2124 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2125 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2126 /* Wa_14012419201:dg2 */ 2127 wa_masked_en(wal, GEN9_ROW_CHICKEN4, 2128 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2129 } 2130 2131 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2132 IS_DG2_G11(i915)) { 2133 /* 2134 * Wa_22012826095:dg2 2135 * Wa_22013059131:dg2 2136 */ 2137 wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2138 MAXREQS_PER_BANK, 2139 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2140 2141 /* Wa_22013059131:dg2 */ 2142 wa_write_or(wal, LSC_CHICKEN_BIT_0, 2143 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2144 } 2145 2146 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2147 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2148 needs_wa_1308578152(engine)) { 2149 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2150 GEN12_REPLAY_MODE_GRANULARITY); 2151 } 2152 2153 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2154 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2155 /* Wa_22013037850:dg2 */ 2156 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2157 DISABLE_128B_EVICTION_COMMAND_UDW); 2158 2159 /* Wa_22012856258:dg2 */ 2160 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2161 GEN12_DISABLE_READ_SUPPRESSION); 2162 2163 /* 2164 * Wa_22010960976:dg2 2165 * Wa_14013347512:dg2 2166 */ 2167 wa_masked_dis(wal, GEN12_HDC_CHICKEN0, 2168 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2169 } 2170 2171 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2172 /* 2173 * Wa_1608949956:dg2_g10 2174 * Wa_14010198302:dg2_g10 2175 */ 2176 wa_masked_en(wal, GEN8_ROW_CHICKEN, 2177 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2178 2179 /* 2180 * Wa_14010918519:dg2_g10 2181 * 2182 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2183 * so ignoring verification. 2184 */ 2185 wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2186 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2187 0, false); 2188 } 2189 2190 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2191 /* Wa_22010430635:dg2 */ 2192 wa_masked_en(wal, 2193 GEN9_ROW_CHICKEN4, 2194 GEN12_DISABLE_GRF_CLEAR); 2195 2196 /* Wa_14010648519:dg2 */ 2197 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2198 } 2199 2200 /* Wa_14013202645:dg2 */ 2201 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2202 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2203 wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2204 2205 /* Wa_22012532006:dg2 */ 2206 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2207 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2208 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2209 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2210 2211 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2212 /* Wa_14010680813:dg2_g10 */ 2213 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2214 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2215 } 2216 2217 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2218 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2219 /* Wa_14012362059:dg2 */ 2220 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2221 } 2222 2223 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2224 IS_DG2_G10(i915)) { 2225 /* Wa_22014600077:dg2 */ 2226 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 2227 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2228 0 /* Wa_14012342262 :write-only reg, so skip 2229 verification */, 2230 true); 2231 } 2232 2233 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2234 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2235 /* 2236 * Wa_1607138336:tgl[a0],dg1[a0] 2237 * Wa_1607063988:tgl[a0],dg1[a0] 2238 */ 2239 wa_write_or(wal, 2240 GEN9_CTX_PREEMPT_REG, 2241 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2242 } 2243 2244 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2245 /* 2246 * Wa_1606679103:tgl 2247 * (see also Wa_1606682166:icl) 2248 */ 2249 wa_write_or(wal, 2250 GEN7_SARCHKMD, 2251 GEN7_DISABLE_SAMPLER_PREFETCH); 2252 } 2253 2254 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2255 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2256 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2257 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2258 2259 /* 2260 * Wa_1407928979:tgl A* 2261 * Wa_18011464164:tgl[B0+],dg1[B0+] 2262 * Wa_22010931296:tgl[B0+],dg1[B0+] 2263 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2264 */ 2265 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2266 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2267 } 2268 2269 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2270 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2271 /* 2272 * Wa_1606700617:tgl,dg1,adl-p 2273 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2274 * Wa_14010826681:tgl,dg1,rkl,adl-p 2275 * Wa_18019627453:dg2 2276 */ 2277 wa_masked_en(wal, 2278 GEN9_CS_DEBUG_MODE1, 2279 FF_DOP_CLOCK_GATE_DISABLE); 2280 } 2281 2282 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2283 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2284 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2285 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2286 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2287 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2288 2289 /* 2290 * Wa_1409085225:tgl 2291 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2292 */ 2293 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2294 } 2295 2296 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2297 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2298 /* 2299 * Wa_1607030317:tgl 2300 * Wa_1607186500:tgl 2301 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2302 * 2303 * On TGL and RKL there are multiple entries for this WA in the 2304 * BSpec; some indicate this is an A0-only WA, others indicate 2305 * it applies to all steppings so we trust the "all steppings." 2306 * For DG1 this only applies to A0. 2307 */ 2308 wa_masked_en(wal, 2309 RING_PSMI_CTL(RENDER_RING_BASE), 2310 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2311 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2312 } 2313 2314 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2315 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2316 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2317 wa_masked_en(wal, 2318 GEN10_SAMPLER_MODE, 2319 ENABLE_SMALLPL); 2320 } 2321 2322 if (GRAPHICS_VER(i915) == 11) { 2323 /* This is not an Wa. Enable for better image quality */ 2324 wa_masked_en(wal, 2325 _3D_CHICKEN3, 2326 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2327 2328 /* 2329 * Wa_1405543622:icl 2330 * Formerly known as WaGAPZPriorityScheme 2331 */ 2332 wa_write_or(wal, 2333 GEN8_GARBCNTL, 2334 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2335 2336 /* 2337 * Wa_1604223664:icl 2338 * Formerly known as WaL3BankAddressHashing 2339 */ 2340 wa_write_clr_set(wal, 2341 GEN8_GARBCNTL, 2342 GEN11_HASH_CTRL_EXCL_MASK, 2343 GEN11_HASH_CTRL_EXCL_BIT0); 2344 wa_write_clr_set(wal, 2345 GEN11_GLBLINVL, 2346 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2347 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2348 2349 /* 2350 * Wa_1405733216:icl 2351 * Formerly known as WaDisableCleanEvicts 2352 */ 2353 wa_write_or(wal, 2354 GEN8_L3SQCREG4, 2355 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2356 2357 /* Wa_1606682166:icl */ 2358 wa_write_or(wal, 2359 GEN7_SARCHKMD, 2360 GEN7_DISABLE_SAMPLER_PREFETCH); 2361 2362 /* Wa_1409178092:icl */ 2363 wa_write_clr_set(wal, 2364 GEN11_SCRATCH2, 2365 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2366 0); 2367 2368 /* WaEnable32PlaneMode:icl */ 2369 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2370 GEN11_ENABLE_32_PLANE_MODE); 2371 2372 /* 2373 * Wa_1408615072:icl,ehl (vsunit) 2374 * Wa_1407596294:icl,ehl (hsunit) 2375 */ 2376 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2377 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2378 2379 /* 2380 * Wa_1408767742:icl[a2..forever],ehl[all] 2381 * Wa_1605460711:icl[a0..c0] 2382 */ 2383 wa_write_or(wal, 2384 GEN7_FF_THREAD_MODE, 2385 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2386 2387 /* Wa_22010271021 */ 2388 wa_masked_en(wal, 2389 GEN9_CS_DEBUG_MODE1, 2390 FF_DOP_CLOCK_GATE_DISABLE); 2391 } 2392 2393 if (HAS_PERCTX_PREEMPT_CTRL(i915)) { 2394 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 2395 wa_masked_en(wal, 2396 GEN7_FF_SLICE_CS_CHICKEN1, 2397 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2398 } 2399 2400 if (IS_SKYLAKE(i915) || 2401 IS_KABYLAKE(i915) || 2402 IS_COFFEELAKE(i915) || 2403 IS_COMETLAKE(i915)) { 2404 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2405 wa_write_or(wal, 2406 GEN8_GARBCNTL, 2407 GEN9_GAPS_TSV_CREDIT_DISABLE); 2408 } 2409 2410 if (IS_BROXTON(i915)) { 2411 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2412 wa_masked_en(wal, 2413 FF_SLICE_CS_CHICKEN2, 2414 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2415 } 2416 2417 if (GRAPHICS_VER(i915) == 9) { 2418 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2419 wa_masked_en(wal, 2420 GEN9_CSFE_CHICKEN1_RCS, 2421 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2422 2423 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2424 wa_write_or(wal, 2425 BDW_SCRATCH1, 2426 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2427 2428 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2429 if (IS_GEN9_LP(i915)) 2430 wa_write_clr_set(wal, 2431 GEN8_L3SQCREG1, 2432 L3_PRIO_CREDITS_MASK, 2433 L3_GENERAL_PRIO_CREDITS(62) | 2434 L3_HIGH_PRIO_CREDITS(2)); 2435 2436 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2437 wa_write_or(wal, 2438 GEN8_L3SQCREG4, 2439 GEN8_LQSC_FLUSH_COHERENT_LINES); 2440 2441 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2442 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2443 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2444 wa_write_clr_set(wal, GEN8_L3SQCREG4, 2445 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2446 wa_write_clr_set(wal, GEN9_SCRATCH1, 2447 EVICTION_PERF_FIX_ENABLE, 0); 2448 } 2449 2450 if (IS_HASWELL(i915)) { 2451 /* WaSampleCChickenBitEnable:hsw */ 2452 wa_masked_en(wal, 2453 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2454 2455 wa_masked_dis(wal, 2456 CACHE_MODE_0_GEN7, 2457 /* enable HiZ Raw Stall Optimization */ 2458 HIZ_RAW_STALL_OPT_DISABLE); 2459 } 2460 2461 if (IS_VALLEYVIEW(i915)) { 2462 /* WaDisableEarlyCull:vlv */ 2463 wa_masked_en(wal, 2464 _3D_CHICKEN3, 2465 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2466 2467 /* 2468 * WaVSThreadDispatchOverride:ivb,vlv 2469 * 2470 * This actually overrides the dispatch 2471 * mode for all thread types. 2472 */ 2473 wa_write_clr_set(wal, 2474 GEN7_FF_THREAD_MODE, 2475 GEN7_FF_SCHED_MASK, 2476 GEN7_FF_TS_SCHED_HW | 2477 GEN7_FF_VS_SCHED_HW | 2478 GEN7_FF_DS_SCHED_HW); 2479 2480 /* WaPsdDispatchEnable:vlv */ 2481 /* WaDisablePSDDualDispatchEnable:vlv */ 2482 wa_masked_en(wal, 2483 GEN7_HALF_SLICE_CHICKEN1, 2484 GEN7_MAX_PS_THREAD_DEP | 2485 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2486 } 2487 2488 if (IS_IVYBRIDGE(i915)) { 2489 /* WaDisableEarlyCull:ivb */ 2490 wa_masked_en(wal, 2491 _3D_CHICKEN3, 2492 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2493 2494 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2495 /* enable HiZ Raw Stall Optimization */ 2496 wa_masked_dis(wal, 2497 CACHE_MODE_0_GEN7, 2498 HIZ_RAW_STALL_OPT_DISABLE); 2499 } 2500 2501 /* 2502 * WaVSThreadDispatchOverride:ivb,vlv 2503 * 2504 * This actually overrides the dispatch 2505 * mode for all thread types. 2506 */ 2507 wa_write_clr_set(wal, 2508 GEN7_FF_THREAD_MODE, 2509 GEN7_FF_SCHED_MASK, 2510 GEN7_FF_TS_SCHED_HW | 2511 GEN7_FF_VS_SCHED_HW | 2512 GEN7_FF_DS_SCHED_HW); 2513 2514 /* WaDisablePSDDualDispatchEnable:ivb */ 2515 if (IS_IVB_GT1(i915)) 2516 wa_masked_en(wal, 2517 GEN7_HALF_SLICE_CHICKEN1, 2518 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2519 } 2520 2521 if (GRAPHICS_VER(i915) == 7) { 2522 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2523 wa_masked_en(wal, 2524 RING_MODE_GEN7(RENDER_RING_BASE), 2525 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2526 2527 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2528 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2529 2530 /* 2531 * BSpec says this must be set, even though 2532 * WaDisable4x2SubspanOptimization:ivb,hsw 2533 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2534 */ 2535 wa_masked_en(wal, 2536 CACHE_MODE_1, 2537 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2538 2539 /* 2540 * BSpec recommends 8x4 when MSAA is used, 2541 * however in practice 16x4 seems fastest. 2542 * 2543 * Note that PS/WM thread counts depend on the WIZ hashing 2544 * disable bit, which we don't touch here, but it's good 2545 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2546 */ 2547 wa_masked_field_set(wal, 2548 GEN7_GT_MODE, 2549 GEN6_WIZ_HASHING_MASK, 2550 GEN6_WIZ_HASHING_16x4); 2551 } 2552 2553 if (IS_GRAPHICS_VER(i915, 6, 7)) 2554 /* 2555 * We need to disable the AsyncFlip performance optimisations in 2556 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2557 * already be programmed to '1' on all products. 2558 * 2559 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2560 */ 2561 wa_masked_en(wal, 2562 RING_MI_MODE(RENDER_RING_BASE), 2563 ASYNC_FLIP_PERF_DISABLE); 2564 2565 if (GRAPHICS_VER(i915) == 6) { 2566 /* 2567 * Required for the hardware to program scanline values for 2568 * waiting 2569 * WaEnableFlushTlbInvalidationMode:snb 2570 */ 2571 wa_masked_en(wal, 2572 GFX_MODE, 2573 GFX_TLB_INVALIDATE_EXPLICIT); 2574 2575 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2576 wa_masked_en(wal, 2577 _3D_CHICKEN, 2578 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2579 2580 wa_masked_en(wal, 2581 _3D_CHICKEN3, 2582 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2583 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2584 /* 2585 * Bspec says: 2586 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2587 * to normal and 3DSTATE_SF number of SF output attributes 2588 * is more than 16." 2589 */ 2590 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2591 2592 /* 2593 * BSpec recommends 8x4 when MSAA is used, 2594 * however in practice 16x4 seems fastest. 2595 * 2596 * Note that PS/WM thread counts depend on the WIZ hashing 2597 * disable bit, which we don't touch here, but it's good 2598 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2599 */ 2600 wa_masked_field_set(wal, 2601 GEN6_GT_MODE, 2602 GEN6_WIZ_HASHING_MASK, 2603 GEN6_WIZ_HASHING_16x4); 2604 2605 /* WaDisable_RenderCache_OperationalFlush:snb */ 2606 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2607 2608 /* 2609 * From the Sandybridge PRM, volume 1 part 3, page 24: 2610 * "If this bit is set, STCunit will have LRA as replacement 2611 * policy. [...] This bit must be reset. LRA replacement 2612 * policy is not supported." 2613 */ 2614 wa_masked_dis(wal, 2615 CACHE_MODE_0, 2616 CM0_STC_EVICT_DISABLE_LRA_SNB); 2617 } 2618 2619 if (IS_GRAPHICS_VER(i915, 4, 6)) 2620 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2621 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2622 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2623 /* XXX bit doesn't stick on Broadwater */ 2624 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2625 2626 if (GRAPHICS_VER(i915) == 4) 2627 /* 2628 * Disable CONSTANT_BUFFER before it is loaded from the context 2629 * image. For as it is loaded, it is executed and the stored 2630 * address may no longer be valid, leading to a GPU hang. 2631 * 2632 * This imposes the requirement that userspace reload their 2633 * CONSTANT_BUFFER on every batch, fortunately a requirement 2634 * they are already accustomed to from before contexts were 2635 * enabled. 2636 */ 2637 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2638 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2639 0 /* XXX bit doesn't stick on Broadwater */, 2640 true); 2641 } 2642 2643 static void 2644 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2645 { 2646 struct drm_i915_private *i915 = engine->i915; 2647 2648 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2649 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2650 wa_write(wal, 2651 RING_SEMA_WAIT_POLL(engine->mmio_base), 2652 1); 2653 } 2654 } 2655 2656 static void 2657 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2658 { 2659 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2660 /* Wa_14014999345:pvc */ 2661 wa_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2662 } 2663 } 2664 2665 /* 2666 * The bspec performance guide has recommended MMIO tuning settings. These 2667 * aren't truly "workarounds" but we want to program them with the same 2668 * workaround infrastructure to ensure that they're automatically added to 2669 * the GuC save/restore lists, re-applied at the right times, and checked for 2670 * any conflicting programming requested by real workarounds. 2671 * 2672 * Programming settings should be added here only if their registers are not 2673 * part of an engine's register state context. If a register is part of a 2674 * context, then any tuning settings should be programmed in an appropriate 2675 * function invoked by __intel_engine_init_ctx_wa(). 2676 */ 2677 static void 2678 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2679 struct i915_wa_list *wal) 2680 { 2681 if (IS_PONTEVECCHIO(i915)) { 2682 wa_write(wal, XEHPC_L3SCRUB, 2683 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2684 } 2685 2686 if (IS_DG2(i915)) { 2687 wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2688 wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2689 wa_write_clr_set(wal, DRAW_WATERMARK, VERT_WM_VAL, 2690 REG_FIELD_PREP(VERT_WM_VAL, 0x3FF)); 2691 2692 /* 2693 * This is also listed as Wa_22012654132 for certain DG2 2694 * steppings, but the tuning setting programming is a superset 2695 * since it applies to all DG2 variants and steppings. 2696 * 2697 * Note that register 0xE420 is write-only and cannot be read 2698 * back for verification on DG2 (due to Wa_14012342262), so 2699 * we need to explicitly skip the readback. 2700 */ 2701 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 2702 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2703 0 /* write-only, so skip validation */, 2704 true); 2705 } 2706 } 2707 2708 /* 2709 * The workarounds in this function apply to shared registers in 2710 * the general render reset domain that aren't tied to a 2711 * specific engine. Since all render+compute engines get reset 2712 * together, and the contents of these registers are lost during 2713 * the shared render domain reset, we'll define such workarounds 2714 * here and then add them to just a single RCS or CCS engine's 2715 * workaround list (whichever engine has the XXXX flag). 2716 */ 2717 static void 2718 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2719 { 2720 struct drm_i915_private *i915 = engine->i915; 2721 2722 add_render_compute_tuning_settings(i915, wal); 2723 2724 if (IS_PONTEVECCHIO(i915)) { 2725 /* Wa_16016694945 */ 2726 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 2727 } 2728 2729 if (IS_XEHPSDV(i915)) { 2730 /* Wa_1409954639 */ 2731 wa_masked_en(wal, 2732 GEN8_ROW_CHICKEN, 2733 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2734 2735 /* Wa_1607196519 */ 2736 wa_masked_en(wal, 2737 GEN9_ROW_CHICKEN4, 2738 GEN12_DISABLE_GRF_CLEAR); 2739 2740 /* Wa_14010670810:xehpsdv */ 2741 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2742 2743 /* Wa_14010449647:xehpsdv */ 2744 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 2745 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2746 2747 /* Wa_18011725039:xehpsdv */ 2748 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2749 wa_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2750 wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2751 } 2752 2753 /* Wa_14012362059:xehpsdv */ 2754 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2755 2756 /* Wa_14014368820:xehpsdv */ 2757 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2758 GLOBAL_INVALIDATION_MODE); 2759 } 2760 2761 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 2762 /* Wa_14015227452:dg2,pvc */ 2763 wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2764 2765 /* Wa_22014226127:dg2,pvc */ 2766 wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2767 2768 /* Wa_16015675438:dg2,pvc */ 2769 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2770 2771 /* Wa_18018781329:dg2,pvc */ 2772 wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2773 wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2774 wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2775 wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2776 } 2777 } 2778 2779 static void 2780 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2781 { 2782 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2783 return; 2784 2785 engine_fake_wa_init(engine, wal); 2786 2787 /* 2788 * These are common workarounds that just need to applied 2789 * to a single RCS/CCS engine's workaround list since 2790 * they're reset as part of the general render domain reset. 2791 */ 2792 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 2793 general_render_compute_wa_init(engine, wal); 2794 2795 if (engine->class == COMPUTE_CLASS) 2796 ccs_engine_wa_init(engine, wal); 2797 else if (engine->class == RENDER_CLASS) 2798 rcs_engine_wa_init(engine, wal); 2799 else 2800 xcs_engine_wa_init(engine, wal); 2801 } 2802 2803 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2804 { 2805 struct i915_wa_list *wal = &engine->wa_list; 2806 2807 if (GRAPHICS_VER(engine->i915) < 4) 2808 return; 2809 2810 wa_init_start(wal, "engine", engine->name); 2811 engine_init_workarounds(engine, wal); 2812 wa_init_finish(wal); 2813 } 2814 2815 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2816 { 2817 wa_list_apply(engine->gt, &engine->wa_list); 2818 } 2819 2820 static const struct i915_range mcr_ranges_gen8[] = { 2821 { .start = 0x5500, .end = 0x55ff }, 2822 { .start = 0x7000, .end = 0x7fff }, 2823 { .start = 0x9400, .end = 0x97ff }, 2824 { .start = 0xb000, .end = 0xb3ff }, 2825 { .start = 0xe000, .end = 0xe7ff }, 2826 {}, 2827 }; 2828 2829 static const struct i915_range mcr_ranges_gen12[] = { 2830 { .start = 0x8150, .end = 0x815f }, 2831 { .start = 0x9520, .end = 0x955f }, 2832 { .start = 0xb100, .end = 0xb3ff }, 2833 { .start = 0xde80, .end = 0xe8ff }, 2834 { .start = 0x24a00, .end = 0x24a7f }, 2835 {}, 2836 }; 2837 2838 static const struct i915_range mcr_ranges_xehp[] = { 2839 { .start = 0x4000, .end = 0x4aff }, 2840 { .start = 0x5200, .end = 0x52ff }, 2841 { .start = 0x5400, .end = 0x7fff }, 2842 { .start = 0x8140, .end = 0x815f }, 2843 { .start = 0x8c80, .end = 0x8dff }, 2844 { .start = 0x94d0, .end = 0x955f }, 2845 { .start = 0x9680, .end = 0x96ff }, 2846 { .start = 0xb000, .end = 0xb3ff }, 2847 { .start = 0xc800, .end = 0xcfff }, 2848 { .start = 0xd800, .end = 0xd8ff }, 2849 { .start = 0xdc00, .end = 0xffff }, 2850 { .start = 0x17000, .end = 0x17fff }, 2851 { .start = 0x24a00, .end = 0x24a7f }, 2852 {}, 2853 }; 2854 2855 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2856 { 2857 const struct i915_range *mcr_ranges; 2858 int i; 2859 2860 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2861 mcr_ranges = mcr_ranges_xehp; 2862 else if (GRAPHICS_VER(i915) >= 12) 2863 mcr_ranges = mcr_ranges_gen12; 2864 else if (GRAPHICS_VER(i915) >= 8) 2865 mcr_ranges = mcr_ranges_gen8; 2866 else 2867 return false; 2868 2869 /* 2870 * Registers in these ranges are affected by the MCR selector 2871 * which only controls CPU initiated MMIO. Routing does not 2872 * work for CS access so we cannot verify them on this path. 2873 */ 2874 for (i = 0; mcr_ranges[i].start; i++) 2875 if (offset >= mcr_ranges[i].start && 2876 offset <= mcr_ranges[i].end) 2877 return true; 2878 2879 return false; 2880 } 2881 2882 static int 2883 wa_list_srm(struct i915_request *rq, 2884 const struct i915_wa_list *wal, 2885 struct i915_vma *vma) 2886 { 2887 struct drm_i915_private *i915 = rq->engine->i915; 2888 unsigned int i, count = 0; 2889 const struct i915_wa *wa; 2890 u32 srm, *cs; 2891 2892 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2893 if (GRAPHICS_VER(i915) >= 8) 2894 srm++; 2895 2896 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2897 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2898 count++; 2899 } 2900 2901 cs = intel_ring_begin(rq, 4 * count); 2902 if (IS_ERR(cs)) 2903 return PTR_ERR(cs); 2904 2905 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2906 u32 offset = i915_mmio_reg_offset(wa->reg); 2907 2908 if (mcr_range(i915, offset)) 2909 continue; 2910 2911 *cs++ = srm; 2912 *cs++ = offset; 2913 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2914 *cs++ = 0; 2915 } 2916 intel_ring_advance(rq, cs); 2917 2918 return 0; 2919 } 2920 2921 static int engine_wa_list_verify(struct intel_context *ce, 2922 const struct i915_wa_list * const wal, 2923 const char *from) 2924 { 2925 const struct i915_wa *wa; 2926 struct i915_request *rq; 2927 struct i915_vma *vma; 2928 struct i915_gem_ww_ctx ww; 2929 unsigned int i; 2930 u32 *results; 2931 int err; 2932 2933 if (!wal->count) 2934 return 0; 2935 2936 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2937 wal->count * sizeof(u32)); 2938 if (IS_ERR(vma)) 2939 return PTR_ERR(vma); 2940 2941 intel_engine_pm_get(ce->engine); 2942 i915_gem_ww_ctx_init(&ww, false); 2943 retry: 2944 err = i915_gem_object_lock(vma->obj, &ww); 2945 if (err == 0) 2946 err = intel_context_pin_ww(ce, &ww); 2947 if (err) 2948 goto err_pm; 2949 2950 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2951 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2952 if (err) 2953 goto err_unpin; 2954 2955 rq = i915_request_create(ce); 2956 if (IS_ERR(rq)) { 2957 err = PTR_ERR(rq); 2958 goto err_vma; 2959 } 2960 2961 err = i915_request_await_object(rq, vma->obj, true); 2962 if (err == 0) 2963 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2964 if (err == 0) 2965 err = wa_list_srm(rq, wal, vma); 2966 2967 i915_request_get(rq); 2968 if (err) 2969 i915_request_set_error_once(rq, err); 2970 i915_request_add(rq); 2971 2972 if (err) 2973 goto err_rq; 2974 2975 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2976 err = -ETIME; 2977 goto err_rq; 2978 } 2979 2980 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2981 if (IS_ERR(results)) { 2982 err = PTR_ERR(results); 2983 goto err_rq; 2984 } 2985 2986 err = 0; 2987 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2988 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2989 continue; 2990 2991 if (!wa_verify(wa, results[i], wal->name, from)) 2992 err = -ENXIO; 2993 } 2994 2995 i915_gem_object_unpin_map(vma->obj); 2996 2997 err_rq: 2998 i915_request_put(rq); 2999 err_vma: 3000 i915_vma_unpin(vma); 3001 err_unpin: 3002 intel_context_unpin(ce); 3003 err_pm: 3004 if (err == -EDEADLK) { 3005 err = i915_gem_ww_ctx_backoff(&ww); 3006 if (!err) 3007 goto retry; 3008 } 3009 i915_gem_ww_ctx_fini(&ww); 3010 intel_engine_pm_put(ce->engine); 3011 i915_vma_put(vma); 3012 return err; 3013 } 3014 3015 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3016 const char *from) 3017 { 3018 return engine_wa_list_verify(engine->kernel_context, 3019 &engine->wa_list, 3020 from); 3021 } 3022 3023 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3024 #include "selftest_workarounds.c" 3025 #endif 3026