1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * Hardware workarounds are register programming documented to be executed in 22 * the driver that fall outside of the normal programming sequences for a 23 * platform. There are some basic categories of workarounds, depending on 24 * how/when they are applied: 25 * 26 * - Context workarounds: workarounds that touch registers that are 27 * saved/restored to/from the HW context image. The list is emitted (via Load 28 * Register Immediate commands) once when initializing the device and saved in 29 * the default context. That default context is then used on every context 30 * creation to have a "primed golden context", i.e. a context image that 31 * already contains the changes needed to all the registers. 32 * 33 * Context workarounds should be implemented in the \*_ctx_workarounds_init() 34 * variants respective to the targeted platforms. 35 * 36 * - Engine workarounds: the list of these WAs is applied whenever the specific 37 * engine is reset. It's also possible that a set of engine classes share a 38 * common power domain and they are reset together. This happens on some 39 * platforms with render and compute engines. In this case (at least) one of 40 * them need to keeep the workaround programming: the approach taken in the 41 * driver is to tie those workarounds to the first compute/render engine that 42 * is registered. When executing with GuC submission, engine resets are 43 * outside of kernel driver control, hence the list of registers involved in 44 * written once, on engine initialization, and then passed to GuC, that 45 * saves/restores their values before/after the reset takes place. See 46 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 47 * 48 * Workarounds for registers specific to RCS and CCS should be implemented in 49 * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for 50 * registers belonging to BCS, VCS or VECS should be implemented in 51 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific 52 * engine's MMIO range but that are part of of the common RCS/CCS reset domain 53 * should be implemented in general_render_compute_wa_init(). 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * GT workarounds should be implemented in the \*_gt_workarounds_init() 59 * variants respective to the targeted platforms. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * Register whitelisting should be done in the \*_whitelist_build() variants 68 * respective to the targeted platforms. 69 * 70 * - Workaround batchbuffers: buffers that get executed automatically by the 71 * hardware on every HW context restore. These buffers are created and 72 * programmed in the default context so the hardware always go through those 73 * programming sequences when switching contexts. The support for workaround 74 * batchbuffers is enabled these hardware mechanisms: 75 * 76 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 77 * context, pointing the hardware to jump to that location when that offset 78 * is reached in the context restore. Workaround batchbuffer in the driver 79 * currently uses this mechanism for all platforms. 80 * 81 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 82 * pointing the hardware to a buffer to continue executing after the 83 * engine registers are restored in a context restore sequence. This is 84 * currently not used in the driver. 85 * 86 * - Other: There are WAs that, due to their nature, cannot be applied from a 87 * central place. Those are peppered around the rest of the code, as needed. 88 * Workarounds related to the display IP are the main example. 89 * 90 * .. [1] Technically, some registers are powercontext saved & restored, so they 91 * survive a suspend/resume. In practice, writing them again is not too 92 * costly and simplifies things, so it's the approach taken in the driver. 93 */ 94 95 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 96 const char *name, const char *engine_name) 97 { 98 wal->gt = gt; 99 wal->name = name; 100 wal->engine_name = engine_name; 101 } 102 103 #define WA_LIST_CHUNK (1 << 4) 104 105 static void wa_init_finish(struct i915_wa_list *wal) 106 { 107 /* Trim unused entries. */ 108 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 109 struct i915_wa *list = kmemdup(wal->list, 110 wal->count * sizeof(*list), 111 GFP_KERNEL); 112 113 if (list) { 114 kfree(wal->list); 115 wal->list = list; 116 } 117 } 118 119 if (!wal->count) 120 return; 121 122 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 123 wal->wa_count, wal->name, wal->engine_name); 124 } 125 126 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 127 { 128 unsigned int addr = i915_mmio_reg_offset(wa->reg); 129 struct drm_i915_private *i915 = wal->gt->i915; 130 unsigned int start = 0, end = wal->count; 131 const unsigned int grow = WA_LIST_CHUNK; 132 struct i915_wa *wa_; 133 134 GEM_BUG_ON(!is_power_of_2(grow)); 135 136 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 137 struct i915_wa *list; 138 139 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 140 GFP_KERNEL); 141 if (!list) { 142 drm_err(&i915->drm, "No space for workaround init!\n"); 143 return; 144 } 145 146 if (wal->list) { 147 memcpy(list, wal->list, sizeof(*wa) * wal->count); 148 kfree(wal->list); 149 } 150 151 wal->list = list; 152 } 153 154 while (start < end) { 155 unsigned int mid = start + (end - start) / 2; 156 157 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 158 start = mid + 1; 159 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 160 end = mid; 161 } else { 162 wa_ = &wal->list[mid]; 163 164 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 165 drm_err(&i915->drm, 166 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 167 i915_mmio_reg_offset(wa_->reg), 168 wa_->clr, wa_->set); 169 170 wa_->set &= ~wa->clr; 171 } 172 173 wal->wa_count++; 174 wa_->set |= wa->set; 175 wa_->clr |= wa->clr; 176 wa_->read |= wa->read; 177 return; 178 } 179 } 180 181 wal->wa_count++; 182 wa_ = &wal->list[wal->count++]; 183 *wa_ = *wa; 184 185 while (wa_-- > wal->list) { 186 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 187 i915_mmio_reg_offset(wa_[1].reg)); 188 if (i915_mmio_reg_offset(wa_[1].reg) > 189 i915_mmio_reg_offset(wa_[0].reg)) 190 break; 191 192 swap(wa_[1], wa_[0]); 193 } 194 } 195 196 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 197 u32 clear, u32 set, u32 read_mask, bool masked_reg) 198 { 199 struct i915_wa wa = { 200 .reg = reg, 201 .clr = clear, 202 .set = set, 203 .read = read_mask, 204 .masked_reg = masked_reg, 205 }; 206 207 _wa_add(wal, &wa); 208 } 209 210 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 211 u32 clear, u32 set, u32 read_mask, bool masked_reg) 212 { 213 struct i915_wa wa = { 214 .mcr_reg = reg, 215 .clr = clear, 216 .set = set, 217 .read = read_mask, 218 .masked_reg = masked_reg, 219 .is_mcr = 1, 220 }; 221 222 _wa_add(wal, &wa); 223 } 224 225 static void 226 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 227 { 228 wa_add(wal, reg, clear, set, clear, false); 229 } 230 231 static void 232 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 233 { 234 wa_mcr_add(wal, reg, clear, set, clear, false); 235 } 236 237 static void 238 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 239 { 240 wa_write_clr_set(wal, reg, ~0, set); 241 } 242 243 static void 244 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 245 { 246 wa_mcr_write_clr_set(wal, reg, ~0, set); 247 } 248 249 static void 250 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 251 { 252 wa_write_clr_set(wal, reg, set, set); 253 } 254 255 static void 256 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 257 { 258 wa_mcr_write_clr_set(wal, reg, set, set); 259 } 260 261 static void 262 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 263 { 264 wa_write_clr_set(wal, reg, clr, 0); 265 } 266 267 static void 268 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 269 { 270 wa_mcr_write_clr_set(wal, reg, clr, 0); 271 } 272 273 /* 274 * WA operations on "masked register". A masked register has the upper 16 bits 275 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 276 * portion of the register without a rmw: you simply write in the upper 16 bits 277 * the mask of bits you are going to modify. 278 * 279 * The wa_masked_* family of functions already does the necessary operations to 280 * calculate the mask based on the parameters passed, so user only has to 281 * provide the lower 16 bits of that register. 282 */ 283 284 static void 285 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 286 { 287 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 288 } 289 290 static void 291 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 292 { 293 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 294 } 295 296 static void 297 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 298 { 299 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 300 } 301 302 static void 303 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 304 { 305 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 306 } 307 308 static void 309 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 310 u32 mask, u32 val) 311 { 312 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 313 } 314 315 static void 316 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 317 u32 mask, u32 val) 318 { 319 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 320 } 321 322 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 323 struct i915_wa_list *wal) 324 { 325 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 326 } 327 328 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 329 struct i915_wa_list *wal) 330 { 331 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 332 } 333 334 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 335 struct i915_wa_list *wal) 336 { 337 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 338 339 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 340 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 341 342 /* WaDisablePartialInstShootdown:bdw,chv */ 343 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 344 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 345 346 /* Use Force Non-Coherent whenever executing a 3D context. This is a 347 * workaround for a possible hang in the unlikely event a TLB 348 * invalidation occurs during a PSD flush. 349 */ 350 /* WaForceEnableNonCoherent:bdw,chv */ 351 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 352 wa_masked_en(wal, HDC_CHICKEN0, 353 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 354 HDC_FORCE_NON_COHERENT); 355 356 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 357 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 358 * polygons in the same 8x4 pixel/sample area to be processed without 359 * stalling waiting for the earlier ones to write to Hierarchical Z 360 * buffer." 361 * 362 * This optimization is off by default for BDW and CHV; turn it on. 363 */ 364 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 365 366 /* Wa4x4STCOptimizationDisable:bdw,chv */ 367 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 368 369 /* 370 * BSpec recommends 8x4 when MSAA is used, 371 * however in practice 16x4 seems fastest. 372 * 373 * Note that PS/WM thread counts depend on the WIZ hashing 374 * disable bit, which we don't touch here, but it's good 375 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 376 */ 377 wa_masked_field_set(wal, GEN7_GT_MODE, 378 GEN6_WIZ_HASHING_MASK, 379 GEN6_WIZ_HASHING_16x4); 380 } 381 382 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 383 struct i915_wa_list *wal) 384 { 385 struct drm_i915_private *i915 = engine->i915; 386 387 gen8_ctx_workarounds_init(engine, wal); 388 389 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 390 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 391 392 /* WaDisableDopClockGating:bdw 393 * 394 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 395 * to disable EUTC clock gating. 396 */ 397 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 398 DOP_CLOCK_GATING_DISABLE); 399 400 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 401 GEN8_SAMPLER_POWER_BYPASS_DIS); 402 403 wa_masked_en(wal, HDC_CHICKEN0, 404 /* WaForceContextSaveRestoreNonCoherent:bdw */ 405 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 406 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 407 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 408 } 409 410 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 411 struct i915_wa_list *wal) 412 { 413 gen8_ctx_workarounds_init(engine, wal); 414 415 /* WaDisableThreadStallDopClockGating:chv */ 416 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 417 418 /* Improve HiZ throughput on CHV. */ 419 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 420 } 421 422 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 423 struct i915_wa_list *wal) 424 { 425 struct drm_i915_private *i915 = engine->i915; 426 427 if (HAS_LLC(i915)) { 428 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 429 * 430 * Must match Display Engine. See 431 * WaCompressedResourceDisplayNewHashMode. 432 */ 433 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 434 GEN9_PBE_COMPRESSED_HASH_SELECTION); 435 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 436 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 437 } 438 439 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 440 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 441 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 442 FLOW_CONTROL_ENABLE | 443 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 444 445 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 446 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 447 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 448 GEN9_ENABLE_YV12_BUGFIX | 449 GEN9_ENABLE_GPGPU_PREEMPTION); 450 451 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 452 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 453 wa_masked_en(wal, CACHE_MODE_1, 454 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 455 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 456 457 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 458 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 459 GEN9_CCS_TLB_PREFETCH_ENABLE); 460 461 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 462 wa_masked_en(wal, HDC_CHICKEN0, 463 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 464 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 465 466 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 467 * both tied to WaForceContextSaveRestoreNonCoherent 468 * in some hsds for skl. We keep the tie for all gen9. The 469 * documentation is a bit hazy and so we want to get common behaviour, 470 * even though there is no clear evidence we would need both on kbl/bxt. 471 * This area has been source of system hangs so we play it safe 472 * and mimic the skl regardless of what bspec says. 473 * 474 * Use Force Non-Coherent whenever executing a 3D context. This 475 * is a workaround for a possible hang in the unlikely event 476 * a TLB invalidation occurs during a PSD flush. 477 */ 478 479 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 480 wa_masked_en(wal, HDC_CHICKEN0, 481 HDC_FORCE_NON_COHERENT); 482 483 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 484 if (IS_SKYLAKE(i915) || 485 IS_KABYLAKE(i915) || 486 IS_COFFEELAKE(i915) || 487 IS_COMETLAKE(i915)) 488 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 489 GEN8_SAMPLER_POWER_BYPASS_DIS); 490 491 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 492 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 493 494 /* 495 * Supporting preemption with fine-granularity requires changes in the 496 * batch buffer programming. Since we can't break old userspace, we 497 * need to set our default preemption level to safe value. Userspace is 498 * still able to use more fine-grained preemption levels, since in 499 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 500 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 501 * not real HW workarounds, but merely a way to start using preemption 502 * while maintaining old contract with userspace. 503 */ 504 505 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 506 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 507 508 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 509 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 510 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 511 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 512 513 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 514 if (IS_GEN9_LP(i915)) 515 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 516 } 517 518 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 struct intel_gt *gt = engine->gt; 522 u8 vals[3] = { 0, 0, 0 }; 523 unsigned int i; 524 525 for (i = 0; i < 3; i++) { 526 u8 ss; 527 528 /* 529 * Only consider slices where one, and only one, subslice has 7 530 * EUs 531 */ 532 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 533 continue; 534 535 /* 536 * subslice_7eu[i] != 0 (because of the check above) and 537 * ss_max == 4 (maximum number of subslices possible per slice) 538 * 539 * -> 0 <= ss <= 3; 540 */ 541 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 542 vals[i] = 3 - ss; 543 } 544 545 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 546 return; 547 548 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 549 wa_masked_field_set(wal, GEN7_GT_MODE, 550 GEN9_IZ_HASHING_MASK(2) | 551 GEN9_IZ_HASHING_MASK(1) | 552 GEN9_IZ_HASHING_MASK(0), 553 GEN9_IZ_HASHING(2, vals[2]) | 554 GEN9_IZ_HASHING(1, vals[1]) | 555 GEN9_IZ_HASHING(0, vals[0])); 556 } 557 558 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 559 struct i915_wa_list *wal) 560 { 561 gen9_ctx_workarounds_init(engine, wal); 562 skl_tune_iz_hashing(engine, wal); 563 } 564 565 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 566 struct i915_wa_list *wal) 567 { 568 gen9_ctx_workarounds_init(engine, wal); 569 570 /* WaDisableThreadStallDopClockGating:bxt */ 571 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 572 STALL_DOP_GATING_DISABLE); 573 574 /* WaToEnableHwFixForPushConstHWBug:bxt */ 575 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 576 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 577 } 578 579 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 580 struct i915_wa_list *wal) 581 { 582 struct drm_i915_private *i915 = engine->i915; 583 584 gen9_ctx_workarounds_init(engine, wal); 585 586 /* WaToEnableHwFixForPushConstHWBug:kbl */ 587 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 588 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 589 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 590 591 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 592 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 593 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 594 } 595 596 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 597 struct i915_wa_list *wal) 598 { 599 gen9_ctx_workarounds_init(engine, wal); 600 601 /* WaToEnableHwFixForPushConstHWBug:glk */ 602 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 603 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 604 } 605 606 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 607 struct i915_wa_list *wal) 608 { 609 gen9_ctx_workarounds_init(engine, wal); 610 611 /* WaToEnableHwFixForPushConstHWBug:cfl */ 612 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 613 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 614 615 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 616 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 617 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 618 } 619 620 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 621 struct i915_wa_list *wal) 622 { 623 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 624 wa_write(wal, 625 GEN8_L3CNTLREG, 626 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 627 GEN8_ERRDETBCTRL); 628 629 /* WaForceEnableNonCoherent:icl 630 * This is not the same workaround as in early Gen9 platforms, where 631 * lacking this could cause system hangs, but coherency performance 632 * overhead is high and only a few compute workloads really need it 633 * (the register is whitelisted in hardware now, so UMDs can opt in 634 * for coherency if they have a good reason). 635 */ 636 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 637 638 /* WaEnableFloatBlendOptimization:icl */ 639 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 640 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 641 0 /* write-only, so skip validation */, 642 true); 643 644 /* WaDisableGPGPUMidThreadPreemption:icl */ 645 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 646 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 647 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 648 649 /* allow headerless messages for preemptible GPGPU context */ 650 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 651 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 652 653 /* Wa_1604278689:icl,ehl */ 654 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 655 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 656 0, /* write-only register; skip validation */ 657 0xFFFFFFFF); 658 659 /* Wa_1406306137:icl,ehl */ 660 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 661 } 662 663 /* 664 * These settings aren't actually workarounds, but general tuning settings that 665 * need to be programmed on dg2 platform. 666 */ 667 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 668 struct i915_wa_list *wal) 669 { 670 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 671 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 672 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 673 wa_mcr_add(wal, 674 XEHP_FF_MODE2, 675 FF_MODE2_TDS_TIMER_MASK, 676 FF_MODE2_TDS_TIMER_128, 677 0, false); 678 } 679 680 /* 681 * These settings aren't actually workarounds, but general tuning settings that 682 * need to be programmed on several platforms. 683 */ 684 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 685 struct i915_wa_list *wal) 686 { 687 /* 688 * Although some platforms refer to it as Wa_1604555607, we need to 689 * program it even on those that don't explicitly list that 690 * workaround. 691 * 692 * Note that the programming of this register is further modified 693 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 694 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 695 * value when read. The default value for this register is zero for all 696 * fields and there are no bit masks. So instead of doing a RMW we 697 * should just write TDS timer value. For the same reason read 698 * verification is ignored. 699 */ 700 wa_add(wal, 701 GEN12_FF_MODE2, 702 FF_MODE2_TDS_TIMER_MASK, 703 FF_MODE2_TDS_TIMER_128, 704 0, false); 705 } 706 707 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 708 struct i915_wa_list *wal) 709 { 710 struct drm_i915_private *i915 = engine->i915; 711 712 gen12_ctx_gt_tuning_init(engine, wal); 713 714 /* 715 * Wa_1409142259:tgl,dg1,adl-p 716 * Wa_1409347922:tgl,dg1,adl-p 717 * Wa_1409252684:tgl,dg1,adl-p 718 * Wa_1409217633:tgl,dg1,adl-p 719 * Wa_1409207793:tgl,dg1,adl-p 720 * Wa_1409178076:tgl,dg1,adl-p 721 * Wa_1408979724:tgl,dg1,adl-p 722 * Wa_14010443199:tgl,rkl,dg1,adl-p 723 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 724 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 725 */ 726 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 727 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 728 729 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 730 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 731 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 732 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 733 734 /* 735 * Wa_16011163337 736 * 737 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 738 * to Wa_1608008084. 739 */ 740 wa_add(wal, 741 GEN12_FF_MODE2, 742 FF_MODE2_GS_TIMER_MASK, 743 FF_MODE2_GS_TIMER_224, 744 0, false); 745 746 if (!IS_DG1(i915)) { 747 /* Wa_1806527549 */ 748 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 749 750 /* Wa_1606376872 */ 751 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); 752 } 753 } 754 755 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 756 struct i915_wa_list *wal) 757 { 758 gen12_ctx_workarounds_init(engine, wal); 759 760 /* Wa_1409044764 */ 761 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 762 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 763 764 /* Wa_22010493298 */ 765 wa_masked_en(wal, HIZ_CHICKEN, 766 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 767 } 768 769 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 770 struct i915_wa_list *wal) 771 { 772 dg2_ctx_gt_tuning_init(engine, wal); 773 774 /* Wa_16011186671:dg2_g11 */ 775 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 776 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 777 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 778 } 779 780 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 781 /* Wa_14010469329:dg2_g10 */ 782 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 783 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 784 785 /* 786 * Wa_22010465075:dg2_g10 787 * Wa_22010613112:dg2_g10 788 * Wa_14010698770:dg2_g10 789 */ 790 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 791 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 792 } 793 794 /* Wa_16013271637:dg2 */ 795 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 796 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 797 798 /* Wa_14014947963:dg2 */ 799 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 800 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 801 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 802 803 /* Wa_18018764978:dg2 */ 804 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || 805 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 806 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 807 808 /* Wa_15010599737:dg2 */ 809 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 810 811 /* Wa_18019271663:dg2 */ 812 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 813 } 814 815 static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine, 816 struct i915_wa_list *wal) 817 { 818 struct drm_i915_private *i915 = engine->i915; 819 820 dg2_ctx_gt_tuning_init(engine, wal); 821 822 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || 823 IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) 824 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); 825 } 826 827 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, 828 struct i915_wa_list *wal) 829 { 830 struct drm_i915_private *i915 = engine->i915; 831 832 mtl_ctx_gt_tuning_init(engine, wal); 833 834 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 835 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 836 /* Wa_14014947963 */ 837 wa_masked_field_set(wal, VF_PREEMPTION, 838 PREEMPTION_VERTEX_COUNT, 0x4000); 839 840 /* Wa_16013271637 */ 841 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 842 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 843 844 /* Wa_18019627453 */ 845 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); 846 847 /* Wa_18018764978 */ 848 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 849 } 850 851 /* Wa_18019271663 */ 852 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 853 } 854 855 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 856 struct i915_wa_list *wal) 857 { 858 /* 859 * This is a "fake" workaround defined by software to ensure we 860 * maintain reliable, backward-compatible behavior for userspace with 861 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 862 * 863 * The per-context setting of MI_MODE[12] determines whether the bits 864 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 865 * in the traditional manner or whether they should instead use a new 866 * tgl+ meaning that breaks backward compatibility, but allows nesting 867 * into 3rd-level batchbuffers. When this new capability was first 868 * added in TGL, it remained off by default unless a context 869 * intentionally opted in to the new behavior. However Xe_HPG now 870 * flips this on by default and requires that we explicitly opt out if 871 * we don't want the new behavior. 872 * 873 * From a SW perspective, we want to maintain the backward-compatible 874 * behavior for userspace, so we'll apply a fake workaround to set it 875 * back to the legacy behavior on platforms where the hardware default 876 * is to break compatibility. At the moment there is no Linux 877 * userspace that utilizes third-level batchbuffers, so this will avoid 878 * userspace from needing to make any changes. using the legacy 879 * meaning is the correct thing to do. If/when we have userspace 880 * consumers that want to utilize third-level batch nesting, we can 881 * provide a context parameter to allow them to opt-in. 882 */ 883 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 884 } 885 886 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 887 struct i915_wa_list *wal) 888 { 889 u8 mocs; 890 891 /* 892 * Some blitter commands do not have a field for MOCS, those 893 * commands will use MOCS index pointed by BLIT_CCTL. 894 * BLIT_CCTL registers are needed to be programmed to un-cached. 895 */ 896 if (engine->class == COPY_ENGINE_CLASS) { 897 mocs = engine->gt->mocs.uc_index; 898 wa_write_clr_set(wal, 899 BLIT_CCTL(engine->mmio_base), 900 BLIT_CCTL_MASK, 901 BLIT_CCTL_MOCS(mocs, mocs)); 902 } 903 } 904 905 /* 906 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 907 * defined by the hardware team, but it programming general context registers. 908 * Adding those context register programming in context workaround 909 * allow us to use the wa framework for proper application and validation. 910 */ 911 static void 912 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 913 struct i915_wa_list *wal) 914 { 915 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 916 fakewa_disable_nestedbb_mode(engine, wal); 917 918 gen12_ctx_gt_mocs_init(engine, wal); 919 } 920 921 static void 922 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 923 struct i915_wa_list *wal, 924 const char *name) 925 { 926 struct drm_i915_private *i915 = engine->i915; 927 928 wa_init_start(wal, engine->gt, name, engine->name); 929 930 /* Applies to all engines */ 931 /* 932 * Fake workarounds are not the actual workaround but 933 * programming of context registers using workaround framework. 934 */ 935 if (GRAPHICS_VER(i915) >= 12) 936 gen12_ctx_gt_fake_wa_init(engine, wal); 937 938 if (engine->class != RENDER_CLASS) 939 goto done; 940 941 if (IS_METEORLAKE(i915)) 942 mtl_ctx_workarounds_init(engine, wal); 943 else if (IS_PONTEVECCHIO(i915)) 944 ; /* noop; none at this time */ 945 else if (IS_DG2(i915)) 946 dg2_ctx_workarounds_init(engine, wal); 947 else if (IS_XEHPSDV(i915)) 948 ; /* noop; none at this time */ 949 else if (IS_DG1(i915)) 950 dg1_ctx_workarounds_init(engine, wal); 951 else if (GRAPHICS_VER(i915) == 12) 952 gen12_ctx_workarounds_init(engine, wal); 953 else if (GRAPHICS_VER(i915) == 11) 954 icl_ctx_workarounds_init(engine, wal); 955 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 956 cfl_ctx_workarounds_init(engine, wal); 957 else if (IS_GEMINILAKE(i915)) 958 glk_ctx_workarounds_init(engine, wal); 959 else if (IS_KABYLAKE(i915)) 960 kbl_ctx_workarounds_init(engine, wal); 961 else if (IS_BROXTON(i915)) 962 bxt_ctx_workarounds_init(engine, wal); 963 else if (IS_SKYLAKE(i915)) 964 skl_ctx_workarounds_init(engine, wal); 965 else if (IS_CHERRYVIEW(i915)) 966 chv_ctx_workarounds_init(engine, wal); 967 else if (IS_BROADWELL(i915)) 968 bdw_ctx_workarounds_init(engine, wal); 969 else if (GRAPHICS_VER(i915) == 7) 970 gen7_ctx_workarounds_init(engine, wal); 971 else if (GRAPHICS_VER(i915) == 6) 972 gen6_ctx_workarounds_init(engine, wal); 973 else if (GRAPHICS_VER(i915) < 8) 974 ; 975 else 976 MISSING_CASE(GRAPHICS_VER(i915)); 977 978 done: 979 wa_init_finish(wal); 980 } 981 982 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 983 { 984 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 985 } 986 987 int intel_engine_emit_ctx_wa(struct i915_request *rq) 988 { 989 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 990 struct i915_wa *wa; 991 unsigned int i; 992 u32 *cs; 993 int ret; 994 995 if (wal->count == 0) 996 return 0; 997 998 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 999 if (ret) 1000 return ret; 1001 1002 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 1003 if (IS_ERR(cs)) 1004 return PTR_ERR(cs); 1005 1006 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 1007 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1008 *cs++ = i915_mmio_reg_offset(wa->reg); 1009 *cs++ = wa->set; 1010 } 1011 *cs++ = MI_NOOP; 1012 1013 intel_ring_advance(rq, cs); 1014 1015 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 1016 if (ret) 1017 return ret; 1018 1019 return 0; 1020 } 1021 1022 static void 1023 gen4_gt_workarounds_init(struct intel_gt *gt, 1024 struct i915_wa_list *wal) 1025 { 1026 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 1027 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1028 } 1029 1030 static void 1031 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1032 { 1033 gen4_gt_workarounds_init(gt, wal); 1034 1035 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 1036 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 1037 } 1038 1039 static void 1040 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1041 { 1042 g4x_gt_workarounds_init(gt, wal); 1043 1044 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 1045 } 1046 1047 static void 1048 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1049 { 1050 } 1051 1052 static void 1053 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1054 { 1055 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 1056 wa_masked_dis(wal, 1057 GEN7_COMMON_SLICE_CHICKEN1, 1058 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 1059 1060 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 1061 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 1062 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 1063 1064 /* WaForceL3Serialization:ivb */ 1065 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1066 } 1067 1068 static void 1069 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1070 { 1071 /* WaForceL3Serialization:vlv */ 1072 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1073 1074 /* 1075 * WaIncreaseL3CreditsForVLVB0:vlv 1076 * This is the hardware default actually. 1077 */ 1078 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1079 } 1080 1081 static void 1082 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1083 { 1084 /* L3 caching of data atomics doesn't work -- disable it. */ 1085 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1086 1087 wa_add(wal, 1088 HSW_ROW_CHICKEN3, 0, 1089 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1090 0 /* XXX does this reg exist? */, true); 1091 1092 /* WaVSRefCountFullforceMissDisable:hsw */ 1093 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1094 } 1095 1096 static void 1097 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1098 { 1099 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1100 unsigned int slice, subslice; 1101 u32 mcr, mcr_mask; 1102 1103 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1104 1105 /* 1106 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1107 * Before any MMIO read into slice/subslice specific registers, MCR 1108 * packet control register needs to be programmed to point to any 1109 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1110 * This means each subsequent MMIO read will be forwarded to an 1111 * specific s/ss combination, but this is OK since these registers 1112 * are consistent across s/ss in almost all cases. In the rare 1113 * occasions, such as INSTDONE, where this value is dependent 1114 * on s/ss combo, the read should be done with read_subslice_reg. 1115 */ 1116 slice = ffs(sseu->slice_mask) - 1; 1117 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1118 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1119 GEM_BUG_ON(!subslice); 1120 subslice--; 1121 1122 /* 1123 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1124 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1125 */ 1126 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1127 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1128 1129 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1130 1131 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1132 } 1133 1134 static void 1135 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1136 { 1137 struct drm_i915_private *i915 = gt->i915; 1138 1139 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1140 gen9_wa_init_mcr(i915, wal); 1141 1142 /* WaDisableKillLogic:bxt,skl,kbl */ 1143 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1144 wa_write_or(wal, 1145 GAM_ECOCHK, 1146 ECOCHK_DIS_TLB); 1147 1148 if (HAS_LLC(i915)) { 1149 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1150 * 1151 * Must match Display Engine. See 1152 * WaCompressedResourceDisplayNewHashMode. 1153 */ 1154 wa_write_or(wal, 1155 MMCD_MISC_CTRL, 1156 MMCD_PCLA | MMCD_HOTSPOT_EN); 1157 } 1158 1159 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1160 wa_write_or(wal, 1161 GAM_ECOCHK, 1162 BDW_DISABLE_HDC_INVALIDATION); 1163 } 1164 1165 static void 1166 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1167 { 1168 gen9_gt_workarounds_init(gt, wal); 1169 1170 /* WaDisableGafsUnitClkGating:skl */ 1171 wa_write_or(wal, 1172 GEN7_UCGCTL4, 1173 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1174 1175 /* WaInPlaceDecompressionHang:skl */ 1176 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1177 wa_write_or(wal, 1178 GEN9_GAMT_ECO_REG_RW_IA, 1179 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1180 } 1181 1182 static void 1183 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1184 { 1185 gen9_gt_workarounds_init(gt, wal); 1186 1187 /* WaDisableDynamicCreditSharing:kbl */ 1188 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1189 wa_write_or(wal, 1190 GAMT_CHKN_BIT_REG, 1191 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1192 1193 /* WaDisableGafsUnitClkGating:kbl */ 1194 wa_write_or(wal, 1195 GEN7_UCGCTL4, 1196 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1197 1198 /* WaInPlaceDecompressionHang:kbl */ 1199 wa_write_or(wal, 1200 GEN9_GAMT_ECO_REG_RW_IA, 1201 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1202 } 1203 1204 static void 1205 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1206 { 1207 gen9_gt_workarounds_init(gt, wal); 1208 } 1209 1210 static void 1211 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1212 { 1213 gen9_gt_workarounds_init(gt, wal); 1214 1215 /* WaDisableGafsUnitClkGating:cfl */ 1216 wa_write_or(wal, 1217 GEN7_UCGCTL4, 1218 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1219 1220 /* WaInPlaceDecompressionHang:cfl */ 1221 wa_write_or(wal, 1222 GEN9_GAMT_ECO_REG_RW_IA, 1223 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1224 } 1225 1226 static void __set_mcr_steering(struct i915_wa_list *wal, 1227 i915_reg_t steering_reg, 1228 unsigned int slice, unsigned int subslice) 1229 { 1230 u32 mcr, mcr_mask; 1231 1232 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1233 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1234 1235 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1236 } 1237 1238 static void debug_dump_steering(struct intel_gt *gt) 1239 { 1240 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1241 1242 if (drm_debug_enabled(DRM_UT_DRIVER)) 1243 intel_gt_mcr_report_steering(&p, gt, false); 1244 } 1245 1246 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1247 unsigned int slice, unsigned int subslice) 1248 { 1249 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1250 1251 gt->default_steering.groupid = slice; 1252 gt->default_steering.instanceid = subslice; 1253 1254 debug_dump_steering(gt); 1255 } 1256 1257 static void 1258 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1259 { 1260 const struct sseu_dev_info *sseu = >->info.sseu; 1261 unsigned int subslice; 1262 1263 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1264 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1265 1266 /* 1267 * Although a platform may have subslices, we need to always steer 1268 * reads to the lowest instance that isn't fused off. When Render 1269 * Power Gating is enabled, grabbing forcewake will only power up a 1270 * single subslice (the "minconfig") if there isn't a real workload 1271 * that needs to be run; this means that if we steer register reads to 1272 * one of the higher subslices, we run the risk of reading back 0's or 1273 * random garbage. 1274 */ 1275 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1276 1277 /* 1278 * If the subslice we picked above also steers us to a valid L3 bank, 1279 * then we can just rely on the default steering and won't need to 1280 * worry about explicitly re-steering L3BANK reads later. 1281 */ 1282 if (gt->info.l3bank_mask & BIT(subslice)) 1283 gt->steering_table[L3BANK] = NULL; 1284 1285 __add_mcr_wa(gt, wal, 0, subslice); 1286 } 1287 1288 static void 1289 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1290 { 1291 const struct sseu_dev_info *sseu = >->info.sseu; 1292 unsigned long slice, subslice = 0, slice_mask = 0; 1293 u32 lncf_mask = 0; 1294 int i; 1295 1296 /* 1297 * On Xe_HP the steering increases in complexity. There are now several 1298 * more units that require steering and we're not guaranteed to be able 1299 * to find a common setting for all of them. These are: 1300 * - GSLICE (fusable) 1301 * - DSS (sub-unit within gslice; fusable) 1302 * - L3 Bank (fusable) 1303 * - MSLICE (fusable) 1304 * - LNCF (sub-unit within mslice; always present if mslice is present) 1305 * 1306 * We'll do our default/implicit steering based on GSLICE (in the 1307 * sliceid field) and DSS (in the subsliceid field). If we can 1308 * find overlap between the valid MSLICE and/or LNCF values with 1309 * a suitable GSLICE, then we can just re-use the default value and 1310 * skip and explicit steering at runtime. 1311 * 1312 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1313 * a valid sliceid value. DSS steering is the only type of steering 1314 * that utilizes the 'subsliceid' bits. 1315 * 1316 * Also note that, even though the steering domain is called "GSlice" 1317 * and it is encoded in the register using the gslice format, the spec 1318 * says that the combined (geometry | compute) fuse should be used to 1319 * select the steering. 1320 */ 1321 1322 /* Find the potential gslice candidates */ 1323 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1324 GEN_DSS_PER_GSLICE); 1325 1326 /* 1327 * Find the potential LNCF candidates. Either LNCF within a valid 1328 * mslice is fine. 1329 */ 1330 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1331 lncf_mask |= (0x3 << (i * 2)); 1332 1333 /* 1334 * Are there any sliceid values that work for both GSLICE and LNCF 1335 * steering? 1336 */ 1337 if (slice_mask & lncf_mask) { 1338 slice_mask &= lncf_mask; 1339 gt->steering_table[LNCF] = NULL; 1340 } 1341 1342 /* How about sliceid values that also work for MSLICE steering? */ 1343 if (slice_mask & gt->info.mslice_mask) { 1344 slice_mask &= gt->info.mslice_mask; 1345 gt->steering_table[MSLICE] = NULL; 1346 } 1347 1348 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1349 gt->steering_table[GAM] = NULL; 1350 1351 slice = __ffs(slice_mask); 1352 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1353 GEN_DSS_PER_GSLICE; 1354 1355 __add_mcr_wa(gt, wal, slice, subslice); 1356 1357 /* 1358 * SQIDI ranges are special because they use different steering 1359 * registers than everything else we work with. On XeHP SDV and 1360 * DG2-G10, any value in the steering registers will work fine since 1361 * all instances are present, but DG2-G11 only has SQIDI instances at 1362 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1363 * we'll just steer to a hardcoded "2" since that value will work 1364 * everywhere. 1365 */ 1366 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1367 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1368 1369 /* 1370 * On DG2, GAM registers have a dedicated steering control register 1371 * and must always be programmed to a hardcoded groupid of "1." 1372 */ 1373 if (IS_DG2(gt->i915)) 1374 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1375 } 1376 1377 static void 1378 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1379 { 1380 unsigned int dss; 1381 1382 /* 1383 * Setup implicit steering for COMPUTE and DSS ranges to the first 1384 * non-fused-off DSS. All other types of MCR registers will be 1385 * explicitly steered. 1386 */ 1387 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1388 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1389 } 1390 1391 static void 1392 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1393 { 1394 struct drm_i915_private *i915 = gt->i915; 1395 1396 icl_wa_init_mcr(gt, wal); 1397 1398 /* WaModifyGamTlbPartitioning:icl */ 1399 wa_write_clr_set(wal, 1400 GEN11_GACB_PERF_CTRL, 1401 GEN11_HASH_CTRL_MASK, 1402 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1403 1404 /* Wa_1405766107:icl 1405 * Formerly known as WaCL2SFHalfMaxAlloc 1406 */ 1407 wa_write_or(wal, 1408 GEN11_LSN_UNSLCVC, 1409 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1410 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1411 1412 /* Wa_220166154:icl 1413 * Formerly known as WaDisCtxReload 1414 */ 1415 wa_write_or(wal, 1416 GEN8_GAMW_ECO_DEV_RW_IA, 1417 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1418 1419 /* Wa_1406463099:icl 1420 * Formerly known as WaGamTlbPendError 1421 */ 1422 wa_write_or(wal, 1423 GAMT_CHKN_BIT_REG, 1424 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1425 1426 /* 1427 * Wa_1408615072:icl,ehl (vsunit) 1428 * Wa_1407596294:icl,ehl (hsunit) 1429 */ 1430 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1431 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1432 1433 /* Wa_1407352427:icl,ehl */ 1434 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1435 PSDUNIT_CLKGATE_DIS); 1436 1437 /* Wa_1406680159:icl,ehl */ 1438 wa_mcr_write_or(wal, 1439 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1440 GWUNIT_CLKGATE_DIS); 1441 1442 /* Wa_1607087056:icl,ehl,jsl */ 1443 if (IS_ICELAKE(i915) || 1444 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1445 wa_write_or(wal, 1446 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1447 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1448 1449 /* 1450 * This is not a documented workaround, but rather an optimization 1451 * to reduce sampler power. 1452 */ 1453 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1454 } 1455 1456 /* 1457 * Though there are per-engine instances of these registers, 1458 * they retain their value through engine resets and should 1459 * only be provided on the GT workaround list rather than 1460 * the engine-specific workaround list. 1461 */ 1462 static void 1463 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1464 { 1465 struct intel_engine_cs *engine; 1466 int id; 1467 1468 for_each_engine(engine, gt, id) { 1469 if (engine->class != VIDEO_DECODE_CLASS || 1470 (engine->instance % 2)) 1471 continue; 1472 1473 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1474 IECPUNIT_CLKGATE_DIS); 1475 } 1476 } 1477 1478 static void 1479 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1480 { 1481 icl_wa_init_mcr(gt, wal); 1482 1483 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1484 wa_14011060649(gt, wal); 1485 1486 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1487 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1488 } 1489 1490 static void 1491 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1492 { 1493 gen12_gt_workarounds_init(gt, wal); 1494 1495 /* Wa_1409420604:dg1 */ 1496 wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, 1497 CPSSUNIT_CLKGATE_DIS); 1498 1499 /* Wa_1408615072:dg1 */ 1500 /* Empirical testing shows this register is unaffected by engine reset. */ 1501 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); 1502 } 1503 1504 static void 1505 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1506 { 1507 struct drm_i915_private *i915 = gt->i915; 1508 1509 xehp_init_mcr(gt, wal); 1510 1511 /* Wa_1409757795:xehpsdv */ 1512 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1513 1514 /* Wa_18011725039:xehpsdv */ 1515 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 1516 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 1517 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 1518 } 1519 1520 /* Wa_16011155590:xehpsdv */ 1521 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1522 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1523 TSGUNIT_CLKGATE_DIS); 1524 1525 /* Wa_14011780169:xehpsdv */ 1526 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1527 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1528 GAMTLBVDBOX7_CLKGATE_DIS | 1529 GAMTLBVDBOX6_CLKGATE_DIS | 1530 GAMTLBVDBOX5_CLKGATE_DIS | 1531 GAMTLBVDBOX4_CLKGATE_DIS | 1532 GAMTLBVDBOX3_CLKGATE_DIS | 1533 GAMTLBVDBOX2_CLKGATE_DIS | 1534 GAMTLBVDBOX1_CLKGATE_DIS | 1535 GAMTLBVDBOX0_CLKGATE_DIS | 1536 GAMTLBKCR_CLKGATE_DIS | 1537 GAMTLBGUC_CLKGATE_DIS | 1538 GAMTLBBLT_CLKGATE_DIS); 1539 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1540 GAMTLBGFXA1_CLKGATE_DIS | 1541 GAMTLBCOMPA0_CLKGATE_DIS | 1542 GAMTLBCOMPA1_CLKGATE_DIS | 1543 GAMTLBCOMPB0_CLKGATE_DIS | 1544 GAMTLBCOMPB1_CLKGATE_DIS | 1545 GAMTLBCOMPC0_CLKGATE_DIS | 1546 GAMTLBCOMPC1_CLKGATE_DIS | 1547 GAMTLBCOMPD0_CLKGATE_DIS | 1548 GAMTLBCOMPD1_CLKGATE_DIS | 1549 GAMTLBMERT_CLKGATE_DIS | 1550 GAMTLBVEBOX3_CLKGATE_DIS | 1551 GAMTLBVEBOX2_CLKGATE_DIS | 1552 GAMTLBVEBOX1_CLKGATE_DIS | 1553 GAMTLBVEBOX0_CLKGATE_DIS); 1554 } 1555 1556 /* Wa_16012725990:xehpsdv */ 1557 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1558 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1559 1560 /* Wa_14011060649:xehpsdv */ 1561 wa_14011060649(gt, wal); 1562 1563 /* Wa_14012362059:xehpsdv */ 1564 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1565 1566 /* Wa_14014368820:xehpsdv */ 1567 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1568 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1569 1570 /* Wa_14010670810:xehpsdv */ 1571 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1572 } 1573 1574 static void 1575 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1576 { 1577 struct intel_engine_cs *engine; 1578 int id; 1579 1580 xehp_init_mcr(gt, wal); 1581 1582 /* Wa_14011060649:dg2 */ 1583 wa_14011060649(gt, wal); 1584 1585 /* 1586 * Although there are per-engine instances of these registers, 1587 * they technically exist outside the engine itself and are not 1588 * impacted by engine resets. Furthermore, they're part of the 1589 * GuC blacklist so trying to treat them as engine workarounds 1590 * will result in GuC initialization failure and a wedged GPU. 1591 */ 1592 for_each_engine(engine, gt, id) { 1593 if (engine->class != VIDEO_DECODE_CLASS) 1594 continue; 1595 1596 /* Wa_16010515920:dg2_g10 */ 1597 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1598 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1599 ALNUNIT_CLKGATE_DIS); 1600 } 1601 1602 if (IS_DG2_G10(gt->i915)) { 1603 /* Wa_22010523718:dg2 */ 1604 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1605 CG3DDISCFEG_CLKGATE_DIS); 1606 1607 /* Wa_14011006942:dg2 */ 1608 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1609 DSS_ROUTER_CLKGATE_DIS); 1610 } 1611 1612 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) || 1613 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) { 1614 /* Wa_14012362059:dg2 */ 1615 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1616 } 1617 1618 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1619 /* Wa_14010948348:dg2_g10 */ 1620 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1621 1622 /* Wa_14011037102:dg2_g10 */ 1623 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1624 1625 /* Wa_14011371254:dg2_g10 */ 1626 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1627 1628 /* Wa_14011431319:dg2_g10 */ 1629 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1630 GAMTLBVDBOX7_CLKGATE_DIS | 1631 GAMTLBVDBOX6_CLKGATE_DIS | 1632 GAMTLBVDBOX5_CLKGATE_DIS | 1633 GAMTLBVDBOX4_CLKGATE_DIS | 1634 GAMTLBVDBOX3_CLKGATE_DIS | 1635 GAMTLBVDBOX2_CLKGATE_DIS | 1636 GAMTLBVDBOX1_CLKGATE_DIS | 1637 GAMTLBVDBOX0_CLKGATE_DIS | 1638 GAMTLBKCR_CLKGATE_DIS | 1639 GAMTLBGUC_CLKGATE_DIS | 1640 GAMTLBBLT_CLKGATE_DIS); 1641 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1642 GAMTLBGFXA1_CLKGATE_DIS | 1643 GAMTLBCOMPA0_CLKGATE_DIS | 1644 GAMTLBCOMPA1_CLKGATE_DIS | 1645 GAMTLBCOMPB0_CLKGATE_DIS | 1646 GAMTLBCOMPB1_CLKGATE_DIS | 1647 GAMTLBCOMPC0_CLKGATE_DIS | 1648 GAMTLBCOMPC1_CLKGATE_DIS | 1649 GAMTLBCOMPD0_CLKGATE_DIS | 1650 GAMTLBCOMPD1_CLKGATE_DIS | 1651 GAMTLBMERT_CLKGATE_DIS | 1652 GAMTLBVEBOX3_CLKGATE_DIS | 1653 GAMTLBVEBOX2_CLKGATE_DIS | 1654 GAMTLBVEBOX1_CLKGATE_DIS | 1655 GAMTLBVEBOX0_CLKGATE_DIS); 1656 1657 /* Wa_14010569222:dg2_g10 */ 1658 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1659 GAMEDIA_CLKGATE_DIS); 1660 1661 /* Wa_14011028019:dg2_g10 */ 1662 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1663 1664 /* Wa_14010680813:dg2_g10 */ 1665 wa_mcr_write_or(wal, XEHP_GAMSTLB_CTRL, 1666 CONTROL_BLOCK_CLKGATE_DIS | 1667 EGRESS_BLOCK_CLKGATE_DIS | 1668 TAG_BLOCK_CLKGATE_DIS); 1669 } 1670 1671 /* Wa_14014830051:dg2 */ 1672 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1673 1674 /* Wa_14015795083 */ 1675 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1676 1677 /* Wa_18018781329 */ 1678 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1679 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1680 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1681 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1682 1683 /* Wa_1509235366:dg2 */ 1684 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1685 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1686 1687 /* Wa_14010648519:dg2 */ 1688 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1689 } 1690 1691 static void 1692 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1693 { 1694 pvc_init_mcr(gt, wal); 1695 1696 /* Wa_14015795083 */ 1697 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1698 1699 /* Wa_18018781329 */ 1700 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1701 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1702 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1703 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1704 1705 /* Wa_16016694945 */ 1706 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 1707 } 1708 1709 static void 1710 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1711 { 1712 /* Wa_14018778641 / Wa_18018781329 */ 1713 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1714 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1715 1716 /* Wa_22016670082 */ 1717 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); 1718 1719 if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) || 1720 IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) { 1721 /* Wa_14014830051 */ 1722 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1723 1724 /* Wa_14015795083 */ 1725 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1726 } 1727 1728 /* 1729 * Unlike older platforms, we no longer setup implicit steering here; 1730 * all MCR accesses are explicitly steered. 1731 */ 1732 debug_dump_steering(gt); 1733 } 1734 1735 static void 1736 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1737 { 1738 /* 1739 * Wa_14018778641 1740 * Wa_18018781329 1741 * 1742 * Note that although these registers are MCR on the primary 1743 * GT, the media GT's versions are regular singleton registers. 1744 */ 1745 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); 1746 wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1747 wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1748 1749 debug_dump_steering(gt); 1750 } 1751 1752 /* 1753 * The bspec performance guide has recommended MMIO tuning settings. These 1754 * aren't truly "workarounds" but we want to program them through the 1755 * workaround infrastructure to make sure they're (re)applied at the proper 1756 * times. 1757 * 1758 * The programming in this function is for settings that persist through 1759 * engine resets and also are not part of any engine's register state context. 1760 * I.e., settings that only need to be re-applied in the event of a full GT 1761 * reset. 1762 */ 1763 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) 1764 { 1765 if (IS_METEORLAKE(gt->i915)) { 1766 if (gt->type != GT_MEDIA) 1767 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1768 1769 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1770 } 1771 1772 if (IS_PONTEVECCHIO(gt->i915)) { 1773 wa_mcr_write(wal, XEHPC_L3SCRUB, 1774 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 1775 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); 1776 } 1777 1778 if (IS_DG2(gt->i915)) { 1779 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1780 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1781 } 1782 } 1783 1784 static void 1785 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1786 { 1787 struct drm_i915_private *i915 = gt->i915; 1788 1789 gt_tuning_settings(gt, wal); 1790 1791 if (gt->type == GT_MEDIA) { 1792 if (MEDIA_VER(i915) >= 13) 1793 xelpmp_gt_workarounds_init(gt, wal); 1794 else 1795 MISSING_CASE(MEDIA_VER(i915)); 1796 1797 return; 1798 } 1799 1800 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1801 xelpg_gt_workarounds_init(gt, wal); 1802 else if (IS_PONTEVECCHIO(i915)) 1803 pvc_gt_workarounds_init(gt, wal); 1804 else if (IS_DG2(i915)) 1805 dg2_gt_workarounds_init(gt, wal); 1806 else if (IS_XEHPSDV(i915)) 1807 xehpsdv_gt_workarounds_init(gt, wal); 1808 else if (IS_DG1(i915)) 1809 dg1_gt_workarounds_init(gt, wal); 1810 else if (GRAPHICS_VER(i915) == 12) 1811 gen12_gt_workarounds_init(gt, wal); 1812 else if (GRAPHICS_VER(i915) == 11) 1813 icl_gt_workarounds_init(gt, wal); 1814 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1815 cfl_gt_workarounds_init(gt, wal); 1816 else if (IS_GEMINILAKE(i915)) 1817 glk_gt_workarounds_init(gt, wal); 1818 else if (IS_KABYLAKE(i915)) 1819 kbl_gt_workarounds_init(gt, wal); 1820 else if (IS_BROXTON(i915)) 1821 gen9_gt_workarounds_init(gt, wal); 1822 else if (IS_SKYLAKE(i915)) 1823 skl_gt_workarounds_init(gt, wal); 1824 else if (IS_HASWELL(i915)) 1825 hsw_gt_workarounds_init(gt, wal); 1826 else if (IS_VALLEYVIEW(i915)) 1827 vlv_gt_workarounds_init(gt, wal); 1828 else if (IS_IVYBRIDGE(i915)) 1829 ivb_gt_workarounds_init(gt, wal); 1830 else if (GRAPHICS_VER(i915) == 6) 1831 snb_gt_workarounds_init(gt, wal); 1832 else if (GRAPHICS_VER(i915) == 5) 1833 ilk_gt_workarounds_init(gt, wal); 1834 else if (IS_G4X(i915)) 1835 g4x_gt_workarounds_init(gt, wal); 1836 else if (GRAPHICS_VER(i915) == 4) 1837 gen4_gt_workarounds_init(gt, wal); 1838 else if (GRAPHICS_VER(i915) <= 8) 1839 ; 1840 else 1841 MISSING_CASE(GRAPHICS_VER(i915)); 1842 } 1843 1844 void intel_gt_init_workarounds(struct intel_gt *gt) 1845 { 1846 struct i915_wa_list *wal = >->wa_list; 1847 1848 wa_init_start(wal, gt, "GT", "global"); 1849 gt_init_workarounds(gt, wal); 1850 wa_init_finish(wal); 1851 } 1852 1853 static enum forcewake_domains 1854 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1855 { 1856 enum forcewake_domains fw = 0; 1857 struct i915_wa *wa; 1858 unsigned int i; 1859 1860 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1861 fw |= intel_uncore_forcewake_for_reg(uncore, 1862 wa->reg, 1863 FW_REG_READ | 1864 FW_REG_WRITE); 1865 1866 return fw; 1867 } 1868 1869 static bool 1870 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1871 const char *name, const char *from) 1872 { 1873 if ((cur ^ wa->set) & wa->read) { 1874 drm_err(>->i915->drm, 1875 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1876 name, from, i915_mmio_reg_offset(wa->reg), 1877 cur, cur & wa->read, wa->set & wa->read); 1878 1879 return false; 1880 } 1881 1882 return true; 1883 } 1884 1885 static void wa_list_apply(const struct i915_wa_list *wal) 1886 { 1887 struct intel_gt *gt = wal->gt; 1888 struct intel_uncore *uncore = gt->uncore; 1889 enum forcewake_domains fw; 1890 unsigned long flags; 1891 struct i915_wa *wa; 1892 unsigned int i; 1893 1894 if (!wal->count) 1895 return; 1896 1897 fw = wal_get_fw_for_rmw(uncore, wal); 1898 1899 intel_gt_mcr_lock(gt, &flags); 1900 spin_lock(&uncore->lock); 1901 intel_uncore_forcewake_get__locked(uncore, fw); 1902 1903 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1904 u32 val, old = 0; 1905 1906 /* open-coded rmw due to steering */ 1907 if (wa->clr) 1908 old = wa->is_mcr ? 1909 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1910 intel_uncore_read_fw(uncore, wa->reg); 1911 val = (old & ~wa->clr) | wa->set; 1912 if (val != old || !wa->clr) { 1913 if (wa->is_mcr) 1914 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1915 else 1916 intel_uncore_write_fw(uncore, wa->reg, val); 1917 } 1918 1919 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1920 u32 val = wa->is_mcr ? 1921 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1922 intel_uncore_read_fw(uncore, wa->reg); 1923 1924 wa_verify(gt, wa, val, wal->name, "application"); 1925 } 1926 } 1927 1928 intel_uncore_forcewake_put__locked(uncore, fw); 1929 spin_unlock(&uncore->lock); 1930 intel_gt_mcr_unlock(gt, flags); 1931 } 1932 1933 void intel_gt_apply_workarounds(struct intel_gt *gt) 1934 { 1935 wa_list_apply(>->wa_list); 1936 } 1937 1938 static bool wa_list_verify(struct intel_gt *gt, 1939 const struct i915_wa_list *wal, 1940 const char *from) 1941 { 1942 struct intel_uncore *uncore = gt->uncore; 1943 struct i915_wa *wa; 1944 enum forcewake_domains fw; 1945 unsigned long flags; 1946 unsigned int i; 1947 bool ok = true; 1948 1949 fw = wal_get_fw_for_rmw(uncore, wal); 1950 1951 intel_gt_mcr_lock(gt, &flags); 1952 spin_lock(&uncore->lock); 1953 intel_uncore_forcewake_get__locked(uncore, fw); 1954 1955 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1956 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1957 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1958 intel_uncore_read_fw(uncore, wa->reg), 1959 wal->name, from); 1960 1961 intel_uncore_forcewake_put__locked(uncore, fw); 1962 spin_unlock(&uncore->lock); 1963 intel_gt_mcr_unlock(gt, flags); 1964 1965 return ok; 1966 } 1967 1968 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1969 { 1970 return wa_list_verify(gt, >->wa_list, from); 1971 } 1972 1973 __maybe_unused 1974 static bool is_nonpriv_flags_valid(u32 flags) 1975 { 1976 /* Check only valid flag bits are set */ 1977 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1978 return false; 1979 1980 /* NB: Only 3 out of 4 enum values are valid for access field */ 1981 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1982 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1983 return false; 1984 1985 return true; 1986 } 1987 1988 static void 1989 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1990 { 1991 struct i915_wa wa = { 1992 .reg = reg 1993 }; 1994 1995 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1996 return; 1997 1998 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1999 return; 2000 2001 wa.reg.reg |= flags; 2002 _wa_add(wal, &wa); 2003 } 2004 2005 static void 2006 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 2007 { 2008 struct i915_wa wa = { 2009 .mcr_reg = reg, 2010 .is_mcr = 1, 2011 }; 2012 2013 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 2014 return; 2015 2016 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 2017 return; 2018 2019 wa.mcr_reg.reg |= flags; 2020 _wa_add(wal, &wa); 2021 } 2022 2023 static void 2024 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 2025 { 2026 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 2027 } 2028 2029 static void 2030 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 2031 { 2032 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 2033 } 2034 2035 static void gen9_whitelist_build(struct i915_wa_list *w) 2036 { 2037 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 2038 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2039 2040 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 2041 whitelist_reg(w, GEN8_CS_CHICKEN1); 2042 2043 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 2044 whitelist_reg(w, GEN8_HDC_CHICKEN1); 2045 2046 /* WaSendPushConstantsFromMMIO:skl,bxt */ 2047 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 2048 } 2049 2050 static void skl_whitelist_build(struct intel_engine_cs *engine) 2051 { 2052 struct i915_wa_list *w = &engine->whitelist; 2053 2054 if (engine->class != RENDER_CLASS) 2055 return; 2056 2057 gen9_whitelist_build(w); 2058 2059 /* WaDisableLSQCROPERFforOCL:skl */ 2060 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 2061 } 2062 2063 static void bxt_whitelist_build(struct intel_engine_cs *engine) 2064 { 2065 if (engine->class != RENDER_CLASS) 2066 return; 2067 2068 gen9_whitelist_build(&engine->whitelist); 2069 } 2070 2071 static void kbl_whitelist_build(struct intel_engine_cs *engine) 2072 { 2073 struct i915_wa_list *w = &engine->whitelist; 2074 2075 if (engine->class != RENDER_CLASS) 2076 return; 2077 2078 gen9_whitelist_build(w); 2079 2080 /* WaDisableLSQCROPERFforOCL:kbl */ 2081 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 2082 } 2083 2084 static void glk_whitelist_build(struct intel_engine_cs *engine) 2085 { 2086 struct i915_wa_list *w = &engine->whitelist; 2087 2088 if (engine->class != RENDER_CLASS) 2089 return; 2090 2091 gen9_whitelist_build(w); 2092 2093 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 2094 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2095 } 2096 2097 static void cfl_whitelist_build(struct intel_engine_cs *engine) 2098 { 2099 struct i915_wa_list *w = &engine->whitelist; 2100 2101 if (engine->class != RENDER_CLASS) 2102 return; 2103 2104 gen9_whitelist_build(w); 2105 2106 /* 2107 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 2108 * 2109 * This covers 4 register which are next to one another : 2110 * - PS_INVOCATION_COUNT 2111 * - PS_INVOCATION_COUNT_UDW 2112 * - PS_DEPTH_COUNT 2113 * - PS_DEPTH_COUNT_UDW 2114 */ 2115 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2116 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2117 RING_FORCE_TO_NONPRIV_RANGE_4); 2118 } 2119 2120 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 2121 { 2122 struct i915_wa_list *w = &engine->whitelist; 2123 2124 if (engine->class != RENDER_CLASS) 2125 whitelist_reg_ext(w, 2126 RING_CTX_TIMESTAMP(engine->mmio_base), 2127 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2128 } 2129 2130 static void cml_whitelist_build(struct intel_engine_cs *engine) 2131 { 2132 allow_read_ctx_timestamp(engine); 2133 2134 cfl_whitelist_build(engine); 2135 } 2136 2137 static void icl_whitelist_build(struct intel_engine_cs *engine) 2138 { 2139 struct i915_wa_list *w = &engine->whitelist; 2140 2141 allow_read_ctx_timestamp(engine); 2142 2143 switch (engine->class) { 2144 case RENDER_CLASS: 2145 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 2146 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 2147 2148 /* WaAllowUMDToModifySamplerMode:icl */ 2149 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2150 2151 /* WaEnableStateCacheRedirectToCS:icl */ 2152 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2153 2154 /* 2155 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2156 * 2157 * This covers 4 register which are next to one another : 2158 * - PS_INVOCATION_COUNT 2159 * - PS_INVOCATION_COUNT_UDW 2160 * - PS_DEPTH_COUNT 2161 * - PS_DEPTH_COUNT_UDW 2162 */ 2163 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2164 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2165 RING_FORCE_TO_NONPRIV_RANGE_4); 2166 break; 2167 2168 case VIDEO_DECODE_CLASS: 2169 /* hucStatusRegOffset */ 2170 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2171 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2172 /* hucUKernelHdrInfoRegOffset */ 2173 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2174 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2175 /* hucStatus2RegOffset */ 2176 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2177 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2178 break; 2179 2180 default: 2181 break; 2182 } 2183 } 2184 2185 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2186 { 2187 struct i915_wa_list *w = &engine->whitelist; 2188 2189 allow_read_ctx_timestamp(engine); 2190 2191 switch (engine->class) { 2192 case RENDER_CLASS: 2193 /* 2194 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2195 * Wa_1408556865:tgl 2196 * 2197 * This covers 4 registers which are next to one another : 2198 * - PS_INVOCATION_COUNT 2199 * - PS_INVOCATION_COUNT_UDW 2200 * - PS_DEPTH_COUNT 2201 * - PS_DEPTH_COUNT_UDW 2202 */ 2203 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2204 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2205 RING_FORCE_TO_NONPRIV_RANGE_4); 2206 2207 /* 2208 * Wa_1808121037:tgl 2209 * Wa_14012131227:dg1 2210 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2211 */ 2212 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2213 2214 /* Wa_1806527549:tgl */ 2215 whitelist_reg(w, HIZ_CHICKEN); 2216 2217 /* Required by recommended tuning setting (not a workaround) */ 2218 whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); 2219 2220 break; 2221 default: 2222 break; 2223 } 2224 } 2225 2226 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2227 { 2228 struct i915_wa_list *w = &engine->whitelist; 2229 2230 switch (engine->class) { 2231 case RENDER_CLASS: 2232 /* 2233 * Wa_1507100340:dg2_g10 2234 * 2235 * This covers 4 registers which are next to one another : 2236 * - PS_INVOCATION_COUNT 2237 * - PS_INVOCATION_COUNT_UDW 2238 * - PS_DEPTH_COUNT 2239 * - PS_DEPTH_COUNT_UDW 2240 */ 2241 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2242 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2243 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2244 RING_FORCE_TO_NONPRIV_RANGE_4); 2245 2246 /* Required by recommended tuning setting (not a workaround) */ 2247 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2248 2249 break; 2250 case COMPUTE_CLASS: 2251 /* Wa_16011157294:dg2_g10 */ 2252 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2253 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2254 break; 2255 default: 2256 break; 2257 } 2258 } 2259 2260 static void blacklist_trtt(struct intel_engine_cs *engine) 2261 { 2262 struct i915_wa_list *w = &engine->whitelist; 2263 2264 /* 2265 * Prevent read/write access to [0x4400, 0x4600) which covers 2266 * the TRTT range across all engines. Note that normally userspace 2267 * cannot access the other engines' trtt control, but for simplicity 2268 * we cover the entire range on each engine. 2269 */ 2270 whitelist_reg_ext(w, _MMIO(0x4400), 2271 RING_FORCE_TO_NONPRIV_DENY | 2272 RING_FORCE_TO_NONPRIV_RANGE_64); 2273 whitelist_reg_ext(w, _MMIO(0x4500), 2274 RING_FORCE_TO_NONPRIV_DENY | 2275 RING_FORCE_TO_NONPRIV_RANGE_64); 2276 } 2277 2278 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2279 { 2280 /* Wa_16014440446:pvc */ 2281 blacklist_trtt(engine); 2282 } 2283 2284 static void mtl_whitelist_build(struct intel_engine_cs *engine) 2285 { 2286 struct i915_wa_list *w = &engine->whitelist; 2287 2288 switch (engine->class) { 2289 case RENDER_CLASS: 2290 /* Required by recommended tuning setting (not a workaround) */ 2291 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2292 2293 break; 2294 default: 2295 break; 2296 } 2297 } 2298 2299 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2300 { 2301 struct drm_i915_private *i915 = engine->i915; 2302 struct i915_wa_list *w = &engine->whitelist; 2303 2304 wa_init_start(w, engine->gt, "whitelist", engine->name); 2305 2306 if (IS_METEORLAKE(i915)) 2307 mtl_whitelist_build(engine); 2308 else if (IS_PONTEVECCHIO(i915)) 2309 pvc_whitelist_build(engine); 2310 else if (IS_DG2(i915)) 2311 dg2_whitelist_build(engine); 2312 else if (IS_XEHPSDV(i915)) 2313 ; /* none needed */ 2314 else if (GRAPHICS_VER(i915) == 12) 2315 tgl_whitelist_build(engine); 2316 else if (GRAPHICS_VER(i915) == 11) 2317 icl_whitelist_build(engine); 2318 else if (IS_COMETLAKE(i915)) 2319 cml_whitelist_build(engine); 2320 else if (IS_COFFEELAKE(i915)) 2321 cfl_whitelist_build(engine); 2322 else if (IS_GEMINILAKE(i915)) 2323 glk_whitelist_build(engine); 2324 else if (IS_KABYLAKE(i915)) 2325 kbl_whitelist_build(engine); 2326 else if (IS_BROXTON(i915)) 2327 bxt_whitelist_build(engine); 2328 else if (IS_SKYLAKE(i915)) 2329 skl_whitelist_build(engine); 2330 else if (GRAPHICS_VER(i915) <= 8) 2331 ; 2332 else 2333 MISSING_CASE(GRAPHICS_VER(i915)); 2334 2335 wa_init_finish(w); 2336 } 2337 2338 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2339 { 2340 const struct i915_wa_list *wal = &engine->whitelist; 2341 struct intel_uncore *uncore = engine->uncore; 2342 const u32 base = engine->mmio_base; 2343 struct i915_wa *wa; 2344 unsigned int i; 2345 2346 if (!wal->count) 2347 return; 2348 2349 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2350 intel_uncore_write(uncore, 2351 RING_FORCE_TO_NONPRIV(base, i), 2352 i915_mmio_reg_offset(wa->reg)); 2353 2354 /* And clear the rest just in case of garbage */ 2355 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2356 intel_uncore_write(uncore, 2357 RING_FORCE_TO_NONPRIV(base, i), 2358 i915_mmio_reg_offset(RING_NOPID(base))); 2359 } 2360 2361 /* 2362 * engine_fake_wa_init(), a place holder to program the registers 2363 * which are not part of an official workaround defined by the 2364 * hardware team. 2365 * Adding programming of those register inside workaround will 2366 * allow utilizing wa framework to proper application and verification. 2367 */ 2368 static void 2369 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2370 { 2371 u8 mocs_w, mocs_r; 2372 2373 /* 2374 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2375 * by the command streamer when executing commands that don't have 2376 * a way to explicitly specify a MOCS setting. The default should 2377 * usually reference whichever MOCS entry corresponds to uncached 2378 * behavior, although use of a WB cached entry is recommended by the 2379 * spec in certain circumstances on specific platforms. 2380 */ 2381 if (GRAPHICS_VER(engine->i915) >= 12) { 2382 mocs_r = engine->gt->mocs.uc_index; 2383 mocs_w = engine->gt->mocs.uc_index; 2384 2385 if (HAS_L3_CCS_READ(engine->i915) && 2386 engine->class == COMPUTE_CLASS) { 2387 mocs_r = engine->gt->mocs.wb_index; 2388 2389 /* 2390 * Even on the few platforms where MOCS 0 is a 2391 * legitimate table entry, it's never the correct 2392 * setting to use here; we can assume the MOCS init 2393 * just forgot to initialize wb_index. 2394 */ 2395 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2396 } 2397 2398 wa_masked_field_set(wal, 2399 RING_CMD_CCTL(engine->mmio_base), 2400 CMD_CCTL_MOCS_MASK, 2401 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2402 } 2403 } 2404 2405 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2406 { 2407 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2408 GEN_DSS_PER_GSLICE; 2409 } 2410 2411 static void 2412 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2413 { 2414 struct drm_i915_private *i915 = engine->i915; 2415 2416 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2417 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { 2418 /* Wa_22014600077 */ 2419 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2420 ENABLE_EU_COUNT_FOR_TDL_FLUSH); 2421 } 2422 2423 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 2424 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 2425 IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2426 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2427 /* Wa_1509727124 */ 2428 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2429 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2430 } 2431 2432 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2433 IS_DG2_G11(i915) || IS_DG2_G12(i915) || 2434 IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) { 2435 /* Wa_22012856258 */ 2436 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2437 GEN12_DISABLE_READ_SUPPRESSION); 2438 } 2439 2440 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2441 /* Wa_14013392000:dg2_g11 */ 2442 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2443 } 2444 2445 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2446 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2447 /* Wa_14012419201:dg2 */ 2448 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2449 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2450 } 2451 2452 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2453 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2454 needs_wa_1308578152(engine)) { 2455 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2456 GEN12_REPLAY_MODE_GRANULARITY); 2457 } 2458 2459 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2460 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2461 /* 2462 * Wa_22010960976:dg2 2463 * Wa_14013347512:dg2 2464 */ 2465 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2466 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2467 } 2468 2469 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2470 /* 2471 * Wa_1608949956:dg2_g10 2472 * Wa_14010198302:dg2_g10 2473 */ 2474 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2475 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2476 } 2477 2478 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) 2479 /* Wa_22010430635:dg2 */ 2480 wa_mcr_masked_en(wal, 2481 GEN9_ROW_CHICKEN4, 2482 GEN12_DISABLE_GRF_CLEAR); 2483 2484 /* Wa_14013202645:dg2 */ 2485 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2486 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2487 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2488 2489 /* Wa_22012532006:dg2 */ 2490 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2491 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2492 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2493 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2494 2495 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2496 IS_DG2_G10(i915)) { 2497 /* Wa_22014600077:dg2 */ 2498 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2499 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2500 0 /* Wa_14012342262 write-only reg, so skip verification */, 2501 true); 2502 } 2503 2504 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2505 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2506 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2507 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2508 2509 /* 2510 * Wa_1407928979:tgl A* 2511 * Wa_18011464164:tgl[B0+],dg1[B0+] 2512 * Wa_22010931296:tgl[B0+],dg1[B0+] 2513 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2514 */ 2515 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2516 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2517 } 2518 2519 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2520 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2521 /* 2522 * Wa_1606700617:tgl,dg1,adl-p 2523 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2524 * Wa_14010826681:tgl,dg1,rkl,adl-p 2525 * Wa_18019627453:dg2 2526 */ 2527 wa_masked_en(wal, 2528 GEN9_CS_DEBUG_MODE1, 2529 FF_DOP_CLOCK_GATE_DISABLE); 2530 } 2531 2532 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2533 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2534 /* Wa_1409804808 */ 2535 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2536 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2537 2538 /* Wa_14010229206 */ 2539 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2540 } 2541 2542 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2543 /* 2544 * Wa_1607297627 2545 * 2546 * On TGL and RKL there are multiple entries for this WA in the 2547 * BSpec; some indicate this is an A0-only WA, others indicate 2548 * it applies to all steppings so we trust the "all steppings." 2549 */ 2550 wa_masked_en(wal, 2551 RING_PSMI_CTL(RENDER_RING_BASE), 2552 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2553 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2554 } 2555 2556 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2557 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2558 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2559 wa_mcr_masked_en(wal, 2560 GEN10_SAMPLER_MODE, 2561 ENABLE_SMALLPL); 2562 } 2563 2564 if (GRAPHICS_VER(i915) == 11) { 2565 /* This is not an Wa. Enable for better image quality */ 2566 wa_masked_en(wal, 2567 _3D_CHICKEN3, 2568 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2569 2570 /* 2571 * Wa_1405543622:icl 2572 * Formerly known as WaGAPZPriorityScheme 2573 */ 2574 wa_write_or(wal, 2575 GEN8_GARBCNTL, 2576 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2577 2578 /* 2579 * Wa_1604223664:icl 2580 * Formerly known as WaL3BankAddressHashing 2581 */ 2582 wa_write_clr_set(wal, 2583 GEN8_GARBCNTL, 2584 GEN11_HASH_CTRL_EXCL_MASK, 2585 GEN11_HASH_CTRL_EXCL_BIT0); 2586 wa_write_clr_set(wal, 2587 GEN11_GLBLINVL, 2588 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2589 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2590 2591 /* 2592 * Wa_1405733216:icl 2593 * Formerly known as WaDisableCleanEvicts 2594 */ 2595 wa_mcr_write_or(wal, 2596 GEN8_L3SQCREG4, 2597 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2598 2599 /* Wa_1606682166:icl */ 2600 wa_write_or(wal, 2601 GEN7_SARCHKMD, 2602 GEN7_DISABLE_SAMPLER_PREFETCH); 2603 2604 /* Wa_1409178092:icl */ 2605 wa_mcr_write_clr_set(wal, 2606 GEN11_SCRATCH2, 2607 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2608 0); 2609 2610 /* WaEnable32PlaneMode:icl */ 2611 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2612 GEN11_ENABLE_32_PLANE_MODE); 2613 2614 /* 2615 * Wa_1408767742:icl[a2..forever],ehl[all] 2616 * Wa_1605460711:icl[a0..c0] 2617 */ 2618 wa_write_or(wal, 2619 GEN7_FF_THREAD_MODE, 2620 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2621 2622 /* Wa_22010271021 */ 2623 wa_masked_en(wal, 2624 GEN9_CS_DEBUG_MODE1, 2625 FF_DOP_CLOCK_GATE_DISABLE); 2626 } 2627 2628 /* 2629 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2630 * beyond) allow the kernel-mode driver to choose between two different 2631 * options for controlling preemption granularity and behavior. 2632 * 2633 * Option 1 (hardware default): 2634 * Preemption settings are controlled in a global manner via 2635 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2636 * and settings chosen by the kernel-mode driver will apply to all 2637 * userspace clients. 2638 * 2639 * Option 2: 2640 * Preemption settings are controlled on a per-context basis via 2641 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2642 * context switch and is writable by userspace (e.g., via 2643 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2644 * which allows different userspace drivers/clients to select 2645 * different settings, or to change those settings on the fly in 2646 * response to runtime needs. This option was known by name 2647 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2648 * that name is somewhat misleading as other non-granularity 2649 * preemption settings are also impacted by this decision. 2650 * 2651 * On Linux, our policy has always been to let userspace drivers 2652 * control preemption granularity/settings (Option 2). This was 2653 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2654 * userspace developed before object-level preemption was enabled would 2655 * not behave well if i915 were to go with Option 1 and enable that 2656 * preemption in a global manner). On gen9 each context would have 2657 * object-level preemption disabled by default (see 2658 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2659 * userspace drivers could opt-in to object-level preemption as they 2660 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2661 * even though it is no longer necessary for ABI compatibility when 2662 * enabling a new platform, it does ensure that userspace will be able 2663 * to implement any workarounds that show up requiring temporary 2664 * adjustments to preemption behavior at runtime. 2665 * 2666 * Notes/Workarounds: 2667 * - Wa_14015141709: On DG2 and early steppings of MTL, 2668 * CS_CHICKEN1[0] does not disable object-level preemption as 2669 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2670 * using Option 1). Effectively this means userspace is unable 2671 * to disable object-level preemption on these platforms/steppings 2672 * despite the setting here. 2673 * 2674 * - Wa_16013994831: May require that userspace program 2675 * CS_CHICKEN1[10] when certain runtime conditions are true. 2676 * Userspace requires Option 2 to be in effect for their update of 2677 * CS_CHICKEN1[10] to be effective. 2678 * 2679 * Other workarounds may appear in the future that will also require 2680 * Option 2 behavior to allow proper userspace implementation. 2681 */ 2682 if (GRAPHICS_VER(i915) >= 9) 2683 wa_masked_en(wal, 2684 GEN7_FF_SLICE_CS_CHICKEN1, 2685 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2686 2687 if (IS_SKYLAKE(i915) || 2688 IS_KABYLAKE(i915) || 2689 IS_COFFEELAKE(i915) || 2690 IS_COMETLAKE(i915)) { 2691 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2692 wa_write_or(wal, 2693 GEN8_GARBCNTL, 2694 GEN9_GAPS_TSV_CREDIT_DISABLE); 2695 } 2696 2697 if (IS_BROXTON(i915)) { 2698 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2699 wa_masked_en(wal, 2700 FF_SLICE_CS_CHICKEN2, 2701 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2702 } 2703 2704 if (GRAPHICS_VER(i915) == 9) { 2705 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2706 wa_masked_en(wal, 2707 GEN9_CSFE_CHICKEN1_RCS, 2708 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2709 2710 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2711 wa_mcr_write_or(wal, 2712 BDW_SCRATCH1, 2713 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2714 2715 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2716 if (IS_GEN9_LP(i915)) 2717 wa_mcr_write_clr_set(wal, 2718 GEN8_L3SQCREG1, 2719 L3_PRIO_CREDITS_MASK, 2720 L3_GENERAL_PRIO_CREDITS(62) | 2721 L3_HIGH_PRIO_CREDITS(2)); 2722 2723 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2724 wa_mcr_write_or(wal, 2725 GEN8_L3SQCREG4, 2726 GEN8_LQSC_FLUSH_COHERENT_LINES); 2727 2728 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2729 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2730 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2731 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2732 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2733 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2734 EVICTION_PERF_FIX_ENABLE, 0); 2735 } 2736 2737 if (IS_HASWELL(i915)) { 2738 /* WaSampleCChickenBitEnable:hsw */ 2739 wa_masked_en(wal, 2740 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2741 2742 wa_masked_dis(wal, 2743 CACHE_MODE_0_GEN7, 2744 /* enable HiZ Raw Stall Optimization */ 2745 HIZ_RAW_STALL_OPT_DISABLE); 2746 } 2747 2748 if (IS_VALLEYVIEW(i915)) { 2749 /* WaDisableEarlyCull:vlv */ 2750 wa_masked_en(wal, 2751 _3D_CHICKEN3, 2752 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2753 2754 /* 2755 * WaVSThreadDispatchOverride:ivb,vlv 2756 * 2757 * This actually overrides the dispatch 2758 * mode for all thread types. 2759 */ 2760 wa_write_clr_set(wal, 2761 GEN7_FF_THREAD_MODE, 2762 GEN7_FF_SCHED_MASK, 2763 GEN7_FF_TS_SCHED_HW | 2764 GEN7_FF_VS_SCHED_HW | 2765 GEN7_FF_DS_SCHED_HW); 2766 2767 /* WaPsdDispatchEnable:vlv */ 2768 /* WaDisablePSDDualDispatchEnable:vlv */ 2769 wa_masked_en(wal, 2770 GEN7_HALF_SLICE_CHICKEN1, 2771 GEN7_MAX_PS_THREAD_DEP | 2772 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2773 } 2774 2775 if (IS_IVYBRIDGE(i915)) { 2776 /* WaDisableEarlyCull:ivb */ 2777 wa_masked_en(wal, 2778 _3D_CHICKEN3, 2779 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2780 2781 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2782 /* enable HiZ Raw Stall Optimization */ 2783 wa_masked_dis(wal, 2784 CACHE_MODE_0_GEN7, 2785 HIZ_RAW_STALL_OPT_DISABLE); 2786 } 2787 2788 /* 2789 * WaVSThreadDispatchOverride:ivb,vlv 2790 * 2791 * This actually overrides the dispatch 2792 * mode for all thread types. 2793 */ 2794 wa_write_clr_set(wal, 2795 GEN7_FF_THREAD_MODE, 2796 GEN7_FF_SCHED_MASK, 2797 GEN7_FF_TS_SCHED_HW | 2798 GEN7_FF_VS_SCHED_HW | 2799 GEN7_FF_DS_SCHED_HW); 2800 2801 /* WaDisablePSDDualDispatchEnable:ivb */ 2802 if (IS_IVB_GT1(i915)) 2803 wa_masked_en(wal, 2804 GEN7_HALF_SLICE_CHICKEN1, 2805 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2806 } 2807 2808 if (GRAPHICS_VER(i915) == 7) { 2809 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2810 wa_masked_en(wal, 2811 RING_MODE_GEN7(RENDER_RING_BASE), 2812 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2813 2814 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2815 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2816 2817 /* 2818 * BSpec says this must be set, even though 2819 * WaDisable4x2SubspanOptimization:ivb,hsw 2820 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2821 */ 2822 wa_masked_en(wal, 2823 CACHE_MODE_1, 2824 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2825 2826 /* 2827 * BSpec recommends 8x4 when MSAA is used, 2828 * however in practice 16x4 seems fastest. 2829 * 2830 * Note that PS/WM thread counts depend on the WIZ hashing 2831 * disable bit, which we don't touch here, but it's good 2832 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2833 */ 2834 wa_masked_field_set(wal, 2835 GEN7_GT_MODE, 2836 GEN6_WIZ_HASHING_MASK, 2837 GEN6_WIZ_HASHING_16x4); 2838 } 2839 2840 if (IS_GRAPHICS_VER(i915, 6, 7)) 2841 /* 2842 * We need to disable the AsyncFlip performance optimisations in 2843 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2844 * already be programmed to '1' on all products. 2845 * 2846 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2847 */ 2848 wa_masked_en(wal, 2849 RING_MI_MODE(RENDER_RING_BASE), 2850 ASYNC_FLIP_PERF_DISABLE); 2851 2852 if (GRAPHICS_VER(i915) == 6) { 2853 /* 2854 * Required for the hardware to program scanline values for 2855 * waiting 2856 * WaEnableFlushTlbInvalidationMode:snb 2857 */ 2858 wa_masked_en(wal, 2859 GFX_MODE, 2860 GFX_TLB_INVALIDATE_EXPLICIT); 2861 2862 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2863 wa_masked_en(wal, 2864 _3D_CHICKEN, 2865 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2866 2867 wa_masked_en(wal, 2868 _3D_CHICKEN3, 2869 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2870 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2871 /* 2872 * Bspec says: 2873 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2874 * to normal and 3DSTATE_SF number of SF output attributes 2875 * is more than 16." 2876 */ 2877 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2878 2879 /* 2880 * BSpec recommends 8x4 when MSAA is used, 2881 * however in practice 16x4 seems fastest. 2882 * 2883 * Note that PS/WM thread counts depend on the WIZ hashing 2884 * disable bit, which we don't touch here, but it's good 2885 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2886 */ 2887 wa_masked_field_set(wal, 2888 GEN6_GT_MODE, 2889 GEN6_WIZ_HASHING_MASK, 2890 GEN6_WIZ_HASHING_16x4); 2891 2892 /* WaDisable_RenderCache_OperationalFlush:snb */ 2893 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2894 2895 /* 2896 * From the Sandybridge PRM, volume 1 part 3, page 24: 2897 * "If this bit is set, STCunit will have LRA as replacement 2898 * policy. [...] This bit must be reset. LRA replacement 2899 * policy is not supported." 2900 */ 2901 wa_masked_dis(wal, 2902 CACHE_MODE_0, 2903 CM0_STC_EVICT_DISABLE_LRA_SNB); 2904 } 2905 2906 if (IS_GRAPHICS_VER(i915, 4, 6)) 2907 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2908 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2909 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2910 /* XXX bit doesn't stick on Broadwater */ 2911 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2912 2913 if (GRAPHICS_VER(i915) == 4) 2914 /* 2915 * Disable CONSTANT_BUFFER before it is loaded from the context 2916 * image. For as it is loaded, it is executed and the stored 2917 * address may no longer be valid, leading to a GPU hang. 2918 * 2919 * This imposes the requirement that userspace reload their 2920 * CONSTANT_BUFFER on every batch, fortunately a requirement 2921 * they are already accustomed to from before contexts were 2922 * enabled. 2923 */ 2924 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2925 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2926 0 /* XXX bit doesn't stick on Broadwater */, 2927 true); 2928 } 2929 2930 static void 2931 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2932 { 2933 struct drm_i915_private *i915 = engine->i915; 2934 2935 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2936 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2937 wa_write(wal, 2938 RING_SEMA_WAIT_POLL(engine->mmio_base), 2939 1); 2940 } 2941 } 2942 2943 static void 2944 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2945 { 2946 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2947 /* Wa_14014999345:pvc */ 2948 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2949 } 2950 } 2951 2952 /* 2953 * The bspec performance guide has recommended MMIO tuning settings. These 2954 * aren't truly "workarounds" but we want to program them with the same 2955 * workaround infrastructure to ensure that they're automatically added to 2956 * the GuC save/restore lists, re-applied at the right times, and checked for 2957 * any conflicting programming requested by real workarounds. 2958 * 2959 * Programming settings should be added here only if their registers are not 2960 * part of an engine's register state context. If a register is part of a 2961 * context, then any tuning settings should be programmed in an appropriate 2962 * function invoked by __intel_engine_init_ctx_wa(). 2963 */ 2964 static void 2965 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2966 struct i915_wa_list *wal) 2967 { 2968 if (IS_METEORLAKE(i915) || IS_DG2(i915)) 2969 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2970 2971 /* 2972 * This tuning setting proves beneficial only on ATS-M designs; the 2973 * default "age based" setting is optimal on regular DG2 and other 2974 * platforms. 2975 */ 2976 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2977 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2978 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2979 2980 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 2981 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 2982 } 2983 2984 /* 2985 * The workarounds in this function apply to shared registers in 2986 * the general render reset domain that aren't tied to a 2987 * specific engine. Since all render+compute engines get reset 2988 * together, and the contents of these registers are lost during 2989 * the shared render domain reset, we'll define such workarounds 2990 * here and then add them to just a single RCS or CCS engine's 2991 * workaround list (whichever engine has the XXXX flag). 2992 */ 2993 static void 2994 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2995 { 2996 struct drm_i915_private *i915 = engine->i915; 2997 2998 add_render_compute_tuning_settings(i915, wal); 2999 3000 if (GRAPHICS_VER(i915) >= 11) { 3001 /* This is not a Wa (although referred to as 3002 * WaSetInidrectStateOverride in places), this allows 3003 * applications that reference sampler states through 3004 * the BindlessSamplerStateBaseAddress to have their 3005 * border color relative to DynamicStateBaseAddress 3006 * rather than BindlessSamplerStateBaseAddress. 3007 * 3008 * Otherwise SAMPLER_STATE border colors have to be 3009 * copied in multiple heaps (DynamicStateBaseAddress & 3010 * BindlessSamplerStateBaseAddress) 3011 * 3012 * BSpec: 46052 3013 */ 3014 wa_mcr_masked_en(wal, 3015 GEN10_SAMPLER_MODE, 3016 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); 3017 } 3018 3019 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) || 3020 IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER)) 3021 /* Wa_14017856879 */ 3022 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); 3023 3024 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3025 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) 3026 /* 3027 * Wa_14017066071 3028 * Wa_14017654203 3029 */ 3030 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 3031 MTL_DISABLE_SAMPLER_SC_OOO); 3032 3033 if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) 3034 /* Wa_22015279794 */ 3035 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 3036 DISABLE_PREFETCH_INTO_IC); 3037 3038 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3039 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3040 IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 3041 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 3042 /* Wa_22013037850 */ 3043 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 3044 DISABLE_128B_EVICTION_COMMAND_UDW); 3045 } 3046 3047 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3048 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3049 IS_PONTEVECCHIO(i915) || 3050 IS_DG2(i915)) { 3051 /* Wa_22014226127 */ 3052 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 3053 } 3054 3055 if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || 3056 IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) || 3057 IS_DG2(i915)) { 3058 /* Wa_18017747507 */ 3059 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3060 } 3061 3062 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 3063 IS_DG2_G11(i915)) { 3064 /* 3065 * Wa_22012826095:dg2 3066 * Wa_22013059131:dg2 3067 */ 3068 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 3069 MAXREQS_PER_BANK, 3070 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 3071 3072 /* Wa_22013059131:dg2 */ 3073 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 3074 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 3075 } 3076 3077 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 3078 /* 3079 * Wa_14010918519:dg2_g10 3080 * 3081 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 3082 * so ignoring verification. 3083 */ 3084 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 3085 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 3086 0, false); 3087 } 3088 3089 if (IS_XEHPSDV(i915)) { 3090 /* Wa_1409954639 */ 3091 wa_mcr_masked_en(wal, 3092 GEN8_ROW_CHICKEN, 3093 SYSTOLIC_DOP_CLOCK_GATING_DIS); 3094 3095 /* Wa_1607196519 */ 3096 wa_mcr_masked_en(wal, 3097 GEN9_ROW_CHICKEN4, 3098 GEN12_DISABLE_GRF_CLEAR); 3099 3100 /* Wa_14010449647:xehpsdv */ 3101 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 3102 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 3103 } 3104 3105 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 3106 /* Wa_14015227452:dg2,pvc */ 3107 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 3108 3109 /* Wa_16015675438:dg2,pvc */ 3110 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 3111 } 3112 3113 if (IS_DG2(i915)) { 3114 /* 3115 * Wa_16011620976:dg2_g11 3116 * Wa_22015475538:dg2 3117 */ 3118 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3119 } 3120 3121 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915)) 3122 /* 3123 * Wa_22012654132 3124 * 3125 * Note that register 0xE420 is write-only and cannot be read 3126 * back for verification on DG2 (due to Wa_14012342262), so 3127 * we need to explicitly skip the readback. 3128 */ 3129 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 3130 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 3131 0 /* write-only, so skip validation */, 3132 true); 3133 } 3134 3135 static void 3136 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3137 { 3138 if (GRAPHICS_VER(engine->i915) < 4) 3139 return; 3140 3141 engine_fake_wa_init(engine, wal); 3142 3143 /* 3144 * These are common workarounds that just need to applied 3145 * to a single RCS/CCS engine's workaround list since 3146 * they're reset as part of the general render domain reset. 3147 */ 3148 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3149 general_render_compute_wa_init(engine, wal); 3150 3151 if (engine->class == COMPUTE_CLASS) 3152 ccs_engine_wa_init(engine, wal); 3153 else if (engine->class == RENDER_CLASS) 3154 rcs_engine_wa_init(engine, wal); 3155 else 3156 xcs_engine_wa_init(engine, wal); 3157 } 3158 3159 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3160 { 3161 struct i915_wa_list *wal = &engine->wa_list; 3162 3163 wa_init_start(wal, engine->gt, "engine", engine->name); 3164 engine_init_workarounds(engine, wal); 3165 wa_init_finish(wal); 3166 } 3167 3168 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3169 { 3170 wa_list_apply(&engine->wa_list); 3171 } 3172 3173 static const struct i915_range mcr_ranges_gen8[] = { 3174 { .start = 0x5500, .end = 0x55ff }, 3175 { .start = 0x7000, .end = 0x7fff }, 3176 { .start = 0x9400, .end = 0x97ff }, 3177 { .start = 0xb000, .end = 0xb3ff }, 3178 { .start = 0xe000, .end = 0xe7ff }, 3179 {}, 3180 }; 3181 3182 static const struct i915_range mcr_ranges_gen12[] = { 3183 { .start = 0x8150, .end = 0x815f }, 3184 { .start = 0x9520, .end = 0x955f }, 3185 { .start = 0xb100, .end = 0xb3ff }, 3186 { .start = 0xde80, .end = 0xe8ff }, 3187 { .start = 0x24a00, .end = 0x24a7f }, 3188 {}, 3189 }; 3190 3191 static const struct i915_range mcr_ranges_xehp[] = { 3192 { .start = 0x4000, .end = 0x4aff }, 3193 { .start = 0x5200, .end = 0x52ff }, 3194 { .start = 0x5400, .end = 0x7fff }, 3195 { .start = 0x8140, .end = 0x815f }, 3196 { .start = 0x8c80, .end = 0x8dff }, 3197 { .start = 0x94d0, .end = 0x955f }, 3198 { .start = 0x9680, .end = 0x96ff }, 3199 { .start = 0xb000, .end = 0xb3ff }, 3200 { .start = 0xc800, .end = 0xcfff }, 3201 { .start = 0xd800, .end = 0xd8ff }, 3202 { .start = 0xdc00, .end = 0xffff }, 3203 { .start = 0x17000, .end = 0x17fff }, 3204 { .start = 0x24a00, .end = 0x24a7f }, 3205 {}, 3206 }; 3207 3208 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3209 { 3210 const struct i915_range *mcr_ranges; 3211 int i; 3212 3213 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3214 mcr_ranges = mcr_ranges_xehp; 3215 else if (GRAPHICS_VER(i915) >= 12) 3216 mcr_ranges = mcr_ranges_gen12; 3217 else if (GRAPHICS_VER(i915) >= 8) 3218 mcr_ranges = mcr_ranges_gen8; 3219 else 3220 return false; 3221 3222 /* 3223 * Registers in these ranges are affected by the MCR selector 3224 * which only controls CPU initiated MMIO. Routing does not 3225 * work for CS access so we cannot verify them on this path. 3226 */ 3227 for (i = 0; mcr_ranges[i].start; i++) 3228 if (offset >= mcr_ranges[i].start && 3229 offset <= mcr_ranges[i].end) 3230 return true; 3231 3232 return false; 3233 } 3234 3235 static int 3236 wa_list_srm(struct i915_request *rq, 3237 const struct i915_wa_list *wal, 3238 struct i915_vma *vma) 3239 { 3240 struct drm_i915_private *i915 = rq->engine->i915; 3241 unsigned int i, count = 0; 3242 const struct i915_wa *wa; 3243 u32 srm, *cs; 3244 3245 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3246 if (GRAPHICS_VER(i915) >= 8) 3247 srm++; 3248 3249 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3250 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3251 count++; 3252 } 3253 3254 cs = intel_ring_begin(rq, 4 * count); 3255 if (IS_ERR(cs)) 3256 return PTR_ERR(cs); 3257 3258 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3259 u32 offset = i915_mmio_reg_offset(wa->reg); 3260 3261 if (mcr_range(i915, offset)) 3262 continue; 3263 3264 *cs++ = srm; 3265 *cs++ = offset; 3266 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3267 *cs++ = 0; 3268 } 3269 intel_ring_advance(rq, cs); 3270 3271 return 0; 3272 } 3273 3274 static int engine_wa_list_verify(struct intel_context *ce, 3275 const struct i915_wa_list * const wal, 3276 const char *from) 3277 { 3278 const struct i915_wa *wa; 3279 struct i915_request *rq; 3280 struct i915_vma *vma; 3281 struct i915_gem_ww_ctx ww; 3282 unsigned int i; 3283 u32 *results; 3284 int err; 3285 3286 if (!wal->count) 3287 return 0; 3288 3289 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3290 wal->count * sizeof(u32)); 3291 if (IS_ERR(vma)) 3292 return PTR_ERR(vma); 3293 3294 intel_engine_pm_get(ce->engine); 3295 i915_gem_ww_ctx_init(&ww, false); 3296 retry: 3297 err = i915_gem_object_lock(vma->obj, &ww); 3298 if (err == 0) 3299 err = intel_context_pin_ww(ce, &ww); 3300 if (err) 3301 goto err_pm; 3302 3303 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3304 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3305 if (err) 3306 goto err_unpin; 3307 3308 rq = i915_request_create(ce); 3309 if (IS_ERR(rq)) { 3310 err = PTR_ERR(rq); 3311 goto err_vma; 3312 } 3313 3314 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3315 if (err == 0) 3316 err = wa_list_srm(rq, wal, vma); 3317 3318 i915_request_get(rq); 3319 if (err) 3320 i915_request_set_error_once(rq, err); 3321 i915_request_add(rq); 3322 3323 if (err) 3324 goto err_rq; 3325 3326 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3327 err = -ETIME; 3328 goto err_rq; 3329 } 3330 3331 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3332 if (IS_ERR(results)) { 3333 err = PTR_ERR(results); 3334 goto err_rq; 3335 } 3336 3337 err = 0; 3338 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3339 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3340 continue; 3341 3342 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3343 err = -ENXIO; 3344 } 3345 3346 i915_gem_object_unpin_map(vma->obj); 3347 3348 err_rq: 3349 i915_request_put(rq); 3350 err_vma: 3351 i915_vma_unpin(vma); 3352 err_unpin: 3353 intel_context_unpin(ce); 3354 err_pm: 3355 if (err == -EDEADLK) { 3356 err = i915_gem_ww_ctx_backoff(&ww); 3357 if (!err) 3358 goto retry; 3359 } 3360 i915_gem_ww_ctx_fini(&ww); 3361 intel_engine_pm_put(ce->engine); 3362 i915_vma_put(vma); 3363 return err; 3364 } 3365 3366 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3367 const char *from) 3368 { 3369 return engine_wa_list_verify(engine->kernel_context, 3370 &engine->wa_list, 3371 from); 3372 } 3373 3374 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3375 #include "selftest_workarounds.c" 3376 #endif 3377