1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gpu_commands.h" 12 #include "intel_gt.h" 13 #include "intel_gt_mcr.h" 14 #include "intel_gt_regs.h" 15 #include "intel_ring.h" 16 #include "intel_workarounds.h" 17 18 /** 19 * DOC: Hardware workarounds 20 * 21 * Hardware workarounds are register programming documented to be executed in 22 * the driver that fall outside of the normal programming sequences for a 23 * platform. There are some basic categories of workarounds, depending on 24 * how/when they are applied: 25 * 26 * - Context workarounds: workarounds that touch registers that are 27 * saved/restored to/from the HW context image. The list is emitted (via Load 28 * Register Immediate commands) once when initializing the device and saved in 29 * the default context. That default context is then used on every context 30 * creation to have a "primed golden context", i.e. a context image that 31 * already contains the changes needed to all the registers. 32 * 33 * Context workarounds should be implemented in the \*_ctx_workarounds_init() 34 * variants respective to the targeted platforms. 35 * 36 * - Engine workarounds: the list of these WAs is applied whenever the specific 37 * engine is reset. It's also possible that a set of engine classes share a 38 * common power domain and they are reset together. This happens on some 39 * platforms with render and compute engines. In this case (at least) one of 40 * them need to keeep the workaround programming: the approach taken in the 41 * driver is to tie those workarounds to the first compute/render engine that 42 * is registered. When executing with GuC submission, engine resets are 43 * outside of kernel driver control, hence the list of registers involved in 44 * written once, on engine initialization, and then passed to GuC, that 45 * saves/restores their values before/after the reset takes place. See 46 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 47 * 48 * Workarounds for registers specific to RCS and CCS should be implemented in 49 * rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for 50 * registers belonging to BCS, VCS or VECS should be implemented in 51 * xcs_engine_wa_init(). Workarounds for registers not belonging to a specific 52 * engine's MMIO range but that are part of of the common RCS/CCS reset domain 53 * should be implemented in general_render_compute_wa_init(). 54 * 55 * - GT workarounds: the list of these WAs is applied whenever these registers 56 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 57 * 58 * GT workarounds should be implemented in the \*_gt_workarounds_init() 59 * variants respective to the targeted platforms. 60 * 61 * - Register whitelist: some workarounds need to be implemented in userspace, 62 * but need to touch privileged registers. The whitelist in the kernel 63 * instructs the hardware to allow the access to happen. From the kernel side, 64 * this is just a special case of a MMIO workaround (as we write the list of 65 * these to/be-whitelisted registers to some special HW registers). 66 * 67 * Register whitelisting should be done in the \*_whitelist_build() variants 68 * respective to the targeted platforms. 69 * 70 * - Workaround batchbuffers: buffers that get executed automatically by the 71 * hardware on every HW context restore. These buffers are created and 72 * programmed in the default context so the hardware always go through those 73 * programming sequences when switching contexts. The support for workaround 74 * batchbuffers is enabled these hardware mechanisms: 75 * 76 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 77 * context, pointing the hardware to jump to that location when that offset 78 * is reached in the context restore. Workaround batchbuffer in the driver 79 * currently uses this mechanism for all platforms. 80 * 81 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 82 * pointing the hardware to a buffer to continue executing after the 83 * engine registers are restored in a context restore sequence. This is 84 * currently not used in the driver. 85 * 86 * - Other: There are WAs that, due to their nature, cannot be applied from a 87 * central place. Those are peppered around the rest of the code, as needed. 88 * Workarounds related to the display IP are the main example. 89 * 90 * .. [1] Technically, some registers are powercontext saved & restored, so they 91 * survive a suspend/resume. In practice, writing them again is not too 92 * costly and simplifies things, so it's the approach taken in the driver. 93 */ 94 95 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 96 const char *name, const char *engine_name) 97 { 98 wal->gt = gt; 99 wal->name = name; 100 wal->engine_name = engine_name; 101 } 102 103 #define WA_LIST_CHUNK (1 << 4) 104 105 static void wa_init_finish(struct i915_wa_list *wal) 106 { 107 /* Trim unused entries. */ 108 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 109 struct i915_wa *list = kmemdup(wal->list, 110 wal->count * sizeof(*list), 111 GFP_KERNEL); 112 113 if (list) { 114 kfree(wal->list); 115 wal->list = list; 116 } 117 } 118 119 if (!wal->count) 120 return; 121 122 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 123 wal->wa_count, wal->name, wal->engine_name); 124 } 125 126 static enum forcewake_domains 127 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 128 { 129 enum forcewake_domains fw = 0; 130 struct i915_wa *wa; 131 unsigned int i; 132 133 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 134 fw |= intel_uncore_forcewake_for_reg(uncore, 135 wa->reg, 136 FW_REG_READ | 137 FW_REG_WRITE); 138 139 return fw; 140 } 141 142 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 143 { 144 unsigned int addr = i915_mmio_reg_offset(wa->reg); 145 struct drm_i915_private *i915 = wal->gt->i915; 146 unsigned int start = 0, end = wal->count; 147 const unsigned int grow = WA_LIST_CHUNK; 148 struct i915_wa *wa_; 149 150 GEM_BUG_ON(!is_power_of_2(grow)); 151 152 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 153 struct i915_wa *list; 154 155 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 156 GFP_KERNEL); 157 if (!list) { 158 drm_err(&i915->drm, "No space for workaround init!\n"); 159 return; 160 } 161 162 if (wal->list) { 163 memcpy(list, wal->list, sizeof(*wa) * wal->count); 164 kfree(wal->list); 165 } 166 167 wal->list = list; 168 } 169 170 while (start < end) { 171 unsigned int mid = start + (end - start) / 2; 172 173 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 174 start = mid + 1; 175 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 176 end = mid; 177 } else { 178 wa_ = &wal->list[mid]; 179 180 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 181 drm_err(&i915->drm, 182 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 183 i915_mmio_reg_offset(wa_->reg), 184 wa_->clr, wa_->set); 185 186 wa_->set &= ~wa->clr; 187 } 188 189 wal->wa_count++; 190 wa_->set |= wa->set; 191 wa_->clr |= wa->clr; 192 wa_->read |= wa->read; 193 return; 194 } 195 } 196 197 wal->wa_count++; 198 wa_ = &wal->list[wal->count++]; 199 *wa_ = *wa; 200 201 while (wa_-- > wal->list) { 202 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 203 i915_mmio_reg_offset(wa_[1].reg)); 204 if (i915_mmio_reg_offset(wa_[1].reg) > 205 i915_mmio_reg_offset(wa_[0].reg)) 206 break; 207 208 swap(wa_[1], wa_[0]); 209 } 210 } 211 212 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 213 u32 clear, u32 set, u32 read_mask, bool masked_reg) 214 { 215 struct i915_wa wa = { 216 .reg = reg, 217 .clr = clear, 218 .set = set, 219 .read = read_mask, 220 .masked_reg = masked_reg, 221 }; 222 223 _wa_add(wal, &wa); 224 } 225 226 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 227 u32 clear, u32 set, u32 read_mask, bool masked_reg) 228 { 229 struct i915_wa wa = { 230 .mcr_reg = reg, 231 .clr = clear, 232 .set = set, 233 .read = read_mask, 234 .masked_reg = masked_reg, 235 .is_mcr = 1, 236 }; 237 238 _wa_add(wal, &wa); 239 } 240 241 static void 242 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 243 { 244 wa_add(wal, reg, clear, set, clear | set, false); 245 } 246 247 static void 248 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 249 { 250 wa_mcr_add(wal, reg, clear, set, clear | set, false); 251 } 252 253 static void 254 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 255 { 256 wa_write_clr_set(wal, reg, ~0, set); 257 } 258 259 static void 260 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 261 { 262 wa_mcr_write_clr_set(wal, reg, ~0, set); 263 } 264 265 static void 266 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 267 { 268 wa_write_clr_set(wal, reg, set, set); 269 } 270 271 static void 272 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 273 { 274 wa_mcr_write_clr_set(wal, reg, set, set); 275 } 276 277 static void 278 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 279 { 280 wa_write_clr_set(wal, reg, clr, 0); 281 } 282 283 static void 284 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 285 { 286 wa_mcr_write_clr_set(wal, reg, clr, 0); 287 } 288 289 /* 290 * WA operations on "masked register". A masked register has the upper 16 bits 291 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 292 * portion of the register without a rmw: you simply write in the upper 16 bits 293 * the mask of bits you are going to modify. 294 * 295 * The wa_masked_* family of functions already does the necessary operations to 296 * calculate the mask based on the parameters passed, so user only has to 297 * provide the lower 16 bits of that register. 298 */ 299 300 static void 301 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 302 { 303 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 304 } 305 306 static void 307 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 308 { 309 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 310 } 311 312 static void 313 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 314 { 315 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 316 } 317 318 static void 319 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 320 { 321 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 322 } 323 324 static void 325 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 326 u32 mask, u32 val) 327 { 328 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 329 } 330 331 static void 332 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 333 u32 mask, u32 val) 334 { 335 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 336 } 337 338 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 339 struct i915_wa_list *wal) 340 { 341 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 342 } 343 344 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 345 struct i915_wa_list *wal) 346 { 347 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 348 } 349 350 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 351 struct i915_wa_list *wal) 352 { 353 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 354 355 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 356 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 357 358 /* WaDisablePartialInstShootdown:bdw,chv */ 359 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 360 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 361 362 /* Use Force Non-Coherent whenever executing a 3D context. This is a 363 * workaround for a possible hang in the unlikely event a TLB 364 * invalidation occurs during a PSD flush. 365 */ 366 /* WaForceEnableNonCoherent:bdw,chv */ 367 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 368 wa_masked_en(wal, HDC_CHICKEN0, 369 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 370 HDC_FORCE_NON_COHERENT); 371 372 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 373 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 374 * polygons in the same 8x4 pixel/sample area to be processed without 375 * stalling waiting for the earlier ones to write to Hierarchical Z 376 * buffer." 377 * 378 * This optimization is off by default for BDW and CHV; turn it on. 379 */ 380 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 381 382 /* Wa4x4STCOptimizationDisable:bdw,chv */ 383 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 384 385 /* 386 * BSpec recommends 8x4 when MSAA is used, 387 * however in practice 16x4 seems fastest. 388 * 389 * Note that PS/WM thread counts depend on the WIZ hashing 390 * disable bit, which we don't touch here, but it's good 391 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 392 */ 393 wa_masked_field_set(wal, GEN7_GT_MODE, 394 GEN6_WIZ_HASHING_MASK, 395 GEN6_WIZ_HASHING_16x4); 396 } 397 398 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 399 struct i915_wa_list *wal) 400 { 401 struct drm_i915_private *i915 = engine->i915; 402 403 gen8_ctx_workarounds_init(engine, wal); 404 405 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 406 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 407 408 /* WaDisableDopClockGating:bdw 409 * 410 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 411 * to disable EUTC clock gating. 412 */ 413 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 414 DOP_CLOCK_GATING_DISABLE); 415 416 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 417 GEN8_SAMPLER_POWER_BYPASS_DIS); 418 419 wa_masked_en(wal, HDC_CHICKEN0, 420 /* WaForceContextSaveRestoreNonCoherent:bdw */ 421 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 422 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 423 (IS_BROADWELL_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 424 } 425 426 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 427 struct i915_wa_list *wal) 428 { 429 gen8_ctx_workarounds_init(engine, wal); 430 431 /* WaDisableThreadStallDopClockGating:chv */ 432 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 433 434 /* Improve HiZ throughput on CHV. */ 435 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 436 } 437 438 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 439 struct i915_wa_list *wal) 440 { 441 struct drm_i915_private *i915 = engine->i915; 442 443 if (HAS_LLC(i915)) { 444 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 445 * 446 * Must match Display Engine. See 447 * WaCompressedResourceDisplayNewHashMode. 448 */ 449 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 450 GEN9_PBE_COMPRESSED_HASH_SELECTION); 451 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 452 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 453 } 454 455 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 456 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 457 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 458 FLOW_CONTROL_ENABLE | 459 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 460 461 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 462 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 463 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 464 GEN9_ENABLE_YV12_BUGFIX | 465 GEN9_ENABLE_GPGPU_PREEMPTION); 466 467 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 468 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 469 wa_masked_en(wal, CACHE_MODE_1, 470 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 471 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 472 473 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 474 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 475 GEN9_CCS_TLB_PREFETCH_ENABLE); 476 477 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 478 wa_masked_en(wal, HDC_CHICKEN0, 479 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 480 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 481 482 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 483 * both tied to WaForceContextSaveRestoreNonCoherent 484 * in some hsds for skl. We keep the tie for all gen9. The 485 * documentation is a bit hazy and so we want to get common behaviour, 486 * even though there is no clear evidence we would need both on kbl/bxt. 487 * This area has been source of system hangs so we play it safe 488 * and mimic the skl regardless of what bspec says. 489 * 490 * Use Force Non-Coherent whenever executing a 3D context. This 491 * is a workaround for a possible hang in the unlikely event 492 * a TLB invalidation occurs during a PSD flush. 493 */ 494 495 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 496 wa_masked_en(wal, HDC_CHICKEN0, 497 HDC_FORCE_NON_COHERENT); 498 499 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 500 if (IS_SKYLAKE(i915) || 501 IS_KABYLAKE(i915) || 502 IS_COFFEELAKE(i915) || 503 IS_COMETLAKE(i915)) 504 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 505 GEN8_SAMPLER_POWER_BYPASS_DIS); 506 507 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 508 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 509 510 /* 511 * Supporting preemption with fine-granularity requires changes in the 512 * batch buffer programming. Since we can't break old userspace, we 513 * need to set our default preemption level to safe value. Userspace is 514 * still able to use more fine-grained preemption levels, since in 515 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 516 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 517 * not real HW workarounds, but merely a way to start using preemption 518 * while maintaining old contract with userspace. 519 */ 520 521 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 522 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 523 524 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 525 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 526 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 527 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 528 529 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 530 if (IS_GEN9_LP(i915)) 531 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 532 } 533 534 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 535 struct i915_wa_list *wal) 536 { 537 struct intel_gt *gt = engine->gt; 538 u8 vals[3] = { 0, 0, 0 }; 539 unsigned int i; 540 541 for (i = 0; i < 3; i++) { 542 u8 ss; 543 544 /* 545 * Only consider slices where one, and only one, subslice has 7 546 * EUs 547 */ 548 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 549 continue; 550 551 /* 552 * subslice_7eu[i] != 0 (because of the check above) and 553 * ss_max == 4 (maximum number of subslices possible per slice) 554 * 555 * -> 0 <= ss <= 3; 556 */ 557 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 558 vals[i] = 3 - ss; 559 } 560 561 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 562 return; 563 564 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 565 wa_masked_field_set(wal, GEN7_GT_MODE, 566 GEN9_IZ_HASHING_MASK(2) | 567 GEN9_IZ_HASHING_MASK(1) | 568 GEN9_IZ_HASHING_MASK(0), 569 GEN9_IZ_HASHING(2, vals[2]) | 570 GEN9_IZ_HASHING(1, vals[1]) | 571 GEN9_IZ_HASHING(0, vals[0])); 572 } 573 574 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 575 struct i915_wa_list *wal) 576 { 577 gen9_ctx_workarounds_init(engine, wal); 578 skl_tune_iz_hashing(engine, wal); 579 } 580 581 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 582 struct i915_wa_list *wal) 583 { 584 gen9_ctx_workarounds_init(engine, wal); 585 586 /* WaDisableThreadStallDopClockGating:bxt */ 587 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 588 STALL_DOP_GATING_DISABLE); 589 590 /* WaToEnableHwFixForPushConstHWBug:bxt */ 591 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 592 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 593 } 594 595 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 596 struct i915_wa_list *wal) 597 { 598 struct drm_i915_private *i915 = engine->i915; 599 600 gen9_ctx_workarounds_init(engine, wal); 601 602 /* WaToEnableHwFixForPushConstHWBug:kbl */ 603 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 604 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 605 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 606 607 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 608 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 609 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 610 } 611 612 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 613 struct i915_wa_list *wal) 614 { 615 gen9_ctx_workarounds_init(engine, wal); 616 617 /* WaToEnableHwFixForPushConstHWBug:glk */ 618 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 619 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 620 } 621 622 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 623 struct i915_wa_list *wal) 624 { 625 gen9_ctx_workarounds_init(engine, wal); 626 627 /* WaToEnableHwFixForPushConstHWBug:cfl */ 628 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 629 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 630 631 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 632 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 633 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 634 } 635 636 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 637 struct i915_wa_list *wal) 638 { 639 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 640 wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); 641 642 /* WaForceEnableNonCoherent:icl 643 * This is not the same workaround as in early Gen9 platforms, where 644 * lacking this could cause system hangs, but coherency performance 645 * overhead is high and only a few compute workloads really need it 646 * (the register is whitelisted in hardware now, so UMDs can opt in 647 * for coherency if they have a good reason). 648 */ 649 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 650 651 /* WaEnableFloatBlendOptimization:icl */ 652 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 653 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 654 0 /* write-only, so skip validation */, 655 true); 656 657 /* WaDisableGPGPUMidThreadPreemption:icl */ 658 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 659 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 660 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 661 662 /* allow headerless messages for preemptible GPGPU context */ 663 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 664 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 665 666 /* Wa_1604278689:icl,ehl */ 667 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 668 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 669 0, 670 0xFFFFFFFF); 671 672 /* Wa_1406306137:icl,ehl */ 673 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 674 } 675 676 /* 677 * These settings aren't actually workarounds, but general tuning settings that 678 * need to be programmed on dg2 platform. 679 */ 680 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 681 struct i915_wa_list *wal) 682 { 683 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 684 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 685 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 686 wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, 687 FF_MODE2_TDS_TIMER_128); 688 } 689 690 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 691 struct i915_wa_list *wal) 692 { 693 struct drm_i915_private *i915 = engine->i915; 694 695 /* 696 * Wa_1409142259:tgl,dg1,adl-p 697 * Wa_1409347922:tgl,dg1,adl-p 698 * Wa_1409252684:tgl,dg1,adl-p 699 * Wa_1409217633:tgl,dg1,adl-p 700 * Wa_1409207793:tgl,dg1,adl-p 701 * Wa_1409178076:tgl,dg1,adl-p 702 * Wa_1408979724:tgl,dg1,adl-p 703 * Wa_14010443199:tgl,rkl,dg1,adl-p 704 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 705 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 706 */ 707 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 708 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 709 710 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 711 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 712 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 713 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 714 715 /* 716 * Wa_16011163337 - GS_TIMER 717 * 718 * TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we 719 * need to program it even on those that don't explicitly list that 720 * workaround. 721 * 722 * Note that the programming of GEN12_FF_MODE2 is further modified 723 * according to the FF_MODE2 guidance given by Wa_1608008084. 724 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 725 * value when read from the CPU. 726 * 727 * The default value for this register is zero for all fields. 728 * So instead of doing a RMW we should just write the desired values 729 * for TDS and GS timers. Note that since the readback can't be trusted, 730 * the clear mask is just set to ~0 to make sure other bits are not 731 * inadvertently set. For the same reason read verification is ignored. 732 */ 733 wa_add(wal, 734 GEN12_FF_MODE2, 735 ~0, 736 FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224, 737 0, false); 738 739 if (!IS_DG1(i915)) { 740 /* Wa_1806527549 */ 741 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 742 743 /* Wa_1606376872 */ 744 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); 745 } 746 } 747 748 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 749 struct i915_wa_list *wal) 750 { 751 gen12_ctx_workarounds_init(engine, wal); 752 753 /* Wa_1409044764 */ 754 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 755 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 756 757 /* Wa_22010493298 */ 758 wa_masked_en(wal, HIZ_CHICKEN, 759 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 760 } 761 762 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 763 struct i915_wa_list *wal) 764 { 765 dg2_ctx_gt_tuning_init(engine, wal); 766 767 /* Wa_16013271637:dg2 */ 768 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 769 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 770 771 /* Wa_14014947963:dg2 */ 772 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 773 774 /* Wa_18018764978:dg2 */ 775 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 776 777 /* Wa_15010599737:dg2 */ 778 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 779 780 /* Wa_18019271663:dg2 */ 781 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 782 } 783 784 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine, 785 struct i915_wa_list *wal) 786 { 787 struct intel_gt *gt = engine->gt; 788 789 dg2_ctx_gt_tuning_init(engine, wal); 790 791 /* 792 * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in 793 * gen12_emit_indirect_ctx_rcs() rather than here on some early 794 * steppings. 795 */ 796 if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 797 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))) 798 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); 799 } 800 801 static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine, 802 struct i915_wa_list *wal) 803 { 804 struct intel_gt *gt = engine->gt; 805 806 xelpg_ctx_gt_tuning_init(engine, wal); 807 808 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 809 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 810 /* Wa_14014947963 */ 811 wa_masked_field_set(wal, VF_PREEMPTION, 812 PREEMPTION_VERTEX_COUNT, 0x4000); 813 814 /* Wa_16013271637 */ 815 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 816 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 817 818 /* Wa_18019627453 */ 819 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); 820 821 /* Wa_18018764978 */ 822 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 823 } 824 825 /* Wa_18019271663 */ 826 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 827 } 828 829 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 830 struct i915_wa_list *wal) 831 { 832 /* 833 * This is a "fake" workaround defined by software to ensure we 834 * maintain reliable, backward-compatible behavior for userspace with 835 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 836 * 837 * The per-context setting of MI_MODE[12] determines whether the bits 838 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 839 * in the traditional manner or whether they should instead use a new 840 * tgl+ meaning that breaks backward compatibility, but allows nesting 841 * into 3rd-level batchbuffers. When this new capability was first 842 * added in TGL, it remained off by default unless a context 843 * intentionally opted in to the new behavior. However Xe_HPG now 844 * flips this on by default and requires that we explicitly opt out if 845 * we don't want the new behavior. 846 * 847 * From a SW perspective, we want to maintain the backward-compatible 848 * behavior for userspace, so we'll apply a fake workaround to set it 849 * back to the legacy behavior on platforms where the hardware default 850 * is to break compatibility. At the moment there is no Linux 851 * userspace that utilizes third-level batchbuffers, so this will avoid 852 * userspace from needing to make any changes. using the legacy 853 * meaning is the correct thing to do. If/when we have userspace 854 * consumers that want to utilize third-level batch nesting, we can 855 * provide a context parameter to allow them to opt-in. 856 */ 857 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 858 } 859 860 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 861 struct i915_wa_list *wal) 862 { 863 u8 mocs; 864 865 /* 866 * Some blitter commands do not have a field for MOCS, those 867 * commands will use MOCS index pointed by BLIT_CCTL. 868 * BLIT_CCTL registers are needed to be programmed to un-cached. 869 */ 870 if (engine->class == COPY_ENGINE_CLASS) { 871 mocs = engine->gt->mocs.uc_index; 872 wa_write_clr_set(wal, 873 BLIT_CCTL(engine->mmio_base), 874 BLIT_CCTL_MASK, 875 BLIT_CCTL_MOCS(mocs, mocs)); 876 } 877 } 878 879 /* 880 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 881 * defined by the hardware team, but it programming general context registers. 882 * Adding those context register programming in context workaround 883 * allow us to use the wa framework for proper application and validation. 884 */ 885 static void 886 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 887 struct i915_wa_list *wal) 888 { 889 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 890 fakewa_disable_nestedbb_mode(engine, wal); 891 892 gen12_ctx_gt_mocs_init(engine, wal); 893 } 894 895 static void 896 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 897 struct i915_wa_list *wal, 898 const char *name) 899 { 900 struct drm_i915_private *i915 = engine->i915; 901 902 wa_init_start(wal, engine->gt, name, engine->name); 903 904 /* Applies to all engines */ 905 /* 906 * Fake workarounds are not the actual workaround but 907 * programming of context registers using workaround framework. 908 */ 909 if (GRAPHICS_VER(i915) >= 12) 910 gen12_ctx_gt_fake_wa_init(engine, wal); 911 912 if (engine->class != RENDER_CLASS) 913 goto done; 914 915 if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) 916 xelpg_ctx_workarounds_init(engine, wal); 917 else if (IS_PONTEVECCHIO(i915)) 918 ; /* noop; none at this time */ 919 else if (IS_DG2(i915)) 920 dg2_ctx_workarounds_init(engine, wal); 921 else if (IS_XEHPSDV(i915)) 922 ; /* noop; none at this time */ 923 else if (IS_DG1(i915)) 924 dg1_ctx_workarounds_init(engine, wal); 925 else if (GRAPHICS_VER(i915) == 12) 926 gen12_ctx_workarounds_init(engine, wal); 927 else if (GRAPHICS_VER(i915) == 11) 928 icl_ctx_workarounds_init(engine, wal); 929 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 930 cfl_ctx_workarounds_init(engine, wal); 931 else if (IS_GEMINILAKE(i915)) 932 glk_ctx_workarounds_init(engine, wal); 933 else if (IS_KABYLAKE(i915)) 934 kbl_ctx_workarounds_init(engine, wal); 935 else if (IS_BROXTON(i915)) 936 bxt_ctx_workarounds_init(engine, wal); 937 else if (IS_SKYLAKE(i915)) 938 skl_ctx_workarounds_init(engine, wal); 939 else if (IS_CHERRYVIEW(i915)) 940 chv_ctx_workarounds_init(engine, wal); 941 else if (IS_BROADWELL(i915)) 942 bdw_ctx_workarounds_init(engine, wal); 943 else if (GRAPHICS_VER(i915) == 7) 944 gen7_ctx_workarounds_init(engine, wal); 945 else if (GRAPHICS_VER(i915) == 6) 946 gen6_ctx_workarounds_init(engine, wal); 947 else if (GRAPHICS_VER(i915) < 8) 948 ; 949 else 950 MISSING_CASE(GRAPHICS_VER(i915)); 951 952 done: 953 wa_init_finish(wal); 954 } 955 956 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 957 { 958 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 959 } 960 961 int intel_engine_emit_ctx_wa(struct i915_request *rq) 962 { 963 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 964 struct intel_uncore *uncore = rq->engine->uncore; 965 enum forcewake_domains fw; 966 unsigned long flags; 967 struct i915_wa *wa; 968 unsigned int i; 969 u32 *cs; 970 int ret; 971 972 if (wal->count == 0) 973 return 0; 974 975 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 976 if (ret) 977 return ret; 978 979 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 980 if (IS_ERR(cs)) 981 return PTR_ERR(cs); 982 983 fw = wal_get_fw_for_rmw(uncore, wal); 984 985 intel_gt_mcr_lock(wal->gt, &flags); 986 spin_lock(&uncore->lock); 987 intel_uncore_forcewake_get__locked(uncore, fw); 988 989 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 990 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 991 u32 val; 992 993 /* Skip reading the register if it's not really needed */ 994 if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) { 995 val = wa->set; 996 } else { 997 val = wa->is_mcr ? 998 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) : 999 intel_uncore_read_fw(uncore, wa->reg); 1000 val &= ~wa->clr; 1001 val |= wa->set; 1002 } 1003 1004 *cs++ = i915_mmio_reg_offset(wa->reg); 1005 *cs++ = val; 1006 } 1007 *cs++ = MI_NOOP; 1008 1009 intel_uncore_forcewake_put__locked(uncore, fw); 1010 spin_unlock(&uncore->lock); 1011 intel_gt_mcr_unlock(wal->gt, flags); 1012 1013 intel_ring_advance(rq, cs); 1014 1015 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 1016 if (ret) 1017 return ret; 1018 1019 return 0; 1020 } 1021 1022 static void 1023 gen4_gt_workarounds_init(struct intel_gt *gt, 1024 struct i915_wa_list *wal) 1025 { 1026 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 1027 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 1028 } 1029 1030 static void 1031 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1032 { 1033 gen4_gt_workarounds_init(gt, wal); 1034 1035 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 1036 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 1037 } 1038 1039 static void 1040 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1041 { 1042 g4x_gt_workarounds_init(gt, wal); 1043 1044 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 1045 } 1046 1047 static void 1048 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1049 { 1050 } 1051 1052 static void 1053 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1054 { 1055 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 1056 wa_masked_dis(wal, 1057 GEN7_COMMON_SLICE_CHICKEN1, 1058 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 1059 1060 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 1061 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 1062 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 1063 1064 /* WaForceL3Serialization:ivb */ 1065 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1066 } 1067 1068 static void 1069 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1070 { 1071 /* WaForceL3Serialization:vlv */ 1072 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1073 1074 /* 1075 * WaIncreaseL3CreditsForVLVB0:vlv 1076 * This is the hardware default actually. 1077 */ 1078 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1079 } 1080 1081 static void 1082 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1083 { 1084 /* L3 caching of data atomics doesn't work -- disable it. */ 1085 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1086 1087 wa_add(wal, 1088 HSW_ROW_CHICKEN3, 0, 1089 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1090 0 /* XXX does this reg exist? */, true); 1091 1092 /* WaVSRefCountFullforceMissDisable:hsw */ 1093 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1094 } 1095 1096 static void 1097 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1098 { 1099 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1100 unsigned int slice, subslice; 1101 u32 mcr, mcr_mask; 1102 1103 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1104 1105 /* 1106 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1107 * Before any MMIO read into slice/subslice specific registers, MCR 1108 * packet control register needs to be programmed to point to any 1109 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1110 * This means each subsequent MMIO read will be forwarded to an 1111 * specific s/ss combination, but this is OK since these registers 1112 * are consistent across s/ss in almost all cases. In the rare 1113 * occasions, such as INSTDONE, where this value is dependent 1114 * on s/ss combo, the read should be done with read_subslice_reg. 1115 */ 1116 slice = ffs(sseu->slice_mask) - 1; 1117 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1118 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1119 GEM_BUG_ON(!subslice); 1120 subslice--; 1121 1122 /* 1123 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1124 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1125 */ 1126 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1127 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1128 1129 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1130 1131 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1132 } 1133 1134 static void 1135 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1136 { 1137 struct drm_i915_private *i915 = gt->i915; 1138 1139 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1140 gen9_wa_init_mcr(i915, wal); 1141 1142 /* WaDisableKillLogic:bxt,skl,kbl */ 1143 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1144 wa_write_or(wal, 1145 GAM_ECOCHK, 1146 ECOCHK_DIS_TLB); 1147 1148 if (HAS_LLC(i915)) { 1149 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1150 * 1151 * Must match Display Engine. See 1152 * WaCompressedResourceDisplayNewHashMode. 1153 */ 1154 wa_write_or(wal, 1155 MMCD_MISC_CTRL, 1156 MMCD_PCLA | MMCD_HOTSPOT_EN); 1157 } 1158 1159 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1160 wa_write_or(wal, 1161 GAM_ECOCHK, 1162 BDW_DISABLE_HDC_INVALIDATION); 1163 } 1164 1165 static void 1166 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1167 { 1168 gen9_gt_workarounds_init(gt, wal); 1169 1170 /* WaDisableGafsUnitClkGating:skl */ 1171 wa_write_or(wal, 1172 GEN7_UCGCTL4, 1173 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1174 1175 /* WaInPlaceDecompressionHang:skl */ 1176 if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1177 wa_write_or(wal, 1178 GEN9_GAMT_ECO_REG_RW_IA, 1179 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1180 } 1181 1182 static void 1183 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1184 { 1185 gen9_gt_workarounds_init(gt, wal); 1186 1187 /* WaDisableDynamicCreditSharing:kbl */ 1188 if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1189 wa_write_or(wal, 1190 GAMT_CHKN_BIT_REG, 1191 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1192 1193 /* WaDisableGafsUnitClkGating:kbl */ 1194 wa_write_or(wal, 1195 GEN7_UCGCTL4, 1196 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1197 1198 /* WaInPlaceDecompressionHang:kbl */ 1199 wa_write_or(wal, 1200 GEN9_GAMT_ECO_REG_RW_IA, 1201 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1202 } 1203 1204 static void 1205 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1206 { 1207 gen9_gt_workarounds_init(gt, wal); 1208 } 1209 1210 static void 1211 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1212 { 1213 gen9_gt_workarounds_init(gt, wal); 1214 1215 /* WaDisableGafsUnitClkGating:cfl */ 1216 wa_write_or(wal, 1217 GEN7_UCGCTL4, 1218 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1219 1220 /* WaInPlaceDecompressionHang:cfl */ 1221 wa_write_or(wal, 1222 GEN9_GAMT_ECO_REG_RW_IA, 1223 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1224 } 1225 1226 static void __set_mcr_steering(struct i915_wa_list *wal, 1227 i915_reg_t steering_reg, 1228 unsigned int slice, unsigned int subslice) 1229 { 1230 u32 mcr, mcr_mask; 1231 1232 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1233 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1234 1235 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1236 } 1237 1238 static void debug_dump_steering(struct intel_gt *gt) 1239 { 1240 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1241 1242 if (drm_debug_enabled(DRM_UT_DRIVER)) 1243 intel_gt_mcr_report_steering(&p, gt, false); 1244 } 1245 1246 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1247 unsigned int slice, unsigned int subslice) 1248 { 1249 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1250 1251 gt->default_steering.groupid = slice; 1252 gt->default_steering.instanceid = subslice; 1253 1254 debug_dump_steering(gt); 1255 } 1256 1257 static void 1258 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1259 { 1260 const struct sseu_dev_info *sseu = >->info.sseu; 1261 unsigned int subslice; 1262 1263 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1264 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1265 1266 /* 1267 * Although a platform may have subslices, we need to always steer 1268 * reads to the lowest instance that isn't fused off. When Render 1269 * Power Gating is enabled, grabbing forcewake will only power up a 1270 * single subslice (the "minconfig") if there isn't a real workload 1271 * that needs to be run; this means that if we steer register reads to 1272 * one of the higher subslices, we run the risk of reading back 0's or 1273 * random garbage. 1274 */ 1275 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1276 1277 /* 1278 * If the subslice we picked above also steers us to a valid L3 bank, 1279 * then we can just rely on the default steering and won't need to 1280 * worry about explicitly re-steering L3BANK reads later. 1281 */ 1282 if (gt->info.l3bank_mask & BIT(subslice)) 1283 gt->steering_table[L3BANK] = NULL; 1284 1285 __add_mcr_wa(gt, wal, 0, subslice); 1286 } 1287 1288 static void 1289 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1290 { 1291 const struct sseu_dev_info *sseu = >->info.sseu; 1292 unsigned long slice, subslice = 0, slice_mask = 0; 1293 u32 lncf_mask = 0; 1294 int i; 1295 1296 /* 1297 * On Xe_HP the steering increases in complexity. There are now several 1298 * more units that require steering and we're not guaranteed to be able 1299 * to find a common setting for all of them. These are: 1300 * - GSLICE (fusable) 1301 * - DSS (sub-unit within gslice; fusable) 1302 * - L3 Bank (fusable) 1303 * - MSLICE (fusable) 1304 * - LNCF (sub-unit within mslice; always present if mslice is present) 1305 * 1306 * We'll do our default/implicit steering based on GSLICE (in the 1307 * sliceid field) and DSS (in the subsliceid field). If we can 1308 * find overlap between the valid MSLICE and/or LNCF values with 1309 * a suitable GSLICE, then we can just re-use the default value and 1310 * skip and explicit steering at runtime. 1311 * 1312 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1313 * a valid sliceid value. DSS steering is the only type of steering 1314 * that utilizes the 'subsliceid' bits. 1315 * 1316 * Also note that, even though the steering domain is called "GSlice" 1317 * and it is encoded in the register using the gslice format, the spec 1318 * says that the combined (geometry | compute) fuse should be used to 1319 * select the steering. 1320 */ 1321 1322 /* Find the potential gslice candidates */ 1323 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1324 GEN_DSS_PER_GSLICE); 1325 1326 /* 1327 * Find the potential LNCF candidates. Either LNCF within a valid 1328 * mslice is fine. 1329 */ 1330 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1331 lncf_mask |= (0x3 << (i * 2)); 1332 1333 /* 1334 * Are there any sliceid values that work for both GSLICE and LNCF 1335 * steering? 1336 */ 1337 if (slice_mask & lncf_mask) { 1338 slice_mask &= lncf_mask; 1339 gt->steering_table[LNCF] = NULL; 1340 } 1341 1342 /* How about sliceid values that also work for MSLICE steering? */ 1343 if (slice_mask & gt->info.mslice_mask) { 1344 slice_mask &= gt->info.mslice_mask; 1345 gt->steering_table[MSLICE] = NULL; 1346 } 1347 1348 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1349 gt->steering_table[GAM] = NULL; 1350 1351 slice = __ffs(slice_mask); 1352 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1353 GEN_DSS_PER_GSLICE; 1354 1355 __add_mcr_wa(gt, wal, slice, subslice); 1356 1357 /* 1358 * SQIDI ranges are special because they use different steering 1359 * registers than everything else we work with. On XeHP SDV and 1360 * DG2-G10, any value in the steering registers will work fine since 1361 * all instances are present, but DG2-G11 only has SQIDI instances at 1362 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1363 * we'll just steer to a hardcoded "2" since that value will work 1364 * everywhere. 1365 */ 1366 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1367 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1368 1369 /* 1370 * On DG2, GAM registers have a dedicated steering control register 1371 * and must always be programmed to a hardcoded groupid of "1." 1372 */ 1373 if (IS_DG2(gt->i915)) 1374 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1375 } 1376 1377 static void 1378 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1379 { 1380 unsigned int dss; 1381 1382 /* 1383 * Setup implicit steering for COMPUTE and DSS ranges to the first 1384 * non-fused-off DSS. All other types of MCR registers will be 1385 * explicitly steered. 1386 */ 1387 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1388 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1389 } 1390 1391 static void 1392 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1393 { 1394 struct drm_i915_private *i915 = gt->i915; 1395 1396 icl_wa_init_mcr(gt, wal); 1397 1398 /* WaModifyGamTlbPartitioning:icl */ 1399 wa_write_clr_set(wal, 1400 GEN11_GACB_PERF_CTRL, 1401 GEN11_HASH_CTRL_MASK, 1402 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1403 1404 /* Wa_1405766107:icl 1405 * Formerly known as WaCL2SFHalfMaxAlloc 1406 */ 1407 wa_write_or(wal, 1408 GEN11_LSN_UNSLCVC, 1409 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1410 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1411 1412 /* Wa_220166154:icl 1413 * Formerly known as WaDisCtxReload 1414 */ 1415 wa_write_or(wal, 1416 GEN8_GAMW_ECO_DEV_RW_IA, 1417 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1418 1419 /* Wa_1406463099:icl 1420 * Formerly known as WaGamTlbPendError 1421 */ 1422 wa_write_or(wal, 1423 GAMT_CHKN_BIT_REG, 1424 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1425 1426 /* 1427 * Wa_1408615072:icl,ehl (vsunit) 1428 * Wa_1407596294:icl,ehl (hsunit) 1429 */ 1430 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1431 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1432 1433 /* Wa_1407352427:icl,ehl */ 1434 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1435 PSDUNIT_CLKGATE_DIS); 1436 1437 /* Wa_1406680159:icl,ehl */ 1438 wa_mcr_write_or(wal, 1439 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1440 GWUNIT_CLKGATE_DIS); 1441 1442 /* Wa_1607087056:icl,ehl,jsl */ 1443 if (IS_ICELAKE(i915) || 1444 ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && 1445 IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))) 1446 wa_write_or(wal, 1447 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1448 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1449 1450 /* 1451 * This is not a documented workaround, but rather an optimization 1452 * to reduce sampler power. 1453 */ 1454 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1455 } 1456 1457 /* 1458 * Though there are per-engine instances of these registers, 1459 * they retain their value through engine resets and should 1460 * only be provided on the GT workaround list rather than 1461 * the engine-specific workaround list. 1462 */ 1463 static void 1464 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1465 { 1466 struct intel_engine_cs *engine; 1467 int id; 1468 1469 for_each_engine(engine, gt, id) { 1470 if (engine->class != VIDEO_DECODE_CLASS || 1471 (engine->instance % 2)) 1472 continue; 1473 1474 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1475 IECPUNIT_CLKGATE_DIS); 1476 } 1477 } 1478 1479 static void 1480 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1481 { 1482 icl_wa_init_mcr(gt, wal); 1483 1484 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1485 wa_14011060649(gt, wal); 1486 1487 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1488 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1489 1490 /* 1491 * Wa_14015795083 1492 * 1493 * Firmware on some gen12 platforms locks the MISCCPCTL register, 1494 * preventing i915 from modifying it for this workaround. Skip the 1495 * readback verification for this workaround on debug builds; if the 1496 * workaround doesn't stick due to firmware behavior, it's not an error 1497 * that we want CI to flag. 1498 */ 1499 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, 1500 0, 0, false); 1501 } 1502 1503 static void 1504 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1505 { 1506 gen12_gt_workarounds_init(gt, wal); 1507 1508 /* Wa_1409420604:dg1 */ 1509 wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, 1510 CPSSUNIT_CLKGATE_DIS); 1511 1512 /* Wa_1408615072:dg1 */ 1513 /* Empirical testing shows this register is unaffected by engine reset. */ 1514 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); 1515 } 1516 1517 static void 1518 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1519 { 1520 struct drm_i915_private *i915 = gt->i915; 1521 1522 xehp_init_mcr(gt, wal); 1523 1524 /* Wa_1409757795:xehpsdv */ 1525 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1526 1527 /* Wa_18011725039:xehpsdv */ 1528 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 1529 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 1530 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 1531 } 1532 1533 /* Wa_16011155590:xehpsdv */ 1534 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1535 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1536 TSGUNIT_CLKGATE_DIS); 1537 1538 /* Wa_14011780169:xehpsdv */ 1539 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1540 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1541 GAMTLBVDBOX7_CLKGATE_DIS | 1542 GAMTLBVDBOX6_CLKGATE_DIS | 1543 GAMTLBVDBOX5_CLKGATE_DIS | 1544 GAMTLBVDBOX4_CLKGATE_DIS | 1545 GAMTLBVDBOX3_CLKGATE_DIS | 1546 GAMTLBVDBOX2_CLKGATE_DIS | 1547 GAMTLBVDBOX1_CLKGATE_DIS | 1548 GAMTLBVDBOX0_CLKGATE_DIS | 1549 GAMTLBKCR_CLKGATE_DIS | 1550 GAMTLBGUC_CLKGATE_DIS | 1551 GAMTLBBLT_CLKGATE_DIS); 1552 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1553 GAMTLBGFXA1_CLKGATE_DIS | 1554 GAMTLBCOMPA0_CLKGATE_DIS | 1555 GAMTLBCOMPA1_CLKGATE_DIS | 1556 GAMTLBCOMPB0_CLKGATE_DIS | 1557 GAMTLBCOMPB1_CLKGATE_DIS | 1558 GAMTLBCOMPC0_CLKGATE_DIS | 1559 GAMTLBCOMPC1_CLKGATE_DIS | 1560 GAMTLBCOMPD0_CLKGATE_DIS | 1561 GAMTLBCOMPD1_CLKGATE_DIS | 1562 GAMTLBMERT_CLKGATE_DIS | 1563 GAMTLBVEBOX3_CLKGATE_DIS | 1564 GAMTLBVEBOX2_CLKGATE_DIS | 1565 GAMTLBVEBOX1_CLKGATE_DIS | 1566 GAMTLBVEBOX0_CLKGATE_DIS); 1567 } 1568 1569 /* Wa_16012725990:xehpsdv */ 1570 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1571 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1572 1573 /* Wa_14011060649:xehpsdv */ 1574 wa_14011060649(gt, wal); 1575 1576 /* Wa_14012362059:xehpsdv */ 1577 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1578 1579 /* Wa_14014368820:xehpsdv */ 1580 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1581 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1582 1583 /* Wa_14010670810:xehpsdv */ 1584 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1585 } 1586 1587 static void 1588 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1589 { 1590 xehp_init_mcr(gt, wal); 1591 1592 /* Wa_14011060649:dg2 */ 1593 wa_14011060649(gt, wal); 1594 1595 if (IS_DG2_G10(gt->i915)) { 1596 /* Wa_22010523718:dg2 */ 1597 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1598 CG3DDISCFEG_CLKGATE_DIS); 1599 1600 /* Wa_14011006942:dg2 */ 1601 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1602 DSS_ROUTER_CLKGATE_DIS); 1603 } 1604 1605 /* Wa_14014830051:dg2 */ 1606 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1607 1608 /* Wa_14015795083 */ 1609 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1610 1611 /* Wa_18018781329 */ 1612 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1613 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1614 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1615 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1616 1617 /* Wa_1509235366:dg2 */ 1618 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, 1619 INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); 1620 1621 /* Wa_14010648519:dg2 */ 1622 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 1623 } 1624 1625 static void 1626 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1627 { 1628 pvc_init_mcr(gt, wal); 1629 1630 /* Wa_14015795083 */ 1631 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1632 1633 /* Wa_18018781329 */ 1634 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1635 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1636 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1637 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1638 1639 /* Wa_16016694945 */ 1640 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 1641 } 1642 1643 static void 1644 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1645 { 1646 /* Wa_14018575942 / Wa_18018781329 */ 1647 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1648 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1649 1650 /* Wa_22016670082 */ 1651 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); 1652 1653 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 1654 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 1655 /* Wa_14014830051 */ 1656 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1657 1658 /* Wa_14015795083 */ 1659 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1660 } 1661 1662 /* 1663 * Unlike older platforms, we no longer setup implicit steering here; 1664 * all MCR accesses are explicitly steered. 1665 */ 1666 debug_dump_steering(gt); 1667 } 1668 1669 static void 1670 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1671 { 1672 /* 1673 * Wa_14018778641 1674 * Wa_18018781329 1675 * 1676 * Note that although these registers are MCR on the primary 1677 * GT, the media GT's versions are regular singleton registers. 1678 */ 1679 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); 1680 1681 debug_dump_steering(gt); 1682 } 1683 1684 /* 1685 * The bspec performance guide has recommended MMIO tuning settings. These 1686 * aren't truly "workarounds" but we want to program them through the 1687 * workaround infrastructure to make sure they're (re)applied at the proper 1688 * times. 1689 * 1690 * The programming in this function is for settings that persist through 1691 * engine resets and also are not part of any engine's register state context. 1692 * I.e., settings that only need to be re-applied in the event of a full GT 1693 * reset. 1694 */ 1695 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) 1696 { 1697 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) { 1698 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1699 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1700 } 1701 1702 if (IS_PONTEVECCHIO(gt->i915)) { 1703 wa_mcr_write(wal, XEHPC_L3SCRUB, 1704 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 1705 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); 1706 } 1707 1708 if (IS_DG2(gt->i915)) { 1709 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1710 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1711 } 1712 } 1713 1714 static void 1715 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1716 { 1717 struct drm_i915_private *i915 = gt->i915; 1718 1719 gt_tuning_settings(gt, wal); 1720 1721 if (gt->type == GT_MEDIA) { 1722 if (MEDIA_VER(i915) >= 13) 1723 xelpmp_gt_workarounds_init(gt, wal); 1724 else 1725 MISSING_CASE(MEDIA_VER(i915)); 1726 1727 return; 1728 } 1729 1730 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) 1731 xelpg_gt_workarounds_init(gt, wal); 1732 else if (IS_PONTEVECCHIO(i915)) 1733 pvc_gt_workarounds_init(gt, wal); 1734 else if (IS_DG2(i915)) 1735 dg2_gt_workarounds_init(gt, wal); 1736 else if (IS_XEHPSDV(i915)) 1737 xehpsdv_gt_workarounds_init(gt, wal); 1738 else if (IS_DG1(i915)) 1739 dg1_gt_workarounds_init(gt, wal); 1740 else if (GRAPHICS_VER(i915) == 12) 1741 gen12_gt_workarounds_init(gt, wal); 1742 else if (GRAPHICS_VER(i915) == 11) 1743 icl_gt_workarounds_init(gt, wal); 1744 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1745 cfl_gt_workarounds_init(gt, wal); 1746 else if (IS_GEMINILAKE(i915)) 1747 glk_gt_workarounds_init(gt, wal); 1748 else if (IS_KABYLAKE(i915)) 1749 kbl_gt_workarounds_init(gt, wal); 1750 else if (IS_BROXTON(i915)) 1751 gen9_gt_workarounds_init(gt, wal); 1752 else if (IS_SKYLAKE(i915)) 1753 skl_gt_workarounds_init(gt, wal); 1754 else if (IS_HASWELL(i915)) 1755 hsw_gt_workarounds_init(gt, wal); 1756 else if (IS_VALLEYVIEW(i915)) 1757 vlv_gt_workarounds_init(gt, wal); 1758 else if (IS_IVYBRIDGE(i915)) 1759 ivb_gt_workarounds_init(gt, wal); 1760 else if (GRAPHICS_VER(i915) == 6) 1761 snb_gt_workarounds_init(gt, wal); 1762 else if (GRAPHICS_VER(i915) == 5) 1763 ilk_gt_workarounds_init(gt, wal); 1764 else if (IS_G4X(i915)) 1765 g4x_gt_workarounds_init(gt, wal); 1766 else if (GRAPHICS_VER(i915) == 4) 1767 gen4_gt_workarounds_init(gt, wal); 1768 else if (GRAPHICS_VER(i915) <= 8) 1769 ; 1770 else 1771 MISSING_CASE(GRAPHICS_VER(i915)); 1772 } 1773 1774 void intel_gt_init_workarounds(struct intel_gt *gt) 1775 { 1776 struct i915_wa_list *wal = >->wa_list; 1777 1778 wa_init_start(wal, gt, "GT", "global"); 1779 gt_init_workarounds(gt, wal); 1780 wa_init_finish(wal); 1781 } 1782 1783 static bool 1784 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1785 const char *name, const char *from) 1786 { 1787 if ((cur ^ wa->set) & wa->read) { 1788 drm_err(>->i915->drm, 1789 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1790 name, from, i915_mmio_reg_offset(wa->reg), 1791 cur, cur & wa->read, wa->set & wa->read); 1792 1793 return false; 1794 } 1795 1796 return true; 1797 } 1798 1799 static void wa_list_apply(const struct i915_wa_list *wal) 1800 { 1801 struct intel_gt *gt = wal->gt; 1802 struct intel_uncore *uncore = gt->uncore; 1803 enum forcewake_domains fw; 1804 unsigned long flags; 1805 struct i915_wa *wa; 1806 unsigned int i; 1807 1808 if (!wal->count) 1809 return; 1810 1811 fw = wal_get_fw_for_rmw(uncore, wal); 1812 1813 intel_gt_mcr_lock(gt, &flags); 1814 spin_lock(&uncore->lock); 1815 intel_uncore_forcewake_get__locked(uncore, fw); 1816 1817 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1818 u32 val, old = 0; 1819 1820 /* open-coded rmw due to steering */ 1821 if (wa->clr) 1822 old = wa->is_mcr ? 1823 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1824 intel_uncore_read_fw(uncore, wa->reg); 1825 val = (old & ~wa->clr) | wa->set; 1826 if (val != old || !wa->clr) { 1827 if (wa->is_mcr) 1828 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1829 else 1830 intel_uncore_write_fw(uncore, wa->reg, val); 1831 } 1832 1833 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1834 u32 val = wa->is_mcr ? 1835 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1836 intel_uncore_read_fw(uncore, wa->reg); 1837 1838 wa_verify(gt, wa, val, wal->name, "application"); 1839 } 1840 } 1841 1842 intel_uncore_forcewake_put__locked(uncore, fw); 1843 spin_unlock(&uncore->lock); 1844 intel_gt_mcr_unlock(gt, flags); 1845 } 1846 1847 void intel_gt_apply_workarounds(struct intel_gt *gt) 1848 { 1849 wa_list_apply(>->wa_list); 1850 } 1851 1852 static bool wa_list_verify(struct intel_gt *gt, 1853 const struct i915_wa_list *wal, 1854 const char *from) 1855 { 1856 struct intel_uncore *uncore = gt->uncore; 1857 struct i915_wa *wa; 1858 enum forcewake_domains fw; 1859 unsigned long flags; 1860 unsigned int i; 1861 bool ok = true; 1862 1863 fw = wal_get_fw_for_rmw(uncore, wal); 1864 1865 intel_gt_mcr_lock(gt, &flags); 1866 spin_lock(&uncore->lock); 1867 intel_uncore_forcewake_get__locked(uncore, fw); 1868 1869 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1870 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1871 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1872 intel_uncore_read_fw(uncore, wa->reg), 1873 wal->name, from); 1874 1875 intel_uncore_forcewake_put__locked(uncore, fw); 1876 spin_unlock(&uncore->lock); 1877 intel_gt_mcr_unlock(gt, flags); 1878 1879 return ok; 1880 } 1881 1882 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1883 { 1884 return wa_list_verify(gt, >->wa_list, from); 1885 } 1886 1887 __maybe_unused 1888 static bool is_nonpriv_flags_valid(u32 flags) 1889 { 1890 /* Check only valid flag bits are set */ 1891 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1892 return false; 1893 1894 /* NB: Only 3 out of 4 enum values are valid for access field */ 1895 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1896 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1897 return false; 1898 1899 return true; 1900 } 1901 1902 static void 1903 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1904 { 1905 struct i915_wa wa = { 1906 .reg = reg 1907 }; 1908 1909 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1910 return; 1911 1912 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1913 return; 1914 1915 wa.reg.reg |= flags; 1916 _wa_add(wal, &wa); 1917 } 1918 1919 static void 1920 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1921 { 1922 struct i915_wa wa = { 1923 .mcr_reg = reg, 1924 .is_mcr = 1, 1925 }; 1926 1927 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1928 return; 1929 1930 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1931 return; 1932 1933 wa.mcr_reg.reg |= flags; 1934 _wa_add(wal, &wa); 1935 } 1936 1937 static void 1938 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1939 { 1940 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1941 } 1942 1943 static void 1944 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1945 { 1946 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1947 } 1948 1949 static void gen9_whitelist_build(struct i915_wa_list *w) 1950 { 1951 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1952 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1953 1954 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1955 whitelist_reg(w, GEN8_CS_CHICKEN1); 1956 1957 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1958 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1959 1960 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1961 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1962 } 1963 1964 static void skl_whitelist_build(struct intel_engine_cs *engine) 1965 { 1966 struct i915_wa_list *w = &engine->whitelist; 1967 1968 if (engine->class != RENDER_CLASS) 1969 return; 1970 1971 gen9_whitelist_build(w); 1972 1973 /* WaDisableLSQCROPERFforOCL:skl */ 1974 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1975 } 1976 1977 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1978 { 1979 if (engine->class != RENDER_CLASS) 1980 return; 1981 1982 gen9_whitelist_build(&engine->whitelist); 1983 } 1984 1985 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1986 { 1987 struct i915_wa_list *w = &engine->whitelist; 1988 1989 if (engine->class != RENDER_CLASS) 1990 return; 1991 1992 gen9_whitelist_build(w); 1993 1994 /* WaDisableLSQCROPERFforOCL:kbl */ 1995 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1996 } 1997 1998 static void glk_whitelist_build(struct intel_engine_cs *engine) 1999 { 2000 struct i915_wa_list *w = &engine->whitelist; 2001 2002 if (engine->class != RENDER_CLASS) 2003 return; 2004 2005 gen9_whitelist_build(w); 2006 2007 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 2008 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2009 } 2010 2011 static void cfl_whitelist_build(struct intel_engine_cs *engine) 2012 { 2013 struct i915_wa_list *w = &engine->whitelist; 2014 2015 if (engine->class != RENDER_CLASS) 2016 return; 2017 2018 gen9_whitelist_build(w); 2019 2020 /* 2021 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 2022 * 2023 * This covers 4 register which are next to one another : 2024 * - PS_INVOCATION_COUNT 2025 * - PS_INVOCATION_COUNT_UDW 2026 * - PS_DEPTH_COUNT 2027 * - PS_DEPTH_COUNT_UDW 2028 */ 2029 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2030 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2031 RING_FORCE_TO_NONPRIV_RANGE_4); 2032 } 2033 2034 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 2035 { 2036 struct i915_wa_list *w = &engine->whitelist; 2037 2038 if (engine->class != RENDER_CLASS) 2039 whitelist_reg_ext(w, 2040 RING_CTX_TIMESTAMP(engine->mmio_base), 2041 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2042 } 2043 2044 static void cml_whitelist_build(struct intel_engine_cs *engine) 2045 { 2046 allow_read_ctx_timestamp(engine); 2047 2048 cfl_whitelist_build(engine); 2049 } 2050 2051 static void icl_whitelist_build(struct intel_engine_cs *engine) 2052 { 2053 struct i915_wa_list *w = &engine->whitelist; 2054 2055 allow_read_ctx_timestamp(engine); 2056 2057 switch (engine->class) { 2058 case RENDER_CLASS: 2059 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 2060 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 2061 2062 /* WaAllowUMDToModifySamplerMode:icl */ 2063 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2064 2065 /* WaEnableStateCacheRedirectToCS:icl */ 2066 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2067 2068 /* 2069 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2070 * 2071 * This covers 4 register which are next to one another : 2072 * - PS_INVOCATION_COUNT 2073 * - PS_INVOCATION_COUNT_UDW 2074 * - PS_DEPTH_COUNT 2075 * - PS_DEPTH_COUNT_UDW 2076 */ 2077 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2078 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2079 RING_FORCE_TO_NONPRIV_RANGE_4); 2080 break; 2081 2082 case VIDEO_DECODE_CLASS: 2083 /* hucStatusRegOffset */ 2084 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2085 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2086 /* hucUKernelHdrInfoRegOffset */ 2087 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2088 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2089 /* hucStatus2RegOffset */ 2090 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2091 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2092 break; 2093 2094 default: 2095 break; 2096 } 2097 } 2098 2099 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2100 { 2101 struct i915_wa_list *w = &engine->whitelist; 2102 2103 allow_read_ctx_timestamp(engine); 2104 2105 switch (engine->class) { 2106 case RENDER_CLASS: 2107 /* 2108 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2109 * Wa_1408556865:tgl 2110 * 2111 * This covers 4 registers which are next to one another : 2112 * - PS_INVOCATION_COUNT 2113 * - PS_INVOCATION_COUNT_UDW 2114 * - PS_DEPTH_COUNT 2115 * - PS_DEPTH_COUNT_UDW 2116 */ 2117 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2118 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2119 RING_FORCE_TO_NONPRIV_RANGE_4); 2120 2121 /* 2122 * Wa_1808121037:tgl 2123 * Wa_14012131227:dg1 2124 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2125 */ 2126 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2127 2128 /* Wa_1806527549:tgl */ 2129 whitelist_reg(w, HIZ_CHICKEN); 2130 2131 /* Required by recommended tuning setting (not a workaround) */ 2132 whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3); 2133 2134 break; 2135 default: 2136 break; 2137 } 2138 } 2139 2140 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2141 { 2142 struct i915_wa_list *w = &engine->whitelist; 2143 2144 switch (engine->class) { 2145 case RENDER_CLASS: 2146 /* Required by recommended tuning setting (not a workaround) */ 2147 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2148 2149 break; 2150 default: 2151 break; 2152 } 2153 } 2154 2155 static void blacklist_trtt(struct intel_engine_cs *engine) 2156 { 2157 struct i915_wa_list *w = &engine->whitelist; 2158 2159 /* 2160 * Prevent read/write access to [0x4400, 0x4600) which covers 2161 * the TRTT range across all engines. Note that normally userspace 2162 * cannot access the other engines' trtt control, but for simplicity 2163 * we cover the entire range on each engine. 2164 */ 2165 whitelist_reg_ext(w, _MMIO(0x4400), 2166 RING_FORCE_TO_NONPRIV_DENY | 2167 RING_FORCE_TO_NONPRIV_RANGE_64); 2168 whitelist_reg_ext(w, _MMIO(0x4500), 2169 RING_FORCE_TO_NONPRIV_DENY | 2170 RING_FORCE_TO_NONPRIV_RANGE_64); 2171 } 2172 2173 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2174 { 2175 /* Wa_16014440446:pvc */ 2176 blacklist_trtt(engine); 2177 } 2178 2179 static void xelpg_whitelist_build(struct intel_engine_cs *engine) 2180 { 2181 struct i915_wa_list *w = &engine->whitelist; 2182 2183 switch (engine->class) { 2184 case RENDER_CLASS: 2185 /* Required by recommended tuning setting (not a workaround) */ 2186 whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); 2187 2188 break; 2189 default: 2190 break; 2191 } 2192 } 2193 2194 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2195 { 2196 struct drm_i915_private *i915 = engine->i915; 2197 struct i915_wa_list *w = &engine->whitelist; 2198 2199 wa_init_start(w, engine->gt, "whitelist", engine->name); 2200 2201 if (engine->gt->type == GT_MEDIA) 2202 ; /* none yet */ 2203 else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74))) 2204 xelpg_whitelist_build(engine); 2205 else if (IS_PONTEVECCHIO(i915)) 2206 pvc_whitelist_build(engine); 2207 else if (IS_DG2(i915)) 2208 dg2_whitelist_build(engine); 2209 else if (IS_XEHPSDV(i915)) 2210 ; /* none needed */ 2211 else if (GRAPHICS_VER(i915) == 12) 2212 tgl_whitelist_build(engine); 2213 else if (GRAPHICS_VER(i915) == 11) 2214 icl_whitelist_build(engine); 2215 else if (IS_COMETLAKE(i915)) 2216 cml_whitelist_build(engine); 2217 else if (IS_COFFEELAKE(i915)) 2218 cfl_whitelist_build(engine); 2219 else if (IS_GEMINILAKE(i915)) 2220 glk_whitelist_build(engine); 2221 else if (IS_KABYLAKE(i915)) 2222 kbl_whitelist_build(engine); 2223 else if (IS_BROXTON(i915)) 2224 bxt_whitelist_build(engine); 2225 else if (IS_SKYLAKE(i915)) 2226 skl_whitelist_build(engine); 2227 else if (GRAPHICS_VER(i915) <= 8) 2228 ; 2229 else 2230 MISSING_CASE(GRAPHICS_VER(i915)); 2231 2232 wa_init_finish(w); 2233 } 2234 2235 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2236 { 2237 const struct i915_wa_list *wal = &engine->whitelist; 2238 struct intel_uncore *uncore = engine->uncore; 2239 const u32 base = engine->mmio_base; 2240 struct i915_wa *wa; 2241 unsigned int i; 2242 2243 if (!wal->count) 2244 return; 2245 2246 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2247 intel_uncore_write(uncore, 2248 RING_FORCE_TO_NONPRIV(base, i), 2249 i915_mmio_reg_offset(wa->reg)); 2250 2251 /* And clear the rest just in case of garbage */ 2252 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2253 intel_uncore_write(uncore, 2254 RING_FORCE_TO_NONPRIV(base, i), 2255 i915_mmio_reg_offset(RING_NOPID(base))); 2256 } 2257 2258 /* 2259 * engine_fake_wa_init(), a place holder to program the registers 2260 * which are not part of an official workaround defined by the 2261 * hardware team. 2262 * Adding programming of those register inside workaround will 2263 * allow utilizing wa framework to proper application and verification. 2264 */ 2265 static void 2266 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2267 { 2268 u8 mocs_w, mocs_r; 2269 2270 /* 2271 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2272 * by the command streamer when executing commands that don't have 2273 * a way to explicitly specify a MOCS setting. The default should 2274 * usually reference whichever MOCS entry corresponds to uncached 2275 * behavior, although use of a WB cached entry is recommended by the 2276 * spec in certain circumstances on specific platforms. 2277 */ 2278 if (GRAPHICS_VER(engine->i915) >= 12) { 2279 mocs_r = engine->gt->mocs.uc_index; 2280 mocs_w = engine->gt->mocs.uc_index; 2281 2282 if (HAS_L3_CCS_READ(engine->i915) && 2283 engine->class == COMPUTE_CLASS) { 2284 mocs_r = engine->gt->mocs.wb_index; 2285 2286 /* 2287 * Even on the few platforms where MOCS 0 is a 2288 * legitimate table entry, it's never the correct 2289 * setting to use here; we can assume the MOCS init 2290 * just forgot to initialize wb_index. 2291 */ 2292 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2293 } 2294 2295 wa_masked_field_set(wal, 2296 RING_CMD_CCTL(engine->mmio_base), 2297 CMD_CCTL_MOCS_MASK, 2298 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2299 } 2300 } 2301 2302 static void 2303 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2304 { 2305 struct drm_i915_private *i915 = engine->i915; 2306 struct intel_gt *gt = engine->gt; 2307 2308 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2309 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { 2310 /* Wa_22014600077 */ 2311 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2312 ENABLE_EU_COUNT_FOR_TDL_FLUSH); 2313 } 2314 2315 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2316 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2317 IS_DG2(i915)) { 2318 /* Wa_1509727124 */ 2319 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2320 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2321 } 2322 2323 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2324 IS_DG2(i915)) { 2325 /* Wa_22012856258 */ 2326 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2327 GEN12_DISABLE_READ_SUPPRESSION); 2328 } 2329 2330 if (IS_DG2(i915)) { 2331 /* 2332 * Wa_22010960976:dg2 2333 * Wa_14013347512:dg2 2334 */ 2335 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2336 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2337 } 2338 2339 if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) { 2340 /* Wa_22014600077:dg2 */ 2341 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2342 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2343 0 /* Wa_14012342262 write-only reg, so skip verification */, 2344 true); 2345 } 2346 2347 if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2348 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2349 /* 2350 * Wa_1606700617:tgl,dg1,adl-p 2351 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2352 * Wa_14010826681:tgl,dg1,rkl,adl-p 2353 * Wa_18019627453:dg2 2354 */ 2355 wa_masked_en(wal, 2356 GEN9_CS_DEBUG_MODE1, 2357 FF_DOP_CLOCK_GATE_DISABLE); 2358 } 2359 2360 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2361 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2362 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2363 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2364 2365 /* 2366 * Wa_1407928979:tgl A* 2367 * Wa_18011464164:tgl[B0+],dg1[B0+] 2368 * Wa_22010931296:tgl[B0+],dg1[B0+] 2369 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2370 */ 2371 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2372 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2373 2374 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2375 wa_mcr_masked_en(wal, 2376 GEN10_SAMPLER_MODE, 2377 ENABLE_SMALLPL); 2378 } 2379 2380 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2381 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2382 /* Wa_1409804808 */ 2383 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2384 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2385 2386 /* Wa_14010229206 */ 2387 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2388 } 2389 2390 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2391 /* 2392 * Wa_1607297627 2393 * 2394 * On TGL and RKL there are multiple entries for this WA in the 2395 * BSpec; some indicate this is an A0-only WA, others indicate 2396 * it applies to all steppings so we trust the "all steppings." 2397 */ 2398 wa_masked_en(wal, 2399 RING_PSMI_CTL(RENDER_RING_BASE), 2400 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2401 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2402 } 2403 2404 if (GRAPHICS_VER(i915) == 11) { 2405 /* This is not an Wa. Enable for better image quality */ 2406 wa_masked_en(wal, 2407 _3D_CHICKEN3, 2408 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2409 2410 /* 2411 * Wa_1405543622:icl 2412 * Formerly known as WaGAPZPriorityScheme 2413 */ 2414 wa_write_or(wal, 2415 GEN8_GARBCNTL, 2416 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2417 2418 /* 2419 * Wa_1604223664:icl 2420 * Formerly known as WaL3BankAddressHashing 2421 */ 2422 wa_write_clr_set(wal, 2423 GEN8_GARBCNTL, 2424 GEN11_HASH_CTRL_EXCL_MASK, 2425 GEN11_HASH_CTRL_EXCL_BIT0); 2426 wa_write_clr_set(wal, 2427 GEN11_GLBLINVL, 2428 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2429 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2430 2431 /* 2432 * Wa_1405733216:icl 2433 * Formerly known as WaDisableCleanEvicts 2434 */ 2435 wa_mcr_write_or(wal, 2436 GEN8_L3SQCREG4, 2437 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2438 2439 /* Wa_1606682166:icl */ 2440 wa_write_or(wal, 2441 GEN7_SARCHKMD, 2442 GEN7_DISABLE_SAMPLER_PREFETCH); 2443 2444 /* Wa_1409178092:icl */ 2445 wa_mcr_write_clr_set(wal, 2446 GEN11_SCRATCH2, 2447 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2448 0); 2449 2450 /* WaEnable32PlaneMode:icl */ 2451 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2452 GEN11_ENABLE_32_PLANE_MODE); 2453 2454 /* 2455 * Wa_1408767742:icl[a2..forever],ehl[all] 2456 * Wa_1605460711:icl[a0..c0] 2457 */ 2458 wa_write_or(wal, 2459 GEN7_FF_THREAD_MODE, 2460 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2461 2462 /* Wa_22010271021 */ 2463 wa_masked_en(wal, 2464 GEN9_CS_DEBUG_MODE1, 2465 FF_DOP_CLOCK_GATE_DISABLE); 2466 } 2467 2468 /* 2469 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2470 * beyond) allow the kernel-mode driver to choose between two different 2471 * options for controlling preemption granularity and behavior. 2472 * 2473 * Option 1 (hardware default): 2474 * Preemption settings are controlled in a global manner via 2475 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2476 * and settings chosen by the kernel-mode driver will apply to all 2477 * userspace clients. 2478 * 2479 * Option 2: 2480 * Preemption settings are controlled on a per-context basis via 2481 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2482 * context switch and is writable by userspace (e.g., via 2483 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2484 * which allows different userspace drivers/clients to select 2485 * different settings, or to change those settings on the fly in 2486 * response to runtime needs. This option was known by name 2487 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2488 * that name is somewhat misleading as other non-granularity 2489 * preemption settings are also impacted by this decision. 2490 * 2491 * On Linux, our policy has always been to let userspace drivers 2492 * control preemption granularity/settings (Option 2). This was 2493 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2494 * userspace developed before object-level preemption was enabled would 2495 * not behave well if i915 were to go with Option 1 and enable that 2496 * preemption in a global manner). On gen9 each context would have 2497 * object-level preemption disabled by default (see 2498 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2499 * userspace drivers could opt-in to object-level preemption as they 2500 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2501 * even though it is no longer necessary for ABI compatibility when 2502 * enabling a new platform, it does ensure that userspace will be able 2503 * to implement any workarounds that show up requiring temporary 2504 * adjustments to preemption behavior at runtime. 2505 * 2506 * Notes/Workarounds: 2507 * - Wa_14015141709: On DG2 and early steppings of MTL, 2508 * CS_CHICKEN1[0] does not disable object-level preemption as 2509 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2510 * using Option 1). Effectively this means userspace is unable 2511 * to disable object-level preemption on these platforms/steppings 2512 * despite the setting here. 2513 * 2514 * - Wa_16013994831: May require that userspace program 2515 * CS_CHICKEN1[10] when certain runtime conditions are true. 2516 * Userspace requires Option 2 to be in effect for their update of 2517 * CS_CHICKEN1[10] to be effective. 2518 * 2519 * Other workarounds may appear in the future that will also require 2520 * Option 2 behavior to allow proper userspace implementation. 2521 */ 2522 if (GRAPHICS_VER(i915) >= 9) 2523 wa_masked_en(wal, 2524 GEN7_FF_SLICE_CS_CHICKEN1, 2525 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2526 2527 if (IS_SKYLAKE(i915) || 2528 IS_KABYLAKE(i915) || 2529 IS_COFFEELAKE(i915) || 2530 IS_COMETLAKE(i915)) { 2531 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2532 wa_write_or(wal, 2533 GEN8_GARBCNTL, 2534 GEN9_GAPS_TSV_CREDIT_DISABLE); 2535 } 2536 2537 if (IS_BROXTON(i915)) { 2538 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2539 wa_masked_en(wal, 2540 FF_SLICE_CS_CHICKEN2, 2541 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2542 } 2543 2544 if (GRAPHICS_VER(i915) == 9) { 2545 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2546 wa_masked_en(wal, 2547 GEN9_CSFE_CHICKEN1_RCS, 2548 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2549 2550 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2551 wa_mcr_write_or(wal, 2552 BDW_SCRATCH1, 2553 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2554 2555 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2556 if (IS_GEN9_LP(i915)) 2557 wa_mcr_write_clr_set(wal, 2558 GEN8_L3SQCREG1, 2559 L3_PRIO_CREDITS_MASK, 2560 L3_GENERAL_PRIO_CREDITS(62) | 2561 L3_HIGH_PRIO_CREDITS(2)); 2562 2563 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2564 wa_mcr_write_or(wal, 2565 GEN8_L3SQCREG4, 2566 GEN8_LQSC_FLUSH_COHERENT_LINES); 2567 2568 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2569 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2570 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2571 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2572 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2573 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2574 EVICTION_PERF_FIX_ENABLE, 0); 2575 } 2576 2577 if (IS_HASWELL(i915)) { 2578 /* WaSampleCChickenBitEnable:hsw */ 2579 wa_masked_en(wal, 2580 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2581 2582 wa_masked_dis(wal, 2583 CACHE_MODE_0_GEN7, 2584 /* enable HiZ Raw Stall Optimization */ 2585 HIZ_RAW_STALL_OPT_DISABLE); 2586 } 2587 2588 if (IS_VALLEYVIEW(i915)) { 2589 /* WaDisableEarlyCull:vlv */ 2590 wa_masked_en(wal, 2591 _3D_CHICKEN3, 2592 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2593 2594 /* 2595 * WaVSThreadDispatchOverride:ivb,vlv 2596 * 2597 * This actually overrides the dispatch 2598 * mode for all thread types. 2599 */ 2600 wa_write_clr_set(wal, 2601 GEN7_FF_THREAD_MODE, 2602 GEN7_FF_SCHED_MASK, 2603 GEN7_FF_TS_SCHED_HW | 2604 GEN7_FF_VS_SCHED_HW | 2605 GEN7_FF_DS_SCHED_HW); 2606 2607 /* WaPsdDispatchEnable:vlv */ 2608 /* WaDisablePSDDualDispatchEnable:vlv */ 2609 wa_masked_en(wal, 2610 GEN7_HALF_SLICE_CHICKEN1, 2611 GEN7_MAX_PS_THREAD_DEP | 2612 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2613 } 2614 2615 if (IS_IVYBRIDGE(i915)) { 2616 /* WaDisableEarlyCull:ivb */ 2617 wa_masked_en(wal, 2618 _3D_CHICKEN3, 2619 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2620 2621 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2622 /* enable HiZ Raw Stall Optimization */ 2623 wa_masked_dis(wal, 2624 CACHE_MODE_0_GEN7, 2625 HIZ_RAW_STALL_OPT_DISABLE); 2626 } 2627 2628 /* 2629 * WaVSThreadDispatchOverride:ivb,vlv 2630 * 2631 * This actually overrides the dispatch 2632 * mode for all thread types. 2633 */ 2634 wa_write_clr_set(wal, 2635 GEN7_FF_THREAD_MODE, 2636 GEN7_FF_SCHED_MASK, 2637 GEN7_FF_TS_SCHED_HW | 2638 GEN7_FF_VS_SCHED_HW | 2639 GEN7_FF_DS_SCHED_HW); 2640 2641 /* WaDisablePSDDualDispatchEnable:ivb */ 2642 if (IS_IVB_GT1(i915)) 2643 wa_masked_en(wal, 2644 GEN7_HALF_SLICE_CHICKEN1, 2645 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2646 } 2647 2648 if (GRAPHICS_VER(i915) == 7) { 2649 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2650 wa_masked_en(wal, 2651 RING_MODE_GEN7(RENDER_RING_BASE), 2652 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2653 2654 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2655 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2656 2657 /* 2658 * BSpec says this must be set, even though 2659 * WaDisable4x2SubspanOptimization:ivb,hsw 2660 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2661 */ 2662 wa_masked_en(wal, 2663 CACHE_MODE_1, 2664 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2665 2666 /* 2667 * BSpec recommends 8x4 when MSAA is used, 2668 * however in practice 16x4 seems fastest. 2669 * 2670 * Note that PS/WM thread counts depend on the WIZ hashing 2671 * disable bit, which we don't touch here, but it's good 2672 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2673 */ 2674 wa_masked_field_set(wal, 2675 GEN7_GT_MODE, 2676 GEN6_WIZ_HASHING_MASK, 2677 GEN6_WIZ_HASHING_16x4); 2678 } 2679 2680 if (IS_GRAPHICS_VER(i915, 6, 7)) 2681 /* 2682 * We need to disable the AsyncFlip performance optimisations in 2683 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2684 * already be programmed to '1' on all products. 2685 * 2686 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2687 */ 2688 wa_masked_en(wal, 2689 RING_MI_MODE(RENDER_RING_BASE), 2690 ASYNC_FLIP_PERF_DISABLE); 2691 2692 if (GRAPHICS_VER(i915) == 6) { 2693 /* 2694 * Required for the hardware to program scanline values for 2695 * waiting 2696 * WaEnableFlushTlbInvalidationMode:snb 2697 */ 2698 wa_masked_en(wal, 2699 GFX_MODE, 2700 GFX_TLB_INVALIDATE_EXPLICIT); 2701 2702 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2703 wa_masked_en(wal, 2704 _3D_CHICKEN, 2705 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2706 2707 wa_masked_en(wal, 2708 _3D_CHICKEN3, 2709 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2710 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2711 /* 2712 * Bspec says: 2713 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2714 * to normal and 3DSTATE_SF number of SF output attributes 2715 * is more than 16." 2716 */ 2717 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2718 2719 /* 2720 * BSpec recommends 8x4 when MSAA is used, 2721 * however in practice 16x4 seems fastest. 2722 * 2723 * Note that PS/WM thread counts depend on the WIZ hashing 2724 * disable bit, which we don't touch here, but it's good 2725 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2726 */ 2727 wa_masked_field_set(wal, 2728 GEN6_GT_MODE, 2729 GEN6_WIZ_HASHING_MASK, 2730 GEN6_WIZ_HASHING_16x4); 2731 2732 /* WaDisable_RenderCache_OperationalFlush:snb */ 2733 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2734 2735 /* 2736 * From the Sandybridge PRM, volume 1 part 3, page 24: 2737 * "If this bit is set, STCunit will have LRA as replacement 2738 * policy. [...] This bit must be reset. LRA replacement 2739 * policy is not supported." 2740 */ 2741 wa_masked_dis(wal, 2742 CACHE_MODE_0, 2743 CM0_STC_EVICT_DISABLE_LRA_SNB); 2744 } 2745 2746 if (IS_GRAPHICS_VER(i915, 4, 6)) 2747 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2748 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2749 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2750 /* XXX bit doesn't stick on Broadwater */ 2751 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2752 2753 if (GRAPHICS_VER(i915) == 4) 2754 /* 2755 * Disable CONSTANT_BUFFER before it is loaded from the context 2756 * image. For as it is loaded, it is executed and the stored 2757 * address may no longer be valid, leading to a GPU hang. 2758 * 2759 * This imposes the requirement that userspace reload their 2760 * CONSTANT_BUFFER on every batch, fortunately a requirement 2761 * they are already accustomed to from before contexts were 2762 * enabled. 2763 */ 2764 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2765 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2766 0 /* XXX bit doesn't stick on Broadwater */, 2767 true); 2768 } 2769 2770 static void 2771 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2772 { 2773 struct drm_i915_private *i915 = engine->i915; 2774 2775 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2776 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2777 wa_write(wal, 2778 RING_SEMA_WAIT_POLL(engine->mmio_base), 2779 1); 2780 } 2781 } 2782 2783 static void 2784 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2785 { 2786 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2787 /* Wa_14014999345:pvc */ 2788 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2789 } 2790 } 2791 2792 /* 2793 * The bspec performance guide has recommended MMIO tuning settings. These 2794 * aren't truly "workarounds" but we want to program them with the same 2795 * workaround infrastructure to ensure that they're automatically added to 2796 * the GuC save/restore lists, re-applied at the right times, and checked for 2797 * any conflicting programming requested by real workarounds. 2798 * 2799 * Programming settings should be added here only if their registers are not 2800 * part of an engine's register state context. If a register is part of a 2801 * context, then any tuning settings should be programmed in an appropriate 2802 * function invoked by __intel_engine_init_ctx_wa(). 2803 */ 2804 static void 2805 add_render_compute_tuning_settings(struct intel_gt *gt, 2806 struct i915_wa_list *wal) 2807 { 2808 struct drm_i915_private *i915 = gt->i915; 2809 2810 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915)) 2811 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2812 2813 /* 2814 * This tuning setting proves beneficial only on ATS-M designs; the 2815 * default "age based" setting is optimal on regular DG2 and other 2816 * platforms. 2817 */ 2818 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2819 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2820 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2821 2822 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 2823 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 2824 } 2825 2826 /* 2827 * The workarounds in this function apply to shared registers in 2828 * the general render reset domain that aren't tied to a 2829 * specific engine. Since all render+compute engines get reset 2830 * together, and the contents of these registers are lost during 2831 * the shared render domain reset, we'll define such workarounds 2832 * here and then add them to just a single RCS or CCS engine's 2833 * workaround list (whichever engine has the XXXX flag). 2834 */ 2835 static void 2836 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2837 { 2838 struct drm_i915_private *i915 = engine->i915; 2839 struct intel_gt *gt = engine->gt; 2840 2841 add_render_compute_tuning_settings(gt, wal); 2842 2843 if (GRAPHICS_VER(i915) >= 11) { 2844 /* This is not a Wa (although referred to as 2845 * WaSetInidrectStateOverride in places), this allows 2846 * applications that reference sampler states through 2847 * the BindlessSamplerStateBaseAddress to have their 2848 * border color relative to DynamicStateBaseAddress 2849 * rather than BindlessSamplerStateBaseAddress. 2850 * 2851 * Otherwise SAMPLER_STATE border colors have to be 2852 * copied in multiple heaps (DynamicStateBaseAddress & 2853 * BindlessSamplerStateBaseAddress) 2854 * 2855 * BSpec: 46052 2856 */ 2857 wa_mcr_masked_en(wal, 2858 GEN10_SAMPLER_MODE, 2859 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); 2860 } 2861 2862 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) || 2863 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) || 2864 IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74))) 2865 /* Wa_14017856879 */ 2866 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); 2867 2868 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2869 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2870 /* 2871 * Wa_14017066071 2872 * Wa_14017654203 2873 */ 2874 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2875 MTL_DISABLE_SAMPLER_SC_OOO); 2876 2877 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2878 /* Wa_22015279794 */ 2879 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2880 DISABLE_PREFETCH_INTO_IC); 2881 2882 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2883 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2884 IS_DG2(i915)) { 2885 /* Wa_22013037850 */ 2886 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2887 DISABLE_128B_EVICTION_COMMAND_UDW); 2888 2889 /* Wa_18017747507 */ 2890 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 2891 } 2892 2893 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2894 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2895 IS_PONTEVECCHIO(i915) || 2896 IS_DG2(i915)) { 2897 /* Wa_22014226127 */ 2898 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2899 } 2900 2901 if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { 2902 /* Wa_14015227452:dg2,pvc */ 2903 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2904 2905 /* Wa_16015675438:dg2,pvc */ 2906 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2907 } 2908 2909 if (IS_DG2(i915)) { 2910 /* 2911 * Wa_16011620976:dg2_g11 2912 * Wa_22015475538:dg2 2913 */ 2914 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2915 } 2916 2917 if (IS_DG2_G11(i915)) { 2918 /* 2919 * Wa_22012826095:dg2 2920 * Wa_22013059131:dg2 2921 */ 2922 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2923 MAXREQS_PER_BANK, 2924 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2925 2926 /* Wa_22013059131:dg2 */ 2927 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2928 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2929 2930 /* 2931 * Wa_22012654132 2932 * 2933 * Note that register 0xE420 is write-only and cannot be read 2934 * back for verification on DG2 (due to Wa_14012342262), so 2935 * we need to explicitly skip the readback. 2936 */ 2937 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2938 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2939 0 /* write-only, so skip validation */, 2940 true); 2941 } 2942 2943 if (IS_XEHPSDV(i915)) { 2944 /* Wa_1409954639 */ 2945 wa_mcr_masked_en(wal, 2946 GEN8_ROW_CHICKEN, 2947 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2948 2949 /* Wa_1607196519 */ 2950 wa_mcr_masked_en(wal, 2951 GEN9_ROW_CHICKEN4, 2952 GEN12_DISABLE_GRF_CLEAR); 2953 2954 /* Wa_14010449647:xehpsdv */ 2955 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2956 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2957 } 2958 } 2959 2960 static void 2961 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2962 { 2963 if (GRAPHICS_VER(engine->i915) < 4) 2964 return; 2965 2966 engine_fake_wa_init(engine, wal); 2967 2968 /* 2969 * These are common workarounds that just need to applied 2970 * to a single RCS/CCS engine's workaround list since 2971 * they're reset as part of the general render domain reset. 2972 */ 2973 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 2974 general_render_compute_wa_init(engine, wal); 2975 2976 if (engine->class == COMPUTE_CLASS) 2977 ccs_engine_wa_init(engine, wal); 2978 else if (engine->class == RENDER_CLASS) 2979 rcs_engine_wa_init(engine, wal); 2980 else 2981 xcs_engine_wa_init(engine, wal); 2982 } 2983 2984 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2985 { 2986 struct i915_wa_list *wal = &engine->wa_list; 2987 2988 wa_init_start(wal, engine->gt, "engine", engine->name); 2989 engine_init_workarounds(engine, wal); 2990 wa_init_finish(wal); 2991 } 2992 2993 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2994 { 2995 wa_list_apply(&engine->wa_list); 2996 } 2997 2998 static const struct i915_range mcr_ranges_gen8[] = { 2999 { .start = 0x5500, .end = 0x55ff }, 3000 { .start = 0x7000, .end = 0x7fff }, 3001 { .start = 0x9400, .end = 0x97ff }, 3002 { .start = 0xb000, .end = 0xb3ff }, 3003 { .start = 0xe000, .end = 0xe7ff }, 3004 {}, 3005 }; 3006 3007 static const struct i915_range mcr_ranges_gen12[] = { 3008 { .start = 0x8150, .end = 0x815f }, 3009 { .start = 0x9520, .end = 0x955f }, 3010 { .start = 0xb100, .end = 0xb3ff }, 3011 { .start = 0xde80, .end = 0xe8ff }, 3012 { .start = 0x24a00, .end = 0x24a7f }, 3013 {}, 3014 }; 3015 3016 static const struct i915_range mcr_ranges_xehp[] = { 3017 { .start = 0x4000, .end = 0x4aff }, 3018 { .start = 0x5200, .end = 0x52ff }, 3019 { .start = 0x5400, .end = 0x7fff }, 3020 { .start = 0x8140, .end = 0x815f }, 3021 { .start = 0x8c80, .end = 0x8dff }, 3022 { .start = 0x94d0, .end = 0x955f }, 3023 { .start = 0x9680, .end = 0x96ff }, 3024 { .start = 0xb000, .end = 0xb3ff }, 3025 { .start = 0xc800, .end = 0xcfff }, 3026 { .start = 0xd800, .end = 0xd8ff }, 3027 { .start = 0xdc00, .end = 0xffff }, 3028 { .start = 0x17000, .end = 0x17fff }, 3029 { .start = 0x24a00, .end = 0x24a7f }, 3030 {}, 3031 }; 3032 3033 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3034 { 3035 const struct i915_range *mcr_ranges; 3036 int i; 3037 3038 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3039 mcr_ranges = mcr_ranges_xehp; 3040 else if (GRAPHICS_VER(i915) >= 12) 3041 mcr_ranges = mcr_ranges_gen12; 3042 else if (GRAPHICS_VER(i915) >= 8) 3043 mcr_ranges = mcr_ranges_gen8; 3044 else 3045 return false; 3046 3047 /* 3048 * Registers in these ranges are affected by the MCR selector 3049 * which only controls CPU initiated MMIO. Routing does not 3050 * work for CS access so we cannot verify them on this path. 3051 */ 3052 for (i = 0; mcr_ranges[i].start; i++) 3053 if (offset >= mcr_ranges[i].start && 3054 offset <= mcr_ranges[i].end) 3055 return true; 3056 3057 return false; 3058 } 3059 3060 static int 3061 wa_list_srm(struct i915_request *rq, 3062 const struct i915_wa_list *wal, 3063 struct i915_vma *vma) 3064 { 3065 struct drm_i915_private *i915 = rq->i915; 3066 unsigned int i, count = 0; 3067 const struct i915_wa *wa; 3068 u32 srm, *cs; 3069 3070 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3071 if (GRAPHICS_VER(i915) >= 8) 3072 srm++; 3073 3074 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3075 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3076 count++; 3077 } 3078 3079 cs = intel_ring_begin(rq, 4 * count); 3080 if (IS_ERR(cs)) 3081 return PTR_ERR(cs); 3082 3083 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3084 u32 offset = i915_mmio_reg_offset(wa->reg); 3085 3086 if (mcr_range(i915, offset)) 3087 continue; 3088 3089 *cs++ = srm; 3090 *cs++ = offset; 3091 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3092 *cs++ = 0; 3093 } 3094 intel_ring_advance(rq, cs); 3095 3096 return 0; 3097 } 3098 3099 static int engine_wa_list_verify(struct intel_context *ce, 3100 const struct i915_wa_list * const wal, 3101 const char *from) 3102 { 3103 const struct i915_wa *wa; 3104 struct i915_request *rq; 3105 struct i915_vma *vma; 3106 struct i915_gem_ww_ctx ww; 3107 unsigned int i; 3108 u32 *results; 3109 int err; 3110 3111 if (!wal->count) 3112 return 0; 3113 3114 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3115 wal->count * sizeof(u32)); 3116 if (IS_ERR(vma)) 3117 return PTR_ERR(vma); 3118 3119 intel_engine_pm_get(ce->engine); 3120 i915_gem_ww_ctx_init(&ww, false); 3121 retry: 3122 err = i915_gem_object_lock(vma->obj, &ww); 3123 if (err == 0) 3124 err = intel_context_pin_ww(ce, &ww); 3125 if (err) 3126 goto err_pm; 3127 3128 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3129 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3130 if (err) 3131 goto err_unpin; 3132 3133 rq = i915_request_create(ce); 3134 if (IS_ERR(rq)) { 3135 err = PTR_ERR(rq); 3136 goto err_vma; 3137 } 3138 3139 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3140 if (err == 0) 3141 err = wa_list_srm(rq, wal, vma); 3142 3143 i915_request_get(rq); 3144 if (err) 3145 i915_request_set_error_once(rq, err); 3146 i915_request_add(rq); 3147 3148 if (err) 3149 goto err_rq; 3150 3151 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3152 err = -ETIME; 3153 goto err_rq; 3154 } 3155 3156 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3157 if (IS_ERR(results)) { 3158 err = PTR_ERR(results); 3159 goto err_rq; 3160 } 3161 3162 err = 0; 3163 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3164 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 3165 continue; 3166 3167 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3168 err = -ENXIO; 3169 } 3170 3171 i915_gem_object_unpin_map(vma->obj); 3172 3173 err_rq: 3174 i915_request_put(rq); 3175 err_vma: 3176 i915_vma_unpin(vma); 3177 err_unpin: 3178 intel_context_unpin(ce); 3179 err_pm: 3180 if (err == -EDEADLK) { 3181 err = i915_gem_ww_ctx_backoff(&ww); 3182 if (!err) 3183 goto retry; 3184 } 3185 i915_gem_ww_ctx_fini(&ww); 3186 intel_engine_pm_put(ce->engine); 3187 i915_vma_put(vma); 3188 return err; 3189 } 3190 3191 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3192 const char *from) 3193 { 3194 return engine_wa_list_verify(engine->kernel_context, 3195 &engine->wa_list, 3196 from); 3197 } 3198 3199 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3200 #include "selftest_workarounds.c" 3201 #endif 3202