1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_engine_regs.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_gt_mcr.h" 13 #include "intel_gt_regs.h" 14 #include "intel_ring.h" 15 #include "intel_workarounds.h" 16 17 /** 18 * DOC: Hardware workarounds 19 * 20 * This file is intended as a central place to implement most [1]_ of the 21 * required workarounds for hardware to work as originally intended. They fall 22 * in five basic categories depending on how/when they are applied: 23 * 24 * - Workarounds that touch registers that are saved/restored to/from the HW 25 * context image. The list is emitted (via Load Register Immediate commands) 26 * everytime a new context is created. 27 * - GT workarounds. The list of these WAs is applied whenever these registers 28 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 29 * - Display workarounds. The list is applied during display clock-gating 30 * initialization. 31 * - Workarounds that whitelist a privileged register, so that UMDs can manage 32 * them directly. This is just a special case of a MMMIO workaround (as we 33 * write the list of these to/be-whitelisted registers to some special HW 34 * registers). 35 * - Workaround batchbuffers, that get executed automatically by the hardware 36 * on every HW context restore. 37 * 38 * .. [1] Please notice that there are other WAs that, due to their nature, 39 * cannot be applied from a central place. Those are peppered around the rest 40 * of the code, as needed. 41 * 42 * .. [2] Technically, some registers are powercontext saved & restored, so they 43 * survive a suspend/resume. In practice, writing them again is not too 44 * costly and simplifies things. We can revisit this in the future. 45 * 46 * Layout 47 * ~~~~~~ 48 * 49 * Keep things in this file ordered by WA type, as per the above (context, GT, 50 * display, register whitelist, batchbuffer). Then, inside each type, keep the 51 * following order: 52 * 53 * - Infrastructure functions and macros 54 * - WAs per platform in standard gen/chrono order 55 * - Public functions to init or apply the given workaround type. 56 */ 57 58 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 59 { 60 wal->name = name; 61 wal->engine_name = engine_name; 62 } 63 64 #define WA_LIST_CHUNK (1 << 4) 65 66 static void wa_init_finish(struct i915_wa_list *wal) 67 { 68 /* Trim unused entries. */ 69 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 70 struct i915_wa *list = kmemdup(wal->list, 71 wal->count * sizeof(*list), 72 GFP_KERNEL); 73 74 if (list) { 75 kfree(wal->list); 76 wal->list = list; 77 } 78 } 79 80 if (!wal->count) 81 return; 82 83 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 84 wal->wa_count, wal->name, wal->engine_name); 85 } 86 87 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 88 { 89 unsigned int addr = i915_mmio_reg_offset(wa->reg); 90 unsigned int start = 0, end = wal->count; 91 const unsigned int grow = WA_LIST_CHUNK; 92 struct i915_wa *wa_; 93 94 GEM_BUG_ON(!is_power_of_2(grow)); 95 96 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 97 struct i915_wa *list; 98 99 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 100 GFP_KERNEL); 101 if (!list) { 102 DRM_ERROR("No space for workaround init!\n"); 103 return; 104 } 105 106 if (wal->list) { 107 memcpy(list, wal->list, sizeof(*wa) * wal->count); 108 kfree(wal->list); 109 } 110 111 wal->list = list; 112 } 113 114 while (start < end) { 115 unsigned int mid = start + (end - start) / 2; 116 117 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 118 start = mid + 1; 119 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 120 end = mid; 121 } else { 122 wa_ = &wal->list[mid]; 123 124 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 125 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 126 i915_mmio_reg_offset(wa_->reg), 127 wa_->clr, wa_->set); 128 129 wa_->set &= ~wa->clr; 130 } 131 132 wal->wa_count++; 133 wa_->set |= wa->set; 134 wa_->clr |= wa->clr; 135 wa_->read |= wa->read; 136 return; 137 } 138 } 139 140 wal->wa_count++; 141 wa_ = &wal->list[wal->count++]; 142 *wa_ = *wa; 143 144 while (wa_-- > wal->list) { 145 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 146 i915_mmio_reg_offset(wa_[1].reg)); 147 if (i915_mmio_reg_offset(wa_[1].reg) > 148 i915_mmio_reg_offset(wa_[0].reg)) 149 break; 150 151 swap(wa_[1], wa_[0]); 152 } 153 } 154 155 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 156 u32 clear, u32 set, u32 read_mask, bool masked_reg) 157 { 158 struct i915_wa wa = { 159 .reg = reg, 160 .clr = clear, 161 .set = set, 162 .read = read_mask, 163 .masked_reg = masked_reg, 164 }; 165 166 _wa_add(wal, &wa); 167 } 168 169 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 170 u32 clear, u32 set, u32 read_mask, bool masked_reg) 171 { 172 struct i915_wa wa = { 173 .mcr_reg = reg, 174 .clr = clear, 175 .set = set, 176 .read = read_mask, 177 .masked_reg = masked_reg, 178 .is_mcr = 1, 179 }; 180 181 _wa_add(wal, &wa); 182 } 183 184 static void 185 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 186 { 187 wa_add(wal, reg, clear, set, clear, false); 188 } 189 190 static void 191 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 192 { 193 wa_mcr_add(wal, reg, clear, set, clear, false); 194 } 195 196 static void 197 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 198 { 199 wa_write_clr_set(wal, reg, ~0, set); 200 } 201 202 static void 203 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 204 { 205 wa_write_clr_set(wal, reg, set, set); 206 } 207 208 static void 209 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 210 { 211 wa_mcr_write_clr_set(wal, reg, set, set); 212 } 213 214 static void 215 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 216 { 217 wa_write_clr_set(wal, reg, clr, 0); 218 } 219 220 static void 221 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 222 { 223 wa_mcr_write_clr_set(wal, reg, clr, 0); 224 } 225 226 /* 227 * WA operations on "masked register". A masked register has the upper 16 bits 228 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 229 * portion of the register without a rmw: you simply write in the upper 16 bits 230 * the mask of bits you are going to modify. 231 * 232 * The wa_masked_* family of functions already does the necessary operations to 233 * calculate the mask based on the parameters passed, so user only has to 234 * provide the lower 16 bits of that register. 235 */ 236 237 static void 238 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 239 { 240 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 241 } 242 243 static void 244 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 245 { 246 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 247 } 248 249 static void 250 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 251 { 252 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 253 } 254 255 static void 256 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 257 { 258 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 259 } 260 261 static void 262 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 263 u32 mask, u32 val) 264 { 265 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 266 } 267 268 static void 269 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 270 u32 mask, u32 val) 271 { 272 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 273 } 274 275 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 276 struct i915_wa_list *wal) 277 { 278 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 279 } 280 281 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 282 struct i915_wa_list *wal) 283 { 284 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 285 } 286 287 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 288 struct i915_wa_list *wal) 289 { 290 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 291 292 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 293 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 294 295 /* WaDisablePartialInstShootdown:bdw,chv */ 296 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 297 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 298 299 /* Use Force Non-Coherent whenever executing a 3D context. This is a 300 * workaround for a possible hang in the unlikely event a TLB 301 * invalidation occurs during a PSD flush. 302 */ 303 /* WaForceEnableNonCoherent:bdw,chv */ 304 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 305 wa_masked_en(wal, HDC_CHICKEN0, 306 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 307 HDC_FORCE_NON_COHERENT); 308 309 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 310 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 311 * polygons in the same 8x4 pixel/sample area to be processed without 312 * stalling waiting for the earlier ones to write to Hierarchical Z 313 * buffer." 314 * 315 * This optimization is off by default for BDW and CHV; turn it on. 316 */ 317 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 318 319 /* Wa4x4STCOptimizationDisable:bdw,chv */ 320 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 321 322 /* 323 * BSpec recommends 8x4 when MSAA is used, 324 * however in practice 16x4 seems fastest. 325 * 326 * Note that PS/WM thread counts depend on the WIZ hashing 327 * disable bit, which we don't touch here, but it's good 328 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 329 */ 330 wa_masked_field_set(wal, GEN7_GT_MODE, 331 GEN6_WIZ_HASHING_MASK, 332 GEN6_WIZ_HASHING_16x4); 333 } 334 335 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 336 struct i915_wa_list *wal) 337 { 338 struct drm_i915_private *i915 = engine->i915; 339 340 gen8_ctx_workarounds_init(engine, wal); 341 342 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 343 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 344 345 /* WaDisableDopClockGating:bdw 346 * 347 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 348 * to disable EUTC clock gating. 349 */ 350 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 351 DOP_CLOCK_GATING_DISABLE); 352 353 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 354 GEN8_SAMPLER_POWER_BYPASS_DIS); 355 356 wa_masked_en(wal, HDC_CHICKEN0, 357 /* WaForceContextSaveRestoreNonCoherent:bdw */ 358 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 359 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 360 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 361 } 362 363 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 364 struct i915_wa_list *wal) 365 { 366 gen8_ctx_workarounds_init(engine, wal); 367 368 /* WaDisableThreadStallDopClockGating:chv */ 369 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 370 371 /* Improve HiZ throughput on CHV. */ 372 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 373 } 374 375 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 376 struct i915_wa_list *wal) 377 { 378 struct drm_i915_private *i915 = engine->i915; 379 380 if (HAS_LLC(i915)) { 381 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 382 * 383 * Must match Display Engine. See 384 * WaCompressedResourceDisplayNewHashMode. 385 */ 386 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 387 GEN9_PBE_COMPRESSED_HASH_SELECTION); 388 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 389 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 390 } 391 392 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 393 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 394 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 395 FLOW_CONTROL_ENABLE | 396 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 397 398 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 399 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 400 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 401 GEN9_ENABLE_YV12_BUGFIX | 402 GEN9_ENABLE_GPGPU_PREEMPTION); 403 404 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 405 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 406 wa_masked_en(wal, CACHE_MODE_1, 407 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 408 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 409 410 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 411 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 412 GEN9_CCS_TLB_PREFETCH_ENABLE); 413 414 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 415 wa_masked_en(wal, HDC_CHICKEN0, 416 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 417 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 418 419 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 420 * both tied to WaForceContextSaveRestoreNonCoherent 421 * in some hsds for skl. We keep the tie for all gen9. The 422 * documentation is a bit hazy and so we want to get common behaviour, 423 * even though there is no clear evidence we would need both on kbl/bxt. 424 * This area has been source of system hangs so we play it safe 425 * and mimic the skl regardless of what bspec says. 426 * 427 * Use Force Non-Coherent whenever executing a 3D context. This 428 * is a workaround for a possible hang in the unlikely event 429 * a TLB invalidation occurs during a PSD flush. 430 */ 431 432 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 433 wa_masked_en(wal, HDC_CHICKEN0, 434 HDC_FORCE_NON_COHERENT); 435 436 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 437 if (IS_SKYLAKE(i915) || 438 IS_KABYLAKE(i915) || 439 IS_COFFEELAKE(i915) || 440 IS_COMETLAKE(i915)) 441 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 442 GEN8_SAMPLER_POWER_BYPASS_DIS); 443 444 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 445 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 446 447 /* 448 * Supporting preemption with fine-granularity requires changes in the 449 * batch buffer programming. Since we can't break old userspace, we 450 * need to set our default preemption level to safe value. Userspace is 451 * still able to use more fine-grained preemption levels, since in 452 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 453 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 454 * not real HW workarounds, but merely a way to start using preemption 455 * while maintaining old contract with userspace. 456 */ 457 458 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 459 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 460 461 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 462 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 463 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 464 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 465 466 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 467 if (IS_GEN9_LP(i915)) 468 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 469 } 470 471 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 472 struct i915_wa_list *wal) 473 { 474 struct intel_gt *gt = engine->gt; 475 u8 vals[3] = { 0, 0, 0 }; 476 unsigned int i; 477 478 for (i = 0; i < 3; i++) { 479 u8 ss; 480 481 /* 482 * Only consider slices where one, and only one, subslice has 7 483 * EUs 484 */ 485 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 486 continue; 487 488 /* 489 * subslice_7eu[i] != 0 (because of the check above) and 490 * ss_max == 4 (maximum number of subslices possible per slice) 491 * 492 * -> 0 <= ss <= 3; 493 */ 494 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 495 vals[i] = 3 - ss; 496 } 497 498 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 499 return; 500 501 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 502 wa_masked_field_set(wal, GEN7_GT_MODE, 503 GEN9_IZ_HASHING_MASK(2) | 504 GEN9_IZ_HASHING_MASK(1) | 505 GEN9_IZ_HASHING_MASK(0), 506 GEN9_IZ_HASHING(2, vals[2]) | 507 GEN9_IZ_HASHING(1, vals[1]) | 508 GEN9_IZ_HASHING(0, vals[0])); 509 } 510 511 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 512 struct i915_wa_list *wal) 513 { 514 gen9_ctx_workarounds_init(engine, wal); 515 skl_tune_iz_hashing(engine, wal); 516 } 517 518 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 gen9_ctx_workarounds_init(engine, wal); 522 523 /* WaDisableThreadStallDopClockGating:bxt */ 524 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 525 STALL_DOP_GATING_DISABLE); 526 527 /* WaToEnableHwFixForPushConstHWBug:bxt */ 528 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 529 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 530 } 531 532 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 533 struct i915_wa_list *wal) 534 { 535 struct drm_i915_private *i915 = engine->i915; 536 537 gen9_ctx_workarounds_init(engine, wal); 538 539 /* WaToEnableHwFixForPushConstHWBug:kbl */ 540 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 541 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 542 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 543 544 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 545 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 546 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 547 } 548 549 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 550 struct i915_wa_list *wal) 551 { 552 gen9_ctx_workarounds_init(engine, wal); 553 554 /* WaToEnableHwFixForPushConstHWBug:glk */ 555 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 556 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 557 } 558 559 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 560 struct i915_wa_list *wal) 561 { 562 gen9_ctx_workarounds_init(engine, wal); 563 564 /* WaToEnableHwFixForPushConstHWBug:cfl */ 565 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 566 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 567 568 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 569 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 570 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 571 } 572 573 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 574 struct i915_wa_list *wal) 575 { 576 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 577 wa_write(wal, 578 GEN8_L3CNTLREG, 579 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 580 GEN8_ERRDETBCTRL); 581 582 /* WaForceEnableNonCoherent:icl 583 * This is not the same workaround as in early Gen9 platforms, where 584 * lacking this could cause system hangs, but coherency performance 585 * overhead is high and only a few compute workloads really need it 586 * (the register is whitelisted in hardware now, so UMDs can opt in 587 * for coherency if they have a good reason). 588 */ 589 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 590 591 /* WaEnableFloatBlendOptimization:icl */ 592 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 593 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 594 0 /* write-only, so skip validation */, 595 true); 596 597 /* WaDisableGPGPUMidThreadPreemption:icl */ 598 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 599 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 600 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 601 602 /* allow headerless messages for preemptible GPGPU context */ 603 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 604 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 605 606 /* Wa_1604278689:icl,ehl */ 607 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 608 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 609 0, /* write-only register; skip validation */ 610 0xFFFFFFFF); 611 612 /* Wa_1406306137:icl,ehl */ 613 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 614 } 615 616 /* 617 * These settings aren't actually workarounds, but general tuning settings that 618 * need to be programmed on dg2 platform. 619 */ 620 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 621 struct i915_wa_list *wal) 622 { 623 wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 624 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 625 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 626 wa_mcr_add(wal, 627 XEHP_FF_MODE2, 628 FF_MODE2_TDS_TIMER_MASK, 629 FF_MODE2_TDS_TIMER_128, 630 0, false); 631 } 632 633 /* 634 * These settings aren't actually workarounds, but general tuning settings that 635 * need to be programmed on several platforms. 636 */ 637 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 638 struct i915_wa_list *wal) 639 { 640 /* 641 * Although some platforms refer to it as Wa_1604555607, we need to 642 * program it even on those that don't explicitly list that 643 * workaround. 644 * 645 * Note that the programming of this register is further modified 646 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 647 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 648 * value when read. The default value for this register is zero for all 649 * fields and there are no bit masks. So instead of doing a RMW we 650 * should just write TDS timer value. For the same reason read 651 * verification is ignored. 652 */ 653 wa_add(wal, 654 GEN12_FF_MODE2, 655 FF_MODE2_TDS_TIMER_MASK, 656 FF_MODE2_TDS_TIMER_128, 657 0, false); 658 } 659 660 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 661 struct i915_wa_list *wal) 662 { 663 gen12_ctx_gt_tuning_init(engine, wal); 664 665 /* 666 * Wa_1409142259:tgl,dg1,adl-p 667 * Wa_1409347922:tgl,dg1,adl-p 668 * Wa_1409252684:tgl,dg1,adl-p 669 * Wa_1409217633:tgl,dg1,adl-p 670 * Wa_1409207793:tgl,dg1,adl-p 671 * Wa_1409178076:tgl,dg1,adl-p 672 * Wa_1408979724:tgl,dg1,adl-p 673 * Wa_14010443199:tgl,rkl,dg1,adl-p 674 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 675 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 676 */ 677 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 678 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 679 680 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 681 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 682 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 683 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 684 685 /* 686 * Wa_16011163337 687 * 688 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 689 * to Wa_1608008084. 690 */ 691 wa_add(wal, 692 GEN12_FF_MODE2, 693 FF_MODE2_GS_TIMER_MASK, 694 FF_MODE2_GS_TIMER_224, 695 0, false); 696 } 697 698 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 699 struct i915_wa_list *wal) 700 { 701 gen12_ctx_workarounds_init(engine, wal); 702 703 /* Wa_1409044764 */ 704 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 705 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 706 707 /* Wa_22010493298 */ 708 wa_masked_en(wal, HIZ_CHICKEN, 709 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 710 } 711 712 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 713 struct i915_wa_list *wal) 714 { 715 dg2_ctx_gt_tuning_init(engine, wal); 716 717 /* Wa_16011186671:dg2_g11 */ 718 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 719 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 720 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 721 } 722 723 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 724 /* Wa_14010469329:dg2_g10 */ 725 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 726 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 727 728 /* 729 * Wa_22010465075:dg2_g10 730 * Wa_22010613112:dg2_g10 731 * Wa_14010698770:dg2_g10 732 */ 733 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 734 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 735 } 736 737 /* Wa_16013271637:dg2 */ 738 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 739 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 740 741 /* Wa_14014947963:dg2 */ 742 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 743 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 744 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 745 746 /* Wa_15010599737:dg2 */ 747 wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 748 } 749 750 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 751 struct i915_wa_list *wal) 752 { 753 /* 754 * This is a "fake" workaround defined by software to ensure we 755 * maintain reliable, backward-compatible behavior for userspace with 756 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 757 * 758 * The per-context setting of MI_MODE[12] determines whether the bits 759 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 760 * in the traditional manner or whether they should instead use a new 761 * tgl+ meaning that breaks backward compatibility, but allows nesting 762 * into 3rd-level batchbuffers. When this new capability was first 763 * added in TGL, it remained off by default unless a context 764 * intentionally opted in to the new behavior. However Xe_HPG now 765 * flips this on by default and requires that we explicitly opt out if 766 * we don't want the new behavior. 767 * 768 * From a SW perspective, we want to maintain the backward-compatible 769 * behavior for userspace, so we'll apply a fake workaround to set it 770 * back to the legacy behavior on platforms where the hardware default 771 * is to break compatibility. At the moment there is no Linux 772 * userspace that utilizes third-level batchbuffers, so this will avoid 773 * userspace from needing to make any changes. using the legacy 774 * meaning is the correct thing to do. If/when we have userspace 775 * consumers that want to utilize third-level batch nesting, we can 776 * provide a context parameter to allow them to opt-in. 777 */ 778 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 779 } 780 781 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 782 struct i915_wa_list *wal) 783 { 784 u8 mocs; 785 786 /* 787 * Some blitter commands do not have a field for MOCS, those 788 * commands will use MOCS index pointed by BLIT_CCTL. 789 * BLIT_CCTL registers are needed to be programmed to un-cached. 790 */ 791 if (engine->class == COPY_ENGINE_CLASS) { 792 mocs = engine->gt->mocs.uc_index; 793 wa_write_clr_set(wal, 794 BLIT_CCTL(engine->mmio_base), 795 BLIT_CCTL_MASK, 796 BLIT_CCTL_MOCS(mocs, mocs)); 797 } 798 } 799 800 /* 801 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 802 * defined by the hardware team, but it programming general context registers. 803 * Adding those context register programming in context workaround 804 * allow us to use the wa framework for proper application and validation. 805 */ 806 static void 807 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 808 struct i915_wa_list *wal) 809 { 810 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 811 fakewa_disable_nestedbb_mode(engine, wal); 812 813 gen12_ctx_gt_mocs_init(engine, wal); 814 } 815 816 static void 817 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 818 struct i915_wa_list *wal, 819 const char *name) 820 { 821 struct drm_i915_private *i915 = engine->i915; 822 823 wa_init_start(wal, name, engine->name); 824 825 /* Applies to all engines */ 826 /* 827 * Fake workarounds are not the actual workaround but 828 * programming of context registers using workaround framework. 829 */ 830 if (GRAPHICS_VER(i915) >= 12) 831 gen12_ctx_gt_fake_wa_init(engine, wal); 832 833 if (engine->class != RENDER_CLASS) 834 goto done; 835 836 if (IS_PONTEVECCHIO(i915)) 837 ; /* noop; none at this time */ 838 else if (IS_DG2(i915)) 839 dg2_ctx_workarounds_init(engine, wal); 840 else if (IS_XEHPSDV(i915)) 841 ; /* noop; none at this time */ 842 else if (IS_DG1(i915)) 843 dg1_ctx_workarounds_init(engine, wal); 844 else if (GRAPHICS_VER(i915) == 12) 845 gen12_ctx_workarounds_init(engine, wal); 846 else if (GRAPHICS_VER(i915) == 11) 847 icl_ctx_workarounds_init(engine, wal); 848 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 849 cfl_ctx_workarounds_init(engine, wal); 850 else if (IS_GEMINILAKE(i915)) 851 glk_ctx_workarounds_init(engine, wal); 852 else if (IS_KABYLAKE(i915)) 853 kbl_ctx_workarounds_init(engine, wal); 854 else if (IS_BROXTON(i915)) 855 bxt_ctx_workarounds_init(engine, wal); 856 else if (IS_SKYLAKE(i915)) 857 skl_ctx_workarounds_init(engine, wal); 858 else if (IS_CHERRYVIEW(i915)) 859 chv_ctx_workarounds_init(engine, wal); 860 else if (IS_BROADWELL(i915)) 861 bdw_ctx_workarounds_init(engine, wal); 862 else if (GRAPHICS_VER(i915) == 7) 863 gen7_ctx_workarounds_init(engine, wal); 864 else if (GRAPHICS_VER(i915) == 6) 865 gen6_ctx_workarounds_init(engine, wal); 866 else if (GRAPHICS_VER(i915) < 8) 867 ; 868 else 869 MISSING_CASE(GRAPHICS_VER(i915)); 870 871 done: 872 wa_init_finish(wal); 873 } 874 875 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 876 { 877 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 878 } 879 880 int intel_engine_emit_ctx_wa(struct i915_request *rq) 881 { 882 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 883 struct i915_wa *wa; 884 unsigned int i; 885 u32 *cs; 886 int ret; 887 888 if (wal->count == 0) 889 return 0; 890 891 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 892 if (ret) 893 return ret; 894 895 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 896 if (IS_ERR(cs)) 897 return PTR_ERR(cs); 898 899 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 900 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 901 *cs++ = i915_mmio_reg_offset(wa->reg); 902 *cs++ = wa->set; 903 } 904 *cs++ = MI_NOOP; 905 906 intel_ring_advance(rq, cs); 907 908 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 909 if (ret) 910 return ret; 911 912 return 0; 913 } 914 915 static void 916 gen4_gt_workarounds_init(struct intel_gt *gt, 917 struct i915_wa_list *wal) 918 { 919 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 920 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 921 } 922 923 static void 924 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 925 { 926 gen4_gt_workarounds_init(gt, wal); 927 928 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 929 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 930 } 931 932 static void 933 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 934 { 935 g4x_gt_workarounds_init(gt, wal); 936 937 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 938 } 939 940 static void 941 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 942 { 943 } 944 945 static void 946 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 947 { 948 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 949 wa_masked_dis(wal, 950 GEN7_COMMON_SLICE_CHICKEN1, 951 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 952 953 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 954 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 955 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 956 957 /* WaForceL3Serialization:ivb */ 958 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 959 } 960 961 static void 962 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 963 { 964 /* WaForceL3Serialization:vlv */ 965 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 966 967 /* 968 * WaIncreaseL3CreditsForVLVB0:vlv 969 * This is the hardware default actually. 970 */ 971 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 972 } 973 974 static void 975 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 976 { 977 /* L3 caching of data atomics doesn't work -- disable it. */ 978 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 979 980 wa_add(wal, 981 HSW_ROW_CHICKEN3, 0, 982 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 983 0 /* XXX does this reg exist? */, true); 984 985 /* WaVSRefCountFullforceMissDisable:hsw */ 986 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 987 } 988 989 static void 990 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 991 { 992 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 993 unsigned int slice, subslice; 994 u32 mcr, mcr_mask; 995 996 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 997 998 /* 999 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1000 * Before any MMIO read into slice/subslice specific registers, MCR 1001 * packet control register needs to be programmed to point to any 1002 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1003 * This means each subsequent MMIO read will be forwarded to an 1004 * specific s/ss combination, but this is OK since these registers 1005 * are consistent across s/ss in almost all cases. In the rare 1006 * occasions, such as INSTDONE, where this value is dependent 1007 * on s/ss combo, the read should be done with read_subslice_reg. 1008 */ 1009 slice = ffs(sseu->slice_mask) - 1; 1010 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1011 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1012 GEM_BUG_ON(!subslice); 1013 subslice--; 1014 1015 /* 1016 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1017 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1018 */ 1019 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1020 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1021 1022 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1023 1024 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1025 } 1026 1027 static void 1028 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1029 { 1030 struct drm_i915_private *i915 = gt->i915; 1031 1032 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1033 gen9_wa_init_mcr(i915, wal); 1034 1035 /* WaDisableKillLogic:bxt,skl,kbl */ 1036 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1037 wa_write_or(wal, 1038 GAM_ECOCHK, 1039 ECOCHK_DIS_TLB); 1040 1041 if (HAS_LLC(i915)) { 1042 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1043 * 1044 * Must match Display Engine. See 1045 * WaCompressedResourceDisplayNewHashMode. 1046 */ 1047 wa_write_or(wal, 1048 MMCD_MISC_CTRL, 1049 MMCD_PCLA | MMCD_HOTSPOT_EN); 1050 } 1051 1052 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1053 wa_write_or(wal, 1054 GAM_ECOCHK, 1055 BDW_DISABLE_HDC_INVALIDATION); 1056 } 1057 1058 static void 1059 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1060 { 1061 gen9_gt_workarounds_init(gt, wal); 1062 1063 /* WaDisableGafsUnitClkGating:skl */ 1064 wa_write_or(wal, 1065 GEN7_UCGCTL4, 1066 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1067 1068 /* WaInPlaceDecompressionHang:skl */ 1069 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1070 wa_write_or(wal, 1071 GEN9_GAMT_ECO_REG_RW_IA, 1072 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1073 } 1074 1075 static void 1076 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1077 { 1078 gen9_gt_workarounds_init(gt, wal); 1079 1080 /* WaDisableDynamicCreditSharing:kbl */ 1081 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1082 wa_write_or(wal, 1083 GAMT_CHKN_BIT_REG, 1084 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1085 1086 /* WaDisableGafsUnitClkGating:kbl */ 1087 wa_write_or(wal, 1088 GEN7_UCGCTL4, 1089 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1090 1091 /* WaInPlaceDecompressionHang:kbl */ 1092 wa_write_or(wal, 1093 GEN9_GAMT_ECO_REG_RW_IA, 1094 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1095 } 1096 1097 static void 1098 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1099 { 1100 gen9_gt_workarounds_init(gt, wal); 1101 } 1102 1103 static void 1104 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1105 { 1106 gen9_gt_workarounds_init(gt, wal); 1107 1108 /* WaDisableGafsUnitClkGating:cfl */ 1109 wa_write_or(wal, 1110 GEN7_UCGCTL4, 1111 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1112 1113 /* WaInPlaceDecompressionHang:cfl */ 1114 wa_write_or(wal, 1115 GEN9_GAMT_ECO_REG_RW_IA, 1116 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1117 } 1118 1119 static void __set_mcr_steering(struct i915_wa_list *wal, 1120 i915_reg_t steering_reg, 1121 unsigned int slice, unsigned int subslice) 1122 { 1123 u32 mcr, mcr_mask; 1124 1125 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1126 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1127 1128 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1129 } 1130 1131 static void debug_dump_steering(struct intel_gt *gt) 1132 { 1133 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1134 1135 if (drm_debug_enabled(DRM_UT_DRIVER)) 1136 intel_gt_mcr_report_steering(&p, gt, false); 1137 } 1138 1139 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1140 unsigned int slice, unsigned int subslice) 1141 { 1142 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1143 1144 gt->default_steering.groupid = slice; 1145 gt->default_steering.instanceid = subslice; 1146 1147 debug_dump_steering(gt); 1148 } 1149 1150 static void 1151 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1152 { 1153 const struct sseu_dev_info *sseu = >->info.sseu; 1154 unsigned int subslice; 1155 1156 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1157 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1158 1159 /* 1160 * Although a platform may have subslices, we need to always steer 1161 * reads to the lowest instance that isn't fused off. When Render 1162 * Power Gating is enabled, grabbing forcewake will only power up a 1163 * single subslice (the "minconfig") if there isn't a real workload 1164 * that needs to be run; this means that if we steer register reads to 1165 * one of the higher subslices, we run the risk of reading back 0's or 1166 * random garbage. 1167 */ 1168 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1169 1170 /* 1171 * If the subslice we picked above also steers us to a valid L3 bank, 1172 * then we can just rely on the default steering and won't need to 1173 * worry about explicitly re-steering L3BANK reads later. 1174 */ 1175 if (gt->info.l3bank_mask & BIT(subslice)) 1176 gt->steering_table[L3BANK] = NULL; 1177 1178 __add_mcr_wa(gt, wal, 0, subslice); 1179 } 1180 1181 static void 1182 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1183 { 1184 const struct sseu_dev_info *sseu = >->info.sseu; 1185 unsigned long slice, subslice = 0, slice_mask = 0; 1186 u32 lncf_mask = 0; 1187 int i; 1188 1189 /* 1190 * On Xe_HP the steering increases in complexity. There are now several 1191 * more units that require steering and we're not guaranteed to be able 1192 * to find a common setting for all of them. These are: 1193 * - GSLICE (fusable) 1194 * - DSS (sub-unit within gslice; fusable) 1195 * - L3 Bank (fusable) 1196 * - MSLICE (fusable) 1197 * - LNCF (sub-unit within mslice; always present if mslice is present) 1198 * 1199 * We'll do our default/implicit steering based on GSLICE (in the 1200 * sliceid field) and DSS (in the subsliceid field). If we can 1201 * find overlap between the valid MSLICE and/or LNCF values with 1202 * a suitable GSLICE, then we can just re-use the default value and 1203 * skip and explicit steering at runtime. 1204 * 1205 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1206 * a valid sliceid value. DSS steering is the only type of steering 1207 * that utilizes the 'subsliceid' bits. 1208 * 1209 * Also note that, even though the steering domain is called "GSlice" 1210 * and it is encoded in the register using the gslice format, the spec 1211 * says that the combined (geometry | compute) fuse should be used to 1212 * select the steering. 1213 */ 1214 1215 /* Find the potential gslice candidates */ 1216 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1217 GEN_DSS_PER_GSLICE); 1218 1219 /* 1220 * Find the potential LNCF candidates. Either LNCF within a valid 1221 * mslice is fine. 1222 */ 1223 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1224 lncf_mask |= (0x3 << (i * 2)); 1225 1226 /* 1227 * Are there any sliceid values that work for both GSLICE and LNCF 1228 * steering? 1229 */ 1230 if (slice_mask & lncf_mask) { 1231 slice_mask &= lncf_mask; 1232 gt->steering_table[LNCF] = NULL; 1233 } 1234 1235 /* How about sliceid values that also work for MSLICE steering? */ 1236 if (slice_mask & gt->info.mslice_mask) { 1237 slice_mask &= gt->info.mslice_mask; 1238 gt->steering_table[MSLICE] = NULL; 1239 } 1240 1241 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1242 gt->steering_table[GAM] = NULL; 1243 1244 slice = __ffs(slice_mask); 1245 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1246 GEN_DSS_PER_GSLICE; 1247 1248 __add_mcr_wa(gt, wal, slice, subslice); 1249 1250 /* 1251 * SQIDI ranges are special because they use different steering 1252 * registers than everything else we work with. On XeHP SDV and 1253 * DG2-G10, any value in the steering registers will work fine since 1254 * all instances are present, but DG2-G11 only has SQIDI instances at 1255 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1256 * we'll just steer to a hardcoded "2" since that value will work 1257 * everywhere. 1258 */ 1259 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1260 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1261 1262 /* 1263 * On DG2, GAM registers have a dedicated steering control register 1264 * and must always be programmed to a hardcoded groupid of "1." 1265 */ 1266 if (IS_DG2(gt->i915)) 1267 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1268 } 1269 1270 static void 1271 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1272 { 1273 unsigned int dss; 1274 1275 /* 1276 * Setup implicit steering for COMPUTE and DSS ranges to the first 1277 * non-fused-off DSS. All other types of MCR registers will be 1278 * explicitly steered. 1279 */ 1280 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1281 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1282 } 1283 1284 static void 1285 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1286 { 1287 struct drm_i915_private *i915 = gt->i915; 1288 1289 icl_wa_init_mcr(gt, wal); 1290 1291 /* WaModifyGamTlbPartitioning:icl */ 1292 wa_write_clr_set(wal, 1293 GEN11_GACB_PERF_CTRL, 1294 GEN11_HASH_CTRL_MASK, 1295 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1296 1297 /* Wa_1405766107:icl 1298 * Formerly known as WaCL2SFHalfMaxAlloc 1299 */ 1300 wa_write_or(wal, 1301 GEN11_LSN_UNSLCVC, 1302 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1303 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1304 1305 /* Wa_220166154:icl 1306 * Formerly known as WaDisCtxReload 1307 */ 1308 wa_write_or(wal, 1309 GEN8_GAMW_ECO_DEV_RW_IA, 1310 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1311 1312 /* Wa_1406463099:icl 1313 * Formerly known as WaGamTlbPendError 1314 */ 1315 wa_write_or(wal, 1316 GAMT_CHKN_BIT_REG, 1317 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1318 1319 /* Wa_1407352427:icl,ehl */ 1320 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1321 PSDUNIT_CLKGATE_DIS); 1322 1323 /* Wa_1406680159:icl,ehl */ 1324 wa_mcr_write_or(wal, 1325 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1326 GWUNIT_CLKGATE_DIS); 1327 1328 /* Wa_1607087056:icl,ehl,jsl */ 1329 if (IS_ICELAKE(i915) || 1330 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1331 wa_write_or(wal, 1332 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1333 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1334 1335 /* 1336 * This is not a documented workaround, but rather an optimization 1337 * to reduce sampler power. 1338 */ 1339 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1340 } 1341 1342 /* 1343 * Though there are per-engine instances of these registers, 1344 * they retain their value through engine resets and should 1345 * only be provided on the GT workaround list rather than 1346 * the engine-specific workaround list. 1347 */ 1348 static void 1349 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1350 { 1351 struct intel_engine_cs *engine; 1352 int id; 1353 1354 for_each_engine(engine, gt, id) { 1355 if (engine->class != VIDEO_DECODE_CLASS || 1356 (engine->instance % 2)) 1357 continue; 1358 1359 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1360 IECPUNIT_CLKGATE_DIS); 1361 } 1362 } 1363 1364 static void 1365 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1366 { 1367 icl_wa_init_mcr(gt, wal); 1368 1369 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1370 wa_14011060649(gt, wal); 1371 1372 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1373 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1374 } 1375 1376 static void 1377 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1378 { 1379 struct drm_i915_private *i915 = gt->i915; 1380 1381 gen12_gt_workarounds_init(gt, wal); 1382 1383 /* Wa_1409420604:tgl */ 1384 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1385 wa_mcr_write_or(wal, 1386 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1387 CPSSUNIT_CLKGATE_DIS); 1388 1389 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1390 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1391 wa_write_or(wal, 1392 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1393 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1394 1395 /* Wa_1408615072:tgl[a0] */ 1396 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1397 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1398 VSUNIT_CLKGATE_DIS_TGL); 1399 } 1400 1401 static void 1402 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1403 { 1404 struct drm_i915_private *i915 = gt->i915; 1405 1406 gen12_gt_workarounds_init(gt, wal); 1407 1408 /* Wa_1607087056:dg1 */ 1409 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1410 wa_write_or(wal, 1411 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1412 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1413 1414 /* Wa_1409420604:dg1 */ 1415 if (IS_DG1(i915)) 1416 wa_mcr_write_or(wal, 1417 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1418 CPSSUNIT_CLKGATE_DIS); 1419 1420 /* Wa_1408615072:dg1 */ 1421 /* Empirical testing shows this register is unaffected by engine reset. */ 1422 if (IS_DG1(i915)) 1423 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1424 VSUNIT_CLKGATE_DIS_TGL); 1425 } 1426 1427 static void 1428 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1429 { 1430 struct drm_i915_private *i915 = gt->i915; 1431 1432 xehp_init_mcr(gt, wal); 1433 1434 /* Wa_1409757795:xehpsdv */ 1435 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1436 1437 /* Wa_16011155590:xehpsdv */ 1438 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1439 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1440 TSGUNIT_CLKGATE_DIS); 1441 1442 /* Wa_14011780169:xehpsdv */ 1443 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1444 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1445 GAMTLBVDBOX7_CLKGATE_DIS | 1446 GAMTLBVDBOX6_CLKGATE_DIS | 1447 GAMTLBVDBOX5_CLKGATE_DIS | 1448 GAMTLBVDBOX4_CLKGATE_DIS | 1449 GAMTLBVDBOX3_CLKGATE_DIS | 1450 GAMTLBVDBOX2_CLKGATE_DIS | 1451 GAMTLBVDBOX1_CLKGATE_DIS | 1452 GAMTLBVDBOX0_CLKGATE_DIS | 1453 GAMTLBKCR_CLKGATE_DIS | 1454 GAMTLBGUC_CLKGATE_DIS | 1455 GAMTLBBLT_CLKGATE_DIS); 1456 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1457 GAMTLBGFXA1_CLKGATE_DIS | 1458 GAMTLBCOMPA0_CLKGATE_DIS | 1459 GAMTLBCOMPA1_CLKGATE_DIS | 1460 GAMTLBCOMPB0_CLKGATE_DIS | 1461 GAMTLBCOMPB1_CLKGATE_DIS | 1462 GAMTLBCOMPC0_CLKGATE_DIS | 1463 GAMTLBCOMPC1_CLKGATE_DIS | 1464 GAMTLBCOMPD0_CLKGATE_DIS | 1465 GAMTLBCOMPD1_CLKGATE_DIS | 1466 GAMTLBMERT_CLKGATE_DIS | 1467 GAMTLBVEBOX3_CLKGATE_DIS | 1468 GAMTLBVEBOX2_CLKGATE_DIS | 1469 GAMTLBVEBOX1_CLKGATE_DIS | 1470 GAMTLBVEBOX0_CLKGATE_DIS); 1471 } 1472 1473 /* Wa_16012725990:xehpsdv */ 1474 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1475 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1476 1477 /* Wa_14011060649:xehpsdv */ 1478 wa_14011060649(gt, wal); 1479 } 1480 1481 static void 1482 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1483 { 1484 struct intel_engine_cs *engine; 1485 int id; 1486 1487 xehp_init_mcr(gt, wal); 1488 1489 /* Wa_14011060649:dg2 */ 1490 wa_14011060649(gt, wal); 1491 1492 /* 1493 * Although there are per-engine instances of these registers, 1494 * they technically exist outside the engine itself and are not 1495 * impacted by engine resets. Furthermore, they're part of the 1496 * GuC blacklist so trying to treat them as engine workarounds 1497 * will result in GuC initialization failure and a wedged GPU. 1498 */ 1499 for_each_engine(engine, gt, id) { 1500 if (engine->class != VIDEO_DECODE_CLASS) 1501 continue; 1502 1503 /* Wa_16010515920:dg2_g10 */ 1504 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1505 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1506 ALNUNIT_CLKGATE_DIS); 1507 } 1508 1509 if (IS_DG2_G10(gt->i915)) { 1510 /* Wa_22010523718:dg2 */ 1511 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1512 CG3DDISCFEG_CLKGATE_DIS); 1513 1514 /* Wa_14011006942:dg2 */ 1515 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1516 DSS_ROUTER_CLKGATE_DIS); 1517 } 1518 1519 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1520 /* Wa_14010948348:dg2_g10 */ 1521 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1522 1523 /* Wa_14011037102:dg2_g10 */ 1524 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1525 1526 /* Wa_14011371254:dg2_g10 */ 1527 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1528 1529 /* Wa_14011431319:dg2_g10 */ 1530 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1531 GAMTLBVDBOX7_CLKGATE_DIS | 1532 GAMTLBVDBOX6_CLKGATE_DIS | 1533 GAMTLBVDBOX5_CLKGATE_DIS | 1534 GAMTLBVDBOX4_CLKGATE_DIS | 1535 GAMTLBVDBOX3_CLKGATE_DIS | 1536 GAMTLBVDBOX2_CLKGATE_DIS | 1537 GAMTLBVDBOX1_CLKGATE_DIS | 1538 GAMTLBVDBOX0_CLKGATE_DIS | 1539 GAMTLBKCR_CLKGATE_DIS | 1540 GAMTLBGUC_CLKGATE_DIS | 1541 GAMTLBBLT_CLKGATE_DIS); 1542 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1543 GAMTLBGFXA1_CLKGATE_DIS | 1544 GAMTLBCOMPA0_CLKGATE_DIS | 1545 GAMTLBCOMPA1_CLKGATE_DIS | 1546 GAMTLBCOMPB0_CLKGATE_DIS | 1547 GAMTLBCOMPB1_CLKGATE_DIS | 1548 GAMTLBCOMPC0_CLKGATE_DIS | 1549 GAMTLBCOMPC1_CLKGATE_DIS | 1550 GAMTLBCOMPD0_CLKGATE_DIS | 1551 GAMTLBCOMPD1_CLKGATE_DIS | 1552 GAMTLBMERT_CLKGATE_DIS | 1553 GAMTLBVEBOX3_CLKGATE_DIS | 1554 GAMTLBVEBOX2_CLKGATE_DIS | 1555 GAMTLBVEBOX1_CLKGATE_DIS | 1556 GAMTLBVEBOX0_CLKGATE_DIS); 1557 1558 /* Wa_14010569222:dg2_g10 */ 1559 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1560 GAMEDIA_CLKGATE_DIS); 1561 1562 /* Wa_14011028019:dg2_g10 */ 1563 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1564 } 1565 1566 /* Wa_14014830051:dg2 */ 1567 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1568 1569 /* 1570 * The following are not actually "workarounds" but rather 1571 * recommended tuning settings documented in the bspec's 1572 * performance guide section. 1573 */ 1574 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1575 1576 /* Wa_14015795083 */ 1577 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1578 } 1579 1580 static void 1581 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1582 { 1583 pvc_init_mcr(gt, wal); 1584 1585 /* Wa_14015795083 */ 1586 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1587 } 1588 1589 static void 1590 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1591 { 1592 /* FIXME: Actual workarounds will be added in future patch(es) */ 1593 1594 /* 1595 * Unlike older platforms, we no longer setup implicit steering here; 1596 * all MCR accesses are explicitly steered. 1597 */ 1598 debug_dump_steering(gt); 1599 } 1600 1601 static void 1602 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1603 { 1604 /* FIXME: Actual workarounds will be added in future patch(es) */ 1605 1606 debug_dump_steering(gt); 1607 } 1608 1609 static void 1610 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1611 { 1612 struct drm_i915_private *i915 = gt->i915; 1613 1614 if (gt->type == GT_MEDIA) { 1615 if (MEDIA_VER(i915) >= 13) 1616 xelpmp_gt_workarounds_init(gt, wal); 1617 else 1618 MISSING_CASE(MEDIA_VER(i915)); 1619 1620 return; 1621 } 1622 1623 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1624 xelpg_gt_workarounds_init(gt, wal); 1625 else if (IS_PONTEVECCHIO(i915)) 1626 pvc_gt_workarounds_init(gt, wal); 1627 else if (IS_DG2(i915)) 1628 dg2_gt_workarounds_init(gt, wal); 1629 else if (IS_XEHPSDV(i915)) 1630 xehpsdv_gt_workarounds_init(gt, wal); 1631 else if (IS_DG1(i915)) 1632 dg1_gt_workarounds_init(gt, wal); 1633 else if (IS_TIGERLAKE(i915)) 1634 tgl_gt_workarounds_init(gt, wal); 1635 else if (GRAPHICS_VER(i915) == 12) 1636 gen12_gt_workarounds_init(gt, wal); 1637 else if (GRAPHICS_VER(i915) == 11) 1638 icl_gt_workarounds_init(gt, wal); 1639 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1640 cfl_gt_workarounds_init(gt, wal); 1641 else if (IS_GEMINILAKE(i915)) 1642 glk_gt_workarounds_init(gt, wal); 1643 else if (IS_KABYLAKE(i915)) 1644 kbl_gt_workarounds_init(gt, wal); 1645 else if (IS_BROXTON(i915)) 1646 gen9_gt_workarounds_init(gt, wal); 1647 else if (IS_SKYLAKE(i915)) 1648 skl_gt_workarounds_init(gt, wal); 1649 else if (IS_HASWELL(i915)) 1650 hsw_gt_workarounds_init(gt, wal); 1651 else if (IS_VALLEYVIEW(i915)) 1652 vlv_gt_workarounds_init(gt, wal); 1653 else if (IS_IVYBRIDGE(i915)) 1654 ivb_gt_workarounds_init(gt, wal); 1655 else if (GRAPHICS_VER(i915) == 6) 1656 snb_gt_workarounds_init(gt, wal); 1657 else if (GRAPHICS_VER(i915) == 5) 1658 ilk_gt_workarounds_init(gt, wal); 1659 else if (IS_G4X(i915)) 1660 g4x_gt_workarounds_init(gt, wal); 1661 else if (GRAPHICS_VER(i915) == 4) 1662 gen4_gt_workarounds_init(gt, wal); 1663 else if (GRAPHICS_VER(i915) <= 8) 1664 ; 1665 else 1666 MISSING_CASE(GRAPHICS_VER(i915)); 1667 } 1668 1669 void intel_gt_init_workarounds(struct intel_gt *gt) 1670 { 1671 struct i915_wa_list *wal = >->wa_list; 1672 1673 wa_init_start(wal, "GT", "global"); 1674 gt_init_workarounds(gt, wal); 1675 wa_init_finish(wal); 1676 } 1677 1678 static enum forcewake_domains 1679 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1680 { 1681 enum forcewake_domains fw = 0; 1682 struct i915_wa *wa; 1683 unsigned int i; 1684 1685 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1686 fw |= intel_uncore_forcewake_for_reg(uncore, 1687 wa->reg, 1688 FW_REG_READ | 1689 FW_REG_WRITE); 1690 1691 return fw; 1692 } 1693 1694 static bool 1695 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1696 { 1697 if ((cur ^ wa->set) & wa->read) { 1698 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1699 name, from, i915_mmio_reg_offset(wa->reg), 1700 cur, cur & wa->read, wa->set & wa->read); 1701 1702 return false; 1703 } 1704 1705 return true; 1706 } 1707 1708 static void 1709 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1710 { 1711 struct intel_uncore *uncore = gt->uncore; 1712 enum forcewake_domains fw; 1713 unsigned long flags; 1714 struct i915_wa *wa; 1715 unsigned int i; 1716 1717 if (!wal->count) 1718 return; 1719 1720 fw = wal_get_fw_for_rmw(uncore, wal); 1721 1722 spin_lock_irqsave(&uncore->lock, flags); 1723 intel_uncore_forcewake_get__locked(uncore, fw); 1724 1725 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1726 u32 val, old = 0; 1727 1728 /* open-coded rmw due to steering */ 1729 if (wa->clr) 1730 old = wa->is_mcr ? 1731 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1732 intel_uncore_read_fw(uncore, wa->reg); 1733 val = (old & ~wa->clr) | wa->set; 1734 if (val != old || !wa->clr) { 1735 if (wa->is_mcr) 1736 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1737 else 1738 intel_uncore_write_fw(uncore, wa->reg, val); 1739 } 1740 1741 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1742 u32 val = wa->is_mcr ? 1743 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1744 intel_uncore_read_fw(uncore, wa->reg); 1745 1746 wa_verify(wa, val, wal->name, "application"); 1747 } 1748 } 1749 1750 intel_uncore_forcewake_put__locked(uncore, fw); 1751 spin_unlock_irqrestore(&uncore->lock, flags); 1752 } 1753 1754 void intel_gt_apply_workarounds(struct intel_gt *gt) 1755 { 1756 wa_list_apply(gt, >->wa_list); 1757 } 1758 1759 static bool wa_list_verify(struct intel_gt *gt, 1760 const struct i915_wa_list *wal, 1761 const char *from) 1762 { 1763 struct intel_uncore *uncore = gt->uncore; 1764 struct i915_wa *wa; 1765 enum forcewake_domains fw; 1766 unsigned long flags; 1767 unsigned int i; 1768 bool ok = true; 1769 1770 fw = wal_get_fw_for_rmw(uncore, wal); 1771 1772 spin_lock_irqsave(&uncore->lock, flags); 1773 intel_uncore_forcewake_get__locked(uncore, fw); 1774 1775 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1776 ok &= wa_verify(wa, wa->is_mcr ? 1777 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1778 intel_uncore_read_fw(uncore, wa->reg), 1779 wal->name, from); 1780 1781 intel_uncore_forcewake_put__locked(uncore, fw); 1782 spin_unlock_irqrestore(&uncore->lock, flags); 1783 1784 return ok; 1785 } 1786 1787 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1788 { 1789 return wa_list_verify(gt, >->wa_list, from); 1790 } 1791 1792 __maybe_unused 1793 static bool is_nonpriv_flags_valid(u32 flags) 1794 { 1795 /* Check only valid flag bits are set */ 1796 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1797 return false; 1798 1799 /* NB: Only 3 out of 4 enum values are valid for access field */ 1800 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1801 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1802 return false; 1803 1804 return true; 1805 } 1806 1807 static void 1808 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1809 { 1810 struct i915_wa wa = { 1811 .reg = reg 1812 }; 1813 1814 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1815 return; 1816 1817 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1818 return; 1819 1820 wa.reg.reg |= flags; 1821 _wa_add(wal, &wa); 1822 } 1823 1824 static void 1825 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1826 { 1827 struct i915_wa wa = { 1828 .mcr_reg = reg, 1829 .is_mcr = 1, 1830 }; 1831 1832 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1833 return; 1834 1835 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1836 return; 1837 1838 wa.mcr_reg.reg |= flags; 1839 _wa_add(wal, &wa); 1840 } 1841 1842 static void 1843 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1844 { 1845 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1846 } 1847 1848 static void 1849 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1850 { 1851 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1852 } 1853 1854 static void gen9_whitelist_build(struct i915_wa_list *w) 1855 { 1856 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1857 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1858 1859 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1860 whitelist_reg(w, GEN8_CS_CHICKEN1); 1861 1862 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1863 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1864 1865 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1866 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1867 } 1868 1869 static void skl_whitelist_build(struct intel_engine_cs *engine) 1870 { 1871 struct i915_wa_list *w = &engine->whitelist; 1872 1873 if (engine->class != RENDER_CLASS) 1874 return; 1875 1876 gen9_whitelist_build(w); 1877 1878 /* WaDisableLSQCROPERFforOCL:skl */ 1879 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1880 } 1881 1882 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1883 { 1884 if (engine->class != RENDER_CLASS) 1885 return; 1886 1887 gen9_whitelist_build(&engine->whitelist); 1888 } 1889 1890 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1891 { 1892 struct i915_wa_list *w = &engine->whitelist; 1893 1894 if (engine->class != RENDER_CLASS) 1895 return; 1896 1897 gen9_whitelist_build(w); 1898 1899 /* WaDisableLSQCROPERFforOCL:kbl */ 1900 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1901 } 1902 1903 static void glk_whitelist_build(struct intel_engine_cs *engine) 1904 { 1905 struct i915_wa_list *w = &engine->whitelist; 1906 1907 if (engine->class != RENDER_CLASS) 1908 return; 1909 1910 gen9_whitelist_build(w); 1911 1912 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1913 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1914 } 1915 1916 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1917 { 1918 struct i915_wa_list *w = &engine->whitelist; 1919 1920 if (engine->class != RENDER_CLASS) 1921 return; 1922 1923 gen9_whitelist_build(w); 1924 1925 /* 1926 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1927 * 1928 * This covers 4 register which are next to one another : 1929 * - PS_INVOCATION_COUNT 1930 * - PS_INVOCATION_COUNT_UDW 1931 * - PS_DEPTH_COUNT 1932 * - PS_DEPTH_COUNT_UDW 1933 */ 1934 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1935 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1936 RING_FORCE_TO_NONPRIV_RANGE_4); 1937 } 1938 1939 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1940 { 1941 struct i915_wa_list *w = &engine->whitelist; 1942 1943 if (engine->class != RENDER_CLASS) 1944 whitelist_reg_ext(w, 1945 RING_CTX_TIMESTAMP(engine->mmio_base), 1946 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1947 } 1948 1949 static void cml_whitelist_build(struct intel_engine_cs *engine) 1950 { 1951 allow_read_ctx_timestamp(engine); 1952 1953 cfl_whitelist_build(engine); 1954 } 1955 1956 static void icl_whitelist_build(struct intel_engine_cs *engine) 1957 { 1958 struct i915_wa_list *w = &engine->whitelist; 1959 1960 allow_read_ctx_timestamp(engine); 1961 1962 switch (engine->class) { 1963 case RENDER_CLASS: 1964 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1965 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1966 1967 /* WaAllowUMDToModifySamplerMode:icl */ 1968 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 1969 1970 /* WaEnableStateCacheRedirectToCS:icl */ 1971 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1972 1973 /* 1974 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1975 * 1976 * This covers 4 register which are next to one another : 1977 * - PS_INVOCATION_COUNT 1978 * - PS_INVOCATION_COUNT_UDW 1979 * - PS_DEPTH_COUNT 1980 * - PS_DEPTH_COUNT_UDW 1981 */ 1982 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1983 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1984 RING_FORCE_TO_NONPRIV_RANGE_4); 1985 break; 1986 1987 case VIDEO_DECODE_CLASS: 1988 /* hucStatusRegOffset */ 1989 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1990 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1991 /* hucUKernelHdrInfoRegOffset */ 1992 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1993 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1994 /* hucStatus2RegOffset */ 1995 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1996 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1997 break; 1998 1999 default: 2000 break; 2001 } 2002 } 2003 2004 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2005 { 2006 struct i915_wa_list *w = &engine->whitelist; 2007 2008 allow_read_ctx_timestamp(engine); 2009 2010 switch (engine->class) { 2011 case RENDER_CLASS: 2012 /* 2013 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2014 * Wa_1408556865:tgl 2015 * 2016 * This covers 4 registers which are next to one another : 2017 * - PS_INVOCATION_COUNT 2018 * - PS_INVOCATION_COUNT_UDW 2019 * - PS_DEPTH_COUNT 2020 * - PS_DEPTH_COUNT_UDW 2021 */ 2022 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2023 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2024 RING_FORCE_TO_NONPRIV_RANGE_4); 2025 2026 /* 2027 * Wa_1808121037:tgl 2028 * Wa_14012131227:dg1 2029 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2030 */ 2031 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2032 2033 /* Wa_1806527549:tgl */ 2034 whitelist_reg(w, HIZ_CHICKEN); 2035 break; 2036 default: 2037 break; 2038 } 2039 } 2040 2041 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2042 { 2043 struct i915_wa_list *w = &engine->whitelist; 2044 2045 tgl_whitelist_build(engine); 2046 2047 /* GEN:BUG:1409280441:dg1 */ 2048 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2049 (engine->class == RENDER_CLASS || 2050 engine->class == COPY_ENGINE_CLASS)) 2051 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2052 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2053 } 2054 2055 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2056 { 2057 allow_read_ctx_timestamp(engine); 2058 } 2059 2060 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2061 { 2062 struct i915_wa_list *w = &engine->whitelist; 2063 2064 allow_read_ctx_timestamp(engine); 2065 2066 switch (engine->class) { 2067 case RENDER_CLASS: 2068 /* 2069 * Wa_1507100340:dg2_g10 2070 * 2071 * This covers 4 registers which are next to one another : 2072 * - PS_INVOCATION_COUNT 2073 * - PS_INVOCATION_COUNT_UDW 2074 * - PS_DEPTH_COUNT 2075 * - PS_DEPTH_COUNT_UDW 2076 */ 2077 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2078 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2079 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2080 RING_FORCE_TO_NONPRIV_RANGE_4); 2081 2082 break; 2083 case COMPUTE_CLASS: 2084 /* Wa_16011157294:dg2_g10 */ 2085 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2086 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 static void blacklist_trtt(struct intel_engine_cs *engine) 2094 { 2095 struct i915_wa_list *w = &engine->whitelist; 2096 2097 /* 2098 * Prevent read/write access to [0x4400, 0x4600) which covers 2099 * the TRTT range across all engines. Note that normally userspace 2100 * cannot access the other engines' trtt control, but for simplicity 2101 * we cover the entire range on each engine. 2102 */ 2103 whitelist_reg_ext(w, _MMIO(0x4400), 2104 RING_FORCE_TO_NONPRIV_DENY | 2105 RING_FORCE_TO_NONPRIV_RANGE_64); 2106 whitelist_reg_ext(w, _MMIO(0x4500), 2107 RING_FORCE_TO_NONPRIV_DENY | 2108 RING_FORCE_TO_NONPRIV_RANGE_64); 2109 } 2110 2111 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2112 { 2113 allow_read_ctx_timestamp(engine); 2114 2115 /* Wa_16014440446:pvc */ 2116 blacklist_trtt(engine); 2117 } 2118 2119 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2120 { 2121 struct drm_i915_private *i915 = engine->i915; 2122 struct i915_wa_list *w = &engine->whitelist; 2123 2124 wa_init_start(w, "whitelist", engine->name); 2125 2126 if (IS_PONTEVECCHIO(i915)) 2127 pvc_whitelist_build(engine); 2128 else if (IS_DG2(i915)) 2129 dg2_whitelist_build(engine); 2130 else if (IS_XEHPSDV(i915)) 2131 xehpsdv_whitelist_build(engine); 2132 else if (IS_DG1(i915)) 2133 dg1_whitelist_build(engine); 2134 else if (GRAPHICS_VER(i915) == 12) 2135 tgl_whitelist_build(engine); 2136 else if (GRAPHICS_VER(i915) == 11) 2137 icl_whitelist_build(engine); 2138 else if (IS_COMETLAKE(i915)) 2139 cml_whitelist_build(engine); 2140 else if (IS_COFFEELAKE(i915)) 2141 cfl_whitelist_build(engine); 2142 else if (IS_GEMINILAKE(i915)) 2143 glk_whitelist_build(engine); 2144 else if (IS_KABYLAKE(i915)) 2145 kbl_whitelist_build(engine); 2146 else if (IS_BROXTON(i915)) 2147 bxt_whitelist_build(engine); 2148 else if (IS_SKYLAKE(i915)) 2149 skl_whitelist_build(engine); 2150 else if (GRAPHICS_VER(i915) <= 8) 2151 ; 2152 else 2153 MISSING_CASE(GRAPHICS_VER(i915)); 2154 2155 wa_init_finish(w); 2156 } 2157 2158 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2159 { 2160 const struct i915_wa_list *wal = &engine->whitelist; 2161 struct intel_uncore *uncore = engine->uncore; 2162 const u32 base = engine->mmio_base; 2163 struct i915_wa *wa; 2164 unsigned int i; 2165 2166 if (!wal->count) 2167 return; 2168 2169 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2170 intel_uncore_write(uncore, 2171 RING_FORCE_TO_NONPRIV(base, i), 2172 i915_mmio_reg_offset(wa->reg)); 2173 2174 /* And clear the rest just in case of garbage */ 2175 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2176 intel_uncore_write(uncore, 2177 RING_FORCE_TO_NONPRIV(base, i), 2178 i915_mmio_reg_offset(RING_NOPID(base))); 2179 } 2180 2181 /* 2182 * engine_fake_wa_init(), a place holder to program the registers 2183 * which are not part of an official workaround defined by the 2184 * hardware team. 2185 * Adding programming of those register inside workaround will 2186 * allow utilizing wa framework to proper application and verification. 2187 */ 2188 static void 2189 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2190 { 2191 u8 mocs_w, mocs_r; 2192 2193 /* 2194 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2195 * by the command streamer when executing commands that don't have 2196 * a way to explicitly specify a MOCS setting. The default should 2197 * usually reference whichever MOCS entry corresponds to uncached 2198 * behavior, although use of a WB cached entry is recommended by the 2199 * spec in certain circumstances on specific platforms. 2200 */ 2201 if (GRAPHICS_VER(engine->i915) >= 12) { 2202 mocs_r = engine->gt->mocs.uc_index; 2203 mocs_w = engine->gt->mocs.uc_index; 2204 2205 if (HAS_L3_CCS_READ(engine->i915) && 2206 engine->class == COMPUTE_CLASS) { 2207 mocs_r = engine->gt->mocs.wb_index; 2208 2209 /* 2210 * Even on the few platforms where MOCS 0 is a 2211 * legitimate table entry, it's never the correct 2212 * setting to use here; we can assume the MOCS init 2213 * just forgot to initialize wb_index. 2214 */ 2215 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2216 } 2217 2218 wa_masked_field_set(wal, 2219 RING_CMD_CCTL(engine->mmio_base), 2220 CMD_CCTL_MOCS_MASK, 2221 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2222 } 2223 } 2224 2225 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2226 { 2227 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2228 GEN_DSS_PER_GSLICE; 2229 } 2230 2231 static void 2232 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2233 { 2234 struct drm_i915_private *i915 = engine->i915; 2235 2236 if (IS_DG2(i915)) { 2237 /* Wa_1509235366:dg2 */ 2238 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2239 GLOBAL_INVALIDATION_MODE); 2240 } 2241 2242 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2243 /* Wa_14013392000:dg2_g11 */ 2244 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2245 } 2246 2247 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2248 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2249 /* Wa_1509727124:dg2 */ 2250 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2251 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2252 } 2253 2254 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2255 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2256 /* Wa_14012419201:dg2 */ 2257 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2258 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2259 } 2260 2261 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2262 IS_DG2_G11(i915)) { 2263 /* 2264 * Wa_22012826095:dg2 2265 * Wa_22013059131:dg2 2266 */ 2267 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2268 MAXREQS_PER_BANK, 2269 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2270 2271 /* Wa_22013059131:dg2 */ 2272 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2273 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2274 } 2275 2276 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2277 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2278 needs_wa_1308578152(engine)) { 2279 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2280 GEN12_REPLAY_MODE_GRANULARITY); 2281 } 2282 2283 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2284 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2285 /* Wa_22013037850:dg2 */ 2286 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2287 DISABLE_128B_EVICTION_COMMAND_UDW); 2288 2289 /* Wa_22012856258:dg2 */ 2290 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2291 GEN12_DISABLE_READ_SUPPRESSION); 2292 2293 /* 2294 * Wa_22010960976:dg2 2295 * Wa_14013347512:dg2 2296 */ 2297 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2298 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2299 } 2300 2301 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2302 /* 2303 * Wa_1608949956:dg2_g10 2304 * Wa_14010198302:dg2_g10 2305 */ 2306 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2307 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2308 2309 /* 2310 * Wa_14010918519:dg2_g10 2311 * 2312 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2313 * so ignoring verification. 2314 */ 2315 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2316 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2317 0, false); 2318 } 2319 2320 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2321 /* Wa_22010430635:dg2 */ 2322 wa_mcr_masked_en(wal, 2323 GEN9_ROW_CHICKEN4, 2324 GEN12_DISABLE_GRF_CLEAR); 2325 2326 /* Wa_14010648519:dg2 */ 2327 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2328 } 2329 2330 /* Wa_14013202645:dg2 */ 2331 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2332 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2333 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2334 2335 /* Wa_22012532006:dg2 */ 2336 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2337 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2338 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2339 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2340 2341 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2342 /* Wa_14010680813:dg2_g10 */ 2343 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2344 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2345 } 2346 2347 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2348 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2349 /* Wa_14012362059:dg2 */ 2350 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2351 } 2352 2353 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2354 IS_DG2_G10(i915)) { 2355 /* Wa_22014600077:dg2 */ 2356 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2357 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2358 0 /* Wa_14012342262 write-only reg, so skip verification */, 2359 true); 2360 } 2361 2362 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2363 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2364 /* 2365 * Wa_1607138336:tgl[a0],dg1[a0] 2366 * Wa_1607063988:tgl[a0],dg1[a0] 2367 */ 2368 wa_write_or(wal, 2369 GEN9_CTX_PREEMPT_REG, 2370 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2371 } 2372 2373 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2374 /* 2375 * Wa_1606679103:tgl 2376 * (see also Wa_1606682166:icl) 2377 */ 2378 wa_write_or(wal, 2379 GEN7_SARCHKMD, 2380 GEN7_DISABLE_SAMPLER_PREFETCH); 2381 } 2382 2383 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2384 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2385 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2386 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2387 2388 /* 2389 * Wa_1407928979:tgl A* 2390 * Wa_18011464164:tgl[B0+],dg1[B0+] 2391 * Wa_22010931296:tgl[B0+],dg1[B0+] 2392 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2393 */ 2394 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2395 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2396 } 2397 2398 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2399 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2400 /* 2401 * Wa_1606700617:tgl,dg1,adl-p 2402 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2403 * Wa_14010826681:tgl,dg1,rkl,adl-p 2404 * Wa_18019627453:dg2 2405 */ 2406 wa_masked_en(wal, 2407 GEN9_CS_DEBUG_MODE1, 2408 FF_DOP_CLOCK_GATE_DISABLE); 2409 } 2410 2411 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2412 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2413 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2414 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2415 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2416 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2417 2418 /* 2419 * Wa_1409085225:tgl 2420 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2421 */ 2422 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2423 } 2424 2425 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2426 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2427 /* 2428 * Wa_1607030317:tgl 2429 * Wa_1607186500:tgl 2430 * Wa_1607297627:tgl,rkl,dg1[a0] 2431 * 2432 * On TGL and RKL there are multiple entries for this WA in the 2433 * BSpec; some indicate this is an A0-only WA, others indicate 2434 * it applies to all steppings so we trust the "all steppings." 2435 * For DG1 this only applies to A0. 2436 */ 2437 wa_masked_en(wal, 2438 RING_PSMI_CTL(RENDER_RING_BASE), 2439 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2440 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2441 } 2442 2443 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2444 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2445 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2446 wa_mcr_masked_en(wal, 2447 GEN10_SAMPLER_MODE, 2448 ENABLE_SMALLPL); 2449 } 2450 2451 if (GRAPHICS_VER(i915) == 11) { 2452 /* This is not an Wa. Enable for better image quality */ 2453 wa_masked_en(wal, 2454 _3D_CHICKEN3, 2455 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2456 2457 /* 2458 * Wa_1405543622:icl 2459 * Formerly known as WaGAPZPriorityScheme 2460 */ 2461 wa_write_or(wal, 2462 GEN8_GARBCNTL, 2463 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2464 2465 /* 2466 * Wa_1604223664:icl 2467 * Formerly known as WaL3BankAddressHashing 2468 */ 2469 wa_write_clr_set(wal, 2470 GEN8_GARBCNTL, 2471 GEN11_HASH_CTRL_EXCL_MASK, 2472 GEN11_HASH_CTRL_EXCL_BIT0); 2473 wa_write_clr_set(wal, 2474 GEN11_GLBLINVL, 2475 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2476 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2477 2478 /* 2479 * Wa_1405733216:icl 2480 * Formerly known as WaDisableCleanEvicts 2481 */ 2482 wa_mcr_write_or(wal, 2483 GEN8_L3SQCREG4, 2484 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2485 2486 /* Wa_1606682166:icl */ 2487 wa_write_or(wal, 2488 GEN7_SARCHKMD, 2489 GEN7_DISABLE_SAMPLER_PREFETCH); 2490 2491 /* Wa_1409178092:icl */ 2492 wa_mcr_write_clr_set(wal, 2493 GEN11_SCRATCH2, 2494 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2495 0); 2496 2497 /* WaEnable32PlaneMode:icl */ 2498 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2499 GEN11_ENABLE_32_PLANE_MODE); 2500 2501 /* 2502 * Wa_1408615072:icl,ehl (vsunit) 2503 * Wa_1407596294:icl,ehl (hsunit) 2504 */ 2505 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2506 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2507 2508 /* 2509 * Wa_1408767742:icl[a2..forever],ehl[all] 2510 * Wa_1605460711:icl[a0..c0] 2511 */ 2512 wa_write_or(wal, 2513 GEN7_FF_THREAD_MODE, 2514 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2515 2516 /* Wa_22010271021 */ 2517 wa_masked_en(wal, 2518 GEN9_CS_DEBUG_MODE1, 2519 FF_DOP_CLOCK_GATE_DISABLE); 2520 } 2521 2522 /* 2523 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2524 * beyond) allow the kernel-mode driver to choose between two different 2525 * options for controlling preemption granularity and behavior. 2526 * 2527 * Option 1 (hardware default): 2528 * Preemption settings are controlled in a global manner via 2529 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2530 * and settings chosen by the kernel-mode driver will apply to all 2531 * userspace clients. 2532 * 2533 * Option 2: 2534 * Preemption settings are controlled on a per-context basis via 2535 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2536 * context switch and is writable by userspace (e.g., via 2537 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2538 * which allows different userspace drivers/clients to select 2539 * different settings, or to change those settings on the fly in 2540 * response to runtime needs. This option was known by name 2541 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2542 * that name is somewhat misleading as other non-granularity 2543 * preemption settings are also impacted by this decision. 2544 * 2545 * On Linux, our policy has always been to let userspace drivers 2546 * control preemption granularity/settings (Option 2). This was 2547 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2548 * userspace developed before object-level preemption was enabled would 2549 * not behave well if i915 were to go with Option 1 and enable that 2550 * preemption in a global manner). On gen9 each context would have 2551 * object-level preemption disabled by default (see 2552 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2553 * userspace drivers could opt-in to object-level preemption as they 2554 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2555 * even though it is no longer necessary for ABI compatibility when 2556 * enabling a new platform, it does ensure that userspace will be able 2557 * to implement any workarounds that show up requiring temporary 2558 * adjustments to preemption behavior at runtime. 2559 * 2560 * Notes/Workarounds: 2561 * - Wa_14015141709: On DG2 and early steppings of MTL, 2562 * CS_CHICKEN1[0] does not disable object-level preemption as 2563 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2564 * using Option 1). Effectively this means userspace is unable 2565 * to disable object-level preemption on these platforms/steppings 2566 * despite the setting here. 2567 * 2568 * - Wa_16013994831: May require that userspace program 2569 * CS_CHICKEN1[10] when certain runtime conditions are true. 2570 * Userspace requires Option 2 to be in effect for their update of 2571 * CS_CHICKEN1[10] to be effective. 2572 * 2573 * Other workarounds may appear in the future that will also require 2574 * Option 2 behavior to allow proper userspace implementation. 2575 */ 2576 if (GRAPHICS_VER(i915) >= 9) 2577 wa_masked_en(wal, 2578 GEN7_FF_SLICE_CS_CHICKEN1, 2579 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2580 2581 if (IS_SKYLAKE(i915) || 2582 IS_KABYLAKE(i915) || 2583 IS_COFFEELAKE(i915) || 2584 IS_COMETLAKE(i915)) { 2585 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2586 wa_write_or(wal, 2587 GEN8_GARBCNTL, 2588 GEN9_GAPS_TSV_CREDIT_DISABLE); 2589 } 2590 2591 if (IS_BROXTON(i915)) { 2592 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2593 wa_masked_en(wal, 2594 FF_SLICE_CS_CHICKEN2, 2595 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2596 } 2597 2598 if (GRAPHICS_VER(i915) == 9) { 2599 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2600 wa_masked_en(wal, 2601 GEN9_CSFE_CHICKEN1_RCS, 2602 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2603 2604 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2605 wa_mcr_write_or(wal, 2606 BDW_SCRATCH1, 2607 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2608 2609 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2610 if (IS_GEN9_LP(i915)) 2611 wa_mcr_write_clr_set(wal, 2612 GEN8_L3SQCREG1, 2613 L3_PRIO_CREDITS_MASK, 2614 L3_GENERAL_PRIO_CREDITS(62) | 2615 L3_HIGH_PRIO_CREDITS(2)); 2616 2617 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2618 wa_mcr_write_or(wal, 2619 GEN8_L3SQCREG4, 2620 GEN8_LQSC_FLUSH_COHERENT_LINES); 2621 2622 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2623 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2624 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2625 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2626 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2627 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2628 EVICTION_PERF_FIX_ENABLE, 0); 2629 } 2630 2631 if (IS_HASWELL(i915)) { 2632 /* WaSampleCChickenBitEnable:hsw */ 2633 wa_masked_en(wal, 2634 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2635 2636 wa_masked_dis(wal, 2637 CACHE_MODE_0_GEN7, 2638 /* enable HiZ Raw Stall Optimization */ 2639 HIZ_RAW_STALL_OPT_DISABLE); 2640 } 2641 2642 if (IS_VALLEYVIEW(i915)) { 2643 /* WaDisableEarlyCull:vlv */ 2644 wa_masked_en(wal, 2645 _3D_CHICKEN3, 2646 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2647 2648 /* 2649 * WaVSThreadDispatchOverride:ivb,vlv 2650 * 2651 * This actually overrides the dispatch 2652 * mode for all thread types. 2653 */ 2654 wa_write_clr_set(wal, 2655 GEN7_FF_THREAD_MODE, 2656 GEN7_FF_SCHED_MASK, 2657 GEN7_FF_TS_SCHED_HW | 2658 GEN7_FF_VS_SCHED_HW | 2659 GEN7_FF_DS_SCHED_HW); 2660 2661 /* WaPsdDispatchEnable:vlv */ 2662 /* WaDisablePSDDualDispatchEnable:vlv */ 2663 wa_masked_en(wal, 2664 GEN7_HALF_SLICE_CHICKEN1, 2665 GEN7_MAX_PS_THREAD_DEP | 2666 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2667 } 2668 2669 if (IS_IVYBRIDGE(i915)) { 2670 /* WaDisableEarlyCull:ivb */ 2671 wa_masked_en(wal, 2672 _3D_CHICKEN3, 2673 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2674 2675 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2676 /* enable HiZ Raw Stall Optimization */ 2677 wa_masked_dis(wal, 2678 CACHE_MODE_0_GEN7, 2679 HIZ_RAW_STALL_OPT_DISABLE); 2680 } 2681 2682 /* 2683 * WaVSThreadDispatchOverride:ivb,vlv 2684 * 2685 * This actually overrides the dispatch 2686 * mode for all thread types. 2687 */ 2688 wa_write_clr_set(wal, 2689 GEN7_FF_THREAD_MODE, 2690 GEN7_FF_SCHED_MASK, 2691 GEN7_FF_TS_SCHED_HW | 2692 GEN7_FF_VS_SCHED_HW | 2693 GEN7_FF_DS_SCHED_HW); 2694 2695 /* WaDisablePSDDualDispatchEnable:ivb */ 2696 if (IS_IVB_GT1(i915)) 2697 wa_masked_en(wal, 2698 GEN7_HALF_SLICE_CHICKEN1, 2699 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2700 } 2701 2702 if (GRAPHICS_VER(i915) == 7) { 2703 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2704 wa_masked_en(wal, 2705 RING_MODE_GEN7(RENDER_RING_BASE), 2706 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2707 2708 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2709 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2710 2711 /* 2712 * BSpec says this must be set, even though 2713 * WaDisable4x2SubspanOptimization:ivb,hsw 2714 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2715 */ 2716 wa_masked_en(wal, 2717 CACHE_MODE_1, 2718 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2719 2720 /* 2721 * BSpec recommends 8x4 when MSAA is used, 2722 * however in practice 16x4 seems fastest. 2723 * 2724 * Note that PS/WM thread counts depend on the WIZ hashing 2725 * disable bit, which we don't touch here, but it's good 2726 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2727 */ 2728 wa_masked_field_set(wal, 2729 GEN7_GT_MODE, 2730 GEN6_WIZ_HASHING_MASK, 2731 GEN6_WIZ_HASHING_16x4); 2732 } 2733 2734 if (IS_GRAPHICS_VER(i915, 6, 7)) 2735 /* 2736 * We need to disable the AsyncFlip performance optimisations in 2737 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2738 * already be programmed to '1' on all products. 2739 * 2740 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2741 */ 2742 wa_masked_en(wal, 2743 RING_MI_MODE(RENDER_RING_BASE), 2744 ASYNC_FLIP_PERF_DISABLE); 2745 2746 if (GRAPHICS_VER(i915) == 6) { 2747 /* 2748 * Required for the hardware to program scanline values for 2749 * waiting 2750 * WaEnableFlushTlbInvalidationMode:snb 2751 */ 2752 wa_masked_en(wal, 2753 GFX_MODE, 2754 GFX_TLB_INVALIDATE_EXPLICIT); 2755 2756 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2757 wa_masked_en(wal, 2758 _3D_CHICKEN, 2759 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2760 2761 wa_masked_en(wal, 2762 _3D_CHICKEN3, 2763 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2764 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2765 /* 2766 * Bspec says: 2767 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2768 * to normal and 3DSTATE_SF number of SF output attributes 2769 * is more than 16." 2770 */ 2771 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2772 2773 /* 2774 * BSpec recommends 8x4 when MSAA is used, 2775 * however in practice 16x4 seems fastest. 2776 * 2777 * Note that PS/WM thread counts depend on the WIZ hashing 2778 * disable bit, which we don't touch here, but it's good 2779 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2780 */ 2781 wa_masked_field_set(wal, 2782 GEN6_GT_MODE, 2783 GEN6_WIZ_HASHING_MASK, 2784 GEN6_WIZ_HASHING_16x4); 2785 2786 /* WaDisable_RenderCache_OperationalFlush:snb */ 2787 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2788 2789 /* 2790 * From the Sandybridge PRM, volume 1 part 3, page 24: 2791 * "If this bit is set, STCunit will have LRA as replacement 2792 * policy. [...] This bit must be reset. LRA replacement 2793 * policy is not supported." 2794 */ 2795 wa_masked_dis(wal, 2796 CACHE_MODE_0, 2797 CM0_STC_EVICT_DISABLE_LRA_SNB); 2798 } 2799 2800 if (IS_GRAPHICS_VER(i915, 4, 6)) 2801 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2802 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2803 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2804 /* XXX bit doesn't stick on Broadwater */ 2805 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2806 2807 if (GRAPHICS_VER(i915) == 4) 2808 /* 2809 * Disable CONSTANT_BUFFER before it is loaded from the context 2810 * image. For as it is loaded, it is executed and the stored 2811 * address may no longer be valid, leading to a GPU hang. 2812 * 2813 * This imposes the requirement that userspace reload their 2814 * CONSTANT_BUFFER on every batch, fortunately a requirement 2815 * they are already accustomed to from before contexts were 2816 * enabled. 2817 */ 2818 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2819 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2820 0 /* XXX bit doesn't stick on Broadwater */, 2821 true); 2822 } 2823 2824 static void 2825 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2826 { 2827 struct drm_i915_private *i915 = engine->i915; 2828 2829 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2830 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2831 wa_write(wal, 2832 RING_SEMA_WAIT_POLL(engine->mmio_base), 2833 1); 2834 } 2835 } 2836 2837 static void 2838 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2839 { 2840 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2841 /* Wa_14014999345:pvc */ 2842 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2843 } 2844 } 2845 2846 /* 2847 * The bspec performance guide has recommended MMIO tuning settings. These 2848 * aren't truly "workarounds" but we want to program them with the same 2849 * workaround infrastructure to ensure that they're automatically added to 2850 * the GuC save/restore lists, re-applied at the right times, and checked for 2851 * any conflicting programming requested by real workarounds. 2852 * 2853 * Programming settings should be added here only if their registers are not 2854 * part of an engine's register state context. If a register is part of a 2855 * context, then any tuning settings should be programmed in an appropriate 2856 * function invoked by __intel_engine_init_ctx_wa(). 2857 */ 2858 static void 2859 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2860 struct i915_wa_list *wal) 2861 { 2862 if (IS_PONTEVECCHIO(i915)) { 2863 wa_write(wal, XEHPC_L3SCRUB, 2864 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2865 } 2866 2867 if (IS_DG2(i915)) { 2868 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2869 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2870 2871 /* 2872 * This is also listed as Wa_22012654132 for certain DG2 2873 * steppings, but the tuning setting programming is a superset 2874 * since it applies to all DG2 variants and steppings. 2875 * 2876 * Note that register 0xE420 is write-only and cannot be read 2877 * back for verification on DG2 (due to Wa_14012342262), so 2878 * we need to explicitly skip the readback. 2879 */ 2880 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2881 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2882 0 /* write-only, so skip validation */, 2883 true); 2884 } 2885 2886 /* 2887 * This tuning setting proves beneficial only on ATS-M designs; the 2888 * default "age based" setting is optimal on regular DG2 and other 2889 * platforms. 2890 */ 2891 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2892 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2893 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2894 } 2895 2896 /* 2897 * The workarounds in this function apply to shared registers in 2898 * the general render reset domain that aren't tied to a 2899 * specific engine. Since all render+compute engines get reset 2900 * together, and the contents of these registers are lost during 2901 * the shared render domain reset, we'll define such workarounds 2902 * here and then add them to just a single RCS or CCS engine's 2903 * workaround list (whichever engine has the XXXX flag). 2904 */ 2905 static void 2906 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2907 { 2908 struct drm_i915_private *i915 = engine->i915; 2909 2910 add_render_compute_tuning_settings(i915, wal); 2911 2912 if (IS_PONTEVECCHIO(i915)) { 2913 /* Wa_16016694945 */ 2914 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 2915 } 2916 2917 if (IS_XEHPSDV(i915)) { 2918 /* Wa_1409954639 */ 2919 wa_mcr_masked_en(wal, 2920 GEN8_ROW_CHICKEN, 2921 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2922 2923 /* Wa_1607196519 */ 2924 wa_mcr_masked_en(wal, 2925 GEN9_ROW_CHICKEN4, 2926 GEN12_DISABLE_GRF_CLEAR); 2927 2928 /* Wa_14010670810:xehpsdv */ 2929 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2930 2931 /* Wa_14010449647:xehpsdv */ 2932 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2933 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2934 2935 /* Wa_18011725039:xehpsdv */ 2936 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2937 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2938 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2939 } 2940 2941 /* Wa_14012362059:xehpsdv */ 2942 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2943 2944 /* Wa_14014368820:xehpsdv */ 2945 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2946 GLOBAL_INVALIDATION_MODE); 2947 } 2948 2949 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 2950 /* Wa_14015227452:dg2,pvc */ 2951 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2952 2953 /* Wa_22014226127:dg2,pvc */ 2954 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2955 2956 /* Wa_16015675438:dg2,pvc */ 2957 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2958 2959 /* Wa_18018781329:dg2,pvc */ 2960 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2961 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2962 wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2963 wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2964 } 2965 2966 if (IS_DG2(i915)) { 2967 /* 2968 * Wa_16011620976:dg2_g11 2969 * Wa_22015475538:dg2 2970 */ 2971 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2972 } 2973 } 2974 2975 static void 2976 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2977 { 2978 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2979 return; 2980 2981 engine_fake_wa_init(engine, wal); 2982 2983 /* 2984 * These are common workarounds that just need to applied 2985 * to a single RCS/CCS engine's workaround list since 2986 * they're reset as part of the general render domain reset. 2987 */ 2988 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 2989 general_render_compute_wa_init(engine, wal); 2990 2991 if (engine->class == COMPUTE_CLASS) 2992 ccs_engine_wa_init(engine, wal); 2993 else if (engine->class == RENDER_CLASS) 2994 rcs_engine_wa_init(engine, wal); 2995 else 2996 xcs_engine_wa_init(engine, wal); 2997 } 2998 2999 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3000 { 3001 struct i915_wa_list *wal = &engine->wa_list; 3002 3003 if (GRAPHICS_VER(engine->i915) < 4) 3004 return; 3005 3006 wa_init_start(wal, "engine", engine->name); 3007 engine_init_workarounds(engine, wal); 3008 wa_init_finish(wal); 3009 } 3010 3011 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3012 { 3013 wa_list_apply(engine->gt, &engine->wa_list); 3014 } 3015 3016 static const struct i915_range mcr_ranges_gen8[] = { 3017 { .start = 0x5500, .end = 0x55ff }, 3018 { .start = 0x7000, .end = 0x7fff }, 3019 { .start = 0x9400, .end = 0x97ff }, 3020 { .start = 0xb000, .end = 0xb3ff }, 3021 { .start = 0xe000, .end = 0xe7ff }, 3022 {}, 3023 }; 3024 3025 static const struct i915_range mcr_ranges_gen12[] = { 3026 { .start = 0x8150, .end = 0x815f }, 3027 { .start = 0x9520, .end = 0x955f }, 3028 { .start = 0xb100, .end = 0xb3ff }, 3029 { .start = 0xde80, .end = 0xe8ff }, 3030 { .start = 0x24a00, .end = 0x24a7f }, 3031 {}, 3032 }; 3033 3034 static const struct i915_range mcr_ranges_xehp[] = { 3035 { .start = 0x4000, .end = 0x4aff }, 3036 { .start = 0x5200, .end = 0x52ff }, 3037 { .start = 0x5400, .end = 0x7fff }, 3038 { .start = 0x8140, .end = 0x815f }, 3039 { .start = 0x8c80, .end = 0x8dff }, 3040 { .start = 0x94d0, .end = 0x955f }, 3041 { .start = 0x9680, .end = 0x96ff }, 3042 { .start = 0xb000, .end = 0xb3ff }, 3043 { .start = 0xc800, .end = 0xcfff }, 3044 { .start = 0xd800, .end = 0xd8ff }, 3045 { .start = 0xdc00, .end = 0xffff }, 3046 { .start = 0x17000, .end = 0x17fff }, 3047 { .start = 0x24a00, .end = 0x24a7f }, 3048 {}, 3049 }; 3050 3051 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3052 { 3053 const struct i915_range *mcr_ranges; 3054 int i; 3055 3056 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3057 mcr_ranges = mcr_ranges_xehp; 3058 else if (GRAPHICS_VER(i915) >= 12) 3059 mcr_ranges = mcr_ranges_gen12; 3060 else if (GRAPHICS_VER(i915) >= 8) 3061 mcr_ranges = mcr_ranges_gen8; 3062 else 3063 return false; 3064 3065 /* 3066 * Registers in these ranges are affected by the MCR selector 3067 * which only controls CPU initiated MMIO. Routing does not 3068 * work for CS access so we cannot verify them on this path. 3069 */ 3070 for (i = 0; mcr_ranges[i].start; i++) 3071 if (offset >= mcr_ranges[i].start && 3072 offset <= mcr_ranges[i].end) 3073 return true; 3074 3075 return false; 3076 } 3077 3078 static int 3079 wa_list_srm(struct i915_request *rq, 3080 const struct i915_wa_list *wal, 3081 struct i915_vma *vma) 3082 { 3083 struct drm_i915_private *i915 = rq->engine->i915; 3084 unsigned int i, count = 0; 3085 const struct i915_wa *wa; 3086 u32 srm, *cs; 3087 3088 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3089 if (GRAPHICS_VER(i915) >= 8) 3090 srm++; 3091 3092 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3093 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3094 count++; 3095 } 3096 3097 cs = intel_ring_begin(rq, 4 * count); 3098 if (IS_ERR(cs)) 3099 return PTR_ERR(cs); 3100 3101 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3102 u32 offset = i915_mmio_reg_offset(wa->reg); 3103 3104 if (mcr_range(i915, offset)) 3105 continue; 3106 3107 *cs++ = srm; 3108 *cs++ = offset; 3109 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3110 *cs++ = 0; 3111 } 3112 intel_ring_advance(rq, cs); 3113 3114 return 0; 3115 } 3116 3117 static int engine_wa_list_verify(struct intel_context *ce, 3118 const struct i915_wa_list * const wal, 3119 const char *from) 3120 { 3121 const struct i915_wa *wa; 3122 struct i915_request *rq; 3123 struct i915_vma *vma; 3124 struct i915_gem_ww_ctx ww; 3125 unsigned int i; 3126 u32 *results; 3127 int err; 3128 3129 if (!wal->count) 3130 return 0; 3131 3132 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3133 wal->count * sizeof(u32)); 3134 if (IS_ERR(vma)) 3135 return PTR_ERR(vma); 3136 3137 intel_engine_pm_get(ce->engine); 3138 i915_gem_ww_ctx_init(&ww, false); 3139 retry: 3140 err = i915_gem_object_lock(vma->obj, &ww); 3141 if (err == 0) 3142 err = intel_context_pin_ww(ce, &ww); 3143 if (err) 3144 goto err_pm; 3145 3146 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3147 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3148 if (err) 3149 goto err_unpin; 3150 3151 rq = i915_request_create(ce); 3152 if (IS_ERR(rq)) { 3153 err = PTR_ERR(rq); 3154 goto err_vma; 3155 } 3156 3157 err = i915_request_await_object(rq, vma->obj, true); 3158 if (err == 0) 3159 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3160 if (err == 0) 3161 err = wa_list_srm(rq, wal, vma); 3162 3163 i915_request_get(rq); 3164 if (err) 3165 i915_request_set_error_once(rq, err); 3166 i915_request_add(rq); 3167 3168 if (err) 3169 goto err_rq; 3170 3171 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3172 err = -ETIME; 3173 goto err_rq; 3174 } 3175 3176 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3177 if (IS_ERR(results)) { 3178 err = PTR_ERR(results); 3179 goto err_rq; 3180 } 3181 3182 err = 0; 3183 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3184 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3185 continue; 3186 3187 if (!wa_verify(wa, results[i], wal->name, from)) 3188 err = -ENXIO; 3189 } 3190 3191 i915_gem_object_unpin_map(vma->obj); 3192 3193 err_rq: 3194 i915_request_put(rq); 3195 err_vma: 3196 i915_vma_unpin(vma); 3197 err_unpin: 3198 intel_context_unpin(ce); 3199 err_pm: 3200 if (err == -EDEADLK) { 3201 err = i915_gem_ww_ctx_backoff(&ww); 3202 if (!err) 3203 goto retry; 3204 } 3205 i915_gem_ww_ctx_fini(&ww); 3206 intel_engine_pm_put(ce->engine); 3207 i915_vma_put(vma); 3208 return err; 3209 } 3210 3211 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3212 const char *from) 3213 { 3214 return engine_wa_list_verify(engine->kernel_context, 3215 &engine->wa_list, 3216 from); 3217 } 3218 3219 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3220 #include "selftest_workarounds.c" 3221 #endif 3222