1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_gpu_commands.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) { 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 kfree(wal->list); 106 } 107 108 wal->list = list; 109 } 110 111 while (start < end) { 112 unsigned int mid = start + (end - start) / 2; 113 114 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 115 start = mid + 1; 116 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 117 end = mid; 118 } else { 119 wa_ = &wal->list[mid]; 120 121 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 122 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 123 i915_mmio_reg_offset(wa_->reg), 124 wa_->clr, wa_->set); 125 126 wa_->set &= ~wa->clr; 127 } 128 129 wal->wa_count++; 130 wa_->set |= wa->set; 131 wa_->clr |= wa->clr; 132 wa_->read |= wa->read; 133 return; 134 } 135 } 136 137 wal->wa_count++; 138 wa_ = &wal->list[wal->count++]; 139 *wa_ = *wa; 140 141 while (wa_-- > wal->list) { 142 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 143 i915_mmio_reg_offset(wa_[1].reg)); 144 if (i915_mmio_reg_offset(wa_[1].reg) > 145 i915_mmio_reg_offset(wa_[0].reg)) 146 break; 147 148 swap(wa_[1], wa_[0]); 149 } 150 } 151 152 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 153 u32 clear, u32 set, u32 read_mask, bool masked_reg) 154 { 155 struct i915_wa wa = { 156 .reg = reg, 157 .clr = clear, 158 .set = set, 159 .read = read_mask, 160 .masked_reg = masked_reg, 161 }; 162 163 _wa_add(wal, &wa); 164 } 165 166 static void 167 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 168 { 169 wa_add(wal, reg, clear, set, clear, false); 170 } 171 172 static void 173 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 174 { 175 wa_write_clr_set(wal, reg, ~0, set); 176 } 177 178 static void 179 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 180 { 181 wa_write_clr_set(wal, reg, set, set); 182 } 183 184 static void 185 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 186 { 187 wa_write_clr_set(wal, reg, clr, 0); 188 } 189 190 /* 191 * WA operations on "masked register". A masked register has the upper 16 bits 192 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 193 * portion of the register without a rmw: you simply write in the upper 16 bits 194 * the mask of bits you are going to modify. 195 * 196 * The wa_masked_* family of functions already does the necessary operations to 197 * calculate the mask based on the parameters passed, so user only has to 198 * provide the lower 16 bits of that register. 199 */ 200 201 static void 202 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 203 { 204 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 205 } 206 207 static void 208 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 209 { 210 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 211 } 212 213 static void 214 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 215 u32 mask, u32 val) 216 { 217 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 218 } 219 220 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 221 struct i915_wa_list *wal) 222 { 223 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 224 } 225 226 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 227 struct i915_wa_list *wal) 228 { 229 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 230 } 231 232 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 233 struct i915_wa_list *wal) 234 { 235 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 236 237 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 238 wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE); 239 240 /* WaDisablePartialInstShootdown:bdw,chv */ 241 wa_masked_en(wal, GEN8_ROW_CHICKEN, 242 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 243 244 /* Use Force Non-Coherent whenever executing a 3D context. This is a 245 * workaround for a possible hang in the unlikely event a TLB 246 * invalidation occurs during a PSD flush. 247 */ 248 /* WaForceEnableNonCoherent:bdw,chv */ 249 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 250 wa_masked_en(wal, HDC_CHICKEN0, 251 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 252 HDC_FORCE_NON_COHERENT); 253 254 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 255 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 256 * polygons in the same 8x4 pixel/sample area to be processed without 257 * stalling waiting for the earlier ones to write to Hierarchical Z 258 * buffer." 259 * 260 * This optimization is off by default for BDW and CHV; turn it on. 261 */ 262 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 263 264 /* Wa4x4STCOptimizationDisable:bdw,chv */ 265 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 266 267 /* 268 * BSpec recommends 8x4 when MSAA is used, 269 * however in practice 16x4 seems fastest. 270 * 271 * Note that PS/WM thread counts depend on the WIZ hashing 272 * disable bit, which we don't touch here, but it's good 273 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 274 */ 275 wa_masked_field_set(wal, GEN7_GT_MODE, 276 GEN6_WIZ_HASHING_MASK, 277 GEN6_WIZ_HASHING_16x4); 278 } 279 280 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 281 struct i915_wa_list *wal) 282 { 283 struct drm_i915_private *i915 = engine->i915; 284 285 gen8_ctx_workarounds_init(engine, wal); 286 287 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 288 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 289 290 /* WaDisableDopClockGating:bdw 291 * 292 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 293 * to disable EUTC clock gating. 294 */ 295 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 296 DOP_CLOCK_GATING_DISABLE); 297 298 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 299 GEN8_SAMPLER_POWER_BYPASS_DIS); 300 301 wa_masked_en(wal, HDC_CHICKEN0, 302 /* WaForceContextSaveRestoreNonCoherent:bdw */ 303 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 304 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 305 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 306 } 307 308 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 309 struct i915_wa_list *wal) 310 { 311 gen8_ctx_workarounds_init(engine, wal); 312 313 /* WaDisableThreadStallDopClockGating:chv */ 314 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 315 316 /* Improve HiZ throughput on CHV. */ 317 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 318 } 319 320 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 321 struct i915_wa_list *wal) 322 { 323 struct drm_i915_private *i915 = engine->i915; 324 325 if (HAS_LLC(i915)) { 326 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 327 * 328 * Must match Display Engine. See 329 * WaCompressedResourceDisplayNewHashMode. 330 */ 331 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 332 GEN9_PBE_COMPRESSED_HASH_SELECTION); 333 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 334 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 335 } 336 337 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 338 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 339 wa_masked_en(wal, GEN8_ROW_CHICKEN, 340 FLOW_CONTROL_ENABLE | 341 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 342 343 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 344 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 345 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 346 GEN9_ENABLE_YV12_BUGFIX | 347 GEN9_ENABLE_GPGPU_PREEMPTION); 348 349 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 350 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 351 wa_masked_en(wal, CACHE_MODE_1, 352 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 353 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 354 355 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 356 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 357 GEN9_CCS_TLB_PREFETCH_ENABLE); 358 359 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 360 wa_masked_en(wal, HDC_CHICKEN0, 361 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 362 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 363 364 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 365 * both tied to WaForceContextSaveRestoreNonCoherent 366 * in some hsds for skl. We keep the tie for all gen9. The 367 * documentation is a bit hazy and so we want to get common behaviour, 368 * even though there is no clear evidence we would need both on kbl/bxt. 369 * This area has been source of system hangs so we play it safe 370 * and mimic the skl regardless of what bspec says. 371 * 372 * Use Force Non-Coherent whenever executing a 3D context. This 373 * is a workaround for a possible hang in the unlikely event 374 * a TLB invalidation occurs during a PSD flush. 375 */ 376 377 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 378 wa_masked_en(wal, HDC_CHICKEN0, 379 HDC_FORCE_NON_COHERENT); 380 381 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 382 if (IS_SKYLAKE(i915) || 383 IS_KABYLAKE(i915) || 384 IS_COFFEELAKE(i915) || 385 IS_COMETLAKE(i915)) 386 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 387 GEN8_SAMPLER_POWER_BYPASS_DIS); 388 389 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 390 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 391 392 /* 393 * Supporting preemption with fine-granularity requires changes in the 394 * batch buffer programming. Since we can't break old userspace, we 395 * need to set our default preemption level to safe value. Userspace is 396 * still able to use more fine-grained preemption levels, since in 397 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 398 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 399 * not real HW workarounds, but merely a way to start using preemption 400 * while maintaining old contract with userspace. 401 */ 402 403 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 404 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 405 406 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 407 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 408 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 409 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 410 411 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 412 if (IS_GEN9_LP(i915)) 413 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 414 } 415 416 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 417 struct i915_wa_list *wal) 418 { 419 struct intel_gt *gt = engine->gt; 420 u8 vals[3] = { 0, 0, 0 }; 421 unsigned int i; 422 423 for (i = 0; i < 3; i++) { 424 u8 ss; 425 426 /* 427 * Only consider slices where one, and only one, subslice has 7 428 * EUs 429 */ 430 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 431 continue; 432 433 /* 434 * subslice_7eu[i] != 0 (because of the check above) and 435 * ss_max == 4 (maximum number of subslices possible per slice) 436 * 437 * -> 0 <= ss <= 3; 438 */ 439 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 440 vals[i] = 3 - ss; 441 } 442 443 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 444 return; 445 446 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 447 wa_masked_field_set(wal, GEN7_GT_MODE, 448 GEN9_IZ_HASHING_MASK(2) | 449 GEN9_IZ_HASHING_MASK(1) | 450 GEN9_IZ_HASHING_MASK(0), 451 GEN9_IZ_HASHING(2, vals[2]) | 452 GEN9_IZ_HASHING(1, vals[1]) | 453 GEN9_IZ_HASHING(0, vals[0])); 454 } 455 456 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 457 struct i915_wa_list *wal) 458 { 459 gen9_ctx_workarounds_init(engine, wal); 460 skl_tune_iz_hashing(engine, wal); 461 } 462 463 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 464 struct i915_wa_list *wal) 465 { 466 gen9_ctx_workarounds_init(engine, wal); 467 468 /* WaDisableThreadStallDopClockGating:bxt */ 469 wa_masked_en(wal, GEN8_ROW_CHICKEN, 470 STALL_DOP_GATING_DISABLE); 471 472 /* WaToEnableHwFixForPushConstHWBug:bxt */ 473 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 474 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 475 } 476 477 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 478 struct i915_wa_list *wal) 479 { 480 struct drm_i915_private *i915 = engine->i915; 481 482 gen9_ctx_workarounds_init(engine, wal); 483 484 /* WaToEnableHwFixForPushConstHWBug:kbl */ 485 if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER)) 486 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 487 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 488 489 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 490 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 491 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 492 } 493 494 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 495 struct i915_wa_list *wal) 496 { 497 gen9_ctx_workarounds_init(engine, wal); 498 499 /* WaToEnableHwFixForPushConstHWBug:glk */ 500 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 501 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 502 } 503 504 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 505 struct i915_wa_list *wal) 506 { 507 gen9_ctx_workarounds_init(engine, wal); 508 509 /* WaToEnableHwFixForPushConstHWBug:cfl */ 510 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 511 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 512 513 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 514 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 515 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 516 } 517 518 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 519 struct i915_wa_list *wal) 520 { 521 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 522 wa_write(wal, 523 GEN8_L3CNTLREG, 524 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 525 GEN8_ERRDETBCTRL); 526 527 /* WaForceEnableNonCoherent:icl 528 * This is not the same workaround as in early Gen9 platforms, where 529 * lacking this could cause system hangs, but coherency performance 530 * overhead is high and only a few compute workloads really need it 531 * (the register is whitelisted in hardware now, so UMDs can opt in 532 * for coherency if they have a good reason). 533 */ 534 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 535 536 /* WaEnableFloatBlendOptimization:icl */ 537 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 538 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 539 0 /* write-only, so skip validation */, 540 true); 541 542 /* WaDisableGPGPUMidThreadPreemption:icl */ 543 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 544 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 545 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 546 547 /* allow headerless messages for preemptible GPGPU context */ 548 wa_masked_en(wal, GEN10_SAMPLER_MODE, 549 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 550 551 /* Wa_1604278689:icl,ehl */ 552 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 553 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 554 0, /* write-only register; skip validation */ 555 0xFFFFFFFF); 556 557 /* Wa_1406306137:icl,ehl */ 558 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 559 } 560 561 /* 562 * These settings aren't actually workarounds, but general tuning settings that 563 * need to be programmed on several platforms. 564 */ 565 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 566 struct i915_wa_list *wal) 567 { 568 /* 569 * Although some platforms refer to it as Wa_1604555607, we need to 570 * program it even on those that don't explicitly list that 571 * workaround. 572 * 573 * Note that the programming of this register is further modified 574 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 575 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 576 * value when read. The default value for this register is zero for all 577 * fields and there are no bit masks. So instead of doing a RMW we 578 * should just write TDS timer value. For the same reason read 579 * verification is ignored. 580 */ 581 wa_add(wal, 582 FF_MODE2, 583 FF_MODE2_TDS_TIMER_MASK, 584 FF_MODE2_TDS_TIMER_128, 585 0, false); 586 } 587 588 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 589 struct i915_wa_list *wal) 590 { 591 gen12_ctx_gt_tuning_init(engine, wal); 592 593 /* 594 * Wa_1409142259:tgl,dg1,adl-p 595 * Wa_1409347922:tgl,dg1,adl-p 596 * Wa_1409252684:tgl,dg1,adl-p 597 * Wa_1409217633:tgl,dg1,adl-p 598 * Wa_1409207793:tgl,dg1,adl-p 599 * Wa_1409178076:tgl,dg1,adl-p 600 * Wa_1408979724:tgl,dg1,adl-p 601 * Wa_14010443199:tgl,rkl,dg1,adl-p 602 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 603 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 604 */ 605 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 606 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 607 608 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 609 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 610 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 611 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 612 613 /* 614 * Wa_16011163337 615 * 616 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 617 * to Wa_1608008084. 618 */ 619 wa_add(wal, 620 FF_MODE2, 621 FF_MODE2_GS_TIMER_MASK, 622 FF_MODE2_GS_TIMER_224, 623 0, false); 624 625 /* 626 * Wa_14012131227:dg1 627 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 628 */ 629 wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1, 630 GEN9_RHWO_OPTIMIZATION_DISABLE); 631 } 632 633 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 634 struct i915_wa_list *wal) 635 { 636 gen12_ctx_workarounds_init(engine, wal); 637 638 /* Wa_1409044764 */ 639 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 640 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 641 642 /* Wa_22010493298 */ 643 wa_masked_en(wal, HIZ_CHICKEN, 644 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 645 } 646 647 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 648 struct i915_wa_list *wal) 649 { 650 /* 651 * This is a "fake" workaround defined by software to ensure we 652 * maintain reliable, backward-compatible behavior for userspace with 653 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 654 * 655 * The per-context setting of MI_MODE[12] determines whether the bits 656 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 657 * in the traditional manner or whether they should instead use a new 658 * tgl+ meaning that breaks backward compatibility, but allows nesting 659 * into 3rd-level batchbuffers. When this new capability was first 660 * added in TGL, it remained off by default unless a context 661 * intentionally opted in to the new behavior. However Xe_HPG now 662 * flips this on by default and requires that we explicitly opt out if 663 * we don't want the new behavior. 664 * 665 * From a SW perspective, we want to maintain the backward-compatible 666 * behavior for userspace, so we'll apply a fake workaround to set it 667 * back to the legacy behavior on platforms where the hardware default 668 * is to break compatibility. At the moment there is no Linux 669 * userspace that utilizes third-level batchbuffers, so this will avoid 670 * userspace from needing to make any changes. using the legacy 671 * meaning is the correct thing to do. If/when we have userspace 672 * consumers that want to utilize third-level batch nesting, we can 673 * provide a context parameter to allow them to opt-in. 674 */ 675 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 676 } 677 678 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 679 struct i915_wa_list *wal) 680 { 681 u8 mocs; 682 683 /* 684 * Some blitter commands do not have a field for MOCS, those 685 * commands will use MOCS index pointed by BLIT_CCTL. 686 * BLIT_CCTL registers are needed to be programmed to un-cached. 687 */ 688 if (engine->class == COPY_ENGINE_CLASS) { 689 mocs = engine->gt->mocs.uc_index; 690 wa_write_clr_set(wal, 691 BLIT_CCTL(engine->mmio_base), 692 BLIT_CCTL_MASK, 693 BLIT_CCTL_MOCS(mocs, mocs)); 694 } 695 } 696 697 /* 698 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 699 * defined by the hardware team, but it programming general context registers. 700 * Adding those context register programming in context workaround 701 * allow us to use the wa framework for proper application and validation. 702 */ 703 static void 704 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 705 struct i915_wa_list *wal) 706 { 707 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 708 fakewa_disable_nestedbb_mode(engine, wal); 709 710 gen12_ctx_gt_mocs_init(engine, wal); 711 } 712 713 static void 714 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 715 struct i915_wa_list *wal, 716 const char *name) 717 { 718 struct drm_i915_private *i915 = engine->i915; 719 720 wa_init_start(wal, name, engine->name); 721 722 /* Applies to all engines */ 723 /* 724 * Fake workarounds are not the actual workaround but 725 * programming of context registers using workaround framework. 726 */ 727 if (GRAPHICS_VER(i915) >= 12) 728 gen12_ctx_gt_fake_wa_init(engine, wal); 729 730 if (engine->class != RENDER_CLASS) 731 goto done; 732 733 if (IS_DG1(i915)) 734 dg1_ctx_workarounds_init(engine, wal); 735 else if (GRAPHICS_VER(i915) == 12) 736 gen12_ctx_workarounds_init(engine, wal); 737 else if (GRAPHICS_VER(i915) == 11) 738 icl_ctx_workarounds_init(engine, wal); 739 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 740 cfl_ctx_workarounds_init(engine, wal); 741 else if (IS_GEMINILAKE(i915)) 742 glk_ctx_workarounds_init(engine, wal); 743 else if (IS_KABYLAKE(i915)) 744 kbl_ctx_workarounds_init(engine, wal); 745 else if (IS_BROXTON(i915)) 746 bxt_ctx_workarounds_init(engine, wal); 747 else if (IS_SKYLAKE(i915)) 748 skl_ctx_workarounds_init(engine, wal); 749 else if (IS_CHERRYVIEW(i915)) 750 chv_ctx_workarounds_init(engine, wal); 751 else if (IS_BROADWELL(i915)) 752 bdw_ctx_workarounds_init(engine, wal); 753 else if (GRAPHICS_VER(i915) == 7) 754 gen7_ctx_workarounds_init(engine, wal); 755 else if (GRAPHICS_VER(i915) == 6) 756 gen6_ctx_workarounds_init(engine, wal); 757 else if (GRAPHICS_VER(i915) < 8) 758 ; 759 else 760 MISSING_CASE(GRAPHICS_VER(i915)); 761 762 done: 763 wa_init_finish(wal); 764 } 765 766 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 767 { 768 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 769 } 770 771 int intel_engine_emit_ctx_wa(struct i915_request *rq) 772 { 773 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 774 struct i915_wa *wa; 775 unsigned int i; 776 u32 *cs; 777 int ret; 778 779 if (wal->count == 0) 780 return 0; 781 782 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 783 if (ret) 784 return ret; 785 786 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 787 if (IS_ERR(cs)) 788 return PTR_ERR(cs); 789 790 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 791 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 792 *cs++ = i915_mmio_reg_offset(wa->reg); 793 *cs++ = wa->set; 794 } 795 *cs++ = MI_NOOP; 796 797 intel_ring_advance(rq, cs); 798 799 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 800 if (ret) 801 return ret; 802 803 return 0; 804 } 805 806 static void 807 gen4_gt_workarounds_init(struct intel_gt *gt, 808 struct i915_wa_list *wal) 809 { 810 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 811 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 812 } 813 814 static void 815 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 816 { 817 gen4_gt_workarounds_init(gt, wal); 818 819 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 820 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 821 } 822 823 static void 824 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 825 { 826 g4x_gt_workarounds_init(gt, wal); 827 828 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 829 } 830 831 static void 832 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 833 { 834 } 835 836 static void 837 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 838 { 839 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 840 wa_masked_dis(wal, 841 GEN7_COMMON_SLICE_CHICKEN1, 842 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 843 844 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 845 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 846 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 847 848 /* WaForceL3Serialization:ivb */ 849 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 850 } 851 852 static void 853 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 854 { 855 /* WaForceL3Serialization:vlv */ 856 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 857 858 /* 859 * WaIncreaseL3CreditsForVLVB0:vlv 860 * This is the hardware default actually. 861 */ 862 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 863 } 864 865 static void 866 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 867 { 868 /* L3 caching of data atomics doesn't work -- disable it. */ 869 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 870 871 wa_add(wal, 872 HSW_ROW_CHICKEN3, 0, 873 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 874 0 /* XXX does this reg exist? */, true); 875 876 /* WaVSRefCountFullforceMissDisable:hsw */ 877 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 878 } 879 880 static void 881 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 882 { 883 struct drm_i915_private *i915 = gt->i915; 884 885 /* WaDisableKillLogic:bxt,skl,kbl */ 886 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 887 wa_write_or(wal, 888 GAM_ECOCHK, 889 ECOCHK_DIS_TLB); 890 891 if (HAS_LLC(i915)) { 892 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 893 * 894 * Must match Display Engine. See 895 * WaCompressedResourceDisplayNewHashMode. 896 */ 897 wa_write_or(wal, 898 MMCD_MISC_CTRL, 899 MMCD_PCLA | MMCD_HOTSPOT_EN); 900 } 901 902 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 903 wa_write_or(wal, 904 GAM_ECOCHK, 905 BDW_DISABLE_HDC_INVALIDATION); 906 } 907 908 static void 909 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 910 { 911 gen9_gt_workarounds_init(gt, wal); 912 913 /* WaDisableGafsUnitClkGating:skl */ 914 wa_write_or(wal, 915 GEN7_UCGCTL4, 916 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 917 918 /* WaInPlaceDecompressionHang:skl */ 919 if (IS_SKL_GT_STEP(gt->i915, STEP_A0, STEP_H0)) 920 wa_write_or(wal, 921 GEN9_GAMT_ECO_REG_RW_IA, 922 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 923 } 924 925 static void 926 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 927 { 928 gen9_gt_workarounds_init(gt, wal); 929 930 /* WaDisableDynamicCreditSharing:kbl */ 931 if (IS_KBL_GT_STEP(gt->i915, 0, STEP_C0)) 932 wa_write_or(wal, 933 GAMT_CHKN_BIT_REG, 934 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 935 936 /* WaDisableGafsUnitClkGating:kbl */ 937 wa_write_or(wal, 938 GEN7_UCGCTL4, 939 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 940 941 /* WaInPlaceDecompressionHang:kbl */ 942 wa_write_or(wal, 943 GEN9_GAMT_ECO_REG_RW_IA, 944 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 945 } 946 947 static void 948 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 949 { 950 gen9_gt_workarounds_init(gt, wal); 951 } 952 953 static void 954 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 955 { 956 gen9_gt_workarounds_init(gt, wal); 957 958 /* WaDisableGafsUnitClkGating:cfl */ 959 wa_write_or(wal, 960 GEN7_UCGCTL4, 961 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 962 963 /* WaInPlaceDecompressionHang:cfl */ 964 wa_write_or(wal, 965 GEN9_GAMT_ECO_REG_RW_IA, 966 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 967 } 968 969 static void __set_mcr_steering(struct i915_wa_list *wal, 970 i915_reg_t steering_reg, 971 unsigned int slice, unsigned int subslice) 972 { 973 u32 mcr, mcr_mask; 974 975 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 976 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 977 978 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 979 } 980 981 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 982 unsigned int slice, unsigned int subslice) 983 { 984 drm_dbg(>->i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); 985 986 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 987 } 988 989 static void 990 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 991 { 992 const struct sseu_dev_info *sseu = >->info.sseu; 993 unsigned int slice, subslice; 994 995 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 996 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 997 slice = 0; 998 999 /* 1000 * Although a platform may have subslices, we need to always steer 1001 * reads to the lowest instance that isn't fused off. When Render 1002 * Power Gating is enabled, grabbing forcewake will only power up a 1003 * single subslice (the "minconfig") if there isn't a real workload 1004 * that needs to be run; this means that if we steer register reads to 1005 * one of the higher subslices, we run the risk of reading back 0's or 1006 * random garbage. 1007 */ 1008 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); 1009 1010 /* 1011 * If the subslice we picked above also steers us to a valid L3 bank, 1012 * then we can just rely on the default steering and won't need to 1013 * worry about explicitly re-steering L3BANK reads later. 1014 */ 1015 if (gt->info.l3bank_mask & BIT(subslice)) 1016 gt->steering_table[L3BANK] = NULL; 1017 1018 __add_mcr_wa(gt, wal, slice, subslice); 1019 } 1020 1021 static void 1022 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1023 { 1024 const struct sseu_dev_info *sseu = >->info.sseu; 1025 unsigned long slice, subslice = 0, slice_mask = 0; 1026 u64 dss_mask = 0; 1027 u32 lncf_mask = 0; 1028 int i; 1029 1030 /* 1031 * On Xe_HP the steering increases in complexity. There are now several 1032 * more units that require steering and we're not guaranteed to be able 1033 * to find a common setting for all of them. These are: 1034 * - GSLICE (fusable) 1035 * - DSS (sub-unit within gslice; fusable) 1036 * - L3 Bank (fusable) 1037 * - MSLICE (fusable) 1038 * - LNCF (sub-unit within mslice; always present if mslice is present) 1039 * 1040 * We'll do our default/implicit steering based on GSLICE (in the 1041 * sliceid field) and DSS (in the subsliceid field). If we can 1042 * find overlap between the valid MSLICE and/or LNCF values with 1043 * a suitable GSLICE, then we can just re-use the default value and 1044 * skip and explicit steering at runtime. 1045 * 1046 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1047 * a valid sliceid value. DSS steering is the only type of steering 1048 * that utilizes the 'subsliceid' bits. 1049 * 1050 * Also note that, even though the steering domain is called "GSlice" 1051 * and it is encoded in the register using the gslice format, the spec 1052 * says that the combined (geometry | compute) fuse should be used to 1053 * select the steering. 1054 */ 1055 1056 /* Find the potential gslice candidates */ 1057 dss_mask = intel_sseu_get_subslices(sseu, 0); 1058 slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE); 1059 1060 /* 1061 * Find the potential LNCF candidates. Either LNCF within a valid 1062 * mslice is fine. 1063 */ 1064 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1065 lncf_mask |= (0x3 << (i * 2)); 1066 1067 /* 1068 * Are there any sliceid values that work for both GSLICE and LNCF 1069 * steering? 1070 */ 1071 if (slice_mask & lncf_mask) { 1072 slice_mask &= lncf_mask; 1073 gt->steering_table[LNCF] = NULL; 1074 } 1075 1076 /* How about sliceid values that also work for MSLICE steering? */ 1077 if (slice_mask & gt->info.mslice_mask) { 1078 slice_mask &= gt->info.mslice_mask; 1079 gt->steering_table[MSLICE] = NULL; 1080 } 1081 1082 slice = __ffs(slice_mask); 1083 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); 1084 WARN_ON(subslice > GEN_DSS_PER_GSLICE); 1085 WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); 1086 1087 __add_mcr_wa(gt, wal, slice, subslice); 1088 1089 /* 1090 * SQIDI ranges are special because they use different steering 1091 * registers than everything else we work with. On XeHP SDV and 1092 * DG2-G10, any value in the steering registers will work fine since 1093 * all instances are present, but DG2-G11 only has SQIDI instances at 1094 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1095 * we'll just steer to a hardcoded "2" since that value will work 1096 * everywhere. 1097 */ 1098 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1099 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1100 } 1101 1102 static void 1103 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1104 { 1105 struct drm_i915_private *i915 = gt->i915; 1106 1107 icl_wa_init_mcr(gt, wal); 1108 1109 /* WaModifyGamTlbPartitioning:icl */ 1110 wa_write_clr_set(wal, 1111 GEN11_GACB_PERF_CTRL, 1112 GEN11_HASH_CTRL_MASK, 1113 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1114 1115 /* Wa_1405766107:icl 1116 * Formerly known as WaCL2SFHalfMaxAlloc 1117 */ 1118 wa_write_or(wal, 1119 GEN11_LSN_UNSLCVC, 1120 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1121 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1122 1123 /* Wa_220166154:icl 1124 * Formerly known as WaDisCtxReload 1125 */ 1126 wa_write_or(wal, 1127 GEN8_GAMW_ECO_DEV_RW_IA, 1128 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1129 1130 /* Wa_1406463099:icl 1131 * Formerly known as WaGamTlbPendError 1132 */ 1133 wa_write_or(wal, 1134 GAMT_CHKN_BIT_REG, 1135 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1136 1137 /* Wa_1607087056:icl,ehl,jsl */ 1138 if (IS_ICELAKE(i915) || 1139 IS_JSL_EHL_GT_STEP(i915, STEP_A0, STEP_B0)) 1140 wa_write_or(wal, 1141 SLICE_UNIT_LEVEL_CLKGATE, 1142 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1143 1144 /* 1145 * This is not a documented workaround, but rather an optimization 1146 * to reduce sampler power. 1147 */ 1148 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1149 } 1150 1151 /* 1152 * Though there are per-engine instances of these registers, 1153 * they retain their value through engine resets and should 1154 * only be provided on the GT workaround list rather than 1155 * the engine-specific workaround list. 1156 */ 1157 static void 1158 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1159 { 1160 struct intel_engine_cs *engine; 1161 int id; 1162 1163 for_each_engine(engine, gt, id) { 1164 if (engine->class != VIDEO_DECODE_CLASS || 1165 (engine->instance % 2)) 1166 continue; 1167 1168 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1169 IECPUNIT_CLKGATE_DIS); 1170 } 1171 } 1172 1173 static void 1174 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1175 { 1176 icl_wa_init_mcr(gt, wal); 1177 1178 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1179 wa_14011060649(gt, wal); 1180 1181 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1182 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1183 } 1184 1185 static void 1186 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1187 { 1188 struct drm_i915_private *i915 = gt->i915; 1189 1190 gen12_gt_workarounds_init(gt, wal); 1191 1192 /* Wa_1409420604:tgl */ 1193 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1194 wa_write_or(wal, 1195 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1196 CPSSUNIT_CLKGATE_DIS); 1197 1198 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1199 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1200 wa_write_or(wal, 1201 SLICE_UNIT_LEVEL_CLKGATE, 1202 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1203 1204 /* Wa_1408615072:tgl[a0] */ 1205 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) 1206 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1207 VSUNIT_CLKGATE_DIS_TGL); 1208 } 1209 1210 static void 1211 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1212 { 1213 struct drm_i915_private *i915 = gt->i915; 1214 1215 gen12_gt_workarounds_init(gt, wal); 1216 1217 /* Wa_1607087056:dg1 */ 1218 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0)) 1219 wa_write_or(wal, 1220 SLICE_UNIT_LEVEL_CLKGATE, 1221 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1222 1223 /* Wa_1409420604:dg1 */ 1224 if (IS_DG1(i915)) 1225 wa_write_or(wal, 1226 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1227 CPSSUNIT_CLKGATE_DIS); 1228 1229 /* Wa_1408615072:dg1 */ 1230 /* Empirical testing shows this register is unaffected by engine reset. */ 1231 if (IS_DG1(i915)) 1232 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1233 VSUNIT_CLKGATE_DIS_TGL); 1234 } 1235 1236 static void 1237 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1238 { 1239 xehp_init_mcr(gt, wal); 1240 } 1241 1242 static void 1243 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1244 { 1245 struct drm_i915_private *i915 = gt->i915; 1246 1247 if (IS_XEHPSDV(i915)) 1248 xehpsdv_gt_workarounds_init(gt, wal); 1249 else if (IS_DG1(i915)) 1250 dg1_gt_workarounds_init(gt, wal); 1251 else if (IS_TIGERLAKE(i915)) 1252 tgl_gt_workarounds_init(gt, wal); 1253 else if (GRAPHICS_VER(i915) == 12) 1254 gen12_gt_workarounds_init(gt, wal); 1255 else if (GRAPHICS_VER(i915) == 11) 1256 icl_gt_workarounds_init(gt, wal); 1257 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1258 cfl_gt_workarounds_init(gt, wal); 1259 else if (IS_GEMINILAKE(i915)) 1260 glk_gt_workarounds_init(gt, wal); 1261 else if (IS_KABYLAKE(i915)) 1262 kbl_gt_workarounds_init(gt, wal); 1263 else if (IS_BROXTON(i915)) 1264 gen9_gt_workarounds_init(gt, wal); 1265 else if (IS_SKYLAKE(i915)) 1266 skl_gt_workarounds_init(gt, wal); 1267 else if (IS_HASWELL(i915)) 1268 hsw_gt_workarounds_init(gt, wal); 1269 else if (IS_VALLEYVIEW(i915)) 1270 vlv_gt_workarounds_init(gt, wal); 1271 else if (IS_IVYBRIDGE(i915)) 1272 ivb_gt_workarounds_init(gt, wal); 1273 else if (GRAPHICS_VER(i915) == 6) 1274 snb_gt_workarounds_init(gt, wal); 1275 else if (GRAPHICS_VER(i915) == 5) 1276 ilk_gt_workarounds_init(gt, wal); 1277 else if (IS_G4X(i915)) 1278 g4x_gt_workarounds_init(gt, wal); 1279 else if (GRAPHICS_VER(i915) == 4) 1280 gen4_gt_workarounds_init(gt, wal); 1281 else if (GRAPHICS_VER(i915) <= 8) 1282 ; 1283 else 1284 MISSING_CASE(GRAPHICS_VER(i915)); 1285 } 1286 1287 void intel_gt_init_workarounds(struct intel_gt *gt) 1288 { 1289 struct i915_wa_list *wal = >->wa_list; 1290 1291 wa_init_start(wal, "GT", "global"); 1292 gt_init_workarounds(gt, wal); 1293 wa_init_finish(wal); 1294 } 1295 1296 static enum forcewake_domains 1297 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1298 { 1299 enum forcewake_domains fw = 0; 1300 struct i915_wa *wa; 1301 unsigned int i; 1302 1303 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1304 fw |= intel_uncore_forcewake_for_reg(uncore, 1305 wa->reg, 1306 FW_REG_READ | 1307 FW_REG_WRITE); 1308 1309 return fw; 1310 } 1311 1312 static bool 1313 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1314 { 1315 if ((cur ^ wa->set) & wa->read) { 1316 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1317 name, from, i915_mmio_reg_offset(wa->reg), 1318 cur, cur & wa->read, wa->set & wa->read); 1319 1320 return false; 1321 } 1322 1323 return true; 1324 } 1325 1326 static void 1327 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1328 { 1329 struct intel_uncore *uncore = gt->uncore; 1330 enum forcewake_domains fw; 1331 unsigned long flags; 1332 struct i915_wa *wa; 1333 unsigned int i; 1334 1335 if (!wal->count) 1336 return; 1337 1338 fw = wal_get_fw_for_rmw(uncore, wal); 1339 1340 spin_lock_irqsave(&uncore->lock, flags); 1341 intel_uncore_forcewake_get__locked(uncore, fw); 1342 1343 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1344 u32 val, old = 0; 1345 1346 /* open-coded rmw due to steering */ 1347 old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; 1348 val = (old & ~wa->clr) | wa->set; 1349 if (val != old || !wa->clr) 1350 intel_uncore_write_fw(uncore, wa->reg, val); 1351 1352 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1353 wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), 1354 wal->name, "application"); 1355 } 1356 1357 intel_uncore_forcewake_put__locked(uncore, fw); 1358 spin_unlock_irqrestore(&uncore->lock, flags); 1359 } 1360 1361 void intel_gt_apply_workarounds(struct intel_gt *gt) 1362 { 1363 wa_list_apply(gt, >->wa_list); 1364 } 1365 1366 static bool wa_list_verify(struct intel_gt *gt, 1367 const struct i915_wa_list *wal, 1368 const char *from) 1369 { 1370 struct intel_uncore *uncore = gt->uncore; 1371 struct i915_wa *wa; 1372 enum forcewake_domains fw; 1373 unsigned long flags; 1374 unsigned int i; 1375 bool ok = true; 1376 1377 fw = wal_get_fw_for_rmw(uncore, wal); 1378 1379 spin_lock_irqsave(&uncore->lock, flags); 1380 intel_uncore_forcewake_get__locked(uncore, fw); 1381 1382 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1383 ok &= wa_verify(wa, 1384 intel_gt_read_register_fw(gt, wa->reg), 1385 wal->name, from); 1386 1387 intel_uncore_forcewake_put__locked(uncore, fw); 1388 spin_unlock_irqrestore(&uncore->lock, flags); 1389 1390 return ok; 1391 } 1392 1393 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1394 { 1395 return wa_list_verify(gt, >->wa_list, from); 1396 } 1397 1398 __maybe_unused 1399 static bool is_nonpriv_flags_valid(u32 flags) 1400 { 1401 /* Check only valid flag bits are set */ 1402 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1403 return false; 1404 1405 /* NB: Only 3 out of 4 enum values are valid for access field */ 1406 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1407 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1408 return false; 1409 1410 return true; 1411 } 1412 1413 static void 1414 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1415 { 1416 struct i915_wa wa = { 1417 .reg = reg 1418 }; 1419 1420 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1421 return; 1422 1423 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1424 return; 1425 1426 wa.reg.reg |= flags; 1427 _wa_add(wal, &wa); 1428 } 1429 1430 static void 1431 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1432 { 1433 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1434 } 1435 1436 static void gen9_whitelist_build(struct i915_wa_list *w) 1437 { 1438 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1439 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1440 1441 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1442 whitelist_reg(w, GEN8_CS_CHICKEN1); 1443 1444 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1445 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1446 1447 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1448 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1449 } 1450 1451 static void skl_whitelist_build(struct intel_engine_cs *engine) 1452 { 1453 struct i915_wa_list *w = &engine->whitelist; 1454 1455 if (engine->class != RENDER_CLASS) 1456 return; 1457 1458 gen9_whitelist_build(w); 1459 1460 /* WaDisableLSQCROPERFforOCL:skl */ 1461 whitelist_reg(w, GEN8_L3SQCREG4); 1462 } 1463 1464 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1465 { 1466 if (engine->class != RENDER_CLASS) 1467 return; 1468 1469 gen9_whitelist_build(&engine->whitelist); 1470 } 1471 1472 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1473 { 1474 struct i915_wa_list *w = &engine->whitelist; 1475 1476 if (engine->class != RENDER_CLASS) 1477 return; 1478 1479 gen9_whitelist_build(w); 1480 1481 /* WaDisableLSQCROPERFforOCL:kbl */ 1482 whitelist_reg(w, GEN8_L3SQCREG4); 1483 } 1484 1485 static void glk_whitelist_build(struct intel_engine_cs *engine) 1486 { 1487 struct i915_wa_list *w = &engine->whitelist; 1488 1489 if (engine->class != RENDER_CLASS) 1490 return; 1491 1492 gen9_whitelist_build(w); 1493 1494 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1495 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1496 } 1497 1498 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1499 { 1500 struct i915_wa_list *w = &engine->whitelist; 1501 1502 if (engine->class != RENDER_CLASS) 1503 return; 1504 1505 gen9_whitelist_build(w); 1506 1507 /* 1508 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1509 * 1510 * This covers 4 register which are next to one another : 1511 * - PS_INVOCATION_COUNT 1512 * - PS_INVOCATION_COUNT_UDW 1513 * - PS_DEPTH_COUNT 1514 * - PS_DEPTH_COUNT_UDW 1515 */ 1516 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1517 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1518 RING_FORCE_TO_NONPRIV_RANGE_4); 1519 } 1520 1521 static void cml_whitelist_build(struct intel_engine_cs *engine) 1522 { 1523 struct i915_wa_list *w = &engine->whitelist; 1524 1525 if (engine->class != RENDER_CLASS) 1526 whitelist_reg_ext(w, 1527 RING_CTX_TIMESTAMP(engine->mmio_base), 1528 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1529 1530 cfl_whitelist_build(engine); 1531 } 1532 1533 static void icl_whitelist_build(struct intel_engine_cs *engine) 1534 { 1535 struct i915_wa_list *w = &engine->whitelist; 1536 1537 switch (engine->class) { 1538 case RENDER_CLASS: 1539 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1540 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1541 1542 /* WaAllowUMDToModifySamplerMode:icl */ 1543 whitelist_reg(w, GEN10_SAMPLER_MODE); 1544 1545 /* WaEnableStateCacheRedirectToCS:icl */ 1546 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1547 1548 /* 1549 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1550 * 1551 * This covers 4 register which are next to one another : 1552 * - PS_INVOCATION_COUNT 1553 * - PS_INVOCATION_COUNT_UDW 1554 * - PS_DEPTH_COUNT 1555 * - PS_DEPTH_COUNT_UDW 1556 */ 1557 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1558 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1559 RING_FORCE_TO_NONPRIV_RANGE_4); 1560 break; 1561 1562 case VIDEO_DECODE_CLASS: 1563 /* hucStatusRegOffset */ 1564 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1565 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1566 /* hucUKernelHdrInfoRegOffset */ 1567 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1568 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1569 /* hucStatus2RegOffset */ 1570 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1571 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1572 whitelist_reg_ext(w, 1573 RING_CTX_TIMESTAMP(engine->mmio_base), 1574 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1575 break; 1576 1577 default: 1578 whitelist_reg_ext(w, 1579 RING_CTX_TIMESTAMP(engine->mmio_base), 1580 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1581 break; 1582 } 1583 } 1584 1585 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1586 { 1587 struct i915_wa_list *w = &engine->whitelist; 1588 1589 switch (engine->class) { 1590 case RENDER_CLASS: 1591 /* 1592 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1593 * Wa_1408556865:tgl 1594 * 1595 * This covers 4 registers which are next to one another : 1596 * - PS_INVOCATION_COUNT 1597 * - PS_INVOCATION_COUNT_UDW 1598 * - PS_DEPTH_COUNT 1599 * - PS_DEPTH_COUNT_UDW 1600 */ 1601 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1602 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1603 RING_FORCE_TO_NONPRIV_RANGE_4); 1604 1605 /* Wa_1808121037:tgl */ 1606 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1607 1608 /* Wa_1806527549:tgl */ 1609 whitelist_reg(w, HIZ_CHICKEN); 1610 break; 1611 default: 1612 whitelist_reg_ext(w, 1613 RING_CTX_TIMESTAMP(engine->mmio_base), 1614 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1615 break; 1616 } 1617 } 1618 1619 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1620 { 1621 struct i915_wa_list *w = &engine->whitelist; 1622 1623 tgl_whitelist_build(engine); 1624 1625 /* GEN:BUG:1409280441:dg1 */ 1626 if (IS_DG1_GT_STEP(engine->i915, STEP_A0, STEP_B0) && 1627 (engine->class == RENDER_CLASS || 1628 engine->class == COPY_ENGINE_CLASS)) 1629 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1630 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1631 } 1632 1633 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1634 { 1635 struct drm_i915_private *i915 = engine->i915; 1636 struct i915_wa_list *w = &engine->whitelist; 1637 1638 wa_init_start(w, "whitelist", engine->name); 1639 1640 if (IS_DG1(i915)) 1641 dg1_whitelist_build(engine); 1642 else if (GRAPHICS_VER(i915) == 12) 1643 tgl_whitelist_build(engine); 1644 else if (GRAPHICS_VER(i915) == 11) 1645 icl_whitelist_build(engine); 1646 else if (IS_COMETLAKE(i915)) 1647 cml_whitelist_build(engine); 1648 else if (IS_COFFEELAKE(i915)) 1649 cfl_whitelist_build(engine); 1650 else if (IS_GEMINILAKE(i915)) 1651 glk_whitelist_build(engine); 1652 else if (IS_KABYLAKE(i915)) 1653 kbl_whitelist_build(engine); 1654 else if (IS_BROXTON(i915)) 1655 bxt_whitelist_build(engine); 1656 else if (IS_SKYLAKE(i915)) 1657 skl_whitelist_build(engine); 1658 else if (GRAPHICS_VER(i915) <= 8) 1659 ; 1660 else 1661 MISSING_CASE(GRAPHICS_VER(i915)); 1662 1663 wa_init_finish(w); 1664 } 1665 1666 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1667 { 1668 const struct i915_wa_list *wal = &engine->whitelist; 1669 struct intel_uncore *uncore = engine->uncore; 1670 const u32 base = engine->mmio_base; 1671 struct i915_wa *wa; 1672 unsigned int i; 1673 1674 if (!wal->count) 1675 return; 1676 1677 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1678 intel_uncore_write(uncore, 1679 RING_FORCE_TO_NONPRIV(base, i), 1680 i915_mmio_reg_offset(wa->reg)); 1681 1682 /* And clear the rest just in case of garbage */ 1683 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1684 intel_uncore_write(uncore, 1685 RING_FORCE_TO_NONPRIV(base, i), 1686 i915_mmio_reg_offset(RING_NOPID(base))); 1687 } 1688 1689 /* 1690 * engine_fake_wa_init(), a place holder to program the registers 1691 * which are not part of an official workaround defined by the 1692 * hardware team. 1693 * Adding programming of those register inside workaround will 1694 * allow utilizing wa framework to proper application and verification. 1695 */ 1696 static void 1697 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1698 { 1699 u8 mocs; 1700 1701 /* 1702 * RING_CMD_CCTL are need to be programed to un-cached 1703 * for memory writes and reads outputted by Command 1704 * Streamers on Gen12 onward platforms. 1705 */ 1706 if (GRAPHICS_VER(engine->i915) >= 12) { 1707 mocs = engine->gt->mocs.uc_index; 1708 wa_masked_field_set(wal, 1709 RING_CMD_CCTL(engine->mmio_base), 1710 CMD_CCTL_MOCS_MASK, 1711 CMD_CCTL_MOCS_OVERRIDE(mocs, mocs)); 1712 } 1713 } 1714 static void 1715 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1716 { 1717 struct drm_i915_private *i915 = engine->i915; 1718 1719 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1720 IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) { 1721 /* 1722 * Wa_1607138336:tgl[a0],dg1[a0] 1723 * Wa_1607063988:tgl[a0],dg1[a0] 1724 */ 1725 wa_write_or(wal, 1726 GEN9_CTX_PREEMPT_REG, 1727 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1728 } 1729 1730 if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_B0)) { 1731 /* 1732 * Wa_1606679103:tgl 1733 * (see also Wa_1606682166:icl) 1734 */ 1735 wa_write_or(wal, 1736 GEN7_SARCHKMD, 1737 GEN7_DISABLE_SAMPLER_PREFETCH); 1738 } 1739 1740 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 1741 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1742 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 1743 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1744 1745 /* 1746 * Wa_1407928979:tgl A* 1747 * Wa_18011464164:tgl[B0+],dg1[B0+] 1748 * Wa_22010931296:tgl[B0+],dg1[B0+] 1749 * Wa_14010919138:rkl,dg1,adl-s,adl-p 1750 */ 1751 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1752 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1753 1754 /* 1755 * Wa_1606700617:tgl,dg1,adl-p 1756 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 1757 * Wa_14010826681:tgl,dg1,rkl,adl-p 1758 */ 1759 wa_masked_en(wal, 1760 GEN9_CS_DEBUG_MODE1, 1761 FF_DOP_CLOCK_GATE_DISABLE); 1762 } 1763 1764 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 1765 IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1766 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1767 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 1768 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1769 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1770 1771 /* 1772 * Wa_1409085225:tgl 1773 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 1774 */ 1775 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1776 } 1777 1778 1779 if (IS_DG1_GT_STEP(i915, STEP_A0, STEP_B0) || 1780 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1781 /* 1782 * Wa_1607030317:tgl 1783 * Wa_1607186500:tgl 1784 * Wa_1607297627:tgl,rkl,dg1[a0] 1785 * 1786 * On TGL and RKL there are multiple entries for this WA in the 1787 * BSpec; some indicate this is an A0-only WA, others indicate 1788 * it applies to all steppings so we trust the "all steppings." 1789 * For DG1 this only applies to A0. 1790 */ 1791 wa_masked_en(wal, 1792 GEN6_RC_SLEEP_PSMI_CONTROL, 1793 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1794 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1795 } 1796 1797 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 1798 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 1799 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 1800 wa_masked_en(wal, 1801 GEN10_SAMPLER_MODE, 1802 ENABLE_SMALLPL); 1803 } 1804 1805 if (GRAPHICS_VER(i915) == 11) { 1806 /* This is not an Wa. Enable for better image quality */ 1807 wa_masked_en(wal, 1808 _3D_CHICKEN3, 1809 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1810 1811 /* 1812 * Wa_1405543622:icl 1813 * Formerly known as WaGAPZPriorityScheme 1814 */ 1815 wa_write_or(wal, 1816 GEN8_GARBCNTL, 1817 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1818 1819 /* 1820 * Wa_1604223664:icl 1821 * Formerly known as WaL3BankAddressHashing 1822 */ 1823 wa_write_clr_set(wal, 1824 GEN8_GARBCNTL, 1825 GEN11_HASH_CTRL_EXCL_MASK, 1826 GEN11_HASH_CTRL_EXCL_BIT0); 1827 wa_write_clr_set(wal, 1828 GEN11_GLBLINVL, 1829 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1830 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1831 1832 /* 1833 * Wa_1405733216:icl 1834 * Formerly known as WaDisableCleanEvicts 1835 */ 1836 wa_write_or(wal, 1837 GEN8_L3SQCREG4, 1838 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1839 1840 /* Wa_1606682166:icl */ 1841 wa_write_or(wal, 1842 GEN7_SARCHKMD, 1843 GEN7_DISABLE_SAMPLER_PREFETCH); 1844 1845 /* Wa_1409178092:icl */ 1846 wa_write_clr_set(wal, 1847 GEN11_SCRATCH2, 1848 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1849 0); 1850 1851 /* WaEnable32PlaneMode:icl */ 1852 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1853 GEN11_ENABLE_32_PLANE_MODE); 1854 1855 /* 1856 * Wa_1408615072:icl,ehl (vsunit) 1857 * Wa_1407596294:icl,ehl (hsunit) 1858 */ 1859 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1860 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1861 1862 /* Wa_1407352427:icl,ehl */ 1863 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1864 PSDUNIT_CLKGATE_DIS); 1865 1866 /* Wa_1406680159:icl,ehl */ 1867 wa_write_or(wal, 1868 SUBSLICE_UNIT_LEVEL_CLKGATE, 1869 GWUNIT_CLKGATE_DIS); 1870 1871 /* 1872 * Wa_1408767742:icl[a2..forever],ehl[all] 1873 * Wa_1605460711:icl[a0..c0] 1874 */ 1875 wa_write_or(wal, 1876 GEN7_FF_THREAD_MODE, 1877 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1878 1879 /* Wa_22010271021 */ 1880 wa_masked_en(wal, 1881 GEN9_CS_DEBUG_MODE1, 1882 FF_DOP_CLOCK_GATE_DISABLE); 1883 } 1884 1885 if (IS_GRAPHICS_VER(i915, 9, 12)) { 1886 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1887 wa_masked_en(wal, 1888 GEN7_FF_SLICE_CS_CHICKEN1, 1889 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1890 } 1891 1892 if (IS_SKYLAKE(i915) || 1893 IS_KABYLAKE(i915) || 1894 IS_COFFEELAKE(i915) || 1895 IS_COMETLAKE(i915)) { 1896 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1897 wa_write_or(wal, 1898 GEN8_GARBCNTL, 1899 GEN9_GAPS_TSV_CREDIT_DISABLE); 1900 } 1901 1902 if (IS_BROXTON(i915)) { 1903 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1904 wa_masked_en(wal, 1905 FF_SLICE_CS_CHICKEN2, 1906 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1907 } 1908 1909 if (GRAPHICS_VER(i915) == 9) { 1910 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1911 wa_masked_en(wal, 1912 GEN9_CSFE_CHICKEN1_RCS, 1913 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1914 1915 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1916 wa_write_or(wal, 1917 BDW_SCRATCH1, 1918 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1919 1920 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1921 if (IS_GEN9_LP(i915)) 1922 wa_write_clr_set(wal, 1923 GEN8_L3SQCREG1, 1924 L3_PRIO_CREDITS_MASK, 1925 L3_GENERAL_PRIO_CREDITS(62) | 1926 L3_HIGH_PRIO_CREDITS(2)); 1927 1928 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1929 wa_write_or(wal, 1930 GEN8_L3SQCREG4, 1931 GEN8_LQSC_FLUSH_COHERENT_LINES); 1932 1933 /* Disable atomics in L3 to prevent unrecoverable hangs */ 1934 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 1935 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 1936 wa_write_clr_set(wal, GEN8_L3SQCREG4, 1937 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 1938 wa_write_clr_set(wal, GEN9_SCRATCH1, 1939 EVICTION_PERF_FIX_ENABLE, 0); 1940 } 1941 1942 if (IS_HASWELL(i915)) { 1943 /* WaSampleCChickenBitEnable:hsw */ 1944 wa_masked_en(wal, 1945 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 1946 1947 wa_masked_dis(wal, 1948 CACHE_MODE_0_GEN7, 1949 /* enable HiZ Raw Stall Optimization */ 1950 HIZ_RAW_STALL_OPT_DISABLE); 1951 } 1952 1953 if (IS_VALLEYVIEW(i915)) { 1954 /* WaDisableEarlyCull:vlv */ 1955 wa_masked_en(wal, 1956 _3D_CHICKEN3, 1957 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1958 1959 /* 1960 * WaVSThreadDispatchOverride:ivb,vlv 1961 * 1962 * This actually overrides the dispatch 1963 * mode for all thread types. 1964 */ 1965 wa_write_clr_set(wal, 1966 GEN7_FF_THREAD_MODE, 1967 GEN7_FF_SCHED_MASK, 1968 GEN7_FF_TS_SCHED_HW | 1969 GEN7_FF_VS_SCHED_HW | 1970 GEN7_FF_DS_SCHED_HW); 1971 1972 /* WaPsdDispatchEnable:vlv */ 1973 /* WaDisablePSDDualDispatchEnable:vlv */ 1974 wa_masked_en(wal, 1975 GEN7_HALF_SLICE_CHICKEN1, 1976 GEN7_MAX_PS_THREAD_DEP | 1977 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 1978 } 1979 1980 if (IS_IVYBRIDGE(i915)) { 1981 /* WaDisableEarlyCull:ivb */ 1982 wa_masked_en(wal, 1983 _3D_CHICKEN3, 1984 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 1985 1986 if (0) { /* causes HiZ corruption on ivb:gt1 */ 1987 /* enable HiZ Raw Stall Optimization */ 1988 wa_masked_dis(wal, 1989 CACHE_MODE_0_GEN7, 1990 HIZ_RAW_STALL_OPT_DISABLE); 1991 } 1992 1993 /* 1994 * WaVSThreadDispatchOverride:ivb,vlv 1995 * 1996 * This actually overrides the dispatch 1997 * mode for all thread types. 1998 */ 1999 wa_write_clr_set(wal, 2000 GEN7_FF_THREAD_MODE, 2001 GEN7_FF_SCHED_MASK, 2002 GEN7_FF_TS_SCHED_HW | 2003 GEN7_FF_VS_SCHED_HW | 2004 GEN7_FF_DS_SCHED_HW); 2005 2006 /* WaDisablePSDDualDispatchEnable:ivb */ 2007 if (IS_IVB_GT1(i915)) 2008 wa_masked_en(wal, 2009 GEN7_HALF_SLICE_CHICKEN1, 2010 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2011 } 2012 2013 if (GRAPHICS_VER(i915) == 7) { 2014 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2015 wa_masked_en(wal, 2016 GFX_MODE_GEN7, 2017 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2018 2019 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2020 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2021 2022 /* 2023 * BSpec says this must be set, even though 2024 * WaDisable4x2SubspanOptimization:ivb,hsw 2025 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2026 */ 2027 wa_masked_en(wal, 2028 CACHE_MODE_1, 2029 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2030 2031 /* 2032 * BSpec recommends 8x4 when MSAA is used, 2033 * however in practice 16x4 seems fastest. 2034 * 2035 * Note that PS/WM thread counts depend on the WIZ hashing 2036 * disable bit, which we don't touch here, but it's good 2037 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2038 */ 2039 wa_masked_field_set(wal, 2040 GEN7_GT_MODE, 2041 GEN6_WIZ_HASHING_MASK, 2042 GEN6_WIZ_HASHING_16x4); 2043 } 2044 2045 if (IS_GRAPHICS_VER(i915, 6, 7)) 2046 /* 2047 * We need to disable the AsyncFlip performance optimisations in 2048 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2049 * already be programmed to '1' on all products. 2050 * 2051 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2052 */ 2053 wa_masked_en(wal, 2054 MI_MODE, 2055 ASYNC_FLIP_PERF_DISABLE); 2056 2057 if (GRAPHICS_VER(i915) == 6) { 2058 /* 2059 * Required for the hardware to program scanline values for 2060 * waiting 2061 * WaEnableFlushTlbInvalidationMode:snb 2062 */ 2063 wa_masked_en(wal, 2064 GFX_MODE, 2065 GFX_TLB_INVALIDATE_EXPLICIT); 2066 2067 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2068 wa_masked_en(wal, 2069 _3D_CHICKEN, 2070 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2071 2072 wa_masked_en(wal, 2073 _3D_CHICKEN3, 2074 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2075 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2076 /* 2077 * Bspec says: 2078 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2079 * to normal and 3DSTATE_SF number of SF output attributes 2080 * is more than 16." 2081 */ 2082 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2083 2084 /* 2085 * BSpec recommends 8x4 when MSAA is used, 2086 * however in practice 16x4 seems fastest. 2087 * 2088 * Note that PS/WM thread counts depend on the WIZ hashing 2089 * disable bit, which we don't touch here, but it's good 2090 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2091 */ 2092 wa_masked_field_set(wal, 2093 GEN6_GT_MODE, 2094 GEN6_WIZ_HASHING_MASK, 2095 GEN6_WIZ_HASHING_16x4); 2096 2097 /* WaDisable_RenderCache_OperationalFlush:snb */ 2098 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2099 2100 /* 2101 * From the Sandybridge PRM, volume 1 part 3, page 24: 2102 * "If this bit is set, STCunit will have LRA as replacement 2103 * policy. [...] This bit must be reset. LRA replacement 2104 * policy is not supported." 2105 */ 2106 wa_masked_dis(wal, 2107 CACHE_MODE_0, 2108 CM0_STC_EVICT_DISABLE_LRA_SNB); 2109 } 2110 2111 if (IS_GRAPHICS_VER(i915, 4, 6)) 2112 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2113 wa_add(wal, MI_MODE, 2114 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2115 /* XXX bit doesn't stick on Broadwater */ 2116 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2117 2118 if (GRAPHICS_VER(i915) == 4) 2119 /* 2120 * Disable CONSTANT_BUFFER before it is loaded from the context 2121 * image. For as it is loaded, it is executed and the stored 2122 * address may no longer be valid, leading to a GPU hang. 2123 * 2124 * This imposes the requirement that userspace reload their 2125 * CONSTANT_BUFFER on every batch, fortunately a requirement 2126 * they are already accustomed to from before contexts were 2127 * enabled. 2128 */ 2129 wa_add(wal, ECOSKPD, 2130 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2131 0 /* XXX bit doesn't stick on Broadwater */, 2132 true); 2133 } 2134 2135 static void 2136 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2137 { 2138 struct drm_i915_private *i915 = engine->i915; 2139 2140 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2141 if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_F0)) { 2142 wa_write(wal, 2143 RING_SEMA_WAIT_POLL(engine->mmio_base), 2144 1); 2145 } 2146 } 2147 2148 static void 2149 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2150 { 2151 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2152 return; 2153 2154 engine_fake_wa_init(engine, wal); 2155 2156 if (engine->class == RENDER_CLASS) 2157 rcs_engine_wa_init(engine, wal); 2158 else 2159 xcs_engine_wa_init(engine, wal); 2160 } 2161 2162 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2163 { 2164 struct i915_wa_list *wal = &engine->wa_list; 2165 2166 if (GRAPHICS_VER(engine->i915) < 4) 2167 return; 2168 2169 wa_init_start(wal, "engine", engine->name); 2170 engine_init_workarounds(engine, wal); 2171 wa_init_finish(wal); 2172 } 2173 2174 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2175 { 2176 wa_list_apply(engine->gt, &engine->wa_list); 2177 } 2178 2179 static const struct i915_range mcr_ranges_gen8[] = { 2180 { .start = 0x5500, .end = 0x55ff }, 2181 { .start = 0x7000, .end = 0x7fff }, 2182 { .start = 0x9400, .end = 0x97ff }, 2183 { .start = 0xb000, .end = 0xb3ff }, 2184 { .start = 0xe000, .end = 0xe7ff }, 2185 {}, 2186 }; 2187 2188 static const struct i915_range mcr_ranges_gen12[] = { 2189 { .start = 0x8150, .end = 0x815f }, 2190 { .start = 0x9520, .end = 0x955f }, 2191 { .start = 0xb100, .end = 0xb3ff }, 2192 { .start = 0xde80, .end = 0xe8ff }, 2193 { .start = 0x24a00, .end = 0x24a7f }, 2194 {}, 2195 }; 2196 2197 static const struct i915_range mcr_ranges_xehp[] = { 2198 { .start = 0x4000, .end = 0x4aff }, 2199 { .start = 0x5200, .end = 0x52ff }, 2200 { .start = 0x5400, .end = 0x7fff }, 2201 { .start = 0x8140, .end = 0x815f }, 2202 { .start = 0x8c80, .end = 0x8dff }, 2203 { .start = 0x94d0, .end = 0x955f }, 2204 { .start = 0x9680, .end = 0x96ff }, 2205 { .start = 0xb000, .end = 0xb3ff }, 2206 { .start = 0xc800, .end = 0xcfff }, 2207 { .start = 0xd800, .end = 0xd8ff }, 2208 { .start = 0xdc00, .end = 0xffff }, 2209 { .start = 0x17000, .end = 0x17fff }, 2210 { .start = 0x24a00, .end = 0x24a7f }, 2211 {}, 2212 }; 2213 2214 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2215 { 2216 const struct i915_range *mcr_ranges; 2217 int i; 2218 2219 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2220 mcr_ranges = mcr_ranges_xehp; 2221 else if (GRAPHICS_VER(i915) >= 12) 2222 mcr_ranges = mcr_ranges_gen12; 2223 else if (GRAPHICS_VER(i915) >= 8) 2224 mcr_ranges = mcr_ranges_gen8; 2225 else 2226 return false; 2227 2228 /* 2229 * Registers in these ranges are affected by the MCR selector 2230 * which only controls CPU initiated MMIO. Routing does not 2231 * work for CS access so we cannot verify them on this path. 2232 */ 2233 for (i = 0; mcr_ranges[i].start; i++) 2234 if (offset >= mcr_ranges[i].start && 2235 offset <= mcr_ranges[i].end) 2236 return true; 2237 2238 return false; 2239 } 2240 2241 static int 2242 wa_list_srm(struct i915_request *rq, 2243 const struct i915_wa_list *wal, 2244 struct i915_vma *vma) 2245 { 2246 struct drm_i915_private *i915 = rq->engine->i915; 2247 unsigned int i, count = 0; 2248 const struct i915_wa *wa; 2249 u32 srm, *cs; 2250 2251 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2252 if (GRAPHICS_VER(i915) >= 8) 2253 srm++; 2254 2255 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2256 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2257 count++; 2258 } 2259 2260 cs = intel_ring_begin(rq, 4 * count); 2261 if (IS_ERR(cs)) 2262 return PTR_ERR(cs); 2263 2264 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2265 u32 offset = i915_mmio_reg_offset(wa->reg); 2266 2267 if (mcr_range(i915, offset)) 2268 continue; 2269 2270 *cs++ = srm; 2271 *cs++ = offset; 2272 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2273 *cs++ = 0; 2274 } 2275 intel_ring_advance(rq, cs); 2276 2277 return 0; 2278 } 2279 2280 static int engine_wa_list_verify(struct intel_context *ce, 2281 const struct i915_wa_list * const wal, 2282 const char *from) 2283 { 2284 const struct i915_wa *wa; 2285 struct i915_request *rq; 2286 struct i915_vma *vma; 2287 struct i915_gem_ww_ctx ww; 2288 unsigned int i; 2289 u32 *results; 2290 int err; 2291 2292 if (!wal->count) 2293 return 0; 2294 2295 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2296 wal->count * sizeof(u32)); 2297 if (IS_ERR(vma)) 2298 return PTR_ERR(vma); 2299 2300 intel_engine_pm_get(ce->engine); 2301 i915_gem_ww_ctx_init(&ww, false); 2302 retry: 2303 err = i915_gem_object_lock(vma->obj, &ww); 2304 if (err == 0) 2305 err = intel_context_pin_ww(ce, &ww); 2306 if (err) 2307 goto err_pm; 2308 2309 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2310 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2311 if (err) 2312 goto err_unpin; 2313 2314 rq = i915_request_create(ce); 2315 if (IS_ERR(rq)) { 2316 err = PTR_ERR(rq); 2317 goto err_vma; 2318 } 2319 2320 err = i915_request_await_object(rq, vma->obj, true); 2321 if (err == 0) 2322 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2323 if (err == 0) 2324 err = wa_list_srm(rq, wal, vma); 2325 2326 i915_request_get(rq); 2327 if (err) 2328 i915_request_set_error_once(rq, err); 2329 i915_request_add(rq); 2330 2331 if (err) 2332 goto err_rq; 2333 2334 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2335 err = -ETIME; 2336 goto err_rq; 2337 } 2338 2339 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2340 if (IS_ERR(results)) { 2341 err = PTR_ERR(results); 2342 goto err_rq; 2343 } 2344 2345 err = 0; 2346 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2347 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2348 continue; 2349 2350 if (!wa_verify(wa, results[i], wal->name, from)) 2351 err = -ENXIO; 2352 } 2353 2354 i915_gem_object_unpin_map(vma->obj); 2355 2356 err_rq: 2357 i915_request_put(rq); 2358 err_vma: 2359 i915_vma_unpin(vma); 2360 err_unpin: 2361 intel_context_unpin(ce); 2362 err_pm: 2363 if (err == -EDEADLK) { 2364 err = i915_gem_ww_ctx_backoff(&ww); 2365 if (!err) 2366 goto retry; 2367 } 2368 i915_gem_ww_ctx_fini(&ww); 2369 intel_engine_pm_put(ce->engine); 2370 i915_vma_put(vma); 2371 return err; 2372 } 2373 2374 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2375 const char *from) 2376 { 2377 return engine_wa_list_verify(engine->kernel_context, 2378 &engine->wa_list, 2379 from); 2380 } 2381 2382 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2383 #include "selftest_workarounds.c" 2384 #endif 2385