1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_engine_regs.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_gt_regs.h" 13 #include "intel_ring.h" 14 #include "intel_workarounds.h" 15 16 /** 17 * DOC: Hardware workarounds 18 * 19 * This file is intended as a central place to implement most [1]_ of the 20 * required workarounds for hardware to work as originally intended. They fall 21 * in five basic categories depending on how/when they are applied: 22 * 23 * - Workarounds that touch registers that are saved/restored to/from the HW 24 * context image. The list is emitted (via Load Register Immediate commands) 25 * everytime a new context is created. 26 * - GT workarounds. The list of these WAs is applied whenever these registers 27 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 28 * - Display workarounds. The list is applied during display clock-gating 29 * initialization. 30 * - Workarounds that whitelist a privileged register, so that UMDs can manage 31 * them directly. This is just a special case of a MMMIO workaround (as we 32 * write the list of these to/be-whitelisted registers to some special HW 33 * registers). 34 * - Workaround batchbuffers, that get executed automatically by the hardware 35 * on every HW context restore. 36 * 37 * .. [1] Please notice that there are other WAs that, due to their nature, 38 * cannot be applied from a central place. Those are peppered around the rest 39 * of the code, as needed. 40 * 41 * .. [2] Technically, some registers are powercontext saved & restored, so they 42 * survive a suspend/resume. In practice, writing them again is not too 43 * costly and simplifies things. We can revisit this in the future. 44 * 45 * Layout 46 * ~~~~~~ 47 * 48 * Keep things in this file ordered by WA type, as per the above (context, GT, 49 * display, register whitelist, batchbuffer). Then, inside each type, keep the 50 * following order: 51 * 52 * - Infrastructure functions and macros 53 * - WAs per platform in standard gen/chrono order 54 * - Public functions to init or apply the given workaround type. 55 */ 56 57 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 58 { 59 wal->name = name; 60 wal->engine_name = engine_name; 61 } 62 63 #define WA_LIST_CHUNK (1 << 4) 64 65 static void wa_init_finish(struct i915_wa_list *wal) 66 { 67 /* Trim unused entries. */ 68 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 69 struct i915_wa *list = kmemdup(wal->list, 70 wal->count * sizeof(*list), 71 GFP_KERNEL); 72 73 if (list) { 74 kfree(wal->list); 75 wal->list = list; 76 } 77 } 78 79 if (!wal->count) 80 return; 81 82 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 83 wal->wa_count, wal->name, wal->engine_name); 84 } 85 86 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 87 { 88 unsigned int addr = i915_mmio_reg_offset(wa->reg); 89 unsigned int start = 0, end = wal->count; 90 const unsigned int grow = WA_LIST_CHUNK; 91 struct i915_wa *wa_; 92 93 GEM_BUG_ON(!is_power_of_2(grow)); 94 95 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 96 struct i915_wa *list; 97 98 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 99 GFP_KERNEL); 100 if (!list) { 101 DRM_ERROR("No space for workaround init!\n"); 102 return; 103 } 104 105 if (wal->list) { 106 memcpy(list, wal->list, sizeof(*wa) * wal->count); 107 kfree(wal->list); 108 } 109 110 wal->list = list; 111 } 112 113 while (start < end) { 114 unsigned int mid = start + (end - start) / 2; 115 116 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 117 start = mid + 1; 118 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 119 end = mid; 120 } else { 121 wa_ = &wal->list[mid]; 122 123 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 124 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 125 i915_mmio_reg_offset(wa_->reg), 126 wa_->clr, wa_->set); 127 128 wa_->set &= ~wa->clr; 129 } 130 131 wal->wa_count++; 132 wa_->set |= wa->set; 133 wa_->clr |= wa->clr; 134 wa_->read |= wa->read; 135 return; 136 } 137 } 138 139 wal->wa_count++; 140 wa_ = &wal->list[wal->count++]; 141 *wa_ = *wa; 142 143 while (wa_-- > wal->list) { 144 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 145 i915_mmio_reg_offset(wa_[1].reg)); 146 if (i915_mmio_reg_offset(wa_[1].reg) > 147 i915_mmio_reg_offset(wa_[0].reg)) 148 break; 149 150 swap(wa_[1], wa_[0]); 151 } 152 } 153 154 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 155 u32 clear, u32 set, u32 read_mask, bool masked_reg) 156 { 157 struct i915_wa wa = { 158 .reg = reg, 159 .clr = clear, 160 .set = set, 161 .read = read_mask, 162 .masked_reg = masked_reg, 163 }; 164 165 _wa_add(wal, &wa); 166 } 167 168 static void 169 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 170 { 171 wa_add(wal, reg, clear, set, clear, false); 172 } 173 174 static void 175 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 176 { 177 wa_write_clr_set(wal, reg, ~0, set); 178 } 179 180 static void 181 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 182 { 183 wa_write_clr_set(wal, reg, set, set); 184 } 185 186 static void 187 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 188 { 189 wa_write_clr_set(wal, reg, clr, 0); 190 } 191 192 /* 193 * WA operations on "masked register". A masked register has the upper 16 bits 194 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 195 * portion of the register without a rmw: you simply write in the upper 16 bits 196 * the mask of bits you are going to modify. 197 * 198 * The wa_masked_* family of functions already does the necessary operations to 199 * calculate the mask based on the parameters passed, so user only has to 200 * provide the lower 16 bits of that register. 201 */ 202 203 static void 204 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 205 { 206 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 207 } 208 209 static void 210 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 211 { 212 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 213 } 214 215 static void 216 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 217 u32 mask, u32 val) 218 { 219 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 220 } 221 222 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 223 struct i915_wa_list *wal) 224 { 225 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 226 } 227 228 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 229 struct i915_wa_list *wal) 230 { 231 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 232 } 233 234 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 235 struct i915_wa_list *wal) 236 { 237 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 238 239 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 240 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 241 242 /* WaDisablePartialInstShootdown:bdw,chv */ 243 wa_masked_en(wal, GEN8_ROW_CHICKEN, 244 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 245 246 /* Use Force Non-Coherent whenever executing a 3D context. This is a 247 * workaround for a possible hang in the unlikely event a TLB 248 * invalidation occurs during a PSD flush. 249 */ 250 /* WaForceEnableNonCoherent:bdw,chv */ 251 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 252 wa_masked_en(wal, HDC_CHICKEN0, 253 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 254 HDC_FORCE_NON_COHERENT); 255 256 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 257 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 258 * polygons in the same 8x4 pixel/sample area to be processed without 259 * stalling waiting for the earlier ones to write to Hierarchical Z 260 * buffer." 261 * 262 * This optimization is off by default for BDW and CHV; turn it on. 263 */ 264 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 265 266 /* Wa4x4STCOptimizationDisable:bdw,chv */ 267 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 268 269 /* 270 * BSpec recommends 8x4 when MSAA is used, 271 * however in practice 16x4 seems fastest. 272 * 273 * Note that PS/WM thread counts depend on the WIZ hashing 274 * disable bit, which we don't touch here, but it's good 275 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 276 */ 277 wa_masked_field_set(wal, GEN7_GT_MODE, 278 GEN6_WIZ_HASHING_MASK, 279 GEN6_WIZ_HASHING_16x4); 280 } 281 282 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 283 struct i915_wa_list *wal) 284 { 285 struct drm_i915_private *i915 = engine->i915; 286 287 gen8_ctx_workarounds_init(engine, wal); 288 289 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 290 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 291 292 /* WaDisableDopClockGating:bdw 293 * 294 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 295 * to disable EUTC clock gating. 296 */ 297 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 298 DOP_CLOCK_GATING_DISABLE); 299 300 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 301 GEN8_SAMPLER_POWER_BYPASS_DIS); 302 303 wa_masked_en(wal, HDC_CHICKEN0, 304 /* WaForceContextSaveRestoreNonCoherent:bdw */ 305 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 306 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 307 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 308 } 309 310 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 311 struct i915_wa_list *wal) 312 { 313 gen8_ctx_workarounds_init(engine, wal); 314 315 /* WaDisableThreadStallDopClockGating:chv */ 316 wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 317 318 /* Improve HiZ throughput on CHV. */ 319 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 320 } 321 322 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 323 struct i915_wa_list *wal) 324 { 325 struct drm_i915_private *i915 = engine->i915; 326 327 if (HAS_LLC(i915)) { 328 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 329 * 330 * Must match Display Engine. See 331 * WaCompressedResourceDisplayNewHashMode. 332 */ 333 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 334 GEN9_PBE_COMPRESSED_HASH_SELECTION); 335 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 336 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 337 } 338 339 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 340 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 341 wa_masked_en(wal, GEN8_ROW_CHICKEN, 342 FLOW_CONTROL_ENABLE | 343 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 344 345 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 346 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 347 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 348 GEN9_ENABLE_YV12_BUGFIX | 349 GEN9_ENABLE_GPGPU_PREEMPTION); 350 351 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 352 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 353 wa_masked_en(wal, CACHE_MODE_1, 354 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 355 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 356 357 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 358 wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 359 GEN9_CCS_TLB_PREFETCH_ENABLE); 360 361 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 362 wa_masked_en(wal, HDC_CHICKEN0, 363 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 364 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 365 366 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 367 * both tied to WaForceContextSaveRestoreNonCoherent 368 * in some hsds for skl. We keep the tie for all gen9. The 369 * documentation is a bit hazy and so we want to get common behaviour, 370 * even though there is no clear evidence we would need both on kbl/bxt. 371 * This area has been source of system hangs so we play it safe 372 * and mimic the skl regardless of what bspec says. 373 * 374 * Use Force Non-Coherent whenever executing a 3D context. This 375 * is a workaround for a possible hang in the unlikely event 376 * a TLB invalidation occurs during a PSD flush. 377 */ 378 379 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 380 wa_masked_en(wal, HDC_CHICKEN0, 381 HDC_FORCE_NON_COHERENT); 382 383 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 384 if (IS_SKYLAKE(i915) || 385 IS_KABYLAKE(i915) || 386 IS_COFFEELAKE(i915) || 387 IS_COMETLAKE(i915)) 388 wa_masked_en(wal, HALF_SLICE_CHICKEN3, 389 GEN8_SAMPLER_POWER_BYPASS_DIS); 390 391 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 392 wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 393 394 /* 395 * Supporting preemption with fine-granularity requires changes in the 396 * batch buffer programming. Since we can't break old userspace, we 397 * need to set our default preemption level to safe value. Userspace is 398 * still able to use more fine-grained preemption levels, since in 399 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 400 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 401 * not real HW workarounds, but merely a way to start using preemption 402 * while maintaining old contract with userspace. 403 */ 404 405 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 406 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 407 408 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 409 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 410 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 411 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 412 413 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 414 if (IS_GEN9_LP(i915)) 415 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 416 } 417 418 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 419 struct i915_wa_list *wal) 420 { 421 struct intel_gt *gt = engine->gt; 422 u8 vals[3] = { 0, 0, 0 }; 423 unsigned int i; 424 425 for (i = 0; i < 3; i++) { 426 u8 ss; 427 428 /* 429 * Only consider slices where one, and only one, subslice has 7 430 * EUs 431 */ 432 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 433 continue; 434 435 /* 436 * subslice_7eu[i] != 0 (because of the check above) and 437 * ss_max == 4 (maximum number of subslices possible per slice) 438 * 439 * -> 0 <= ss <= 3; 440 */ 441 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 442 vals[i] = 3 - ss; 443 } 444 445 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 446 return; 447 448 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 449 wa_masked_field_set(wal, GEN7_GT_MODE, 450 GEN9_IZ_HASHING_MASK(2) | 451 GEN9_IZ_HASHING_MASK(1) | 452 GEN9_IZ_HASHING_MASK(0), 453 GEN9_IZ_HASHING(2, vals[2]) | 454 GEN9_IZ_HASHING(1, vals[1]) | 455 GEN9_IZ_HASHING(0, vals[0])); 456 } 457 458 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 459 struct i915_wa_list *wal) 460 { 461 gen9_ctx_workarounds_init(engine, wal); 462 skl_tune_iz_hashing(engine, wal); 463 } 464 465 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 466 struct i915_wa_list *wal) 467 { 468 gen9_ctx_workarounds_init(engine, wal); 469 470 /* WaDisableThreadStallDopClockGating:bxt */ 471 wa_masked_en(wal, GEN8_ROW_CHICKEN, 472 STALL_DOP_GATING_DISABLE); 473 474 /* WaToEnableHwFixForPushConstHWBug:bxt */ 475 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 476 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 477 } 478 479 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 480 struct i915_wa_list *wal) 481 { 482 struct drm_i915_private *i915 = engine->i915; 483 484 gen9_ctx_workarounds_init(engine, wal); 485 486 /* WaToEnableHwFixForPushConstHWBug:kbl */ 487 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 488 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 489 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 490 491 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 492 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 493 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 494 } 495 496 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 497 struct i915_wa_list *wal) 498 { 499 gen9_ctx_workarounds_init(engine, wal); 500 501 /* WaToEnableHwFixForPushConstHWBug:glk */ 502 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 503 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 504 } 505 506 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 507 struct i915_wa_list *wal) 508 { 509 gen9_ctx_workarounds_init(engine, wal); 510 511 /* WaToEnableHwFixForPushConstHWBug:cfl */ 512 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 513 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 514 515 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 516 wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1, 517 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 518 } 519 520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 521 struct i915_wa_list *wal) 522 { 523 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 524 wa_write(wal, 525 GEN8_L3CNTLREG, 526 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 527 GEN8_ERRDETBCTRL); 528 529 /* WaForceEnableNonCoherent:icl 530 * This is not the same workaround as in early Gen9 platforms, where 531 * lacking this could cause system hangs, but coherency performance 532 * overhead is high and only a few compute workloads really need it 533 * (the register is whitelisted in hardware now, so UMDs can opt in 534 * for coherency if they have a good reason). 535 */ 536 wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 537 538 /* WaEnableFloatBlendOptimization:icl */ 539 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 540 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 541 0 /* write-only, so skip validation */, 542 true); 543 544 /* WaDisableGPGPUMidThreadPreemption:icl */ 545 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 546 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 547 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 548 549 /* allow headerless messages for preemptible GPGPU context */ 550 wa_masked_en(wal, GEN10_SAMPLER_MODE, 551 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 552 553 /* Wa_1604278689:icl,ehl */ 554 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 555 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 556 0, /* write-only register; skip validation */ 557 0xFFFFFFFF); 558 559 /* Wa_1406306137:icl,ehl */ 560 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 561 } 562 563 /* 564 * These settings aren't actually workarounds, but general tuning settings that 565 * need to be programmed on dg2 platform. 566 */ 567 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 568 struct i915_wa_list *wal) 569 { 570 wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 571 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 572 wa_add(wal, 573 FF_MODE2, 574 FF_MODE2_TDS_TIMER_MASK, 575 FF_MODE2_TDS_TIMER_128, 576 0, false); 577 } 578 579 /* 580 * These settings aren't actually workarounds, but general tuning settings that 581 * need to be programmed on several platforms. 582 */ 583 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 584 struct i915_wa_list *wal) 585 { 586 /* 587 * Although some platforms refer to it as Wa_1604555607, we need to 588 * program it even on those that don't explicitly list that 589 * workaround. 590 * 591 * Note that the programming of this register is further modified 592 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 593 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 594 * value when read. The default value for this register is zero for all 595 * fields and there are no bit masks. So instead of doing a RMW we 596 * should just write TDS timer value. For the same reason read 597 * verification is ignored. 598 */ 599 wa_add(wal, 600 FF_MODE2, 601 FF_MODE2_TDS_TIMER_MASK, 602 FF_MODE2_TDS_TIMER_128, 603 0, false); 604 } 605 606 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 607 struct i915_wa_list *wal) 608 { 609 gen12_ctx_gt_tuning_init(engine, wal); 610 611 /* 612 * Wa_1409142259:tgl,dg1,adl-p 613 * Wa_1409347922:tgl,dg1,adl-p 614 * Wa_1409252684:tgl,dg1,adl-p 615 * Wa_1409217633:tgl,dg1,adl-p 616 * Wa_1409207793:tgl,dg1,adl-p 617 * Wa_1409178076:tgl,dg1,adl-p 618 * Wa_1408979724:tgl,dg1,adl-p 619 * Wa_14010443199:tgl,rkl,dg1,adl-p 620 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 621 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 622 */ 623 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 624 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 625 626 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 627 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 628 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 629 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 630 631 /* 632 * Wa_16011163337 633 * 634 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 635 * to Wa_1608008084. 636 */ 637 wa_add(wal, 638 FF_MODE2, 639 FF_MODE2_GS_TIMER_MASK, 640 FF_MODE2_GS_TIMER_224, 641 0, false); 642 } 643 644 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 645 struct i915_wa_list *wal) 646 { 647 gen12_ctx_workarounds_init(engine, wal); 648 649 /* Wa_1409044764 */ 650 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 651 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 652 653 /* Wa_22010493298 */ 654 wa_masked_en(wal, HIZ_CHICKEN, 655 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 656 } 657 658 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 659 struct i915_wa_list *wal) 660 { 661 dg2_ctx_gt_tuning_init(engine, wal); 662 663 /* Wa_16011186671:dg2_g11 */ 664 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 665 wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 666 wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 667 } 668 669 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 670 /* Wa_14010469329:dg2_g10 */ 671 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 672 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 673 674 /* 675 * Wa_22010465075:dg2_g10 676 * Wa_22010613112:dg2_g10 677 * Wa_14010698770:dg2_g10 678 */ 679 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 680 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 681 } 682 683 /* Wa_16013271637:dg2 */ 684 wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1, 685 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 686 687 /* Wa_22012532006:dg2 */ 688 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 689 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 690 wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 691 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 692 } 693 694 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 695 struct i915_wa_list *wal) 696 { 697 /* 698 * This is a "fake" workaround defined by software to ensure we 699 * maintain reliable, backward-compatible behavior for userspace with 700 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 701 * 702 * The per-context setting of MI_MODE[12] determines whether the bits 703 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 704 * in the traditional manner or whether they should instead use a new 705 * tgl+ meaning that breaks backward compatibility, but allows nesting 706 * into 3rd-level batchbuffers. When this new capability was first 707 * added in TGL, it remained off by default unless a context 708 * intentionally opted in to the new behavior. However Xe_HPG now 709 * flips this on by default and requires that we explicitly opt out if 710 * we don't want the new behavior. 711 * 712 * From a SW perspective, we want to maintain the backward-compatible 713 * behavior for userspace, so we'll apply a fake workaround to set it 714 * back to the legacy behavior on platforms where the hardware default 715 * is to break compatibility. At the moment there is no Linux 716 * userspace that utilizes third-level batchbuffers, so this will avoid 717 * userspace from needing to make any changes. using the legacy 718 * meaning is the correct thing to do. If/when we have userspace 719 * consumers that want to utilize third-level batch nesting, we can 720 * provide a context parameter to allow them to opt-in. 721 */ 722 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 723 } 724 725 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 726 struct i915_wa_list *wal) 727 { 728 u8 mocs; 729 730 /* 731 * Some blitter commands do not have a field for MOCS, those 732 * commands will use MOCS index pointed by BLIT_CCTL. 733 * BLIT_CCTL registers are needed to be programmed to un-cached. 734 */ 735 if (engine->class == COPY_ENGINE_CLASS) { 736 mocs = engine->gt->mocs.uc_index; 737 wa_write_clr_set(wal, 738 BLIT_CCTL(engine->mmio_base), 739 BLIT_CCTL_MASK, 740 BLIT_CCTL_MOCS(mocs, mocs)); 741 } 742 } 743 744 /* 745 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 746 * defined by the hardware team, but it programming general context registers. 747 * Adding those context register programming in context workaround 748 * allow us to use the wa framework for proper application and validation. 749 */ 750 static void 751 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 752 struct i915_wa_list *wal) 753 { 754 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 755 fakewa_disable_nestedbb_mode(engine, wal); 756 757 gen12_ctx_gt_mocs_init(engine, wal); 758 } 759 760 static void 761 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 762 struct i915_wa_list *wal, 763 const char *name) 764 { 765 struct drm_i915_private *i915 = engine->i915; 766 767 wa_init_start(wal, name, engine->name); 768 769 /* Applies to all engines */ 770 /* 771 * Fake workarounds are not the actual workaround but 772 * programming of context registers using workaround framework. 773 */ 774 if (GRAPHICS_VER(i915) >= 12) 775 gen12_ctx_gt_fake_wa_init(engine, wal); 776 777 if (engine->class != RENDER_CLASS) 778 goto done; 779 780 if (IS_DG2(i915)) 781 dg2_ctx_workarounds_init(engine, wal); 782 else if (IS_XEHPSDV(i915)) 783 ; /* noop; none at this time */ 784 else if (IS_DG1(i915)) 785 dg1_ctx_workarounds_init(engine, wal); 786 else if (GRAPHICS_VER(i915) == 12) 787 gen12_ctx_workarounds_init(engine, wal); 788 else if (GRAPHICS_VER(i915) == 11) 789 icl_ctx_workarounds_init(engine, wal); 790 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 791 cfl_ctx_workarounds_init(engine, wal); 792 else if (IS_GEMINILAKE(i915)) 793 glk_ctx_workarounds_init(engine, wal); 794 else if (IS_KABYLAKE(i915)) 795 kbl_ctx_workarounds_init(engine, wal); 796 else if (IS_BROXTON(i915)) 797 bxt_ctx_workarounds_init(engine, wal); 798 else if (IS_SKYLAKE(i915)) 799 skl_ctx_workarounds_init(engine, wal); 800 else if (IS_CHERRYVIEW(i915)) 801 chv_ctx_workarounds_init(engine, wal); 802 else if (IS_BROADWELL(i915)) 803 bdw_ctx_workarounds_init(engine, wal); 804 else if (GRAPHICS_VER(i915) == 7) 805 gen7_ctx_workarounds_init(engine, wal); 806 else if (GRAPHICS_VER(i915) == 6) 807 gen6_ctx_workarounds_init(engine, wal); 808 else if (GRAPHICS_VER(i915) < 8) 809 ; 810 else 811 MISSING_CASE(GRAPHICS_VER(i915)); 812 813 done: 814 wa_init_finish(wal); 815 } 816 817 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 818 { 819 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 820 } 821 822 int intel_engine_emit_ctx_wa(struct i915_request *rq) 823 { 824 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 825 struct i915_wa *wa; 826 unsigned int i; 827 u32 *cs; 828 int ret; 829 830 if (wal->count == 0) 831 return 0; 832 833 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 834 if (ret) 835 return ret; 836 837 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 838 if (IS_ERR(cs)) 839 return PTR_ERR(cs); 840 841 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 842 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 843 *cs++ = i915_mmio_reg_offset(wa->reg); 844 *cs++ = wa->set; 845 } 846 *cs++ = MI_NOOP; 847 848 intel_ring_advance(rq, cs); 849 850 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 851 if (ret) 852 return ret; 853 854 return 0; 855 } 856 857 static void 858 gen4_gt_workarounds_init(struct intel_gt *gt, 859 struct i915_wa_list *wal) 860 { 861 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 862 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 863 } 864 865 static void 866 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 867 { 868 gen4_gt_workarounds_init(gt, wal); 869 870 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 871 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 872 } 873 874 static void 875 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 876 { 877 g4x_gt_workarounds_init(gt, wal); 878 879 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 880 } 881 882 static void 883 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 884 { 885 } 886 887 static void 888 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 889 { 890 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 891 wa_masked_dis(wal, 892 GEN7_COMMON_SLICE_CHICKEN1, 893 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 894 895 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 896 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 897 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 898 899 /* WaForceL3Serialization:ivb */ 900 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 901 } 902 903 static void 904 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 905 { 906 /* WaForceL3Serialization:vlv */ 907 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 908 909 /* 910 * WaIncreaseL3CreditsForVLVB0:vlv 911 * This is the hardware default actually. 912 */ 913 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 914 } 915 916 static void 917 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 918 { 919 /* L3 caching of data atomics doesn't work -- disable it. */ 920 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 921 922 wa_add(wal, 923 HSW_ROW_CHICKEN3, 0, 924 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 925 0 /* XXX does this reg exist? */, true); 926 927 /* WaVSRefCountFullforceMissDisable:hsw */ 928 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 929 } 930 931 static void 932 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 933 { 934 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 935 unsigned int slice, subslice; 936 u32 mcr, mcr_mask; 937 938 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 939 940 /* 941 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 942 * Before any MMIO read into slice/subslice specific registers, MCR 943 * packet control register needs to be programmed to point to any 944 * enabled s/ss pair. Otherwise, incorrect values will be returned. 945 * This means each subsequent MMIO read will be forwarded to an 946 * specific s/ss combination, but this is OK since these registers 947 * are consistent across s/ss in almost all cases. In the rare 948 * occasions, such as INSTDONE, where this value is dependent 949 * on s/ss combo, the read should be done with read_subslice_reg. 950 */ 951 slice = ffs(sseu->slice_mask) - 1; 952 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); 953 subslice = ffs(intel_sseu_get_subslices(sseu, slice)); 954 GEM_BUG_ON(!subslice); 955 subslice--; 956 957 /* 958 * We use GEN8_MCR..() macros to calculate the |mcr| value for 959 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 960 */ 961 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 962 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 963 964 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 965 966 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 967 } 968 969 static void 970 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 971 { 972 struct drm_i915_private *i915 = gt->i915; 973 974 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 975 gen9_wa_init_mcr(i915, wal); 976 977 /* WaDisableKillLogic:bxt,skl,kbl */ 978 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 979 wa_write_or(wal, 980 GAM_ECOCHK, 981 ECOCHK_DIS_TLB); 982 983 if (HAS_LLC(i915)) { 984 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 985 * 986 * Must match Display Engine. See 987 * WaCompressedResourceDisplayNewHashMode. 988 */ 989 wa_write_or(wal, 990 MMCD_MISC_CTRL, 991 MMCD_PCLA | MMCD_HOTSPOT_EN); 992 } 993 994 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 995 wa_write_or(wal, 996 GAM_ECOCHK, 997 BDW_DISABLE_HDC_INVALIDATION); 998 } 999 1000 static void 1001 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1002 { 1003 gen9_gt_workarounds_init(gt, wal); 1004 1005 /* WaDisableGafsUnitClkGating:skl */ 1006 wa_write_or(wal, 1007 GEN7_UCGCTL4, 1008 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1009 1010 /* WaInPlaceDecompressionHang:skl */ 1011 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1012 wa_write_or(wal, 1013 GEN9_GAMT_ECO_REG_RW_IA, 1014 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1015 } 1016 1017 static void 1018 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1019 { 1020 gen9_gt_workarounds_init(gt, wal); 1021 1022 /* WaDisableDynamicCreditSharing:kbl */ 1023 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1024 wa_write_or(wal, 1025 GAMT_CHKN_BIT_REG, 1026 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1027 1028 /* WaDisableGafsUnitClkGating:kbl */ 1029 wa_write_or(wal, 1030 GEN7_UCGCTL4, 1031 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1032 1033 /* WaInPlaceDecompressionHang:kbl */ 1034 wa_write_or(wal, 1035 GEN9_GAMT_ECO_REG_RW_IA, 1036 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1037 } 1038 1039 static void 1040 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1041 { 1042 gen9_gt_workarounds_init(gt, wal); 1043 } 1044 1045 static void 1046 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1047 { 1048 gen9_gt_workarounds_init(gt, wal); 1049 1050 /* WaDisableGafsUnitClkGating:cfl */ 1051 wa_write_or(wal, 1052 GEN7_UCGCTL4, 1053 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1054 1055 /* WaInPlaceDecompressionHang:cfl */ 1056 wa_write_or(wal, 1057 GEN9_GAMT_ECO_REG_RW_IA, 1058 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1059 } 1060 1061 static void __set_mcr_steering(struct i915_wa_list *wal, 1062 i915_reg_t steering_reg, 1063 unsigned int slice, unsigned int subslice) 1064 { 1065 u32 mcr, mcr_mask; 1066 1067 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1068 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1069 1070 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1071 } 1072 1073 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1074 unsigned int slice, unsigned int subslice) 1075 { 1076 drm_dbg(>->i915->drm, "MCR slice=0x%x, subslice=0x%x\n", slice, subslice); 1077 1078 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1079 } 1080 1081 static void 1082 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1083 { 1084 const struct sseu_dev_info *sseu = >->info.sseu; 1085 unsigned int slice, subslice; 1086 1087 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1088 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1089 slice = 0; 1090 1091 /* 1092 * Although a platform may have subslices, we need to always steer 1093 * reads to the lowest instance that isn't fused off. When Render 1094 * Power Gating is enabled, grabbing forcewake will only power up a 1095 * single subslice (the "minconfig") if there isn't a real workload 1096 * that needs to be run; this means that if we steer register reads to 1097 * one of the higher subslices, we run the risk of reading back 0's or 1098 * random garbage. 1099 */ 1100 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); 1101 1102 /* 1103 * If the subslice we picked above also steers us to a valid L3 bank, 1104 * then we can just rely on the default steering and won't need to 1105 * worry about explicitly re-steering L3BANK reads later. 1106 */ 1107 if (gt->info.l3bank_mask & BIT(subslice)) 1108 gt->steering_table[L3BANK] = NULL; 1109 1110 __add_mcr_wa(gt, wal, slice, subslice); 1111 } 1112 1113 static void 1114 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1115 { 1116 const struct sseu_dev_info *sseu = >->info.sseu; 1117 unsigned long slice, subslice = 0, slice_mask = 0; 1118 u64 dss_mask = 0; 1119 u32 lncf_mask = 0; 1120 int i; 1121 1122 /* 1123 * On Xe_HP the steering increases in complexity. There are now several 1124 * more units that require steering and we're not guaranteed to be able 1125 * to find a common setting for all of them. These are: 1126 * - GSLICE (fusable) 1127 * - DSS (sub-unit within gslice; fusable) 1128 * - L3 Bank (fusable) 1129 * - MSLICE (fusable) 1130 * - LNCF (sub-unit within mslice; always present if mslice is present) 1131 * 1132 * We'll do our default/implicit steering based on GSLICE (in the 1133 * sliceid field) and DSS (in the subsliceid field). If we can 1134 * find overlap between the valid MSLICE and/or LNCF values with 1135 * a suitable GSLICE, then we can just re-use the default value and 1136 * skip and explicit steering at runtime. 1137 * 1138 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1139 * a valid sliceid value. DSS steering is the only type of steering 1140 * that utilizes the 'subsliceid' bits. 1141 * 1142 * Also note that, even though the steering domain is called "GSlice" 1143 * and it is encoded in the register using the gslice format, the spec 1144 * says that the combined (geometry | compute) fuse should be used to 1145 * select the steering. 1146 */ 1147 1148 /* Find the potential gslice candidates */ 1149 dss_mask = intel_sseu_get_subslices(sseu, 0); 1150 slice_mask = intel_slicemask_from_dssmask(dss_mask, GEN_DSS_PER_GSLICE); 1151 1152 /* 1153 * Find the potential LNCF candidates. Either LNCF within a valid 1154 * mslice is fine. 1155 */ 1156 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1157 lncf_mask |= (0x3 << (i * 2)); 1158 1159 /* 1160 * Are there any sliceid values that work for both GSLICE and LNCF 1161 * steering? 1162 */ 1163 if (slice_mask & lncf_mask) { 1164 slice_mask &= lncf_mask; 1165 gt->steering_table[LNCF] = NULL; 1166 } 1167 1168 /* How about sliceid values that also work for MSLICE steering? */ 1169 if (slice_mask & gt->info.mslice_mask) { 1170 slice_mask &= gt->info.mslice_mask; 1171 gt->steering_table[MSLICE] = NULL; 1172 } 1173 1174 slice = __ffs(slice_mask); 1175 subslice = __ffs(dss_mask >> (slice * GEN_DSS_PER_GSLICE)); 1176 WARN_ON(subslice > GEN_DSS_PER_GSLICE); 1177 WARN_ON(dss_mask >> (slice * GEN_DSS_PER_GSLICE) == 0); 1178 1179 __add_mcr_wa(gt, wal, slice, subslice); 1180 1181 /* 1182 * SQIDI ranges are special because they use different steering 1183 * registers than everything else we work with. On XeHP SDV and 1184 * DG2-G10, any value in the steering registers will work fine since 1185 * all instances are present, but DG2-G11 only has SQIDI instances at 1186 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1187 * we'll just steer to a hardcoded "2" since that value will work 1188 * everywhere. 1189 */ 1190 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1191 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1192 } 1193 1194 static void 1195 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1196 { 1197 struct drm_i915_private *i915 = gt->i915; 1198 1199 icl_wa_init_mcr(gt, wal); 1200 1201 /* WaModifyGamTlbPartitioning:icl */ 1202 wa_write_clr_set(wal, 1203 GEN11_GACB_PERF_CTRL, 1204 GEN11_HASH_CTRL_MASK, 1205 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1206 1207 /* Wa_1405766107:icl 1208 * Formerly known as WaCL2SFHalfMaxAlloc 1209 */ 1210 wa_write_or(wal, 1211 GEN11_LSN_UNSLCVC, 1212 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1213 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1214 1215 /* Wa_220166154:icl 1216 * Formerly known as WaDisCtxReload 1217 */ 1218 wa_write_or(wal, 1219 GEN8_GAMW_ECO_DEV_RW_IA, 1220 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1221 1222 /* Wa_1406463099:icl 1223 * Formerly known as WaGamTlbPendError 1224 */ 1225 wa_write_or(wal, 1226 GAMT_CHKN_BIT_REG, 1227 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1228 1229 /* Wa_1407352427:icl,ehl */ 1230 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1231 PSDUNIT_CLKGATE_DIS); 1232 1233 /* Wa_1406680159:icl,ehl */ 1234 wa_write_or(wal, 1235 SUBSLICE_UNIT_LEVEL_CLKGATE, 1236 GWUNIT_CLKGATE_DIS); 1237 1238 /* Wa_1607087056:icl,ehl,jsl */ 1239 if (IS_ICELAKE(i915) || 1240 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1241 wa_write_or(wal, 1242 SLICE_UNIT_LEVEL_CLKGATE, 1243 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1244 1245 /* 1246 * This is not a documented workaround, but rather an optimization 1247 * to reduce sampler power. 1248 */ 1249 wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1250 } 1251 1252 /* 1253 * Though there are per-engine instances of these registers, 1254 * they retain their value through engine resets and should 1255 * only be provided on the GT workaround list rather than 1256 * the engine-specific workaround list. 1257 */ 1258 static void 1259 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1260 { 1261 struct intel_engine_cs *engine; 1262 int id; 1263 1264 for_each_engine(engine, gt, id) { 1265 if (engine->class != VIDEO_DECODE_CLASS || 1266 (engine->instance % 2)) 1267 continue; 1268 1269 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1270 IECPUNIT_CLKGATE_DIS); 1271 } 1272 } 1273 1274 static void 1275 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1276 { 1277 icl_wa_init_mcr(gt, wal); 1278 1279 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1280 wa_14011060649(gt, wal); 1281 1282 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1283 wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1284 } 1285 1286 static void 1287 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1288 { 1289 struct drm_i915_private *i915 = gt->i915; 1290 1291 gen12_gt_workarounds_init(gt, wal); 1292 1293 /* Wa_1409420604:tgl */ 1294 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1295 wa_write_or(wal, 1296 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1297 CPSSUNIT_CLKGATE_DIS); 1298 1299 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1300 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1301 wa_write_or(wal, 1302 SLICE_UNIT_LEVEL_CLKGATE, 1303 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1304 1305 /* Wa_1408615072:tgl[a0] */ 1306 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1307 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1308 VSUNIT_CLKGATE_DIS_TGL); 1309 } 1310 1311 static void 1312 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1313 { 1314 struct drm_i915_private *i915 = gt->i915; 1315 1316 gen12_gt_workarounds_init(gt, wal); 1317 1318 /* Wa_1607087056:dg1 */ 1319 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1320 wa_write_or(wal, 1321 SLICE_UNIT_LEVEL_CLKGATE, 1322 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1323 1324 /* Wa_1409420604:dg1 */ 1325 if (IS_DG1(i915)) 1326 wa_write_or(wal, 1327 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1328 CPSSUNIT_CLKGATE_DIS); 1329 1330 /* Wa_1408615072:dg1 */ 1331 /* Empirical testing shows this register is unaffected by engine reset. */ 1332 if (IS_DG1(i915)) 1333 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1334 VSUNIT_CLKGATE_DIS_TGL); 1335 } 1336 1337 static void 1338 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1339 { 1340 struct drm_i915_private *i915 = gt->i915; 1341 1342 xehp_init_mcr(gt, wal); 1343 1344 /* Wa_1409757795:xehpsdv */ 1345 wa_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1346 1347 /* Wa_18011725039:xehpsdv */ 1348 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 1349 wa_masked_dis(wal, MLTICTXCTL, TDONRENDER); 1350 wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 1351 } 1352 1353 /* Wa_16011155590:xehpsdv */ 1354 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1355 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1356 TSGUNIT_CLKGATE_DIS); 1357 1358 /* Wa_14011780169:xehpsdv */ 1359 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1360 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1361 GAMTLBVDBOX7_CLKGATE_DIS | 1362 GAMTLBVDBOX6_CLKGATE_DIS | 1363 GAMTLBVDBOX5_CLKGATE_DIS | 1364 GAMTLBVDBOX4_CLKGATE_DIS | 1365 GAMTLBVDBOX3_CLKGATE_DIS | 1366 GAMTLBVDBOX2_CLKGATE_DIS | 1367 GAMTLBVDBOX1_CLKGATE_DIS | 1368 GAMTLBVDBOX0_CLKGATE_DIS | 1369 GAMTLBKCR_CLKGATE_DIS | 1370 GAMTLBGUC_CLKGATE_DIS | 1371 GAMTLBBLT_CLKGATE_DIS); 1372 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1373 GAMTLBGFXA1_CLKGATE_DIS | 1374 GAMTLBCOMPA0_CLKGATE_DIS | 1375 GAMTLBCOMPA1_CLKGATE_DIS | 1376 GAMTLBCOMPB0_CLKGATE_DIS | 1377 GAMTLBCOMPB1_CLKGATE_DIS | 1378 GAMTLBCOMPC0_CLKGATE_DIS | 1379 GAMTLBCOMPC1_CLKGATE_DIS | 1380 GAMTLBCOMPD0_CLKGATE_DIS | 1381 GAMTLBCOMPD1_CLKGATE_DIS | 1382 GAMTLBMERT_CLKGATE_DIS | 1383 GAMTLBVEBOX3_CLKGATE_DIS | 1384 GAMTLBVEBOX2_CLKGATE_DIS | 1385 GAMTLBVEBOX1_CLKGATE_DIS | 1386 GAMTLBVEBOX0_CLKGATE_DIS); 1387 } 1388 1389 /* Wa_14012362059:xehpsdv */ 1390 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1391 1392 /* Wa_16012725990:xehpsdv */ 1393 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1394 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1395 1396 /* Wa_14011060649:xehpsdv */ 1397 wa_14011060649(gt, wal); 1398 1399 /* Wa_14014368820:xehpsdv */ 1400 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 1401 GLOBAL_INVALIDATION_MODE); 1402 } 1403 1404 static void 1405 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1406 { 1407 struct intel_engine_cs *engine; 1408 int id; 1409 1410 xehp_init_mcr(gt, wal); 1411 1412 /* Wa_14011060649:dg2 */ 1413 wa_14011060649(gt, wal); 1414 1415 /* 1416 * Although there are per-engine instances of these registers, 1417 * they technically exist outside the engine itself and are not 1418 * impacted by engine resets. Furthermore, they're part of the 1419 * GuC blacklist so trying to treat them as engine workarounds 1420 * will result in GuC initialization failure and a wedged GPU. 1421 */ 1422 for_each_engine(engine, gt, id) { 1423 if (engine->class != VIDEO_DECODE_CLASS) 1424 continue; 1425 1426 /* Wa_16010515920:dg2_g10 */ 1427 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1428 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1429 ALNUNIT_CLKGATE_DIS); 1430 } 1431 1432 if (IS_DG2_G10(gt->i915)) { 1433 /* Wa_22010523718:dg2 */ 1434 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1435 CG3DDISCFEG_CLKGATE_DIS); 1436 1437 /* Wa_14011006942:dg2 */ 1438 wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE, 1439 DSS_ROUTER_CLKGATE_DIS); 1440 } 1441 1442 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1443 /* Wa_14010680813:dg2_g10 */ 1444 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 1445 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 1446 1447 /* Wa_14010948348:dg2_g10 */ 1448 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1449 1450 /* Wa_14011037102:dg2_g10 */ 1451 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1452 1453 /* Wa_14011371254:dg2_g10 */ 1454 wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1455 1456 /* Wa_14011431319:dg2_g10 */ 1457 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1458 GAMTLBVDBOX7_CLKGATE_DIS | 1459 GAMTLBVDBOX6_CLKGATE_DIS | 1460 GAMTLBVDBOX5_CLKGATE_DIS | 1461 GAMTLBVDBOX4_CLKGATE_DIS | 1462 GAMTLBVDBOX3_CLKGATE_DIS | 1463 GAMTLBVDBOX2_CLKGATE_DIS | 1464 GAMTLBVDBOX1_CLKGATE_DIS | 1465 GAMTLBVDBOX0_CLKGATE_DIS | 1466 GAMTLBKCR_CLKGATE_DIS | 1467 GAMTLBGUC_CLKGATE_DIS | 1468 GAMTLBBLT_CLKGATE_DIS); 1469 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1470 GAMTLBGFXA1_CLKGATE_DIS | 1471 GAMTLBCOMPA0_CLKGATE_DIS | 1472 GAMTLBCOMPA1_CLKGATE_DIS | 1473 GAMTLBCOMPB0_CLKGATE_DIS | 1474 GAMTLBCOMPB1_CLKGATE_DIS | 1475 GAMTLBCOMPC0_CLKGATE_DIS | 1476 GAMTLBCOMPC1_CLKGATE_DIS | 1477 GAMTLBCOMPD0_CLKGATE_DIS | 1478 GAMTLBCOMPD1_CLKGATE_DIS | 1479 GAMTLBMERT_CLKGATE_DIS | 1480 GAMTLBVEBOX3_CLKGATE_DIS | 1481 GAMTLBVEBOX2_CLKGATE_DIS | 1482 GAMTLBVEBOX1_CLKGATE_DIS | 1483 GAMTLBVEBOX0_CLKGATE_DIS); 1484 1485 /* Wa_14010569222:dg2_g10 */ 1486 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1487 GAMEDIA_CLKGATE_DIS); 1488 1489 /* Wa_14011028019:dg2_g10 */ 1490 wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1491 } 1492 1493 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) || 1494 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) { 1495 /* Wa_14012362059:dg2 */ 1496 wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB); 1497 } 1498 1499 /* Wa_1509235366:dg2 */ 1500 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 1501 GLOBAL_INVALIDATION_MODE); 1502 1503 /* Wa_14014830051:dg2 */ 1504 wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1505 1506 /* 1507 * The following are not actually "workarounds" but rather 1508 * recommended tuning settings documented in the bspec's 1509 * performance guide section. 1510 */ 1511 wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 1512 wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); 1513 1514 /* Wa_18018781329:dg2 */ 1515 wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 1516 wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 1517 wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 1518 wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 1519 } 1520 1521 static void 1522 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1523 { 1524 struct drm_i915_private *i915 = gt->i915; 1525 1526 if (IS_DG2(i915)) 1527 dg2_gt_workarounds_init(gt, wal); 1528 else if (IS_XEHPSDV(i915)) 1529 xehpsdv_gt_workarounds_init(gt, wal); 1530 else if (IS_DG1(i915)) 1531 dg1_gt_workarounds_init(gt, wal); 1532 else if (IS_TIGERLAKE(i915)) 1533 tgl_gt_workarounds_init(gt, wal); 1534 else if (GRAPHICS_VER(i915) == 12) 1535 gen12_gt_workarounds_init(gt, wal); 1536 else if (GRAPHICS_VER(i915) == 11) 1537 icl_gt_workarounds_init(gt, wal); 1538 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1539 cfl_gt_workarounds_init(gt, wal); 1540 else if (IS_GEMINILAKE(i915)) 1541 glk_gt_workarounds_init(gt, wal); 1542 else if (IS_KABYLAKE(i915)) 1543 kbl_gt_workarounds_init(gt, wal); 1544 else if (IS_BROXTON(i915)) 1545 gen9_gt_workarounds_init(gt, wal); 1546 else if (IS_SKYLAKE(i915)) 1547 skl_gt_workarounds_init(gt, wal); 1548 else if (IS_HASWELL(i915)) 1549 hsw_gt_workarounds_init(gt, wal); 1550 else if (IS_VALLEYVIEW(i915)) 1551 vlv_gt_workarounds_init(gt, wal); 1552 else if (IS_IVYBRIDGE(i915)) 1553 ivb_gt_workarounds_init(gt, wal); 1554 else if (GRAPHICS_VER(i915) == 6) 1555 snb_gt_workarounds_init(gt, wal); 1556 else if (GRAPHICS_VER(i915) == 5) 1557 ilk_gt_workarounds_init(gt, wal); 1558 else if (IS_G4X(i915)) 1559 g4x_gt_workarounds_init(gt, wal); 1560 else if (GRAPHICS_VER(i915) == 4) 1561 gen4_gt_workarounds_init(gt, wal); 1562 else if (GRAPHICS_VER(i915) <= 8) 1563 ; 1564 else 1565 MISSING_CASE(GRAPHICS_VER(i915)); 1566 } 1567 1568 void intel_gt_init_workarounds(struct intel_gt *gt) 1569 { 1570 struct i915_wa_list *wal = >->wa_list; 1571 1572 wa_init_start(wal, "GT", "global"); 1573 gt_init_workarounds(gt, wal); 1574 wa_init_finish(wal); 1575 } 1576 1577 static enum forcewake_domains 1578 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1579 { 1580 enum forcewake_domains fw = 0; 1581 struct i915_wa *wa; 1582 unsigned int i; 1583 1584 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1585 fw |= intel_uncore_forcewake_for_reg(uncore, 1586 wa->reg, 1587 FW_REG_READ | 1588 FW_REG_WRITE); 1589 1590 return fw; 1591 } 1592 1593 static bool 1594 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1595 { 1596 if ((cur ^ wa->set) & wa->read) { 1597 DRM_ERROR("%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1598 name, from, i915_mmio_reg_offset(wa->reg), 1599 cur, cur & wa->read, wa->set & wa->read); 1600 1601 return false; 1602 } 1603 1604 return true; 1605 } 1606 1607 static void 1608 wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) 1609 { 1610 struct intel_uncore *uncore = gt->uncore; 1611 enum forcewake_domains fw; 1612 unsigned long flags; 1613 struct i915_wa *wa; 1614 unsigned int i; 1615 1616 if (!wal->count) 1617 return; 1618 1619 fw = wal_get_fw_for_rmw(uncore, wal); 1620 1621 spin_lock_irqsave(&uncore->lock, flags); 1622 intel_uncore_forcewake_get__locked(uncore, fw); 1623 1624 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1625 u32 val, old = 0; 1626 1627 /* open-coded rmw due to steering */ 1628 old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; 1629 val = (old & ~wa->clr) | wa->set; 1630 if (val != old || !wa->clr) 1631 intel_uncore_write_fw(uncore, wa->reg, val); 1632 1633 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1634 wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), 1635 wal->name, "application"); 1636 } 1637 1638 intel_uncore_forcewake_put__locked(uncore, fw); 1639 spin_unlock_irqrestore(&uncore->lock, flags); 1640 } 1641 1642 void intel_gt_apply_workarounds(struct intel_gt *gt) 1643 { 1644 wa_list_apply(gt, >->wa_list); 1645 } 1646 1647 static bool wa_list_verify(struct intel_gt *gt, 1648 const struct i915_wa_list *wal, 1649 const char *from) 1650 { 1651 struct intel_uncore *uncore = gt->uncore; 1652 struct i915_wa *wa; 1653 enum forcewake_domains fw; 1654 unsigned long flags; 1655 unsigned int i; 1656 bool ok = true; 1657 1658 fw = wal_get_fw_for_rmw(uncore, wal); 1659 1660 spin_lock_irqsave(&uncore->lock, flags); 1661 intel_uncore_forcewake_get__locked(uncore, fw); 1662 1663 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1664 ok &= wa_verify(wa, 1665 intel_gt_read_register_fw(gt, wa->reg), 1666 wal->name, from); 1667 1668 intel_uncore_forcewake_put__locked(uncore, fw); 1669 spin_unlock_irqrestore(&uncore->lock, flags); 1670 1671 return ok; 1672 } 1673 1674 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1675 { 1676 return wa_list_verify(gt, >->wa_list, from); 1677 } 1678 1679 __maybe_unused 1680 static bool is_nonpriv_flags_valid(u32 flags) 1681 { 1682 /* Check only valid flag bits are set */ 1683 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1684 return false; 1685 1686 /* NB: Only 3 out of 4 enum values are valid for access field */ 1687 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1688 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1689 return false; 1690 1691 return true; 1692 } 1693 1694 static void 1695 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1696 { 1697 struct i915_wa wa = { 1698 .reg = reg 1699 }; 1700 1701 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1702 return; 1703 1704 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1705 return; 1706 1707 wa.reg.reg |= flags; 1708 _wa_add(wal, &wa); 1709 } 1710 1711 static void 1712 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1713 { 1714 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1715 } 1716 1717 static void gen9_whitelist_build(struct i915_wa_list *w) 1718 { 1719 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1720 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1721 1722 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1723 whitelist_reg(w, GEN8_CS_CHICKEN1); 1724 1725 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1726 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1727 1728 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1729 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1730 } 1731 1732 static void skl_whitelist_build(struct intel_engine_cs *engine) 1733 { 1734 struct i915_wa_list *w = &engine->whitelist; 1735 1736 if (engine->class != RENDER_CLASS) 1737 return; 1738 1739 gen9_whitelist_build(w); 1740 1741 /* WaDisableLSQCROPERFforOCL:skl */ 1742 whitelist_reg(w, GEN8_L3SQCREG4); 1743 } 1744 1745 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1746 { 1747 if (engine->class != RENDER_CLASS) 1748 return; 1749 1750 gen9_whitelist_build(&engine->whitelist); 1751 } 1752 1753 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1754 { 1755 struct i915_wa_list *w = &engine->whitelist; 1756 1757 if (engine->class != RENDER_CLASS) 1758 return; 1759 1760 gen9_whitelist_build(w); 1761 1762 /* WaDisableLSQCROPERFforOCL:kbl */ 1763 whitelist_reg(w, GEN8_L3SQCREG4); 1764 } 1765 1766 static void glk_whitelist_build(struct intel_engine_cs *engine) 1767 { 1768 struct i915_wa_list *w = &engine->whitelist; 1769 1770 if (engine->class != RENDER_CLASS) 1771 return; 1772 1773 gen9_whitelist_build(w); 1774 1775 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1776 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1777 } 1778 1779 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1780 { 1781 struct i915_wa_list *w = &engine->whitelist; 1782 1783 if (engine->class != RENDER_CLASS) 1784 return; 1785 1786 gen9_whitelist_build(w); 1787 1788 /* 1789 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1790 * 1791 * This covers 4 register which are next to one another : 1792 * - PS_INVOCATION_COUNT 1793 * - PS_INVOCATION_COUNT_UDW 1794 * - PS_DEPTH_COUNT 1795 * - PS_DEPTH_COUNT_UDW 1796 */ 1797 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1798 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1799 RING_FORCE_TO_NONPRIV_RANGE_4); 1800 } 1801 1802 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1803 { 1804 struct i915_wa_list *w = &engine->whitelist; 1805 1806 if (engine->class != RENDER_CLASS) 1807 whitelist_reg_ext(w, 1808 RING_CTX_TIMESTAMP(engine->mmio_base), 1809 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1810 } 1811 1812 static void cml_whitelist_build(struct intel_engine_cs *engine) 1813 { 1814 allow_read_ctx_timestamp(engine); 1815 1816 cfl_whitelist_build(engine); 1817 } 1818 1819 static void icl_whitelist_build(struct intel_engine_cs *engine) 1820 { 1821 struct i915_wa_list *w = &engine->whitelist; 1822 1823 allow_read_ctx_timestamp(engine); 1824 1825 switch (engine->class) { 1826 case RENDER_CLASS: 1827 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1828 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1829 1830 /* WaAllowUMDToModifySamplerMode:icl */ 1831 whitelist_reg(w, GEN10_SAMPLER_MODE); 1832 1833 /* WaEnableStateCacheRedirectToCS:icl */ 1834 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1835 1836 /* 1837 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1838 * 1839 * This covers 4 register which are next to one another : 1840 * - PS_INVOCATION_COUNT 1841 * - PS_INVOCATION_COUNT_UDW 1842 * - PS_DEPTH_COUNT 1843 * - PS_DEPTH_COUNT_UDW 1844 */ 1845 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1846 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1847 RING_FORCE_TO_NONPRIV_RANGE_4); 1848 break; 1849 1850 case VIDEO_DECODE_CLASS: 1851 /* hucStatusRegOffset */ 1852 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1853 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1854 /* hucUKernelHdrInfoRegOffset */ 1855 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1856 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1857 /* hucStatus2RegOffset */ 1858 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1859 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1860 break; 1861 1862 default: 1863 break; 1864 } 1865 } 1866 1867 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1868 { 1869 struct i915_wa_list *w = &engine->whitelist; 1870 1871 allow_read_ctx_timestamp(engine); 1872 1873 switch (engine->class) { 1874 case RENDER_CLASS: 1875 /* 1876 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1877 * Wa_1408556865:tgl 1878 * 1879 * This covers 4 registers which are next to one another : 1880 * - PS_INVOCATION_COUNT 1881 * - PS_INVOCATION_COUNT_UDW 1882 * - PS_DEPTH_COUNT 1883 * - PS_DEPTH_COUNT_UDW 1884 */ 1885 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1886 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1887 RING_FORCE_TO_NONPRIV_RANGE_4); 1888 1889 /* 1890 * Wa_1808121037:tgl 1891 * Wa_14012131227:dg1 1892 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 1893 */ 1894 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1895 1896 /* Wa_1806527549:tgl */ 1897 whitelist_reg(w, HIZ_CHICKEN); 1898 break; 1899 default: 1900 break; 1901 } 1902 } 1903 1904 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1905 { 1906 struct i915_wa_list *w = &engine->whitelist; 1907 1908 tgl_whitelist_build(engine); 1909 1910 /* GEN:BUG:1409280441:dg1 */ 1911 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 1912 (engine->class == RENDER_CLASS || 1913 engine->class == COPY_ENGINE_CLASS)) 1914 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1915 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1916 } 1917 1918 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 1919 { 1920 allow_read_ctx_timestamp(engine); 1921 } 1922 1923 static void dg2_whitelist_build(struct intel_engine_cs *engine) 1924 { 1925 struct i915_wa_list *w = &engine->whitelist; 1926 1927 allow_read_ctx_timestamp(engine); 1928 1929 switch (engine->class) { 1930 case RENDER_CLASS: 1931 /* 1932 * Wa_1507100340:dg2_g10 1933 * 1934 * This covers 4 registers which are next to one another : 1935 * - PS_INVOCATION_COUNT 1936 * - PS_INVOCATION_COUNT_UDW 1937 * - PS_DEPTH_COUNT 1938 * - PS_DEPTH_COUNT_UDW 1939 */ 1940 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 1941 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1942 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1943 RING_FORCE_TO_NONPRIV_RANGE_4); 1944 1945 break; 1946 default: 1947 break; 1948 } 1949 } 1950 1951 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1952 { 1953 struct drm_i915_private *i915 = engine->i915; 1954 struct i915_wa_list *w = &engine->whitelist; 1955 1956 wa_init_start(w, "whitelist", engine->name); 1957 1958 if (IS_DG2(i915)) 1959 dg2_whitelist_build(engine); 1960 else if (IS_XEHPSDV(i915)) 1961 xehpsdv_whitelist_build(engine); 1962 else if (IS_DG1(i915)) 1963 dg1_whitelist_build(engine); 1964 else if (GRAPHICS_VER(i915) == 12) 1965 tgl_whitelist_build(engine); 1966 else if (GRAPHICS_VER(i915) == 11) 1967 icl_whitelist_build(engine); 1968 else if (IS_COMETLAKE(i915)) 1969 cml_whitelist_build(engine); 1970 else if (IS_COFFEELAKE(i915)) 1971 cfl_whitelist_build(engine); 1972 else if (IS_GEMINILAKE(i915)) 1973 glk_whitelist_build(engine); 1974 else if (IS_KABYLAKE(i915)) 1975 kbl_whitelist_build(engine); 1976 else if (IS_BROXTON(i915)) 1977 bxt_whitelist_build(engine); 1978 else if (IS_SKYLAKE(i915)) 1979 skl_whitelist_build(engine); 1980 else if (GRAPHICS_VER(i915) <= 8) 1981 ; 1982 else 1983 MISSING_CASE(GRAPHICS_VER(i915)); 1984 1985 wa_init_finish(w); 1986 } 1987 1988 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1989 { 1990 const struct i915_wa_list *wal = &engine->whitelist; 1991 struct intel_uncore *uncore = engine->uncore; 1992 const u32 base = engine->mmio_base; 1993 struct i915_wa *wa; 1994 unsigned int i; 1995 1996 if (!wal->count) 1997 return; 1998 1999 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2000 intel_uncore_write(uncore, 2001 RING_FORCE_TO_NONPRIV(base, i), 2002 i915_mmio_reg_offset(wa->reg)); 2003 2004 /* And clear the rest just in case of garbage */ 2005 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2006 intel_uncore_write(uncore, 2007 RING_FORCE_TO_NONPRIV(base, i), 2008 i915_mmio_reg_offset(RING_NOPID(base))); 2009 } 2010 2011 /* 2012 * engine_fake_wa_init(), a place holder to program the registers 2013 * which are not part of an official workaround defined by the 2014 * hardware team. 2015 * Adding programming of those register inside workaround will 2016 * allow utilizing wa framework to proper application and verification. 2017 */ 2018 static void 2019 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2020 { 2021 u8 mocs; 2022 2023 /* 2024 * RING_CMD_CCTL are need to be programed to un-cached 2025 * for memory writes and reads outputted by Command 2026 * Streamers on Gen12 onward platforms. 2027 */ 2028 if (GRAPHICS_VER(engine->i915) >= 12) { 2029 mocs = engine->gt->mocs.uc_index; 2030 wa_masked_field_set(wal, 2031 RING_CMD_CCTL(engine->mmio_base), 2032 CMD_CCTL_MOCS_MASK, 2033 CMD_CCTL_MOCS_OVERRIDE(mocs, mocs)); 2034 } 2035 } 2036 2037 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2038 { 2039 u64 dss_mask = intel_sseu_get_subslices(&engine->gt->info.sseu, 0); 2040 2041 return (dss_mask & GENMASK(GEN_DSS_PER_GSLICE - 1, 0)) == 0; 2042 } 2043 2044 static void 2045 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2046 { 2047 struct drm_i915_private *i915 = engine->i915; 2048 2049 if (IS_DG2(i915)) { 2050 /* Wa_14015227452:dg2 */ 2051 wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2052 } 2053 2054 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2055 /* Wa_14013392000:dg2_g11 */ 2056 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2057 2058 /* Wa_16011620976:dg2_g11 */ 2059 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2060 } 2061 2062 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2063 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2064 /* Wa_14012419201:dg2 */ 2065 wa_masked_en(wal, GEN9_ROW_CHICKEN4, 2066 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2067 } 2068 2069 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2070 IS_DG2_G11(i915)) { 2071 /* 2072 * Wa_22012826095:dg2 2073 * Wa_22013059131:dg2 2074 */ 2075 wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2076 MAXREQS_PER_BANK, 2077 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2078 2079 /* Wa_22013059131:dg2 */ 2080 wa_write_or(wal, LSC_CHICKEN_BIT_0, 2081 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2082 } 2083 2084 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2085 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2086 needs_wa_1308578152(engine)) { 2087 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2088 GEN12_REPLAY_MODE_GRANULARITY); 2089 } 2090 2091 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2092 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2093 /* Wa_22013037850:dg2 */ 2094 wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2095 DISABLE_128B_EVICTION_COMMAND_UDW); 2096 2097 /* Wa_22012856258:dg2 */ 2098 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2099 GEN12_DISABLE_READ_SUPPRESSION); 2100 2101 /* 2102 * Wa_22010960976:dg2 2103 * Wa_14013347512:dg2 2104 */ 2105 wa_masked_dis(wal, GEN12_HDC_CHICKEN0, 2106 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2107 } 2108 2109 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2110 /* 2111 * Wa_1608949956:dg2_g10 2112 * Wa_14010198302:dg2_g10 2113 */ 2114 wa_masked_en(wal, GEN8_ROW_CHICKEN, 2115 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2116 2117 /* 2118 * Wa_14010918519:dg2_g10 2119 * 2120 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2121 * so ignoring verification. 2122 */ 2123 wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2124 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2125 0, false); 2126 } 2127 2128 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2129 /* Wa_22010430635:dg2 */ 2130 wa_masked_en(wal, 2131 GEN9_ROW_CHICKEN4, 2132 GEN12_DISABLE_GRF_CLEAR); 2133 2134 /* Wa_14010648519:dg2 */ 2135 wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2136 } 2137 2138 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || 2139 IS_DG2_G11(i915)) { 2140 /* Wa_22012654132:dg2 */ 2141 wa_add(wal, GEN10_CACHE_MODE_SS, 0, 2142 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2143 0 /* write-only, so skip validation */, 2144 true); 2145 } 2146 2147 /* Wa_14013202645:dg2 */ 2148 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2149 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2150 wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2151 2152 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2153 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2154 /* 2155 * Wa_1607138336:tgl[a0],dg1[a0] 2156 * Wa_1607063988:tgl[a0],dg1[a0] 2157 */ 2158 wa_write_or(wal, 2159 GEN9_CTX_PREEMPT_REG, 2160 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2161 } 2162 2163 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2164 /* 2165 * Wa_1606679103:tgl 2166 * (see also Wa_1606682166:icl) 2167 */ 2168 wa_write_or(wal, 2169 GEN7_SARCHKMD, 2170 GEN7_DISABLE_SAMPLER_PREFETCH); 2171 } 2172 2173 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2174 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2175 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2176 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2177 2178 /* 2179 * Wa_1407928979:tgl A* 2180 * Wa_18011464164:tgl[B0+],dg1[B0+] 2181 * Wa_22010931296:tgl[B0+],dg1[B0+] 2182 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2183 */ 2184 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2185 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2186 2187 /* 2188 * Wa_1606700617:tgl,dg1,adl-p 2189 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2190 * Wa_14010826681:tgl,dg1,rkl,adl-p 2191 */ 2192 wa_masked_en(wal, 2193 GEN9_CS_DEBUG_MODE1, 2194 FF_DOP_CLOCK_GATE_DISABLE); 2195 } 2196 2197 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2198 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2199 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2200 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2201 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 2202 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2203 2204 /* 2205 * Wa_1409085225:tgl 2206 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2207 */ 2208 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2209 } 2210 2211 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2212 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2213 /* 2214 * Wa_1607030317:tgl 2215 * Wa_1607186500:tgl 2216 * Wa_1607297627:tgl,rkl,dg1[a0] 2217 * 2218 * On TGL and RKL there are multiple entries for this WA in the 2219 * BSpec; some indicate this is an A0-only WA, others indicate 2220 * it applies to all steppings so we trust the "all steppings." 2221 * For DG1 this only applies to A0. 2222 */ 2223 wa_masked_en(wal, 2224 RING_PSMI_CTL(RENDER_RING_BASE), 2225 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2226 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2227 } 2228 2229 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2230 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2231 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2232 wa_masked_en(wal, 2233 GEN10_SAMPLER_MODE, 2234 ENABLE_SMALLPL); 2235 } 2236 2237 if (GRAPHICS_VER(i915) == 11) { 2238 /* This is not an Wa. Enable for better image quality */ 2239 wa_masked_en(wal, 2240 _3D_CHICKEN3, 2241 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2242 2243 /* 2244 * Wa_1405543622:icl 2245 * Formerly known as WaGAPZPriorityScheme 2246 */ 2247 wa_write_or(wal, 2248 GEN8_GARBCNTL, 2249 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2250 2251 /* 2252 * Wa_1604223664:icl 2253 * Formerly known as WaL3BankAddressHashing 2254 */ 2255 wa_write_clr_set(wal, 2256 GEN8_GARBCNTL, 2257 GEN11_HASH_CTRL_EXCL_MASK, 2258 GEN11_HASH_CTRL_EXCL_BIT0); 2259 wa_write_clr_set(wal, 2260 GEN11_GLBLINVL, 2261 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2262 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2263 2264 /* 2265 * Wa_1405733216:icl 2266 * Formerly known as WaDisableCleanEvicts 2267 */ 2268 wa_write_or(wal, 2269 GEN8_L3SQCREG4, 2270 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2271 2272 /* Wa_1606682166:icl */ 2273 wa_write_or(wal, 2274 GEN7_SARCHKMD, 2275 GEN7_DISABLE_SAMPLER_PREFETCH); 2276 2277 /* Wa_1409178092:icl */ 2278 wa_write_clr_set(wal, 2279 GEN11_SCRATCH2, 2280 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2281 0); 2282 2283 /* WaEnable32PlaneMode:icl */ 2284 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2285 GEN11_ENABLE_32_PLANE_MODE); 2286 2287 /* 2288 * Wa_1408615072:icl,ehl (vsunit) 2289 * Wa_1407596294:icl,ehl (hsunit) 2290 */ 2291 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2292 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2293 2294 /* 2295 * Wa_1408767742:icl[a2..forever],ehl[all] 2296 * Wa_1605460711:icl[a0..c0] 2297 */ 2298 wa_write_or(wal, 2299 GEN7_FF_THREAD_MODE, 2300 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2301 2302 /* Wa_22010271021 */ 2303 wa_masked_en(wal, 2304 GEN9_CS_DEBUG_MODE1, 2305 FF_DOP_CLOCK_GATE_DISABLE); 2306 } 2307 2308 if (IS_GRAPHICS_VER(i915, 9, 12)) { 2309 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 2310 wa_masked_en(wal, 2311 GEN7_FF_SLICE_CS_CHICKEN1, 2312 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2313 } 2314 2315 if (IS_SKYLAKE(i915) || 2316 IS_KABYLAKE(i915) || 2317 IS_COFFEELAKE(i915) || 2318 IS_COMETLAKE(i915)) { 2319 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2320 wa_write_or(wal, 2321 GEN8_GARBCNTL, 2322 GEN9_GAPS_TSV_CREDIT_DISABLE); 2323 } 2324 2325 if (IS_BROXTON(i915)) { 2326 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2327 wa_masked_en(wal, 2328 FF_SLICE_CS_CHICKEN2, 2329 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2330 } 2331 2332 if (GRAPHICS_VER(i915) == 9) { 2333 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2334 wa_masked_en(wal, 2335 GEN9_CSFE_CHICKEN1_RCS, 2336 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2337 2338 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2339 wa_write_or(wal, 2340 BDW_SCRATCH1, 2341 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2342 2343 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2344 if (IS_GEN9_LP(i915)) 2345 wa_write_clr_set(wal, 2346 GEN8_L3SQCREG1, 2347 L3_PRIO_CREDITS_MASK, 2348 L3_GENERAL_PRIO_CREDITS(62) | 2349 L3_HIGH_PRIO_CREDITS(2)); 2350 2351 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2352 wa_write_or(wal, 2353 GEN8_L3SQCREG4, 2354 GEN8_LQSC_FLUSH_COHERENT_LINES); 2355 2356 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2357 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2358 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2359 wa_write_clr_set(wal, GEN8_L3SQCREG4, 2360 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2361 wa_write_clr_set(wal, GEN9_SCRATCH1, 2362 EVICTION_PERF_FIX_ENABLE, 0); 2363 } 2364 2365 if (IS_HASWELL(i915)) { 2366 /* WaSampleCChickenBitEnable:hsw */ 2367 wa_masked_en(wal, 2368 HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2369 2370 wa_masked_dis(wal, 2371 CACHE_MODE_0_GEN7, 2372 /* enable HiZ Raw Stall Optimization */ 2373 HIZ_RAW_STALL_OPT_DISABLE); 2374 } 2375 2376 if (IS_VALLEYVIEW(i915)) { 2377 /* WaDisableEarlyCull:vlv */ 2378 wa_masked_en(wal, 2379 _3D_CHICKEN3, 2380 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2381 2382 /* 2383 * WaVSThreadDispatchOverride:ivb,vlv 2384 * 2385 * This actually overrides the dispatch 2386 * mode for all thread types. 2387 */ 2388 wa_write_clr_set(wal, 2389 GEN7_FF_THREAD_MODE, 2390 GEN7_FF_SCHED_MASK, 2391 GEN7_FF_TS_SCHED_HW | 2392 GEN7_FF_VS_SCHED_HW | 2393 GEN7_FF_DS_SCHED_HW); 2394 2395 /* WaPsdDispatchEnable:vlv */ 2396 /* WaDisablePSDDualDispatchEnable:vlv */ 2397 wa_masked_en(wal, 2398 GEN7_HALF_SLICE_CHICKEN1, 2399 GEN7_MAX_PS_THREAD_DEP | 2400 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2401 } 2402 2403 if (IS_IVYBRIDGE(i915)) { 2404 /* WaDisableEarlyCull:ivb */ 2405 wa_masked_en(wal, 2406 _3D_CHICKEN3, 2407 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2408 2409 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2410 /* enable HiZ Raw Stall Optimization */ 2411 wa_masked_dis(wal, 2412 CACHE_MODE_0_GEN7, 2413 HIZ_RAW_STALL_OPT_DISABLE); 2414 } 2415 2416 /* 2417 * WaVSThreadDispatchOverride:ivb,vlv 2418 * 2419 * This actually overrides the dispatch 2420 * mode for all thread types. 2421 */ 2422 wa_write_clr_set(wal, 2423 GEN7_FF_THREAD_MODE, 2424 GEN7_FF_SCHED_MASK, 2425 GEN7_FF_TS_SCHED_HW | 2426 GEN7_FF_VS_SCHED_HW | 2427 GEN7_FF_DS_SCHED_HW); 2428 2429 /* WaDisablePSDDualDispatchEnable:ivb */ 2430 if (IS_IVB_GT1(i915)) 2431 wa_masked_en(wal, 2432 GEN7_HALF_SLICE_CHICKEN1, 2433 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2434 } 2435 2436 if (GRAPHICS_VER(i915) == 7) { 2437 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2438 wa_masked_en(wal, 2439 RING_MODE_GEN7(RENDER_RING_BASE), 2440 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2441 2442 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2443 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2444 2445 /* 2446 * BSpec says this must be set, even though 2447 * WaDisable4x2SubspanOptimization:ivb,hsw 2448 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2449 */ 2450 wa_masked_en(wal, 2451 CACHE_MODE_1, 2452 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2453 2454 /* 2455 * BSpec recommends 8x4 when MSAA is used, 2456 * however in practice 16x4 seems fastest. 2457 * 2458 * Note that PS/WM thread counts depend on the WIZ hashing 2459 * disable bit, which we don't touch here, but it's good 2460 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2461 */ 2462 wa_masked_field_set(wal, 2463 GEN7_GT_MODE, 2464 GEN6_WIZ_HASHING_MASK, 2465 GEN6_WIZ_HASHING_16x4); 2466 } 2467 2468 if (IS_GRAPHICS_VER(i915, 6, 7)) 2469 /* 2470 * We need to disable the AsyncFlip performance optimisations in 2471 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2472 * already be programmed to '1' on all products. 2473 * 2474 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2475 */ 2476 wa_masked_en(wal, 2477 RING_MI_MODE(RENDER_RING_BASE), 2478 ASYNC_FLIP_PERF_DISABLE); 2479 2480 if (GRAPHICS_VER(i915) == 6) { 2481 /* 2482 * Required for the hardware to program scanline values for 2483 * waiting 2484 * WaEnableFlushTlbInvalidationMode:snb 2485 */ 2486 wa_masked_en(wal, 2487 GFX_MODE, 2488 GFX_TLB_INVALIDATE_EXPLICIT); 2489 2490 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2491 wa_masked_en(wal, 2492 _3D_CHICKEN, 2493 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2494 2495 wa_masked_en(wal, 2496 _3D_CHICKEN3, 2497 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2498 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2499 /* 2500 * Bspec says: 2501 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2502 * to normal and 3DSTATE_SF number of SF output attributes 2503 * is more than 16." 2504 */ 2505 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2506 2507 /* 2508 * BSpec recommends 8x4 when MSAA is used, 2509 * however in practice 16x4 seems fastest. 2510 * 2511 * Note that PS/WM thread counts depend on the WIZ hashing 2512 * disable bit, which we don't touch here, but it's good 2513 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2514 */ 2515 wa_masked_field_set(wal, 2516 GEN6_GT_MODE, 2517 GEN6_WIZ_HASHING_MASK, 2518 GEN6_WIZ_HASHING_16x4); 2519 2520 /* WaDisable_RenderCache_OperationalFlush:snb */ 2521 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2522 2523 /* 2524 * From the Sandybridge PRM, volume 1 part 3, page 24: 2525 * "If this bit is set, STCunit will have LRA as replacement 2526 * policy. [...] This bit must be reset. LRA replacement 2527 * policy is not supported." 2528 */ 2529 wa_masked_dis(wal, 2530 CACHE_MODE_0, 2531 CM0_STC_EVICT_DISABLE_LRA_SNB); 2532 } 2533 2534 if (IS_GRAPHICS_VER(i915, 4, 6)) 2535 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2536 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2537 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2538 /* XXX bit doesn't stick on Broadwater */ 2539 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2540 2541 if (GRAPHICS_VER(i915) == 4) 2542 /* 2543 * Disable CONSTANT_BUFFER before it is loaded from the context 2544 * image. For as it is loaded, it is executed and the stored 2545 * address may no longer be valid, leading to a GPU hang. 2546 * 2547 * This imposes the requirement that userspace reload their 2548 * CONSTANT_BUFFER on every batch, fortunately a requirement 2549 * they are already accustomed to from before contexts were 2550 * enabled. 2551 */ 2552 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2553 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2554 0 /* XXX bit doesn't stick on Broadwater */, 2555 true); 2556 } 2557 2558 static void 2559 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2560 { 2561 struct drm_i915_private *i915 = engine->i915; 2562 2563 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2564 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2565 wa_write(wal, 2566 RING_SEMA_WAIT_POLL(engine->mmio_base), 2567 1); 2568 } 2569 } 2570 2571 static void 2572 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2573 { 2574 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 2575 return; 2576 2577 engine_fake_wa_init(engine, wal); 2578 2579 if (engine->class == RENDER_CLASS) 2580 rcs_engine_wa_init(engine, wal); 2581 else 2582 xcs_engine_wa_init(engine, wal); 2583 } 2584 2585 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2586 { 2587 struct i915_wa_list *wal = &engine->wa_list; 2588 2589 if (GRAPHICS_VER(engine->i915) < 4) 2590 return; 2591 2592 wa_init_start(wal, "engine", engine->name); 2593 engine_init_workarounds(engine, wal); 2594 wa_init_finish(wal); 2595 } 2596 2597 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2598 { 2599 wa_list_apply(engine->gt, &engine->wa_list); 2600 } 2601 2602 static const struct i915_range mcr_ranges_gen8[] = { 2603 { .start = 0x5500, .end = 0x55ff }, 2604 { .start = 0x7000, .end = 0x7fff }, 2605 { .start = 0x9400, .end = 0x97ff }, 2606 { .start = 0xb000, .end = 0xb3ff }, 2607 { .start = 0xe000, .end = 0xe7ff }, 2608 {}, 2609 }; 2610 2611 static const struct i915_range mcr_ranges_gen12[] = { 2612 { .start = 0x8150, .end = 0x815f }, 2613 { .start = 0x9520, .end = 0x955f }, 2614 { .start = 0xb100, .end = 0xb3ff }, 2615 { .start = 0xde80, .end = 0xe8ff }, 2616 { .start = 0x24a00, .end = 0x24a7f }, 2617 {}, 2618 }; 2619 2620 static const struct i915_range mcr_ranges_xehp[] = { 2621 { .start = 0x4000, .end = 0x4aff }, 2622 { .start = 0x5200, .end = 0x52ff }, 2623 { .start = 0x5400, .end = 0x7fff }, 2624 { .start = 0x8140, .end = 0x815f }, 2625 { .start = 0x8c80, .end = 0x8dff }, 2626 { .start = 0x94d0, .end = 0x955f }, 2627 { .start = 0x9680, .end = 0x96ff }, 2628 { .start = 0xb000, .end = 0xb3ff }, 2629 { .start = 0xc800, .end = 0xcfff }, 2630 { .start = 0xd800, .end = 0xd8ff }, 2631 { .start = 0xdc00, .end = 0xffff }, 2632 { .start = 0x17000, .end = 0x17fff }, 2633 { .start = 0x24a00, .end = 0x24a7f }, 2634 {}, 2635 }; 2636 2637 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2638 { 2639 const struct i915_range *mcr_ranges; 2640 int i; 2641 2642 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 2643 mcr_ranges = mcr_ranges_xehp; 2644 else if (GRAPHICS_VER(i915) >= 12) 2645 mcr_ranges = mcr_ranges_gen12; 2646 else if (GRAPHICS_VER(i915) >= 8) 2647 mcr_ranges = mcr_ranges_gen8; 2648 else 2649 return false; 2650 2651 /* 2652 * Registers in these ranges are affected by the MCR selector 2653 * which only controls CPU initiated MMIO. Routing does not 2654 * work for CS access so we cannot verify them on this path. 2655 */ 2656 for (i = 0; mcr_ranges[i].start; i++) 2657 if (offset >= mcr_ranges[i].start && 2658 offset <= mcr_ranges[i].end) 2659 return true; 2660 2661 return false; 2662 } 2663 2664 static int 2665 wa_list_srm(struct i915_request *rq, 2666 const struct i915_wa_list *wal, 2667 struct i915_vma *vma) 2668 { 2669 struct drm_i915_private *i915 = rq->engine->i915; 2670 unsigned int i, count = 0; 2671 const struct i915_wa *wa; 2672 u32 srm, *cs; 2673 2674 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2675 if (GRAPHICS_VER(i915) >= 8) 2676 srm++; 2677 2678 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2679 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2680 count++; 2681 } 2682 2683 cs = intel_ring_begin(rq, 4 * count); 2684 if (IS_ERR(cs)) 2685 return PTR_ERR(cs); 2686 2687 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2688 u32 offset = i915_mmio_reg_offset(wa->reg); 2689 2690 if (mcr_range(i915, offset)) 2691 continue; 2692 2693 *cs++ = srm; 2694 *cs++ = offset; 2695 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2696 *cs++ = 0; 2697 } 2698 intel_ring_advance(rq, cs); 2699 2700 return 0; 2701 } 2702 2703 static int engine_wa_list_verify(struct intel_context *ce, 2704 const struct i915_wa_list * const wal, 2705 const char *from) 2706 { 2707 const struct i915_wa *wa; 2708 struct i915_request *rq; 2709 struct i915_vma *vma; 2710 struct i915_gem_ww_ctx ww; 2711 unsigned int i; 2712 u32 *results; 2713 int err; 2714 2715 if (!wal->count) 2716 return 0; 2717 2718 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 2719 wal->count * sizeof(u32)); 2720 if (IS_ERR(vma)) 2721 return PTR_ERR(vma); 2722 2723 intel_engine_pm_get(ce->engine); 2724 i915_gem_ww_ctx_init(&ww, false); 2725 retry: 2726 err = i915_gem_object_lock(vma->obj, &ww); 2727 if (err == 0) 2728 err = intel_context_pin_ww(ce, &ww); 2729 if (err) 2730 goto err_pm; 2731 2732 err = i915_vma_pin_ww(vma, &ww, 0, 0, 2733 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2734 if (err) 2735 goto err_unpin; 2736 2737 rq = i915_request_create(ce); 2738 if (IS_ERR(rq)) { 2739 err = PTR_ERR(rq); 2740 goto err_vma; 2741 } 2742 2743 err = i915_request_await_object(rq, vma->obj, true); 2744 if (err == 0) 2745 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2746 if (err == 0) 2747 err = wa_list_srm(rq, wal, vma); 2748 2749 i915_request_get(rq); 2750 if (err) 2751 i915_request_set_error_once(rq, err); 2752 i915_request_add(rq); 2753 2754 if (err) 2755 goto err_rq; 2756 2757 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2758 err = -ETIME; 2759 goto err_rq; 2760 } 2761 2762 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2763 if (IS_ERR(results)) { 2764 err = PTR_ERR(results); 2765 goto err_rq; 2766 } 2767 2768 err = 0; 2769 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2770 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2771 continue; 2772 2773 if (!wa_verify(wa, results[i], wal->name, from)) 2774 err = -ENXIO; 2775 } 2776 2777 i915_gem_object_unpin_map(vma->obj); 2778 2779 err_rq: 2780 i915_request_put(rq); 2781 err_vma: 2782 i915_vma_unpin(vma); 2783 err_unpin: 2784 intel_context_unpin(ce); 2785 err_pm: 2786 if (err == -EDEADLK) { 2787 err = i915_gem_ww_ctx_backoff(&ww); 2788 if (!err) 2789 goto retry; 2790 } 2791 i915_gem_ww_ctx_fini(&ww); 2792 intel_engine_pm_put(ce->engine); 2793 i915_vma_put(vma); 2794 return err; 2795 } 2796 2797 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2798 const char *from) 2799 { 2800 return engine_wa_list_verify(engine->kernel_context, 2801 &engine->wa_list, 2802 from); 2803 } 2804 2805 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2806 #include "selftest_workarounds.c" 2807 #endif 2808