1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_engine_regs.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_gt_mcr.h" 13 #include "intel_gt_regs.h" 14 #include "intel_ring.h" 15 #include "intel_workarounds.h" 16 17 /** 18 * DOC: Hardware workarounds 19 * 20 * Hardware workarounds are register programming documented to be executed in 21 * the driver that fall outside of the normal programming sequences for a 22 * platform. There are some basic categories of workarounds, depending on 23 * how/when they are applied: 24 * 25 * - Context workarounds: workarounds that touch registers that are 26 * saved/restored to/from the HW context image. The list is emitted (via Load 27 * Register Immediate commands) once when initializing the device and saved in 28 * the default context. That default context is then used on every context 29 * creation to have a "primed golden context", i.e. a context image that 30 * already contains the changes needed to all the registers. 31 * 32 * - Engine workarounds: the list of these WAs is applied whenever the specific 33 * engine is reset. It's also possible that a set of engine classes share a 34 * common power domain and they are reset together. This happens on some 35 * platforms with render and compute engines. In this case (at least) one of 36 * them need to keeep the workaround programming: the approach taken in the 37 * driver is to tie those workarounds to the first compute/render engine that 38 * is registered. When executing with GuC submission, engine resets are 39 * outside of kernel driver control, hence the list of registers involved in 40 * written once, on engine initialization, and then passed to GuC, that 41 * saves/restores their values before/after the reset takes place. See 42 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 43 * 44 * - GT workarounds: the list of these WAs is applied whenever these registers 45 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 46 * 47 * - Register whitelist: some workarounds need to be implemented in userspace, 48 * but need to touch privileged registers. The whitelist in the kernel 49 * instructs the hardware to allow the access to happen. From the kernel side, 50 * this is just a special case of a MMIO workaround (as we write the list of 51 * these to/be-whitelisted registers to some special HW registers). 52 * 53 * - Workaround batchbuffers: buffers that get executed automatically by the 54 * hardware on every HW context restore. These buffers are created and 55 * programmed in the default context so the hardware always go through those 56 * programming sequences when switching contexts. The support for workaround 57 * batchbuffers is enabled these hardware mechanisms: 58 * 59 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 60 * context, pointing the hardware to jump to that location when that offset 61 * is reached in the context restore. Workaround batchbuffer in the driver 62 * currently uses this mechanism for all platforms. 63 * 64 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 65 * pointing the hardware to a buffer to continue executing after the 66 * engine registers are restored in a context restore sequence. This is 67 * currently not used in the driver. 68 * 69 * - Other: There are WAs that, due to their nature, cannot be applied from a 70 * central place. Those are peppered around the rest of the code, as needed. 71 * Workarounds related to the display IP are the main example. 72 * 73 * .. [1] Technically, some registers are powercontext saved & restored, so they 74 * survive a suspend/resume. In practice, writing them again is not too 75 * costly and simplifies things, so it's the approach taken in the driver. 76 */ 77 78 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 79 const char *name, const char *engine_name) 80 { 81 wal->gt = gt; 82 wal->name = name; 83 wal->engine_name = engine_name; 84 } 85 86 #define WA_LIST_CHUNK (1 << 4) 87 88 static void wa_init_finish(struct i915_wa_list *wal) 89 { 90 /* Trim unused entries. */ 91 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 92 struct i915_wa *list = kmemdup(wal->list, 93 wal->count * sizeof(*list), 94 GFP_KERNEL); 95 96 if (list) { 97 kfree(wal->list); 98 wal->list = list; 99 } 100 } 101 102 if (!wal->count) 103 return; 104 105 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 106 wal->wa_count, wal->name, wal->engine_name); 107 } 108 109 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 110 { 111 unsigned int addr = i915_mmio_reg_offset(wa->reg); 112 struct drm_i915_private *i915 = wal->gt->i915; 113 unsigned int start = 0, end = wal->count; 114 const unsigned int grow = WA_LIST_CHUNK; 115 struct i915_wa *wa_; 116 117 GEM_BUG_ON(!is_power_of_2(grow)); 118 119 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 120 struct i915_wa *list; 121 122 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 123 GFP_KERNEL); 124 if (!list) { 125 drm_err(&i915->drm, "No space for workaround init!\n"); 126 return; 127 } 128 129 if (wal->list) { 130 memcpy(list, wal->list, sizeof(*wa) * wal->count); 131 kfree(wal->list); 132 } 133 134 wal->list = list; 135 } 136 137 while (start < end) { 138 unsigned int mid = start + (end - start) / 2; 139 140 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 141 start = mid + 1; 142 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 143 end = mid; 144 } else { 145 wa_ = &wal->list[mid]; 146 147 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 148 drm_err(&i915->drm, 149 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 150 i915_mmio_reg_offset(wa_->reg), 151 wa_->clr, wa_->set); 152 153 wa_->set &= ~wa->clr; 154 } 155 156 wal->wa_count++; 157 wa_->set |= wa->set; 158 wa_->clr |= wa->clr; 159 wa_->read |= wa->read; 160 return; 161 } 162 } 163 164 wal->wa_count++; 165 wa_ = &wal->list[wal->count++]; 166 *wa_ = *wa; 167 168 while (wa_-- > wal->list) { 169 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 170 i915_mmio_reg_offset(wa_[1].reg)); 171 if (i915_mmio_reg_offset(wa_[1].reg) > 172 i915_mmio_reg_offset(wa_[0].reg)) 173 break; 174 175 swap(wa_[1], wa_[0]); 176 } 177 } 178 179 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 180 u32 clear, u32 set, u32 read_mask, bool masked_reg) 181 { 182 struct i915_wa wa = { 183 .reg = reg, 184 .clr = clear, 185 .set = set, 186 .read = read_mask, 187 .masked_reg = masked_reg, 188 }; 189 190 _wa_add(wal, &wa); 191 } 192 193 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 194 u32 clear, u32 set, u32 read_mask, bool masked_reg) 195 { 196 struct i915_wa wa = { 197 .mcr_reg = reg, 198 .clr = clear, 199 .set = set, 200 .read = read_mask, 201 .masked_reg = masked_reg, 202 .is_mcr = 1, 203 }; 204 205 _wa_add(wal, &wa); 206 } 207 208 static void 209 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 210 { 211 wa_add(wal, reg, clear, set, clear, false); 212 } 213 214 static void 215 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 216 { 217 wa_mcr_add(wal, reg, clear, set, clear, false); 218 } 219 220 static void 221 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 222 { 223 wa_write_clr_set(wal, reg, ~0, set); 224 } 225 226 static void 227 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 228 { 229 wa_write_clr_set(wal, reg, set, set); 230 } 231 232 static void 233 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 234 { 235 wa_mcr_write_clr_set(wal, reg, set, set); 236 } 237 238 static void 239 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 240 { 241 wa_write_clr_set(wal, reg, clr, 0); 242 } 243 244 static void 245 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 246 { 247 wa_mcr_write_clr_set(wal, reg, clr, 0); 248 } 249 250 /* 251 * WA operations on "masked register". A masked register has the upper 16 bits 252 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 253 * portion of the register without a rmw: you simply write in the upper 16 bits 254 * the mask of bits you are going to modify. 255 * 256 * The wa_masked_* family of functions already does the necessary operations to 257 * calculate the mask based on the parameters passed, so user only has to 258 * provide the lower 16 bits of that register. 259 */ 260 261 static void 262 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 263 { 264 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 265 } 266 267 static void 268 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 269 { 270 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 271 } 272 273 static void 274 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 275 { 276 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 277 } 278 279 static void 280 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 281 { 282 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 283 } 284 285 static void 286 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 287 u32 mask, u32 val) 288 { 289 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 290 } 291 292 static void 293 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 294 u32 mask, u32 val) 295 { 296 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 297 } 298 299 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 300 struct i915_wa_list *wal) 301 { 302 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 303 } 304 305 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 306 struct i915_wa_list *wal) 307 { 308 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 309 } 310 311 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 312 struct i915_wa_list *wal) 313 { 314 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 315 316 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 317 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 318 319 /* WaDisablePartialInstShootdown:bdw,chv */ 320 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 321 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 322 323 /* Use Force Non-Coherent whenever executing a 3D context. This is a 324 * workaround for a possible hang in the unlikely event a TLB 325 * invalidation occurs during a PSD flush. 326 */ 327 /* WaForceEnableNonCoherent:bdw,chv */ 328 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 329 wa_masked_en(wal, HDC_CHICKEN0, 330 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 331 HDC_FORCE_NON_COHERENT); 332 333 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 334 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 335 * polygons in the same 8x4 pixel/sample area to be processed without 336 * stalling waiting for the earlier ones to write to Hierarchical Z 337 * buffer." 338 * 339 * This optimization is off by default for BDW and CHV; turn it on. 340 */ 341 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 342 343 /* Wa4x4STCOptimizationDisable:bdw,chv */ 344 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 345 346 /* 347 * BSpec recommends 8x4 when MSAA is used, 348 * however in practice 16x4 seems fastest. 349 * 350 * Note that PS/WM thread counts depend on the WIZ hashing 351 * disable bit, which we don't touch here, but it's good 352 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 353 */ 354 wa_masked_field_set(wal, GEN7_GT_MODE, 355 GEN6_WIZ_HASHING_MASK, 356 GEN6_WIZ_HASHING_16x4); 357 } 358 359 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 360 struct i915_wa_list *wal) 361 { 362 struct drm_i915_private *i915 = engine->i915; 363 364 gen8_ctx_workarounds_init(engine, wal); 365 366 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 367 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 368 369 /* WaDisableDopClockGating:bdw 370 * 371 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 372 * to disable EUTC clock gating. 373 */ 374 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 375 DOP_CLOCK_GATING_DISABLE); 376 377 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 378 GEN8_SAMPLER_POWER_BYPASS_DIS); 379 380 wa_masked_en(wal, HDC_CHICKEN0, 381 /* WaForceContextSaveRestoreNonCoherent:bdw */ 382 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 383 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 384 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 385 } 386 387 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 388 struct i915_wa_list *wal) 389 { 390 gen8_ctx_workarounds_init(engine, wal); 391 392 /* WaDisableThreadStallDopClockGating:chv */ 393 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 394 395 /* Improve HiZ throughput on CHV. */ 396 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 397 } 398 399 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 400 struct i915_wa_list *wal) 401 { 402 struct drm_i915_private *i915 = engine->i915; 403 404 if (HAS_LLC(i915)) { 405 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 406 * 407 * Must match Display Engine. See 408 * WaCompressedResourceDisplayNewHashMode. 409 */ 410 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 411 GEN9_PBE_COMPRESSED_HASH_SELECTION); 412 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 413 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 414 } 415 416 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 417 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 418 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 419 FLOW_CONTROL_ENABLE | 420 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 421 422 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 423 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 424 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 425 GEN9_ENABLE_YV12_BUGFIX | 426 GEN9_ENABLE_GPGPU_PREEMPTION); 427 428 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 429 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 430 wa_masked_en(wal, CACHE_MODE_1, 431 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 432 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 433 434 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 435 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 436 GEN9_CCS_TLB_PREFETCH_ENABLE); 437 438 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 439 wa_masked_en(wal, HDC_CHICKEN0, 440 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 441 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 442 443 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 444 * both tied to WaForceContextSaveRestoreNonCoherent 445 * in some hsds for skl. We keep the tie for all gen9. The 446 * documentation is a bit hazy and so we want to get common behaviour, 447 * even though there is no clear evidence we would need both on kbl/bxt. 448 * This area has been source of system hangs so we play it safe 449 * and mimic the skl regardless of what bspec says. 450 * 451 * Use Force Non-Coherent whenever executing a 3D context. This 452 * is a workaround for a possible hang in the unlikely event 453 * a TLB invalidation occurs during a PSD flush. 454 */ 455 456 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 457 wa_masked_en(wal, HDC_CHICKEN0, 458 HDC_FORCE_NON_COHERENT); 459 460 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 461 if (IS_SKYLAKE(i915) || 462 IS_KABYLAKE(i915) || 463 IS_COFFEELAKE(i915) || 464 IS_COMETLAKE(i915)) 465 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 466 GEN8_SAMPLER_POWER_BYPASS_DIS); 467 468 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 469 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 470 471 /* 472 * Supporting preemption with fine-granularity requires changes in the 473 * batch buffer programming. Since we can't break old userspace, we 474 * need to set our default preemption level to safe value. Userspace is 475 * still able to use more fine-grained preemption levels, since in 476 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 477 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 478 * not real HW workarounds, but merely a way to start using preemption 479 * while maintaining old contract with userspace. 480 */ 481 482 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 483 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 484 485 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 486 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 487 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 488 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 489 490 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 491 if (IS_GEN9_LP(i915)) 492 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 493 } 494 495 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 496 struct i915_wa_list *wal) 497 { 498 struct intel_gt *gt = engine->gt; 499 u8 vals[3] = { 0, 0, 0 }; 500 unsigned int i; 501 502 for (i = 0; i < 3; i++) { 503 u8 ss; 504 505 /* 506 * Only consider slices where one, and only one, subslice has 7 507 * EUs 508 */ 509 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 510 continue; 511 512 /* 513 * subslice_7eu[i] != 0 (because of the check above) and 514 * ss_max == 4 (maximum number of subslices possible per slice) 515 * 516 * -> 0 <= ss <= 3; 517 */ 518 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 519 vals[i] = 3 - ss; 520 } 521 522 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 523 return; 524 525 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 526 wa_masked_field_set(wal, GEN7_GT_MODE, 527 GEN9_IZ_HASHING_MASK(2) | 528 GEN9_IZ_HASHING_MASK(1) | 529 GEN9_IZ_HASHING_MASK(0), 530 GEN9_IZ_HASHING(2, vals[2]) | 531 GEN9_IZ_HASHING(1, vals[1]) | 532 GEN9_IZ_HASHING(0, vals[0])); 533 } 534 535 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 536 struct i915_wa_list *wal) 537 { 538 gen9_ctx_workarounds_init(engine, wal); 539 skl_tune_iz_hashing(engine, wal); 540 } 541 542 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 543 struct i915_wa_list *wal) 544 { 545 gen9_ctx_workarounds_init(engine, wal); 546 547 /* WaDisableThreadStallDopClockGating:bxt */ 548 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 549 STALL_DOP_GATING_DISABLE); 550 551 /* WaToEnableHwFixForPushConstHWBug:bxt */ 552 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 553 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 554 } 555 556 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 557 struct i915_wa_list *wal) 558 { 559 struct drm_i915_private *i915 = engine->i915; 560 561 gen9_ctx_workarounds_init(engine, wal); 562 563 /* WaToEnableHwFixForPushConstHWBug:kbl */ 564 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 565 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 566 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 567 568 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 569 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 570 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 571 } 572 573 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 574 struct i915_wa_list *wal) 575 { 576 gen9_ctx_workarounds_init(engine, wal); 577 578 /* WaToEnableHwFixForPushConstHWBug:glk */ 579 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 580 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 581 } 582 583 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 584 struct i915_wa_list *wal) 585 { 586 gen9_ctx_workarounds_init(engine, wal); 587 588 /* WaToEnableHwFixForPushConstHWBug:cfl */ 589 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 590 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 591 592 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 593 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 594 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 595 } 596 597 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 598 struct i915_wa_list *wal) 599 { 600 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 601 wa_write(wal, 602 GEN8_L3CNTLREG, 603 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 604 GEN8_ERRDETBCTRL); 605 606 /* WaForceEnableNonCoherent:icl 607 * This is not the same workaround as in early Gen9 platforms, where 608 * lacking this could cause system hangs, but coherency performance 609 * overhead is high and only a few compute workloads really need it 610 * (the register is whitelisted in hardware now, so UMDs can opt in 611 * for coherency if they have a good reason). 612 */ 613 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 614 615 /* WaEnableFloatBlendOptimization:icl */ 616 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 617 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 618 0 /* write-only, so skip validation */, 619 true); 620 621 /* WaDisableGPGPUMidThreadPreemption:icl */ 622 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 623 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 624 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 625 626 /* allow headerless messages for preemptible GPGPU context */ 627 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 628 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 629 630 /* Wa_1604278689:icl,ehl */ 631 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 632 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 633 0, /* write-only register; skip validation */ 634 0xFFFFFFFF); 635 636 /* Wa_1406306137:icl,ehl */ 637 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 638 } 639 640 /* 641 * These settings aren't actually workarounds, but general tuning settings that 642 * need to be programmed on dg2 platform. 643 */ 644 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 645 struct i915_wa_list *wal) 646 { 647 wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 648 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 649 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 650 wa_mcr_add(wal, 651 XEHP_FF_MODE2, 652 FF_MODE2_TDS_TIMER_MASK, 653 FF_MODE2_TDS_TIMER_128, 654 0, false); 655 } 656 657 /* 658 * These settings aren't actually workarounds, but general tuning settings that 659 * need to be programmed on several platforms. 660 */ 661 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 662 struct i915_wa_list *wal) 663 { 664 /* 665 * Although some platforms refer to it as Wa_1604555607, we need to 666 * program it even on those that don't explicitly list that 667 * workaround. 668 * 669 * Note that the programming of this register is further modified 670 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 671 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 672 * value when read. The default value for this register is zero for all 673 * fields and there are no bit masks. So instead of doing a RMW we 674 * should just write TDS timer value. For the same reason read 675 * verification is ignored. 676 */ 677 wa_add(wal, 678 GEN12_FF_MODE2, 679 FF_MODE2_TDS_TIMER_MASK, 680 FF_MODE2_TDS_TIMER_128, 681 0, false); 682 } 683 684 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 685 struct i915_wa_list *wal) 686 { 687 struct drm_i915_private *i915 = engine->i915; 688 689 gen12_ctx_gt_tuning_init(engine, wal); 690 691 /* 692 * Wa_1409142259:tgl,dg1,adl-p 693 * Wa_1409347922:tgl,dg1,adl-p 694 * Wa_1409252684:tgl,dg1,adl-p 695 * Wa_1409217633:tgl,dg1,adl-p 696 * Wa_1409207793:tgl,dg1,adl-p 697 * Wa_1409178076:tgl,dg1,adl-p 698 * Wa_1408979724:tgl,dg1,adl-p 699 * Wa_14010443199:tgl,rkl,dg1,adl-p 700 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 701 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 702 */ 703 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 704 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 705 706 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 707 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 708 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 709 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 710 711 /* 712 * Wa_16011163337 713 * 714 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 715 * to Wa_1608008084. 716 */ 717 wa_add(wal, 718 GEN12_FF_MODE2, 719 FF_MODE2_GS_TIMER_MASK, 720 FF_MODE2_GS_TIMER_224, 721 0, false); 722 723 if (!IS_DG1(i915)) 724 /* Wa_1806527549 */ 725 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 726 } 727 728 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 729 struct i915_wa_list *wal) 730 { 731 gen12_ctx_workarounds_init(engine, wal); 732 733 /* Wa_1409044764 */ 734 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 735 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 736 737 /* Wa_22010493298 */ 738 wa_masked_en(wal, HIZ_CHICKEN, 739 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 740 } 741 742 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 743 struct i915_wa_list *wal) 744 { 745 dg2_ctx_gt_tuning_init(engine, wal); 746 747 /* Wa_16011186671:dg2_g11 */ 748 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 749 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 750 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 751 } 752 753 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 754 /* Wa_14010469329:dg2_g10 */ 755 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 756 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 757 758 /* 759 * Wa_22010465075:dg2_g10 760 * Wa_22010613112:dg2_g10 761 * Wa_14010698770:dg2_g10 762 */ 763 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 764 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 765 } 766 767 /* Wa_16013271637:dg2 */ 768 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 769 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 770 771 /* Wa_14014947963:dg2 */ 772 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 773 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 774 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 775 776 /* Wa_15010599737:dg2 */ 777 wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 778 } 779 780 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 781 struct i915_wa_list *wal) 782 { 783 /* 784 * This is a "fake" workaround defined by software to ensure we 785 * maintain reliable, backward-compatible behavior for userspace with 786 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 787 * 788 * The per-context setting of MI_MODE[12] determines whether the bits 789 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 790 * in the traditional manner or whether they should instead use a new 791 * tgl+ meaning that breaks backward compatibility, but allows nesting 792 * into 3rd-level batchbuffers. When this new capability was first 793 * added in TGL, it remained off by default unless a context 794 * intentionally opted in to the new behavior. However Xe_HPG now 795 * flips this on by default and requires that we explicitly opt out if 796 * we don't want the new behavior. 797 * 798 * From a SW perspective, we want to maintain the backward-compatible 799 * behavior for userspace, so we'll apply a fake workaround to set it 800 * back to the legacy behavior on platforms where the hardware default 801 * is to break compatibility. At the moment there is no Linux 802 * userspace that utilizes third-level batchbuffers, so this will avoid 803 * userspace from needing to make any changes. using the legacy 804 * meaning is the correct thing to do. If/when we have userspace 805 * consumers that want to utilize third-level batch nesting, we can 806 * provide a context parameter to allow them to opt-in. 807 */ 808 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 809 } 810 811 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 812 struct i915_wa_list *wal) 813 { 814 u8 mocs; 815 816 /* 817 * Some blitter commands do not have a field for MOCS, those 818 * commands will use MOCS index pointed by BLIT_CCTL. 819 * BLIT_CCTL registers are needed to be programmed to un-cached. 820 */ 821 if (engine->class == COPY_ENGINE_CLASS) { 822 mocs = engine->gt->mocs.uc_index; 823 wa_write_clr_set(wal, 824 BLIT_CCTL(engine->mmio_base), 825 BLIT_CCTL_MASK, 826 BLIT_CCTL_MOCS(mocs, mocs)); 827 } 828 } 829 830 /* 831 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 832 * defined by the hardware team, but it programming general context registers. 833 * Adding those context register programming in context workaround 834 * allow us to use the wa framework for proper application and validation. 835 */ 836 static void 837 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 838 struct i915_wa_list *wal) 839 { 840 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 841 fakewa_disable_nestedbb_mode(engine, wal); 842 843 gen12_ctx_gt_mocs_init(engine, wal); 844 } 845 846 static void 847 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 848 struct i915_wa_list *wal, 849 const char *name) 850 { 851 struct drm_i915_private *i915 = engine->i915; 852 853 wa_init_start(wal, engine->gt, name, engine->name); 854 855 /* Applies to all engines */ 856 /* 857 * Fake workarounds are not the actual workaround but 858 * programming of context registers using workaround framework. 859 */ 860 if (GRAPHICS_VER(i915) >= 12) 861 gen12_ctx_gt_fake_wa_init(engine, wal); 862 863 if (engine->class != RENDER_CLASS) 864 goto done; 865 866 if (IS_PONTEVECCHIO(i915)) 867 ; /* noop; none at this time */ 868 else if (IS_DG2(i915)) 869 dg2_ctx_workarounds_init(engine, wal); 870 else if (IS_XEHPSDV(i915)) 871 ; /* noop; none at this time */ 872 else if (IS_DG1(i915)) 873 dg1_ctx_workarounds_init(engine, wal); 874 else if (GRAPHICS_VER(i915) == 12) 875 gen12_ctx_workarounds_init(engine, wal); 876 else if (GRAPHICS_VER(i915) == 11) 877 icl_ctx_workarounds_init(engine, wal); 878 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 879 cfl_ctx_workarounds_init(engine, wal); 880 else if (IS_GEMINILAKE(i915)) 881 glk_ctx_workarounds_init(engine, wal); 882 else if (IS_KABYLAKE(i915)) 883 kbl_ctx_workarounds_init(engine, wal); 884 else if (IS_BROXTON(i915)) 885 bxt_ctx_workarounds_init(engine, wal); 886 else if (IS_SKYLAKE(i915)) 887 skl_ctx_workarounds_init(engine, wal); 888 else if (IS_CHERRYVIEW(i915)) 889 chv_ctx_workarounds_init(engine, wal); 890 else if (IS_BROADWELL(i915)) 891 bdw_ctx_workarounds_init(engine, wal); 892 else if (GRAPHICS_VER(i915) == 7) 893 gen7_ctx_workarounds_init(engine, wal); 894 else if (GRAPHICS_VER(i915) == 6) 895 gen6_ctx_workarounds_init(engine, wal); 896 else if (GRAPHICS_VER(i915) < 8) 897 ; 898 else 899 MISSING_CASE(GRAPHICS_VER(i915)); 900 901 done: 902 wa_init_finish(wal); 903 } 904 905 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 906 { 907 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 908 } 909 910 int intel_engine_emit_ctx_wa(struct i915_request *rq) 911 { 912 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 913 struct i915_wa *wa; 914 unsigned int i; 915 u32 *cs; 916 int ret; 917 918 if (wal->count == 0) 919 return 0; 920 921 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 922 if (ret) 923 return ret; 924 925 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 926 if (IS_ERR(cs)) 927 return PTR_ERR(cs); 928 929 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 930 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 931 *cs++ = i915_mmio_reg_offset(wa->reg); 932 *cs++ = wa->set; 933 } 934 *cs++ = MI_NOOP; 935 936 intel_ring_advance(rq, cs); 937 938 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 939 if (ret) 940 return ret; 941 942 return 0; 943 } 944 945 static void 946 gen4_gt_workarounds_init(struct intel_gt *gt, 947 struct i915_wa_list *wal) 948 { 949 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 950 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 951 } 952 953 static void 954 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 955 { 956 gen4_gt_workarounds_init(gt, wal); 957 958 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 959 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 960 } 961 962 static void 963 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 964 { 965 g4x_gt_workarounds_init(gt, wal); 966 967 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 968 } 969 970 static void 971 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 972 { 973 } 974 975 static void 976 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 977 { 978 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 979 wa_masked_dis(wal, 980 GEN7_COMMON_SLICE_CHICKEN1, 981 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 982 983 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 984 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 985 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 986 987 /* WaForceL3Serialization:ivb */ 988 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 989 } 990 991 static void 992 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 993 { 994 /* WaForceL3Serialization:vlv */ 995 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 996 997 /* 998 * WaIncreaseL3CreditsForVLVB0:vlv 999 * This is the hardware default actually. 1000 */ 1001 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1002 } 1003 1004 static void 1005 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1006 { 1007 /* L3 caching of data atomics doesn't work -- disable it. */ 1008 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1009 1010 wa_add(wal, 1011 HSW_ROW_CHICKEN3, 0, 1012 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1013 0 /* XXX does this reg exist? */, true); 1014 1015 /* WaVSRefCountFullforceMissDisable:hsw */ 1016 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1017 } 1018 1019 static void 1020 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1021 { 1022 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1023 unsigned int slice, subslice; 1024 u32 mcr, mcr_mask; 1025 1026 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1027 1028 /* 1029 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1030 * Before any MMIO read into slice/subslice specific registers, MCR 1031 * packet control register needs to be programmed to point to any 1032 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1033 * This means each subsequent MMIO read will be forwarded to an 1034 * specific s/ss combination, but this is OK since these registers 1035 * are consistent across s/ss in almost all cases. In the rare 1036 * occasions, such as INSTDONE, where this value is dependent 1037 * on s/ss combo, the read should be done with read_subslice_reg. 1038 */ 1039 slice = ffs(sseu->slice_mask) - 1; 1040 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1041 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1042 GEM_BUG_ON(!subslice); 1043 subslice--; 1044 1045 /* 1046 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1047 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1048 */ 1049 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1050 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1051 1052 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1053 1054 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1055 } 1056 1057 static void 1058 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1059 { 1060 struct drm_i915_private *i915 = gt->i915; 1061 1062 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1063 gen9_wa_init_mcr(i915, wal); 1064 1065 /* WaDisableKillLogic:bxt,skl,kbl */ 1066 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1067 wa_write_or(wal, 1068 GAM_ECOCHK, 1069 ECOCHK_DIS_TLB); 1070 1071 if (HAS_LLC(i915)) { 1072 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1073 * 1074 * Must match Display Engine. See 1075 * WaCompressedResourceDisplayNewHashMode. 1076 */ 1077 wa_write_or(wal, 1078 MMCD_MISC_CTRL, 1079 MMCD_PCLA | MMCD_HOTSPOT_EN); 1080 } 1081 1082 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1083 wa_write_or(wal, 1084 GAM_ECOCHK, 1085 BDW_DISABLE_HDC_INVALIDATION); 1086 } 1087 1088 static void 1089 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1090 { 1091 gen9_gt_workarounds_init(gt, wal); 1092 1093 /* WaDisableGafsUnitClkGating:skl */ 1094 wa_write_or(wal, 1095 GEN7_UCGCTL4, 1096 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1097 1098 /* WaInPlaceDecompressionHang:skl */ 1099 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1100 wa_write_or(wal, 1101 GEN9_GAMT_ECO_REG_RW_IA, 1102 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1103 } 1104 1105 static void 1106 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1107 { 1108 gen9_gt_workarounds_init(gt, wal); 1109 1110 /* WaDisableDynamicCreditSharing:kbl */ 1111 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1112 wa_write_or(wal, 1113 GAMT_CHKN_BIT_REG, 1114 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1115 1116 /* WaDisableGafsUnitClkGating:kbl */ 1117 wa_write_or(wal, 1118 GEN7_UCGCTL4, 1119 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1120 1121 /* WaInPlaceDecompressionHang:kbl */ 1122 wa_write_or(wal, 1123 GEN9_GAMT_ECO_REG_RW_IA, 1124 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1125 } 1126 1127 static void 1128 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1129 { 1130 gen9_gt_workarounds_init(gt, wal); 1131 } 1132 1133 static void 1134 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1135 { 1136 gen9_gt_workarounds_init(gt, wal); 1137 1138 /* WaDisableGafsUnitClkGating:cfl */ 1139 wa_write_or(wal, 1140 GEN7_UCGCTL4, 1141 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1142 1143 /* WaInPlaceDecompressionHang:cfl */ 1144 wa_write_or(wal, 1145 GEN9_GAMT_ECO_REG_RW_IA, 1146 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1147 } 1148 1149 static void __set_mcr_steering(struct i915_wa_list *wal, 1150 i915_reg_t steering_reg, 1151 unsigned int slice, unsigned int subslice) 1152 { 1153 u32 mcr, mcr_mask; 1154 1155 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1156 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1157 1158 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1159 } 1160 1161 static void debug_dump_steering(struct intel_gt *gt) 1162 { 1163 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1164 1165 if (drm_debug_enabled(DRM_UT_DRIVER)) 1166 intel_gt_mcr_report_steering(&p, gt, false); 1167 } 1168 1169 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1170 unsigned int slice, unsigned int subslice) 1171 { 1172 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1173 1174 gt->default_steering.groupid = slice; 1175 gt->default_steering.instanceid = subslice; 1176 1177 debug_dump_steering(gt); 1178 } 1179 1180 static void 1181 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1182 { 1183 const struct sseu_dev_info *sseu = >->info.sseu; 1184 unsigned int subslice; 1185 1186 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1187 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1188 1189 /* 1190 * Although a platform may have subslices, we need to always steer 1191 * reads to the lowest instance that isn't fused off. When Render 1192 * Power Gating is enabled, grabbing forcewake will only power up a 1193 * single subslice (the "minconfig") if there isn't a real workload 1194 * that needs to be run; this means that if we steer register reads to 1195 * one of the higher subslices, we run the risk of reading back 0's or 1196 * random garbage. 1197 */ 1198 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1199 1200 /* 1201 * If the subslice we picked above also steers us to a valid L3 bank, 1202 * then we can just rely on the default steering and won't need to 1203 * worry about explicitly re-steering L3BANK reads later. 1204 */ 1205 if (gt->info.l3bank_mask & BIT(subslice)) 1206 gt->steering_table[L3BANK] = NULL; 1207 1208 __add_mcr_wa(gt, wal, 0, subslice); 1209 } 1210 1211 static void 1212 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1213 { 1214 const struct sseu_dev_info *sseu = >->info.sseu; 1215 unsigned long slice, subslice = 0, slice_mask = 0; 1216 u32 lncf_mask = 0; 1217 int i; 1218 1219 /* 1220 * On Xe_HP the steering increases in complexity. There are now several 1221 * more units that require steering and we're not guaranteed to be able 1222 * to find a common setting for all of them. These are: 1223 * - GSLICE (fusable) 1224 * - DSS (sub-unit within gslice; fusable) 1225 * - L3 Bank (fusable) 1226 * - MSLICE (fusable) 1227 * - LNCF (sub-unit within mslice; always present if mslice is present) 1228 * 1229 * We'll do our default/implicit steering based on GSLICE (in the 1230 * sliceid field) and DSS (in the subsliceid field). If we can 1231 * find overlap between the valid MSLICE and/or LNCF values with 1232 * a suitable GSLICE, then we can just re-use the default value and 1233 * skip and explicit steering at runtime. 1234 * 1235 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1236 * a valid sliceid value. DSS steering is the only type of steering 1237 * that utilizes the 'subsliceid' bits. 1238 * 1239 * Also note that, even though the steering domain is called "GSlice" 1240 * and it is encoded in the register using the gslice format, the spec 1241 * says that the combined (geometry | compute) fuse should be used to 1242 * select the steering. 1243 */ 1244 1245 /* Find the potential gslice candidates */ 1246 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1247 GEN_DSS_PER_GSLICE); 1248 1249 /* 1250 * Find the potential LNCF candidates. Either LNCF within a valid 1251 * mslice is fine. 1252 */ 1253 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1254 lncf_mask |= (0x3 << (i * 2)); 1255 1256 /* 1257 * Are there any sliceid values that work for both GSLICE and LNCF 1258 * steering? 1259 */ 1260 if (slice_mask & lncf_mask) { 1261 slice_mask &= lncf_mask; 1262 gt->steering_table[LNCF] = NULL; 1263 } 1264 1265 /* How about sliceid values that also work for MSLICE steering? */ 1266 if (slice_mask & gt->info.mslice_mask) { 1267 slice_mask &= gt->info.mslice_mask; 1268 gt->steering_table[MSLICE] = NULL; 1269 } 1270 1271 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1272 gt->steering_table[GAM] = NULL; 1273 1274 slice = __ffs(slice_mask); 1275 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1276 GEN_DSS_PER_GSLICE; 1277 1278 __add_mcr_wa(gt, wal, slice, subslice); 1279 1280 /* 1281 * SQIDI ranges are special because they use different steering 1282 * registers than everything else we work with. On XeHP SDV and 1283 * DG2-G10, any value in the steering registers will work fine since 1284 * all instances are present, but DG2-G11 only has SQIDI instances at 1285 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1286 * we'll just steer to a hardcoded "2" since that value will work 1287 * everywhere. 1288 */ 1289 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1290 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1291 1292 /* 1293 * On DG2, GAM registers have a dedicated steering control register 1294 * and must always be programmed to a hardcoded groupid of "1." 1295 */ 1296 if (IS_DG2(gt->i915)) 1297 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1298 } 1299 1300 static void 1301 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1302 { 1303 unsigned int dss; 1304 1305 /* 1306 * Setup implicit steering for COMPUTE and DSS ranges to the first 1307 * non-fused-off DSS. All other types of MCR registers will be 1308 * explicitly steered. 1309 */ 1310 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1311 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1312 } 1313 1314 static void 1315 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1316 { 1317 struct drm_i915_private *i915 = gt->i915; 1318 1319 icl_wa_init_mcr(gt, wal); 1320 1321 /* WaModifyGamTlbPartitioning:icl */ 1322 wa_write_clr_set(wal, 1323 GEN11_GACB_PERF_CTRL, 1324 GEN11_HASH_CTRL_MASK, 1325 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1326 1327 /* Wa_1405766107:icl 1328 * Formerly known as WaCL2SFHalfMaxAlloc 1329 */ 1330 wa_write_or(wal, 1331 GEN11_LSN_UNSLCVC, 1332 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1333 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1334 1335 /* Wa_220166154:icl 1336 * Formerly known as WaDisCtxReload 1337 */ 1338 wa_write_or(wal, 1339 GEN8_GAMW_ECO_DEV_RW_IA, 1340 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1341 1342 /* Wa_1406463099:icl 1343 * Formerly known as WaGamTlbPendError 1344 */ 1345 wa_write_or(wal, 1346 GAMT_CHKN_BIT_REG, 1347 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1348 1349 /* Wa_1407352427:icl,ehl */ 1350 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1351 PSDUNIT_CLKGATE_DIS); 1352 1353 /* Wa_1406680159:icl,ehl */ 1354 wa_mcr_write_or(wal, 1355 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1356 GWUNIT_CLKGATE_DIS); 1357 1358 /* Wa_1607087056:icl,ehl,jsl */ 1359 if (IS_ICELAKE(i915) || 1360 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1361 wa_write_or(wal, 1362 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1363 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1364 1365 /* 1366 * This is not a documented workaround, but rather an optimization 1367 * to reduce sampler power. 1368 */ 1369 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1370 } 1371 1372 /* 1373 * Though there are per-engine instances of these registers, 1374 * they retain their value through engine resets and should 1375 * only be provided on the GT workaround list rather than 1376 * the engine-specific workaround list. 1377 */ 1378 static void 1379 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1380 { 1381 struct intel_engine_cs *engine; 1382 int id; 1383 1384 for_each_engine(engine, gt, id) { 1385 if (engine->class != VIDEO_DECODE_CLASS || 1386 (engine->instance % 2)) 1387 continue; 1388 1389 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1390 IECPUNIT_CLKGATE_DIS); 1391 } 1392 } 1393 1394 static void 1395 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1396 { 1397 icl_wa_init_mcr(gt, wal); 1398 1399 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1400 wa_14011060649(gt, wal); 1401 1402 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1403 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1404 } 1405 1406 static void 1407 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1408 { 1409 struct drm_i915_private *i915 = gt->i915; 1410 1411 gen12_gt_workarounds_init(gt, wal); 1412 1413 /* Wa_1409420604:tgl */ 1414 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1415 wa_mcr_write_or(wal, 1416 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1417 CPSSUNIT_CLKGATE_DIS); 1418 1419 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1420 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1421 wa_write_or(wal, 1422 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1423 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1424 1425 /* Wa_1408615072:tgl[a0] */ 1426 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1427 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1428 VSUNIT_CLKGATE_DIS_TGL); 1429 } 1430 1431 static void 1432 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1433 { 1434 struct drm_i915_private *i915 = gt->i915; 1435 1436 gen12_gt_workarounds_init(gt, wal); 1437 1438 /* Wa_1607087056:dg1 */ 1439 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1440 wa_write_or(wal, 1441 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1442 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1443 1444 /* Wa_1409420604:dg1 */ 1445 if (IS_DG1(i915)) 1446 wa_mcr_write_or(wal, 1447 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1448 CPSSUNIT_CLKGATE_DIS); 1449 1450 /* Wa_1408615072:dg1 */ 1451 /* Empirical testing shows this register is unaffected by engine reset. */ 1452 if (IS_DG1(i915)) 1453 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1454 VSUNIT_CLKGATE_DIS_TGL); 1455 } 1456 1457 static void 1458 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1459 { 1460 struct drm_i915_private *i915 = gt->i915; 1461 1462 xehp_init_mcr(gt, wal); 1463 1464 /* Wa_1409757795:xehpsdv */ 1465 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1466 1467 /* Wa_16011155590:xehpsdv */ 1468 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1469 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1470 TSGUNIT_CLKGATE_DIS); 1471 1472 /* Wa_14011780169:xehpsdv */ 1473 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1474 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1475 GAMTLBVDBOX7_CLKGATE_DIS | 1476 GAMTLBVDBOX6_CLKGATE_DIS | 1477 GAMTLBVDBOX5_CLKGATE_DIS | 1478 GAMTLBVDBOX4_CLKGATE_DIS | 1479 GAMTLBVDBOX3_CLKGATE_DIS | 1480 GAMTLBVDBOX2_CLKGATE_DIS | 1481 GAMTLBVDBOX1_CLKGATE_DIS | 1482 GAMTLBVDBOX0_CLKGATE_DIS | 1483 GAMTLBKCR_CLKGATE_DIS | 1484 GAMTLBGUC_CLKGATE_DIS | 1485 GAMTLBBLT_CLKGATE_DIS); 1486 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1487 GAMTLBGFXA1_CLKGATE_DIS | 1488 GAMTLBCOMPA0_CLKGATE_DIS | 1489 GAMTLBCOMPA1_CLKGATE_DIS | 1490 GAMTLBCOMPB0_CLKGATE_DIS | 1491 GAMTLBCOMPB1_CLKGATE_DIS | 1492 GAMTLBCOMPC0_CLKGATE_DIS | 1493 GAMTLBCOMPC1_CLKGATE_DIS | 1494 GAMTLBCOMPD0_CLKGATE_DIS | 1495 GAMTLBCOMPD1_CLKGATE_DIS | 1496 GAMTLBMERT_CLKGATE_DIS | 1497 GAMTLBVEBOX3_CLKGATE_DIS | 1498 GAMTLBVEBOX2_CLKGATE_DIS | 1499 GAMTLBVEBOX1_CLKGATE_DIS | 1500 GAMTLBVEBOX0_CLKGATE_DIS); 1501 } 1502 1503 /* Wa_16012725990:xehpsdv */ 1504 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1505 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1506 1507 /* Wa_14011060649:xehpsdv */ 1508 wa_14011060649(gt, wal); 1509 } 1510 1511 static void 1512 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1513 { 1514 struct intel_engine_cs *engine; 1515 int id; 1516 1517 xehp_init_mcr(gt, wal); 1518 1519 /* Wa_14011060649:dg2 */ 1520 wa_14011060649(gt, wal); 1521 1522 /* 1523 * Although there are per-engine instances of these registers, 1524 * they technically exist outside the engine itself and are not 1525 * impacted by engine resets. Furthermore, they're part of the 1526 * GuC blacklist so trying to treat them as engine workarounds 1527 * will result in GuC initialization failure and a wedged GPU. 1528 */ 1529 for_each_engine(engine, gt, id) { 1530 if (engine->class != VIDEO_DECODE_CLASS) 1531 continue; 1532 1533 /* Wa_16010515920:dg2_g10 */ 1534 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1535 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1536 ALNUNIT_CLKGATE_DIS); 1537 } 1538 1539 if (IS_DG2_G10(gt->i915)) { 1540 /* Wa_22010523718:dg2 */ 1541 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1542 CG3DDISCFEG_CLKGATE_DIS); 1543 1544 /* Wa_14011006942:dg2 */ 1545 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1546 DSS_ROUTER_CLKGATE_DIS); 1547 } 1548 1549 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1550 /* Wa_14010948348:dg2_g10 */ 1551 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1552 1553 /* Wa_14011037102:dg2_g10 */ 1554 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1555 1556 /* Wa_14011371254:dg2_g10 */ 1557 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1558 1559 /* Wa_14011431319:dg2_g10 */ 1560 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1561 GAMTLBVDBOX7_CLKGATE_DIS | 1562 GAMTLBVDBOX6_CLKGATE_DIS | 1563 GAMTLBVDBOX5_CLKGATE_DIS | 1564 GAMTLBVDBOX4_CLKGATE_DIS | 1565 GAMTLBVDBOX3_CLKGATE_DIS | 1566 GAMTLBVDBOX2_CLKGATE_DIS | 1567 GAMTLBVDBOX1_CLKGATE_DIS | 1568 GAMTLBVDBOX0_CLKGATE_DIS | 1569 GAMTLBKCR_CLKGATE_DIS | 1570 GAMTLBGUC_CLKGATE_DIS | 1571 GAMTLBBLT_CLKGATE_DIS); 1572 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1573 GAMTLBGFXA1_CLKGATE_DIS | 1574 GAMTLBCOMPA0_CLKGATE_DIS | 1575 GAMTLBCOMPA1_CLKGATE_DIS | 1576 GAMTLBCOMPB0_CLKGATE_DIS | 1577 GAMTLBCOMPB1_CLKGATE_DIS | 1578 GAMTLBCOMPC0_CLKGATE_DIS | 1579 GAMTLBCOMPC1_CLKGATE_DIS | 1580 GAMTLBCOMPD0_CLKGATE_DIS | 1581 GAMTLBCOMPD1_CLKGATE_DIS | 1582 GAMTLBMERT_CLKGATE_DIS | 1583 GAMTLBVEBOX3_CLKGATE_DIS | 1584 GAMTLBVEBOX2_CLKGATE_DIS | 1585 GAMTLBVEBOX1_CLKGATE_DIS | 1586 GAMTLBVEBOX0_CLKGATE_DIS); 1587 1588 /* Wa_14010569222:dg2_g10 */ 1589 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1590 GAMEDIA_CLKGATE_DIS); 1591 1592 /* Wa_14011028019:dg2_g10 */ 1593 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1594 } 1595 1596 /* Wa_14014830051:dg2 */ 1597 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1598 1599 /* 1600 * The following are not actually "workarounds" but rather 1601 * recommended tuning settings documented in the bspec's 1602 * performance guide section. 1603 */ 1604 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1605 1606 /* Wa_14015795083 */ 1607 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1608 } 1609 1610 static void 1611 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1612 { 1613 pvc_init_mcr(gt, wal); 1614 1615 /* Wa_14015795083 */ 1616 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1617 } 1618 1619 static void 1620 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1621 { 1622 /* FIXME: Actual workarounds will be added in future patch(es) */ 1623 1624 /* 1625 * Unlike older platforms, we no longer setup implicit steering here; 1626 * all MCR accesses are explicitly steered. 1627 */ 1628 debug_dump_steering(gt); 1629 } 1630 1631 static void 1632 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1633 { 1634 /* FIXME: Actual workarounds will be added in future patch(es) */ 1635 1636 debug_dump_steering(gt); 1637 } 1638 1639 static void 1640 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1641 { 1642 struct drm_i915_private *i915 = gt->i915; 1643 1644 if (gt->type == GT_MEDIA) { 1645 if (MEDIA_VER(i915) >= 13) 1646 xelpmp_gt_workarounds_init(gt, wal); 1647 else 1648 MISSING_CASE(MEDIA_VER(i915)); 1649 1650 return; 1651 } 1652 1653 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1654 xelpg_gt_workarounds_init(gt, wal); 1655 else if (IS_PONTEVECCHIO(i915)) 1656 pvc_gt_workarounds_init(gt, wal); 1657 else if (IS_DG2(i915)) 1658 dg2_gt_workarounds_init(gt, wal); 1659 else if (IS_XEHPSDV(i915)) 1660 xehpsdv_gt_workarounds_init(gt, wal); 1661 else if (IS_DG1(i915)) 1662 dg1_gt_workarounds_init(gt, wal); 1663 else if (IS_TIGERLAKE(i915)) 1664 tgl_gt_workarounds_init(gt, wal); 1665 else if (GRAPHICS_VER(i915) == 12) 1666 gen12_gt_workarounds_init(gt, wal); 1667 else if (GRAPHICS_VER(i915) == 11) 1668 icl_gt_workarounds_init(gt, wal); 1669 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1670 cfl_gt_workarounds_init(gt, wal); 1671 else if (IS_GEMINILAKE(i915)) 1672 glk_gt_workarounds_init(gt, wal); 1673 else if (IS_KABYLAKE(i915)) 1674 kbl_gt_workarounds_init(gt, wal); 1675 else if (IS_BROXTON(i915)) 1676 gen9_gt_workarounds_init(gt, wal); 1677 else if (IS_SKYLAKE(i915)) 1678 skl_gt_workarounds_init(gt, wal); 1679 else if (IS_HASWELL(i915)) 1680 hsw_gt_workarounds_init(gt, wal); 1681 else if (IS_VALLEYVIEW(i915)) 1682 vlv_gt_workarounds_init(gt, wal); 1683 else if (IS_IVYBRIDGE(i915)) 1684 ivb_gt_workarounds_init(gt, wal); 1685 else if (GRAPHICS_VER(i915) == 6) 1686 snb_gt_workarounds_init(gt, wal); 1687 else if (GRAPHICS_VER(i915) == 5) 1688 ilk_gt_workarounds_init(gt, wal); 1689 else if (IS_G4X(i915)) 1690 g4x_gt_workarounds_init(gt, wal); 1691 else if (GRAPHICS_VER(i915) == 4) 1692 gen4_gt_workarounds_init(gt, wal); 1693 else if (GRAPHICS_VER(i915) <= 8) 1694 ; 1695 else 1696 MISSING_CASE(GRAPHICS_VER(i915)); 1697 } 1698 1699 void intel_gt_init_workarounds(struct intel_gt *gt) 1700 { 1701 struct i915_wa_list *wal = >->wa_list; 1702 1703 wa_init_start(wal, gt, "GT", "global"); 1704 gt_init_workarounds(gt, wal); 1705 wa_init_finish(wal); 1706 } 1707 1708 static enum forcewake_domains 1709 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1710 { 1711 enum forcewake_domains fw = 0; 1712 struct i915_wa *wa; 1713 unsigned int i; 1714 1715 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1716 fw |= intel_uncore_forcewake_for_reg(uncore, 1717 wa->reg, 1718 FW_REG_READ | 1719 FW_REG_WRITE); 1720 1721 return fw; 1722 } 1723 1724 static bool 1725 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1726 const char *name, const char *from) 1727 { 1728 if ((cur ^ wa->set) & wa->read) { 1729 drm_err(>->i915->drm, 1730 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1731 name, from, i915_mmio_reg_offset(wa->reg), 1732 cur, cur & wa->read, wa->set & wa->read); 1733 1734 return false; 1735 } 1736 1737 return true; 1738 } 1739 1740 static void wa_list_apply(const struct i915_wa_list *wal) 1741 { 1742 struct intel_gt *gt = wal->gt; 1743 struct intel_uncore *uncore = gt->uncore; 1744 enum forcewake_domains fw; 1745 unsigned long flags; 1746 struct i915_wa *wa; 1747 unsigned int i; 1748 1749 if (!wal->count) 1750 return; 1751 1752 fw = wal_get_fw_for_rmw(uncore, wal); 1753 1754 spin_lock_irqsave(&uncore->lock, flags); 1755 intel_uncore_forcewake_get__locked(uncore, fw); 1756 1757 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1758 u32 val, old = 0; 1759 1760 /* open-coded rmw due to steering */ 1761 if (wa->clr) 1762 old = wa->is_mcr ? 1763 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1764 intel_uncore_read_fw(uncore, wa->reg); 1765 val = (old & ~wa->clr) | wa->set; 1766 if (val != old || !wa->clr) { 1767 if (wa->is_mcr) 1768 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1769 else 1770 intel_uncore_write_fw(uncore, wa->reg, val); 1771 } 1772 1773 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1774 u32 val = wa->is_mcr ? 1775 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1776 intel_uncore_read_fw(uncore, wa->reg); 1777 1778 wa_verify(gt, wa, val, wal->name, "application"); 1779 } 1780 } 1781 1782 intel_uncore_forcewake_put__locked(uncore, fw); 1783 spin_unlock_irqrestore(&uncore->lock, flags); 1784 } 1785 1786 void intel_gt_apply_workarounds(struct intel_gt *gt) 1787 { 1788 wa_list_apply(>->wa_list); 1789 } 1790 1791 static bool wa_list_verify(struct intel_gt *gt, 1792 const struct i915_wa_list *wal, 1793 const char *from) 1794 { 1795 struct intel_uncore *uncore = gt->uncore; 1796 struct i915_wa *wa; 1797 enum forcewake_domains fw; 1798 unsigned long flags; 1799 unsigned int i; 1800 bool ok = true; 1801 1802 fw = wal_get_fw_for_rmw(uncore, wal); 1803 1804 spin_lock_irqsave(&uncore->lock, flags); 1805 intel_uncore_forcewake_get__locked(uncore, fw); 1806 1807 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1808 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1809 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1810 intel_uncore_read_fw(uncore, wa->reg), 1811 wal->name, from); 1812 1813 intel_uncore_forcewake_put__locked(uncore, fw); 1814 spin_unlock_irqrestore(&uncore->lock, flags); 1815 1816 return ok; 1817 } 1818 1819 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1820 { 1821 return wa_list_verify(gt, >->wa_list, from); 1822 } 1823 1824 __maybe_unused 1825 static bool is_nonpriv_flags_valid(u32 flags) 1826 { 1827 /* Check only valid flag bits are set */ 1828 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1829 return false; 1830 1831 /* NB: Only 3 out of 4 enum values are valid for access field */ 1832 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1833 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1834 return false; 1835 1836 return true; 1837 } 1838 1839 static void 1840 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1841 { 1842 struct i915_wa wa = { 1843 .reg = reg 1844 }; 1845 1846 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1847 return; 1848 1849 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1850 return; 1851 1852 wa.reg.reg |= flags; 1853 _wa_add(wal, &wa); 1854 } 1855 1856 static void 1857 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1858 { 1859 struct i915_wa wa = { 1860 .mcr_reg = reg, 1861 .is_mcr = 1, 1862 }; 1863 1864 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1865 return; 1866 1867 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1868 return; 1869 1870 wa.mcr_reg.reg |= flags; 1871 _wa_add(wal, &wa); 1872 } 1873 1874 static void 1875 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1876 { 1877 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1878 } 1879 1880 static void 1881 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1882 { 1883 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1884 } 1885 1886 static void gen9_whitelist_build(struct i915_wa_list *w) 1887 { 1888 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1889 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1890 1891 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1892 whitelist_reg(w, GEN8_CS_CHICKEN1); 1893 1894 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1895 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1896 1897 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1898 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1899 } 1900 1901 static void skl_whitelist_build(struct intel_engine_cs *engine) 1902 { 1903 struct i915_wa_list *w = &engine->whitelist; 1904 1905 if (engine->class != RENDER_CLASS) 1906 return; 1907 1908 gen9_whitelist_build(w); 1909 1910 /* WaDisableLSQCROPERFforOCL:skl */ 1911 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1912 } 1913 1914 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1915 { 1916 if (engine->class != RENDER_CLASS) 1917 return; 1918 1919 gen9_whitelist_build(&engine->whitelist); 1920 } 1921 1922 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1923 { 1924 struct i915_wa_list *w = &engine->whitelist; 1925 1926 if (engine->class != RENDER_CLASS) 1927 return; 1928 1929 gen9_whitelist_build(w); 1930 1931 /* WaDisableLSQCROPERFforOCL:kbl */ 1932 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1933 } 1934 1935 static void glk_whitelist_build(struct intel_engine_cs *engine) 1936 { 1937 struct i915_wa_list *w = &engine->whitelist; 1938 1939 if (engine->class != RENDER_CLASS) 1940 return; 1941 1942 gen9_whitelist_build(w); 1943 1944 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1945 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1946 } 1947 1948 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1949 { 1950 struct i915_wa_list *w = &engine->whitelist; 1951 1952 if (engine->class != RENDER_CLASS) 1953 return; 1954 1955 gen9_whitelist_build(w); 1956 1957 /* 1958 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1959 * 1960 * This covers 4 register which are next to one another : 1961 * - PS_INVOCATION_COUNT 1962 * - PS_INVOCATION_COUNT_UDW 1963 * - PS_DEPTH_COUNT 1964 * - PS_DEPTH_COUNT_UDW 1965 */ 1966 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1967 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1968 RING_FORCE_TO_NONPRIV_RANGE_4); 1969 } 1970 1971 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1972 { 1973 struct i915_wa_list *w = &engine->whitelist; 1974 1975 if (engine->class != RENDER_CLASS) 1976 whitelist_reg_ext(w, 1977 RING_CTX_TIMESTAMP(engine->mmio_base), 1978 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1979 } 1980 1981 static void cml_whitelist_build(struct intel_engine_cs *engine) 1982 { 1983 allow_read_ctx_timestamp(engine); 1984 1985 cfl_whitelist_build(engine); 1986 } 1987 1988 static void icl_whitelist_build(struct intel_engine_cs *engine) 1989 { 1990 struct i915_wa_list *w = &engine->whitelist; 1991 1992 allow_read_ctx_timestamp(engine); 1993 1994 switch (engine->class) { 1995 case RENDER_CLASS: 1996 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1997 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1998 1999 /* WaAllowUMDToModifySamplerMode:icl */ 2000 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2001 2002 /* WaEnableStateCacheRedirectToCS:icl */ 2003 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2004 2005 /* 2006 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2007 * 2008 * This covers 4 register which are next to one another : 2009 * - PS_INVOCATION_COUNT 2010 * - PS_INVOCATION_COUNT_UDW 2011 * - PS_DEPTH_COUNT 2012 * - PS_DEPTH_COUNT_UDW 2013 */ 2014 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2015 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2016 RING_FORCE_TO_NONPRIV_RANGE_4); 2017 break; 2018 2019 case VIDEO_DECODE_CLASS: 2020 /* hucStatusRegOffset */ 2021 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2022 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2023 /* hucUKernelHdrInfoRegOffset */ 2024 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2025 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2026 /* hucStatus2RegOffset */ 2027 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2028 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2029 break; 2030 2031 default: 2032 break; 2033 } 2034 } 2035 2036 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2037 { 2038 struct i915_wa_list *w = &engine->whitelist; 2039 2040 allow_read_ctx_timestamp(engine); 2041 2042 switch (engine->class) { 2043 case RENDER_CLASS: 2044 /* 2045 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2046 * Wa_1408556865:tgl 2047 * 2048 * This covers 4 registers which are next to one another : 2049 * - PS_INVOCATION_COUNT 2050 * - PS_INVOCATION_COUNT_UDW 2051 * - PS_DEPTH_COUNT 2052 * - PS_DEPTH_COUNT_UDW 2053 */ 2054 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2055 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2056 RING_FORCE_TO_NONPRIV_RANGE_4); 2057 2058 /* 2059 * Wa_1808121037:tgl 2060 * Wa_14012131227:dg1 2061 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2062 */ 2063 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2064 2065 /* Wa_1806527549:tgl */ 2066 whitelist_reg(w, HIZ_CHICKEN); 2067 break; 2068 default: 2069 break; 2070 } 2071 } 2072 2073 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2074 { 2075 struct i915_wa_list *w = &engine->whitelist; 2076 2077 tgl_whitelist_build(engine); 2078 2079 /* GEN:BUG:1409280441:dg1 */ 2080 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2081 (engine->class == RENDER_CLASS || 2082 engine->class == COPY_ENGINE_CLASS)) 2083 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2084 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2085 } 2086 2087 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2088 { 2089 allow_read_ctx_timestamp(engine); 2090 } 2091 2092 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2093 { 2094 struct i915_wa_list *w = &engine->whitelist; 2095 2096 allow_read_ctx_timestamp(engine); 2097 2098 switch (engine->class) { 2099 case RENDER_CLASS: 2100 /* 2101 * Wa_1507100340:dg2_g10 2102 * 2103 * This covers 4 registers which are next to one another : 2104 * - PS_INVOCATION_COUNT 2105 * - PS_INVOCATION_COUNT_UDW 2106 * - PS_DEPTH_COUNT 2107 * - PS_DEPTH_COUNT_UDW 2108 */ 2109 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2110 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2111 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2112 RING_FORCE_TO_NONPRIV_RANGE_4); 2113 2114 break; 2115 case COMPUTE_CLASS: 2116 /* Wa_16011157294:dg2_g10 */ 2117 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2118 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2119 break; 2120 default: 2121 break; 2122 } 2123 } 2124 2125 static void blacklist_trtt(struct intel_engine_cs *engine) 2126 { 2127 struct i915_wa_list *w = &engine->whitelist; 2128 2129 /* 2130 * Prevent read/write access to [0x4400, 0x4600) which covers 2131 * the TRTT range across all engines. Note that normally userspace 2132 * cannot access the other engines' trtt control, but for simplicity 2133 * we cover the entire range on each engine. 2134 */ 2135 whitelist_reg_ext(w, _MMIO(0x4400), 2136 RING_FORCE_TO_NONPRIV_DENY | 2137 RING_FORCE_TO_NONPRIV_RANGE_64); 2138 whitelist_reg_ext(w, _MMIO(0x4500), 2139 RING_FORCE_TO_NONPRIV_DENY | 2140 RING_FORCE_TO_NONPRIV_RANGE_64); 2141 } 2142 2143 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2144 { 2145 allow_read_ctx_timestamp(engine); 2146 2147 /* Wa_16014440446:pvc */ 2148 blacklist_trtt(engine); 2149 } 2150 2151 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2152 { 2153 struct drm_i915_private *i915 = engine->i915; 2154 struct i915_wa_list *w = &engine->whitelist; 2155 2156 wa_init_start(w, engine->gt, "whitelist", engine->name); 2157 2158 if (IS_PONTEVECCHIO(i915)) 2159 pvc_whitelist_build(engine); 2160 else if (IS_DG2(i915)) 2161 dg2_whitelist_build(engine); 2162 else if (IS_XEHPSDV(i915)) 2163 xehpsdv_whitelist_build(engine); 2164 else if (IS_DG1(i915)) 2165 dg1_whitelist_build(engine); 2166 else if (GRAPHICS_VER(i915) == 12) 2167 tgl_whitelist_build(engine); 2168 else if (GRAPHICS_VER(i915) == 11) 2169 icl_whitelist_build(engine); 2170 else if (IS_COMETLAKE(i915)) 2171 cml_whitelist_build(engine); 2172 else if (IS_COFFEELAKE(i915)) 2173 cfl_whitelist_build(engine); 2174 else if (IS_GEMINILAKE(i915)) 2175 glk_whitelist_build(engine); 2176 else if (IS_KABYLAKE(i915)) 2177 kbl_whitelist_build(engine); 2178 else if (IS_BROXTON(i915)) 2179 bxt_whitelist_build(engine); 2180 else if (IS_SKYLAKE(i915)) 2181 skl_whitelist_build(engine); 2182 else if (GRAPHICS_VER(i915) <= 8) 2183 ; 2184 else 2185 MISSING_CASE(GRAPHICS_VER(i915)); 2186 2187 wa_init_finish(w); 2188 } 2189 2190 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2191 { 2192 const struct i915_wa_list *wal = &engine->whitelist; 2193 struct intel_uncore *uncore = engine->uncore; 2194 const u32 base = engine->mmio_base; 2195 struct i915_wa *wa; 2196 unsigned int i; 2197 2198 if (!wal->count) 2199 return; 2200 2201 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2202 intel_uncore_write(uncore, 2203 RING_FORCE_TO_NONPRIV(base, i), 2204 i915_mmio_reg_offset(wa->reg)); 2205 2206 /* And clear the rest just in case of garbage */ 2207 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2208 intel_uncore_write(uncore, 2209 RING_FORCE_TO_NONPRIV(base, i), 2210 i915_mmio_reg_offset(RING_NOPID(base))); 2211 } 2212 2213 /* 2214 * engine_fake_wa_init(), a place holder to program the registers 2215 * which are not part of an official workaround defined by the 2216 * hardware team. 2217 * Adding programming of those register inside workaround will 2218 * allow utilizing wa framework to proper application and verification. 2219 */ 2220 static void 2221 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2222 { 2223 u8 mocs_w, mocs_r; 2224 2225 /* 2226 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2227 * by the command streamer when executing commands that don't have 2228 * a way to explicitly specify a MOCS setting. The default should 2229 * usually reference whichever MOCS entry corresponds to uncached 2230 * behavior, although use of a WB cached entry is recommended by the 2231 * spec in certain circumstances on specific platforms. 2232 */ 2233 if (GRAPHICS_VER(engine->i915) >= 12) { 2234 mocs_r = engine->gt->mocs.uc_index; 2235 mocs_w = engine->gt->mocs.uc_index; 2236 2237 if (HAS_L3_CCS_READ(engine->i915) && 2238 engine->class == COMPUTE_CLASS) { 2239 mocs_r = engine->gt->mocs.wb_index; 2240 2241 /* 2242 * Even on the few platforms where MOCS 0 is a 2243 * legitimate table entry, it's never the correct 2244 * setting to use here; we can assume the MOCS init 2245 * just forgot to initialize wb_index. 2246 */ 2247 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2248 } 2249 2250 wa_masked_field_set(wal, 2251 RING_CMD_CCTL(engine->mmio_base), 2252 CMD_CCTL_MOCS_MASK, 2253 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2254 } 2255 } 2256 2257 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2258 { 2259 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2260 GEN_DSS_PER_GSLICE; 2261 } 2262 2263 static void 2264 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2265 { 2266 struct drm_i915_private *i915 = engine->i915; 2267 2268 if (IS_DG2(i915)) { 2269 /* Wa_1509235366:dg2 */ 2270 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2271 GLOBAL_INVALIDATION_MODE); 2272 } 2273 2274 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2275 /* Wa_14013392000:dg2_g11 */ 2276 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2277 } 2278 2279 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2280 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2281 /* Wa_1509727124:dg2 */ 2282 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2283 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2284 } 2285 2286 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2287 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2288 /* Wa_14012419201:dg2 */ 2289 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2290 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2291 } 2292 2293 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2294 IS_DG2_G11(i915)) { 2295 /* 2296 * Wa_22012826095:dg2 2297 * Wa_22013059131:dg2 2298 */ 2299 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2300 MAXREQS_PER_BANK, 2301 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2302 2303 /* Wa_22013059131:dg2 */ 2304 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2305 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2306 } 2307 2308 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2309 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2310 needs_wa_1308578152(engine)) { 2311 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2312 GEN12_REPLAY_MODE_GRANULARITY); 2313 } 2314 2315 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2316 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2317 /* Wa_22013037850:dg2 */ 2318 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2319 DISABLE_128B_EVICTION_COMMAND_UDW); 2320 2321 /* Wa_22012856258:dg2 */ 2322 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2323 GEN12_DISABLE_READ_SUPPRESSION); 2324 2325 /* 2326 * Wa_22010960976:dg2 2327 * Wa_14013347512:dg2 2328 */ 2329 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2330 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2331 } 2332 2333 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2334 /* 2335 * Wa_1608949956:dg2_g10 2336 * Wa_14010198302:dg2_g10 2337 */ 2338 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2339 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2340 2341 /* 2342 * Wa_14010918519:dg2_g10 2343 * 2344 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2345 * so ignoring verification. 2346 */ 2347 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2348 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2349 0, false); 2350 } 2351 2352 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2353 /* Wa_22010430635:dg2 */ 2354 wa_mcr_masked_en(wal, 2355 GEN9_ROW_CHICKEN4, 2356 GEN12_DISABLE_GRF_CLEAR); 2357 2358 /* Wa_14010648519:dg2 */ 2359 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2360 } 2361 2362 /* Wa_14013202645:dg2 */ 2363 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2364 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2365 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2366 2367 /* Wa_22012532006:dg2 */ 2368 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2369 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2370 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2371 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2372 2373 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2374 /* Wa_14010680813:dg2_g10 */ 2375 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2376 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2377 } 2378 2379 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2380 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2381 /* Wa_14012362059:dg2 */ 2382 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2383 } 2384 2385 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2386 IS_DG2_G10(i915)) { 2387 /* Wa_22014600077:dg2 */ 2388 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2389 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2390 0 /* Wa_14012342262 write-only reg, so skip verification */, 2391 true); 2392 } 2393 2394 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2395 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2396 /* 2397 * Wa_1607138336:tgl[a0],dg1[a0] 2398 * Wa_1607063988:tgl[a0],dg1[a0] 2399 */ 2400 wa_write_or(wal, 2401 GEN9_CTX_PREEMPT_REG, 2402 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2403 } 2404 2405 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2406 /* 2407 * Wa_1606679103:tgl 2408 * (see also Wa_1606682166:icl) 2409 */ 2410 wa_write_or(wal, 2411 GEN7_SARCHKMD, 2412 GEN7_DISABLE_SAMPLER_PREFETCH); 2413 } 2414 2415 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2416 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2417 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2418 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2419 2420 /* 2421 * Wa_1407928979:tgl A* 2422 * Wa_18011464164:tgl[B0+],dg1[B0+] 2423 * Wa_22010931296:tgl[B0+],dg1[B0+] 2424 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2425 */ 2426 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2427 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2428 } 2429 2430 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2431 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2432 /* 2433 * Wa_1606700617:tgl,dg1,adl-p 2434 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2435 * Wa_14010826681:tgl,dg1,rkl,adl-p 2436 * Wa_18019627453:dg2 2437 */ 2438 wa_masked_en(wal, 2439 GEN9_CS_DEBUG_MODE1, 2440 FF_DOP_CLOCK_GATE_DISABLE); 2441 } 2442 2443 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2444 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2445 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2446 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2447 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2448 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2449 2450 /* 2451 * Wa_1409085225:tgl 2452 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2453 */ 2454 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2455 } 2456 2457 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2458 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2459 /* 2460 * Wa_1607030317:tgl 2461 * Wa_1607186500:tgl 2462 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2463 * 2464 * On TGL and RKL there are multiple entries for this WA in the 2465 * BSpec; some indicate this is an A0-only WA, others indicate 2466 * it applies to all steppings so we trust the "all steppings." 2467 * For DG1 this only applies to A0. 2468 */ 2469 wa_masked_en(wal, 2470 RING_PSMI_CTL(RENDER_RING_BASE), 2471 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2472 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2473 } 2474 2475 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2476 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2477 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2478 wa_mcr_masked_en(wal, 2479 GEN10_SAMPLER_MODE, 2480 ENABLE_SMALLPL); 2481 } 2482 2483 if (GRAPHICS_VER(i915) == 11) { 2484 /* This is not an Wa. Enable for better image quality */ 2485 wa_masked_en(wal, 2486 _3D_CHICKEN3, 2487 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2488 2489 /* 2490 * Wa_1405543622:icl 2491 * Formerly known as WaGAPZPriorityScheme 2492 */ 2493 wa_write_or(wal, 2494 GEN8_GARBCNTL, 2495 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2496 2497 /* 2498 * Wa_1604223664:icl 2499 * Formerly known as WaL3BankAddressHashing 2500 */ 2501 wa_write_clr_set(wal, 2502 GEN8_GARBCNTL, 2503 GEN11_HASH_CTRL_EXCL_MASK, 2504 GEN11_HASH_CTRL_EXCL_BIT0); 2505 wa_write_clr_set(wal, 2506 GEN11_GLBLINVL, 2507 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2508 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2509 2510 /* 2511 * Wa_1405733216:icl 2512 * Formerly known as WaDisableCleanEvicts 2513 */ 2514 wa_mcr_write_or(wal, 2515 GEN8_L3SQCREG4, 2516 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2517 2518 /* Wa_1606682166:icl */ 2519 wa_write_or(wal, 2520 GEN7_SARCHKMD, 2521 GEN7_DISABLE_SAMPLER_PREFETCH); 2522 2523 /* Wa_1409178092:icl */ 2524 wa_mcr_write_clr_set(wal, 2525 GEN11_SCRATCH2, 2526 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2527 0); 2528 2529 /* WaEnable32PlaneMode:icl */ 2530 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2531 GEN11_ENABLE_32_PLANE_MODE); 2532 2533 /* 2534 * Wa_1408615072:icl,ehl (vsunit) 2535 * Wa_1407596294:icl,ehl (hsunit) 2536 */ 2537 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2538 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2539 2540 /* 2541 * Wa_1408767742:icl[a2..forever],ehl[all] 2542 * Wa_1605460711:icl[a0..c0] 2543 */ 2544 wa_write_or(wal, 2545 GEN7_FF_THREAD_MODE, 2546 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2547 2548 /* Wa_22010271021 */ 2549 wa_masked_en(wal, 2550 GEN9_CS_DEBUG_MODE1, 2551 FF_DOP_CLOCK_GATE_DISABLE); 2552 } 2553 2554 /* 2555 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2556 * beyond) allow the kernel-mode driver to choose between two different 2557 * options for controlling preemption granularity and behavior. 2558 * 2559 * Option 1 (hardware default): 2560 * Preemption settings are controlled in a global manner via 2561 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2562 * and settings chosen by the kernel-mode driver will apply to all 2563 * userspace clients. 2564 * 2565 * Option 2: 2566 * Preemption settings are controlled on a per-context basis via 2567 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2568 * context switch and is writable by userspace (e.g., via 2569 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2570 * which allows different userspace drivers/clients to select 2571 * different settings, or to change those settings on the fly in 2572 * response to runtime needs. This option was known by name 2573 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2574 * that name is somewhat misleading as other non-granularity 2575 * preemption settings are also impacted by this decision. 2576 * 2577 * On Linux, our policy has always been to let userspace drivers 2578 * control preemption granularity/settings (Option 2). This was 2579 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2580 * userspace developed before object-level preemption was enabled would 2581 * not behave well if i915 were to go with Option 1 and enable that 2582 * preemption in a global manner). On gen9 each context would have 2583 * object-level preemption disabled by default (see 2584 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2585 * userspace drivers could opt-in to object-level preemption as they 2586 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2587 * even though it is no longer necessary for ABI compatibility when 2588 * enabling a new platform, it does ensure that userspace will be able 2589 * to implement any workarounds that show up requiring temporary 2590 * adjustments to preemption behavior at runtime. 2591 * 2592 * Notes/Workarounds: 2593 * - Wa_14015141709: On DG2 and early steppings of MTL, 2594 * CS_CHICKEN1[0] does not disable object-level preemption as 2595 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2596 * using Option 1). Effectively this means userspace is unable 2597 * to disable object-level preemption on these platforms/steppings 2598 * despite the setting here. 2599 * 2600 * - Wa_16013994831: May require that userspace program 2601 * CS_CHICKEN1[10] when certain runtime conditions are true. 2602 * Userspace requires Option 2 to be in effect for their update of 2603 * CS_CHICKEN1[10] to be effective. 2604 * 2605 * Other workarounds may appear in the future that will also require 2606 * Option 2 behavior to allow proper userspace implementation. 2607 */ 2608 if (GRAPHICS_VER(i915) >= 9) 2609 wa_masked_en(wal, 2610 GEN7_FF_SLICE_CS_CHICKEN1, 2611 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2612 2613 if (IS_SKYLAKE(i915) || 2614 IS_KABYLAKE(i915) || 2615 IS_COFFEELAKE(i915) || 2616 IS_COMETLAKE(i915)) { 2617 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2618 wa_write_or(wal, 2619 GEN8_GARBCNTL, 2620 GEN9_GAPS_TSV_CREDIT_DISABLE); 2621 } 2622 2623 if (IS_BROXTON(i915)) { 2624 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2625 wa_masked_en(wal, 2626 FF_SLICE_CS_CHICKEN2, 2627 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2628 } 2629 2630 if (GRAPHICS_VER(i915) == 9) { 2631 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2632 wa_masked_en(wal, 2633 GEN9_CSFE_CHICKEN1_RCS, 2634 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2635 2636 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2637 wa_mcr_write_or(wal, 2638 BDW_SCRATCH1, 2639 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2640 2641 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2642 if (IS_GEN9_LP(i915)) 2643 wa_mcr_write_clr_set(wal, 2644 GEN8_L3SQCREG1, 2645 L3_PRIO_CREDITS_MASK, 2646 L3_GENERAL_PRIO_CREDITS(62) | 2647 L3_HIGH_PRIO_CREDITS(2)); 2648 2649 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2650 wa_mcr_write_or(wal, 2651 GEN8_L3SQCREG4, 2652 GEN8_LQSC_FLUSH_COHERENT_LINES); 2653 2654 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2655 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2656 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2657 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2658 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2659 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2660 EVICTION_PERF_FIX_ENABLE, 0); 2661 } 2662 2663 if (IS_HASWELL(i915)) { 2664 /* WaSampleCChickenBitEnable:hsw */ 2665 wa_masked_en(wal, 2666 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2667 2668 wa_masked_dis(wal, 2669 CACHE_MODE_0_GEN7, 2670 /* enable HiZ Raw Stall Optimization */ 2671 HIZ_RAW_STALL_OPT_DISABLE); 2672 } 2673 2674 if (IS_VALLEYVIEW(i915)) { 2675 /* WaDisableEarlyCull:vlv */ 2676 wa_masked_en(wal, 2677 _3D_CHICKEN3, 2678 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2679 2680 /* 2681 * WaVSThreadDispatchOverride:ivb,vlv 2682 * 2683 * This actually overrides the dispatch 2684 * mode for all thread types. 2685 */ 2686 wa_write_clr_set(wal, 2687 GEN7_FF_THREAD_MODE, 2688 GEN7_FF_SCHED_MASK, 2689 GEN7_FF_TS_SCHED_HW | 2690 GEN7_FF_VS_SCHED_HW | 2691 GEN7_FF_DS_SCHED_HW); 2692 2693 /* WaPsdDispatchEnable:vlv */ 2694 /* WaDisablePSDDualDispatchEnable:vlv */ 2695 wa_masked_en(wal, 2696 GEN7_HALF_SLICE_CHICKEN1, 2697 GEN7_MAX_PS_THREAD_DEP | 2698 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2699 } 2700 2701 if (IS_IVYBRIDGE(i915)) { 2702 /* WaDisableEarlyCull:ivb */ 2703 wa_masked_en(wal, 2704 _3D_CHICKEN3, 2705 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2706 2707 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2708 /* enable HiZ Raw Stall Optimization */ 2709 wa_masked_dis(wal, 2710 CACHE_MODE_0_GEN7, 2711 HIZ_RAW_STALL_OPT_DISABLE); 2712 } 2713 2714 /* 2715 * WaVSThreadDispatchOverride:ivb,vlv 2716 * 2717 * This actually overrides the dispatch 2718 * mode for all thread types. 2719 */ 2720 wa_write_clr_set(wal, 2721 GEN7_FF_THREAD_MODE, 2722 GEN7_FF_SCHED_MASK, 2723 GEN7_FF_TS_SCHED_HW | 2724 GEN7_FF_VS_SCHED_HW | 2725 GEN7_FF_DS_SCHED_HW); 2726 2727 /* WaDisablePSDDualDispatchEnable:ivb */ 2728 if (IS_IVB_GT1(i915)) 2729 wa_masked_en(wal, 2730 GEN7_HALF_SLICE_CHICKEN1, 2731 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2732 } 2733 2734 if (GRAPHICS_VER(i915) == 7) { 2735 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2736 wa_masked_en(wal, 2737 RING_MODE_GEN7(RENDER_RING_BASE), 2738 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2739 2740 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2741 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2742 2743 /* 2744 * BSpec says this must be set, even though 2745 * WaDisable4x2SubspanOptimization:ivb,hsw 2746 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2747 */ 2748 wa_masked_en(wal, 2749 CACHE_MODE_1, 2750 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2751 2752 /* 2753 * BSpec recommends 8x4 when MSAA is used, 2754 * however in practice 16x4 seems fastest. 2755 * 2756 * Note that PS/WM thread counts depend on the WIZ hashing 2757 * disable bit, which we don't touch here, but it's good 2758 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2759 */ 2760 wa_masked_field_set(wal, 2761 GEN7_GT_MODE, 2762 GEN6_WIZ_HASHING_MASK, 2763 GEN6_WIZ_HASHING_16x4); 2764 } 2765 2766 if (IS_GRAPHICS_VER(i915, 6, 7)) 2767 /* 2768 * We need to disable the AsyncFlip performance optimisations in 2769 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2770 * already be programmed to '1' on all products. 2771 * 2772 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2773 */ 2774 wa_masked_en(wal, 2775 RING_MI_MODE(RENDER_RING_BASE), 2776 ASYNC_FLIP_PERF_DISABLE); 2777 2778 if (GRAPHICS_VER(i915) == 6) { 2779 /* 2780 * Required for the hardware to program scanline values for 2781 * waiting 2782 * WaEnableFlushTlbInvalidationMode:snb 2783 */ 2784 wa_masked_en(wal, 2785 GFX_MODE, 2786 GFX_TLB_INVALIDATE_EXPLICIT); 2787 2788 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2789 wa_masked_en(wal, 2790 _3D_CHICKEN, 2791 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2792 2793 wa_masked_en(wal, 2794 _3D_CHICKEN3, 2795 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2796 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2797 /* 2798 * Bspec says: 2799 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2800 * to normal and 3DSTATE_SF number of SF output attributes 2801 * is more than 16." 2802 */ 2803 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2804 2805 /* 2806 * BSpec recommends 8x4 when MSAA is used, 2807 * however in practice 16x4 seems fastest. 2808 * 2809 * Note that PS/WM thread counts depend on the WIZ hashing 2810 * disable bit, which we don't touch here, but it's good 2811 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2812 */ 2813 wa_masked_field_set(wal, 2814 GEN6_GT_MODE, 2815 GEN6_WIZ_HASHING_MASK, 2816 GEN6_WIZ_HASHING_16x4); 2817 2818 /* WaDisable_RenderCache_OperationalFlush:snb */ 2819 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2820 2821 /* 2822 * From the Sandybridge PRM, volume 1 part 3, page 24: 2823 * "If this bit is set, STCunit will have LRA as replacement 2824 * policy. [...] This bit must be reset. LRA replacement 2825 * policy is not supported." 2826 */ 2827 wa_masked_dis(wal, 2828 CACHE_MODE_0, 2829 CM0_STC_EVICT_DISABLE_LRA_SNB); 2830 } 2831 2832 if (IS_GRAPHICS_VER(i915, 4, 6)) 2833 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2834 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2835 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2836 /* XXX bit doesn't stick on Broadwater */ 2837 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2838 2839 if (GRAPHICS_VER(i915) == 4) 2840 /* 2841 * Disable CONSTANT_BUFFER before it is loaded from the context 2842 * image. For as it is loaded, it is executed and the stored 2843 * address may no longer be valid, leading to a GPU hang. 2844 * 2845 * This imposes the requirement that userspace reload their 2846 * CONSTANT_BUFFER on every batch, fortunately a requirement 2847 * they are already accustomed to from before contexts were 2848 * enabled. 2849 */ 2850 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2851 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2852 0 /* XXX bit doesn't stick on Broadwater */, 2853 true); 2854 } 2855 2856 static void 2857 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2858 { 2859 struct drm_i915_private *i915 = engine->i915; 2860 2861 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2862 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2863 wa_write(wal, 2864 RING_SEMA_WAIT_POLL(engine->mmio_base), 2865 1); 2866 } 2867 } 2868 2869 static void 2870 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2871 { 2872 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2873 /* Wa_14014999345:pvc */ 2874 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2875 } 2876 } 2877 2878 /* 2879 * The bspec performance guide has recommended MMIO tuning settings. These 2880 * aren't truly "workarounds" but we want to program them with the same 2881 * workaround infrastructure to ensure that they're automatically added to 2882 * the GuC save/restore lists, re-applied at the right times, and checked for 2883 * any conflicting programming requested by real workarounds. 2884 * 2885 * Programming settings should be added here only if their registers are not 2886 * part of an engine's register state context. If a register is part of a 2887 * context, then any tuning settings should be programmed in an appropriate 2888 * function invoked by __intel_engine_init_ctx_wa(). 2889 */ 2890 static void 2891 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2892 struct i915_wa_list *wal) 2893 { 2894 if (IS_PONTEVECCHIO(i915)) { 2895 wa_write(wal, XEHPC_L3SCRUB, 2896 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2897 } 2898 2899 if (IS_DG2(i915)) { 2900 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2901 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2902 2903 /* 2904 * This is also listed as Wa_22012654132 for certain DG2 2905 * steppings, but the tuning setting programming is a superset 2906 * since it applies to all DG2 variants and steppings. 2907 * 2908 * Note that register 0xE420 is write-only and cannot be read 2909 * back for verification on DG2 (due to Wa_14012342262), so 2910 * we need to explicitly skip the readback. 2911 */ 2912 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2913 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2914 0 /* write-only, so skip validation */, 2915 true); 2916 } 2917 2918 /* 2919 * This tuning setting proves beneficial only on ATS-M designs; the 2920 * default "age based" setting is optimal on regular DG2 and other 2921 * platforms. 2922 */ 2923 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2924 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2925 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2926 } 2927 2928 /* 2929 * The workarounds in this function apply to shared registers in 2930 * the general render reset domain that aren't tied to a 2931 * specific engine. Since all render+compute engines get reset 2932 * together, and the contents of these registers are lost during 2933 * the shared render domain reset, we'll define such workarounds 2934 * here and then add them to just a single RCS or CCS engine's 2935 * workaround list (whichever engine has the XXXX flag). 2936 */ 2937 static void 2938 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2939 { 2940 struct drm_i915_private *i915 = engine->i915; 2941 2942 add_render_compute_tuning_settings(i915, wal); 2943 2944 if (IS_PONTEVECCHIO(i915)) { 2945 /* Wa_16016694945 */ 2946 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 2947 } 2948 2949 if (IS_XEHPSDV(i915)) { 2950 /* Wa_1409954639 */ 2951 wa_mcr_masked_en(wal, 2952 GEN8_ROW_CHICKEN, 2953 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2954 2955 /* Wa_1607196519 */ 2956 wa_mcr_masked_en(wal, 2957 GEN9_ROW_CHICKEN4, 2958 GEN12_DISABLE_GRF_CLEAR); 2959 2960 /* Wa_14010670810:xehpsdv */ 2961 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2962 2963 /* Wa_14010449647:xehpsdv */ 2964 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2965 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2966 2967 /* Wa_18011725039:xehpsdv */ 2968 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2969 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2970 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2971 } 2972 2973 /* Wa_14012362059:xehpsdv */ 2974 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2975 2976 /* Wa_14014368820:xehpsdv */ 2977 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2978 GLOBAL_INVALIDATION_MODE); 2979 } 2980 2981 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 2982 /* Wa_14015227452:dg2,pvc */ 2983 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2984 2985 /* Wa_22014226127:dg2,pvc */ 2986 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2987 2988 /* Wa_16015675438:dg2,pvc */ 2989 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2990 2991 /* Wa_18018781329:dg2,pvc */ 2992 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2993 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2994 wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2995 wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2996 } 2997 2998 if (IS_DG2(i915)) { 2999 /* 3000 * Wa_16011620976:dg2_g11 3001 * Wa_22015475538:dg2 3002 */ 3003 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3004 3005 /* Wa_18017747507:dg2 */ 3006 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3007 } 3008 } 3009 3010 static void 3011 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3012 { 3013 if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4)) 3014 return; 3015 3016 engine_fake_wa_init(engine, wal); 3017 3018 /* 3019 * These are common workarounds that just need to applied 3020 * to a single RCS/CCS engine's workaround list since 3021 * they're reset as part of the general render domain reset. 3022 */ 3023 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3024 general_render_compute_wa_init(engine, wal); 3025 3026 if (engine->class == COMPUTE_CLASS) 3027 ccs_engine_wa_init(engine, wal); 3028 else if (engine->class == RENDER_CLASS) 3029 rcs_engine_wa_init(engine, wal); 3030 else 3031 xcs_engine_wa_init(engine, wal); 3032 } 3033 3034 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3035 { 3036 struct i915_wa_list *wal = &engine->wa_list; 3037 3038 if (GRAPHICS_VER(engine->i915) < 4) 3039 return; 3040 3041 wa_init_start(wal, engine->gt, "engine", engine->name); 3042 engine_init_workarounds(engine, wal); 3043 wa_init_finish(wal); 3044 } 3045 3046 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3047 { 3048 wa_list_apply(&engine->wa_list); 3049 } 3050 3051 static const struct i915_range mcr_ranges_gen8[] = { 3052 { .start = 0x5500, .end = 0x55ff }, 3053 { .start = 0x7000, .end = 0x7fff }, 3054 { .start = 0x9400, .end = 0x97ff }, 3055 { .start = 0xb000, .end = 0xb3ff }, 3056 { .start = 0xe000, .end = 0xe7ff }, 3057 {}, 3058 }; 3059 3060 static const struct i915_range mcr_ranges_gen12[] = { 3061 { .start = 0x8150, .end = 0x815f }, 3062 { .start = 0x9520, .end = 0x955f }, 3063 { .start = 0xb100, .end = 0xb3ff }, 3064 { .start = 0xde80, .end = 0xe8ff }, 3065 { .start = 0x24a00, .end = 0x24a7f }, 3066 {}, 3067 }; 3068 3069 static const struct i915_range mcr_ranges_xehp[] = { 3070 { .start = 0x4000, .end = 0x4aff }, 3071 { .start = 0x5200, .end = 0x52ff }, 3072 { .start = 0x5400, .end = 0x7fff }, 3073 { .start = 0x8140, .end = 0x815f }, 3074 { .start = 0x8c80, .end = 0x8dff }, 3075 { .start = 0x94d0, .end = 0x955f }, 3076 { .start = 0x9680, .end = 0x96ff }, 3077 { .start = 0xb000, .end = 0xb3ff }, 3078 { .start = 0xc800, .end = 0xcfff }, 3079 { .start = 0xd800, .end = 0xd8ff }, 3080 { .start = 0xdc00, .end = 0xffff }, 3081 { .start = 0x17000, .end = 0x17fff }, 3082 { .start = 0x24a00, .end = 0x24a7f }, 3083 {}, 3084 }; 3085 3086 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3087 { 3088 const struct i915_range *mcr_ranges; 3089 int i; 3090 3091 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3092 mcr_ranges = mcr_ranges_xehp; 3093 else if (GRAPHICS_VER(i915) >= 12) 3094 mcr_ranges = mcr_ranges_gen12; 3095 else if (GRAPHICS_VER(i915) >= 8) 3096 mcr_ranges = mcr_ranges_gen8; 3097 else 3098 return false; 3099 3100 /* 3101 * Registers in these ranges are affected by the MCR selector 3102 * which only controls CPU initiated MMIO. Routing does not 3103 * work for CS access so we cannot verify them on this path. 3104 */ 3105 for (i = 0; mcr_ranges[i].start; i++) 3106 if (offset >= mcr_ranges[i].start && 3107 offset <= mcr_ranges[i].end) 3108 return true; 3109 3110 return false; 3111 } 3112 3113 static int 3114 wa_list_srm(struct i915_request *rq, 3115 const struct i915_wa_list *wal, 3116 struct i915_vma *vma) 3117 { 3118 struct drm_i915_private *i915 = rq->engine->i915; 3119 unsigned int i, count = 0; 3120 const struct i915_wa *wa; 3121 u32 srm, *cs; 3122 3123 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3124 if (GRAPHICS_VER(i915) >= 8) 3125 srm++; 3126 3127 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3128 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3129 count++; 3130 } 3131 3132 cs = intel_ring_begin(rq, 4 * count); 3133 if (IS_ERR(cs)) 3134 return PTR_ERR(cs); 3135 3136 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3137 u32 offset = i915_mmio_reg_offset(wa->reg); 3138 3139 if (mcr_range(i915, offset)) 3140 continue; 3141 3142 *cs++ = srm; 3143 *cs++ = offset; 3144 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3145 *cs++ = 0; 3146 } 3147 intel_ring_advance(rq, cs); 3148 3149 return 0; 3150 } 3151 3152 static int engine_wa_list_verify(struct intel_context *ce, 3153 const struct i915_wa_list * const wal, 3154 const char *from) 3155 { 3156 const struct i915_wa *wa; 3157 struct i915_request *rq; 3158 struct i915_vma *vma; 3159 struct i915_gem_ww_ctx ww; 3160 unsigned int i; 3161 u32 *results; 3162 int err; 3163 3164 if (!wal->count) 3165 return 0; 3166 3167 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3168 wal->count * sizeof(u32)); 3169 if (IS_ERR(vma)) 3170 return PTR_ERR(vma); 3171 3172 intel_engine_pm_get(ce->engine); 3173 i915_gem_ww_ctx_init(&ww, false); 3174 retry: 3175 err = i915_gem_object_lock(vma->obj, &ww); 3176 if (err == 0) 3177 err = intel_context_pin_ww(ce, &ww); 3178 if (err) 3179 goto err_pm; 3180 3181 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3182 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3183 if (err) 3184 goto err_unpin; 3185 3186 rq = i915_request_create(ce); 3187 if (IS_ERR(rq)) { 3188 err = PTR_ERR(rq); 3189 goto err_vma; 3190 } 3191 3192 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3193 if (err == 0) 3194 err = wa_list_srm(rq, wal, vma); 3195 3196 i915_request_get(rq); 3197 if (err) 3198 i915_request_set_error_once(rq, err); 3199 i915_request_add(rq); 3200 3201 if (err) 3202 goto err_rq; 3203 3204 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3205 err = -ETIME; 3206 goto err_rq; 3207 } 3208 3209 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3210 if (IS_ERR(results)) { 3211 err = PTR_ERR(results); 3212 goto err_rq; 3213 } 3214 3215 err = 0; 3216 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3217 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3218 continue; 3219 3220 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3221 err = -ENXIO; 3222 } 3223 3224 i915_gem_object_unpin_map(vma->obj); 3225 3226 err_rq: 3227 i915_request_put(rq); 3228 err_vma: 3229 i915_vma_unpin(vma); 3230 err_unpin: 3231 intel_context_unpin(ce); 3232 err_pm: 3233 if (err == -EDEADLK) { 3234 err = i915_gem_ww_ctx_backoff(&ww); 3235 if (!err) 3236 goto retry; 3237 } 3238 i915_gem_ww_ctx_fini(&ww); 3239 intel_engine_pm_put(ce->engine); 3240 i915_vma_put(vma); 3241 return err; 3242 } 3243 3244 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3245 const char *from) 3246 { 3247 return engine_wa_list_verify(engine->kernel_context, 3248 &engine->wa_list, 3249 from); 3250 } 3251 3252 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3253 #include "selftest_workarounds.c" 3254 #endif 3255