1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 /* 56 * KBL revision ID ordering is bizarre; higher revision ID's map to lower 57 * steppings in some cases. So rather than test against the revision ID 58 * directly, let's map that into our own range of increasing ID's that we 59 * can test against in a regular manner. 60 */ 61 62 const struct i915_rev_steppings kbl_revids[] = { 63 [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, 64 [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, 65 [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, 66 [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, 67 [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, 68 [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, 69 [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, 70 [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, 71 }; 72 73 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 74 { 75 wal->name = name; 76 wal->engine_name = engine_name; 77 } 78 79 #define WA_LIST_CHUNK (1 << 4) 80 81 static void wa_init_finish(struct i915_wa_list *wal) 82 { 83 /* Trim unused entries. */ 84 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 85 struct i915_wa *list = kmemdup(wal->list, 86 wal->count * sizeof(*list), 87 GFP_KERNEL); 88 89 if (list) { 90 kfree(wal->list); 91 wal->list = list; 92 } 93 } 94 95 if (!wal->count) 96 return; 97 98 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 99 wal->wa_count, wal->name, wal->engine_name); 100 } 101 102 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 103 { 104 unsigned int addr = i915_mmio_reg_offset(wa->reg); 105 unsigned int start = 0, end = wal->count; 106 const unsigned int grow = WA_LIST_CHUNK; 107 struct i915_wa *wa_; 108 109 GEM_BUG_ON(!is_power_of_2(grow)); 110 111 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 112 struct i915_wa *list; 113 114 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 115 GFP_KERNEL); 116 if (!list) { 117 DRM_ERROR("No space for workaround init!\n"); 118 return; 119 } 120 121 if (wal->list) 122 memcpy(list, wal->list, sizeof(*wa) * wal->count); 123 124 wal->list = list; 125 } 126 127 while (start < end) { 128 unsigned int mid = start + (end - start) / 2; 129 130 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 131 start = mid + 1; 132 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 133 end = mid; 134 } else { 135 wa_ = &wal->list[mid]; 136 137 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 138 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 139 i915_mmio_reg_offset(wa_->reg), 140 wa_->clr, wa_->set); 141 142 wa_->set &= ~wa->clr; 143 } 144 145 wal->wa_count++; 146 wa_->set |= wa->set; 147 wa_->clr |= wa->clr; 148 wa_->read |= wa->read; 149 return; 150 } 151 } 152 153 wal->wa_count++; 154 wa_ = &wal->list[wal->count++]; 155 *wa_ = *wa; 156 157 while (wa_-- > wal->list) { 158 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 159 i915_mmio_reg_offset(wa_[1].reg)); 160 if (i915_mmio_reg_offset(wa_[1].reg) > 161 i915_mmio_reg_offset(wa_[0].reg)) 162 break; 163 164 swap(wa_[1], wa_[0]); 165 } 166 } 167 168 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 169 u32 clear, u32 set, u32 read_mask) 170 { 171 struct i915_wa wa = { 172 .reg = reg, 173 .clr = clear, 174 .set = set, 175 .read = read_mask, 176 }; 177 178 _wa_add(wal, &wa); 179 } 180 181 static void 182 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 183 { 184 wa_add(wal, reg, clear, set, clear); 185 } 186 187 static void 188 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 189 { 190 wa_write_masked_or(wal, reg, ~0, set); 191 } 192 193 static void 194 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 195 { 196 wa_write_masked_or(wal, reg, set, set); 197 } 198 199 static void 200 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 201 { 202 wa_write_masked_or(wal, reg, clr, 0); 203 } 204 205 static void 206 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 207 { 208 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 209 } 210 211 static void 212 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 213 { 214 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 215 } 216 217 #define WA_SET_BIT_MASKED(addr, mask) \ 218 wa_masked_en(wal, (addr), (mask)) 219 220 #define WA_CLR_BIT_MASKED(addr, mask) \ 221 wa_masked_dis(wal, (addr), (mask)) 222 223 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 224 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 225 226 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 227 struct i915_wa_list *wal) 228 { 229 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 230 } 231 232 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 233 struct i915_wa_list *wal) 234 { 235 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 236 } 237 238 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 239 struct i915_wa_list *wal) 240 { 241 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 242 243 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 244 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 245 246 /* WaDisablePartialInstShootdown:bdw,chv */ 247 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 248 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 249 250 /* Use Force Non-Coherent whenever executing a 3D context. This is a 251 * workaround for for a possible hang in the unlikely event a TLB 252 * invalidation occurs during a PSD flush. 253 */ 254 /* WaForceEnableNonCoherent:bdw,chv */ 255 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 256 WA_SET_BIT_MASKED(HDC_CHICKEN0, 257 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 258 HDC_FORCE_NON_COHERENT); 259 260 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 261 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 262 * polygons in the same 8x4 pixel/sample area to be processed without 263 * stalling waiting for the earlier ones to write to Hierarchical Z 264 * buffer." 265 * 266 * This optimization is off by default for BDW and CHV; turn it on. 267 */ 268 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 269 270 /* Wa4x4STCOptimizationDisable:bdw,chv */ 271 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 272 273 /* 274 * BSpec recommends 8x4 when MSAA is used, 275 * however in practice 16x4 seems fastest. 276 * 277 * Note that PS/WM thread counts depend on the WIZ hashing 278 * disable bit, which we don't touch here, but it's good 279 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 280 */ 281 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 282 GEN6_WIZ_HASHING_MASK, 283 GEN6_WIZ_HASHING_16x4); 284 } 285 286 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 287 struct i915_wa_list *wal) 288 { 289 struct drm_i915_private *i915 = engine->i915; 290 291 gen8_ctx_workarounds_init(engine, wal); 292 293 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 294 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 295 296 /* WaDisableDopClockGating:bdw 297 * 298 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 299 * to disable EUTC clock gating. 300 */ 301 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 302 DOP_CLOCK_GATING_DISABLE); 303 304 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 305 GEN8_SAMPLER_POWER_BYPASS_DIS); 306 307 WA_SET_BIT_MASKED(HDC_CHICKEN0, 308 /* WaForceContextSaveRestoreNonCoherent:bdw */ 309 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 310 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 311 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 312 } 313 314 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 315 struct i915_wa_list *wal) 316 { 317 gen8_ctx_workarounds_init(engine, wal); 318 319 /* WaDisableThreadStallDopClockGating:chv */ 320 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 321 322 /* Improve HiZ throughput on CHV. */ 323 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 324 } 325 326 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 327 struct i915_wa_list *wal) 328 { 329 struct drm_i915_private *i915 = engine->i915; 330 331 if (HAS_LLC(i915)) { 332 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 333 * 334 * Must match Display Engine. See 335 * WaCompressedResourceDisplayNewHashMode. 336 */ 337 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 338 GEN9_PBE_COMPRESSED_HASH_SELECTION); 339 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 340 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 341 } 342 343 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 344 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 345 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 346 FLOW_CONTROL_ENABLE | 347 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 348 349 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 350 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 351 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 352 GEN9_ENABLE_YV12_BUGFIX | 353 GEN9_ENABLE_GPGPU_PREEMPTION); 354 355 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 356 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 357 WA_SET_BIT_MASKED(CACHE_MODE_1, 358 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 359 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 360 361 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 362 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 363 GEN9_CCS_TLB_PREFETCH_ENABLE); 364 365 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 366 WA_SET_BIT_MASKED(HDC_CHICKEN0, 367 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 368 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 369 370 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 371 * both tied to WaForceContextSaveRestoreNonCoherent 372 * in some hsds for skl. We keep the tie for all gen9. The 373 * documentation is a bit hazy and so we want to get common behaviour, 374 * even though there is no clear evidence we would need both on kbl/bxt. 375 * This area has been source of system hangs so we play it safe 376 * and mimic the skl regardless of what bspec says. 377 * 378 * Use Force Non-Coherent whenever executing a 3D context. This 379 * is a workaround for a possible hang in the unlikely event 380 * a TLB invalidation occurs during a PSD flush. 381 */ 382 383 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 384 WA_SET_BIT_MASKED(HDC_CHICKEN0, 385 HDC_FORCE_NON_COHERENT); 386 387 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 388 if (IS_SKYLAKE(i915) || 389 IS_KABYLAKE(i915) || 390 IS_COFFEELAKE(i915) || 391 IS_COMETLAKE(i915)) 392 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 393 GEN8_SAMPLER_POWER_BYPASS_DIS); 394 395 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 396 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 397 398 /* 399 * Supporting preemption with fine-granularity requires changes in the 400 * batch buffer programming. Since we can't break old userspace, we 401 * need to set our default preemption level to safe value. Userspace is 402 * still able to use more fine-grained preemption levels, since in 403 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 404 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 405 * not real HW workarounds, but merely a way to start using preemption 406 * while maintaining old contract with userspace. 407 */ 408 409 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 410 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 411 412 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 413 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 414 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 415 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 416 417 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 418 if (IS_GEN9_LP(i915)) 419 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 420 } 421 422 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 423 struct i915_wa_list *wal) 424 { 425 struct intel_gt *gt = engine->gt; 426 u8 vals[3] = { 0, 0, 0 }; 427 unsigned int i; 428 429 for (i = 0; i < 3; i++) { 430 u8 ss; 431 432 /* 433 * Only consider slices where one, and only one, subslice has 7 434 * EUs 435 */ 436 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 437 continue; 438 439 /* 440 * subslice_7eu[i] != 0 (because of the check above) and 441 * ss_max == 4 (maximum number of subslices possible per slice) 442 * 443 * -> 0 <= ss <= 3; 444 */ 445 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 446 vals[i] = 3 - ss; 447 } 448 449 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 450 return; 451 452 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 453 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 454 GEN9_IZ_HASHING_MASK(2) | 455 GEN9_IZ_HASHING_MASK(1) | 456 GEN9_IZ_HASHING_MASK(0), 457 GEN9_IZ_HASHING(2, vals[2]) | 458 GEN9_IZ_HASHING(1, vals[1]) | 459 GEN9_IZ_HASHING(0, vals[0])); 460 } 461 462 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 463 struct i915_wa_list *wal) 464 { 465 gen9_ctx_workarounds_init(engine, wal); 466 skl_tune_iz_hashing(engine, wal); 467 } 468 469 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 470 struct i915_wa_list *wal) 471 { 472 gen9_ctx_workarounds_init(engine, wal); 473 474 /* WaDisableThreadStallDopClockGating:bxt */ 475 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 476 STALL_DOP_GATING_DISABLE); 477 478 /* WaToEnableHwFixForPushConstHWBug:bxt */ 479 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 480 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 481 } 482 483 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 484 struct i915_wa_list *wal) 485 { 486 struct drm_i915_private *i915 = engine->i915; 487 488 gen9_ctx_workarounds_init(engine, wal); 489 490 /* WaToEnableHwFixForPushConstHWBug:kbl */ 491 if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 492 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 493 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 494 495 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 496 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 497 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 498 } 499 500 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 501 struct i915_wa_list *wal) 502 { 503 gen9_ctx_workarounds_init(engine, wal); 504 505 /* WaToEnableHwFixForPushConstHWBug:glk */ 506 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 507 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 508 } 509 510 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 511 struct i915_wa_list *wal) 512 { 513 gen9_ctx_workarounds_init(engine, wal); 514 515 /* WaToEnableHwFixForPushConstHWBug:cfl */ 516 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 517 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 518 519 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 520 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 521 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 522 } 523 524 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 525 struct i915_wa_list *wal) 526 { 527 /* WaForceContextSaveRestoreNonCoherent:cnl */ 528 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 529 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 530 531 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 532 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 533 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 534 535 /* WaPushConstantDereferenceHoldDisable:cnl */ 536 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 537 538 /* FtrEnableFastAnisoL1BankingFix:cnl */ 539 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 540 541 /* WaDisable3DMidCmdPreemption:cnl */ 542 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 543 544 /* WaDisableGPGPUMidCmdPreemption:cnl */ 545 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 546 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 547 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 548 549 /* WaDisableEarlyEOT:cnl */ 550 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 551 } 552 553 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 554 struct i915_wa_list *wal) 555 { 556 struct drm_i915_private *i915 = engine->i915; 557 558 /* WaDisableBankHangMode:icl */ 559 wa_write(wal, 560 GEN8_L3CNTLREG, 561 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 562 GEN8_ERRDETBCTRL); 563 564 /* Wa_1604370585:icl (pre-prod) 565 * Formerly known as WaPushConstantDereferenceHoldDisable 566 */ 567 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 568 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 569 PUSH_CONSTANT_DEREF_DISABLE); 570 571 /* WaForceEnableNonCoherent:icl 572 * This is not the same workaround as in early Gen9 platforms, where 573 * lacking this could cause system hangs, but coherency performance 574 * overhead is high and only a few compute workloads really need it 575 * (the register is whitelisted in hardware now, so UMDs can opt in 576 * for coherency if they have a good reason). 577 */ 578 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 579 580 /* Wa_2006611047:icl (pre-prod) 581 * Formerly known as WaDisableImprovedTdlClkGating 582 */ 583 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 584 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 585 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 586 587 /* Wa_2006665173:icl (pre-prod) */ 588 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 589 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 590 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 591 592 /* WaEnableFloatBlendOptimization:icl */ 593 wa_write_masked_or(wal, 594 GEN10_CACHE_MODE_SS, 595 0, /* write-only, so skip validation */ 596 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 597 598 /* WaDisableGPGPUMidThreadPreemption:icl */ 599 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 600 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 601 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 602 603 /* allow headerless messages for preemptible GPGPU context */ 604 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 605 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 606 607 /* Wa_1604278689:icl,ehl */ 608 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 609 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 610 0, /* write-only register; skip validation */ 611 0xFFFFFFFF); 612 613 /* Wa_1406306137:icl,ehl */ 614 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 615 } 616 617 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 618 struct i915_wa_list *wal) 619 { 620 /* 621 * Wa_1409142259:tgl 622 * Wa_1409347922:tgl 623 * Wa_1409252684:tgl 624 * Wa_1409217633:tgl 625 * Wa_1409207793:tgl 626 * Wa_1409178076:tgl 627 * Wa_1408979724:tgl 628 * Wa_14010443199:rkl 629 * Wa_14010698770:rkl 630 */ 631 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 632 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 633 634 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 635 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 636 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 637 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 638 } 639 640 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 641 struct i915_wa_list *wal) 642 { 643 gen12_ctx_workarounds_init(engine, wal); 644 645 /* 646 * Wa_1604555607:tgl,rkl 647 * 648 * Note that the implementation of this workaround is further modified 649 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 650 * FF_MODE2 register will return the wrong value when read. The default 651 * value for this register is zero for all fields and there are no bit 652 * masks. So instead of doing a RMW we should just write the GS Timer 653 * and TDS timer values for Wa_1604555607 and Wa_16011163337. 654 */ 655 wa_add(wal, 656 FF_MODE2, 657 FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, 658 FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 659 0); 660 } 661 662 static void 663 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 664 struct i915_wa_list *wal, 665 const char *name) 666 { 667 struct drm_i915_private *i915 = engine->i915; 668 669 if (engine->class != RENDER_CLASS) 670 return; 671 672 wa_init_start(wal, name, engine->name); 673 674 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) 675 tgl_ctx_workarounds_init(engine, wal); 676 else if (IS_GEN(i915, 12)) 677 gen12_ctx_workarounds_init(engine, wal); 678 else if (IS_GEN(i915, 11)) 679 icl_ctx_workarounds_init(engine, wal); 680 else if (IS_CANNONLAKE(i915)) 681 cnl_ctx_workarounds_init(engine, wal); 682 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 683 cfl_ctx_workarounds_init(engine, wal); 684 else if (IS_GEMINILAKE(i915)) 685 glk_ctx_workarounds_init(engine, wal); 686 else if (IS_KABYLAKE(i915)) 687 kbl_ctx_workarounds_init(engine, wal); 688 else if (IS_BROXTON(i915)) 689 bxt_ctx_workarounds_init(engine, wal); 690 else if (IS_SKYLAKE(i915)) 691 skl_ctx_workarounds_init(engine, wal); 692 else if (IS_CHERRYVIEW(i915)) 693 chv_ctx_workarounds_init(engine, wal); 694 else if (IS_BROADWELL(i915)) 695 bdw_ctx_workarounds_init(engine, wal); 696 else if (IS_GEN(i915, 7)) 697 gen7_ctx_workarounds_init(engine, wal); 698 else if (IS_GEN(i915, 6)) 699 gen6_ctx_workarounds_init(engine, wal); 700 else if (INTEL_GEN(i915) < 8) 701 return; 702 else 703 MISSING_CASE(INTEL_GEN(i915)); 704 705 wa_init_finish(wal); 706 } 707 708 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 709 { 710 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 711 } 712 713 int intel_engine_emit_ctx_wa(struct i915_request *rq) 714 { 715 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 716 struct i915_wa *wa; 717 unsigned int i; 718 u32 *cs; 719 int ret; 720 721 if (wal->count == 0) 722 return 0; 723 724 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 725 if (ret) 726 return ret; 727 728 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 729 if (IS_ERR(cs)) 730 return PTR_ERR(cs); 731 732 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 733 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 734 *cs++ = i915_mmio_reg_offset(wa->reg); 735 *cs++ = wa->set; 736 } 737 *cs++ = MI_NOOP; 738 739 intel_ring_advance(rq, cs); 740 741 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 742 if (ret) 743 return ret; 744 745 return 0; 746 } 747 748 static void 749 gen4_gt_workarounds_init(struct drm_i915_private *i915, 750 struct i915_wa_list *wal) 751 { 752 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 753 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 754 } 755 756 static void 757 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 758 { 759 gen4_gt_workarounds_init(i915, wal); 760 761 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 762 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 763 } 764 765 static void 766 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 767 { 768 g4x_gt_workarounds_init(i915, wal); 769 770 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 771 } 772 773 static void 774 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 775 { 776 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 777 wa_masked_en(wal, 778 _3D_CHICKEN, 779 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 780 781 /* WaDisable_RenderCache_OperationalFlush:snb */ 782 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 783 784 /* 785 * BSpec recommends 8x4 when MSAA is used, 786 * however in practice 16x4 seems fastest. 787 * 788 * Note that PS/WM thread counts depend on the WIZ hashing 789 * disable bit, which we don't touch here, but it's good 790 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 791 */ 792 wa_add(wal, 793 GEN6_GT_MODE, 0, 794 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 795 GEN6_WIZ_HASHING_16x4); 796 797 wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); 798 799 wa_masked_en(wal, 800 _3D_CHICKEN3, 801 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 802 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 803 /* 804 * Bspec says: 805 * "This bit must be set if 3DSTATE_CLIP clip mode is set 806 * to normal and 3DSTATE_SF number of SF output attributes 807 * is more than 16." 808 */ 809 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 810 } 811 812 static void 813 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 814 { 815 /* WaDisableEarlyCull:ivb */ 816 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 817 818 /* WaDisablePSDDualDispatchEnable:ivb */ 819 if (IS_IVB_GT1(i915)) 820 wa_masked_en(wal, 821 GEN7_HALF_SLICE_CHICKEN1, 822 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 823 824 /* WaDisable_RenderCache_OperationalFlush:ivb */ 825 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 826 827 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 828 wa_masked_dis(wal, 829 GEN7_COMMON_SLICE_CHICKEN1, 830 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 831 832 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 833 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 834 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 835 836 /* WaForceL3Serialization:ivb */ 837 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 838 839 /* 840 * WaVSThreadDispatchOverride:ivb,vlv 841 * 842 * This actually overrides the dispatch 843 * mode for all thread types. 844 */ 845 wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, 846 GEN7_FF_SCHED_MASK, 847 GEN7_FF_TS_SCHED_HW | 848 GEN7_FF_VS_SCHED_HW | 849 GEN7_FF_DS_SCHED_HW); 850 851 if (0) { /* causes HiZ corruption on ivb:gt1 */ 852 /* enable HiZ Raw Stall Optimization */ 853 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 854 } 855 856 /* WaDisable4x2SubspanOptimization:ivb */ 857 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 858 859 /* 860 * BSpec recommends 8x4 when MSAA is used, 861 * however in practice 16x4 seems fastest. 862 * 863 * Note that PS/WM thread counts depend on the WIZ hashing 864 * disable bit, which we don't touch here, but it's good 865 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 866 */ 867 wa_add(wal, GEN7_GT_MODE, 0, 868 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 869 GEN6_WIZ_HASHING_16x4); 870 } 871 872 static void 873 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 874 { 875 /* WaDisableEarlyCull:vlv */ 876 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 877 878 /* WaPsdDispatchEnable:vlv */ 879 /* WaDisablePSDDualDispatchEnable:vlv */ 880 wa_masked_en(wal, 881 GEN7_HALF_SLICE_CHICKEN1, 882 GEN7_MAX_PS_THREAD_DEP | 883 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 884 885 /* WaDisable_RenderCache_OperationalFlush:vlv */ 886 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 887 888 /* WaForceL3Serialization:vlv */ 889 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 890 891 /* 892 * WaVSThreadDispatchOverride:ivb,vlv 893 * 894 * This actually overrides the dispatch 895 * mode for all thread types. 896 */ 897 wa_write_masked_or(wal, 898 GEN7_FF_THREAD_MODE, 899 GEN7_FF_SCHED_MASK, 900 GEN7_FF_TS_SCHED_HW | 901 GEN7_FF_VS_SCHED_HW | 902 GEN7_FF_DS_SCHED_HW); 903 904 /* 905 * BSpec says this must be set, even though 906 * WaDisable4x2SubspanOptimization isn't listed for VLV. 907 */ 908 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 909 910 /* 911 * BSpec recommends 8x4 when MSAA is used, 912 * however in practice 16x4 seems fastest. 913 * 914 * Note that PS/WM thread counts depend on the WIZ hashing 915 * disable bit, which we don't touch here, but it's good 916 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 917 */ 918 wa_add(wal, GEN7_GT_MODE, 0, 919 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 920 GEN6_WIZ_HASHING_16x4); 921 922 /* 923 * WaIncreaseL3CreditsForVLVB0:vlv 924 * This is the hardware default actually. 925 */ 926 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 927 } 928 929 static void 930 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 931 { 932 /* L3 caching of data atomics doesn't work -- disable it. */ 933 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 934 935 wa_add(wal, 936 HSW_ROW_CHICKEN3, 0, 937 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 938 0 /* XXX does this reg exist? */); 939 940 /* WaVSRefCountFullforceMissDisable:hsw */ 941 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 942 943 wa_masked_dis(wal, 944 CACHE_MODE_0_GEN7, 945 /* WaDisable_RenderCache_OperationalFlush:hsw */ 946 RC_OP_FLUSH_ENABLE | 947 /* enable HiZ Raw Stall Optimization */ 948 HIZ_RAW_STALL_OPT_DISABLE); 949 950 /* WaDisable4x2SubspanOptimization:hsw */ 951 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 952 953 /* 954 * BSpec recommends 8x4 when MSAA is used, 955 * however in practice 16x4 seems fastest. 956 * 957 * Note that PS/WM thread counts depend on the WIZ hashing 958 * disable bit, which we don't touch here, but it's good 959 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 960 */ 961 wa_add(wal, GEN7_GT_MODE, 0, 962 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 963 GEN6_WIZ_HASHING_16x4); 964 965 /* WaSampleCChickenBitEnable:hsw */ 966 wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 967 } 968 969 static void 970 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 971 { 972 /* WaDisableKillLogic:bxt,skl,kbl */ 973 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 974 wa_write_or(wal, 975 GAM_ECOCHK, 976 ECOCHK_DIS_TLB); 977 978 if (HAS_LLC(i915)) { 979 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 980 * 981 * Must match Display Engine. See 982 * WaCompressedResourceDisplayNewHashMode. 983 */ 984 wa_write_or(wal, 985 MMCD_MISC_CTRL, 986 MMCD_PCLA | MMCD_HOTSPOT_EN); 987 } 988 989 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 990 wa_write_or(wal, 991 GAM_ECOCHK, 992 BDW_DISABLE_HDC_INVALIDATION); 993 } 994 995 static void 996 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 997 { 998 gen9_gt_workarounds_init(i915, wal); 999 1000 /* WaDisableGafsUnitClkGating:skl */ 1001 wa_write_or(wal, 1002 GEN7_UCGCTL4, 1003 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1004 1005 /* WaInPlaceDecompressionHang:skl */ 1006 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 1007 wa_write_or(wal, 1008 GEN9_GAMT_ECO_REG_RW_IA, 1009 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1010 } 1011 1012 static void 1013 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1014 { 1015 gen9_gt_workarounds_init(i915, wal); 1016 1017 /* WaInPlaceDecompressionHang:bxt */ 1018 wa_write_or(wal, 1019 GEN9_GAMT_ECO_REG_RW_IA, 1020 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1021 } 1022 1023 static void 1024 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1025 { 1026 gen9_gt_workarounds_init(i915, wal); 1027 1028 /* WaDisableDynamicCreditSharing:kbl */ 1029 if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)) 1030 wa_write_or(wal, 1031 GAMT_CHKN_BIT_REG, 1032 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1033 1034 /* WaDisableGafsUnitClkGating:kbl */ 1035 wa_write_or(wal, 1036 GEN7_UCGCTL4, 1037 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1038 1039 /* WaInPlaceDecompressionHang:kbl */ 1040 wa_write_or(wal, 1041 GEN9_GAMT_ECO_REG_RW_IA, 1042 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1043 } 1044 1045 static void 1046 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1047 { 1048 gen9_gt_workarounds_init(i915, wal); 1049 } 1050 1051 static void 1052 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1053 { 1054 gen9_gt_workarounds_init(i915, wal); 1055 1056 /* WaDisableGafsUnitClkGating:cfl */ 1057 wa_write_or(wal, 1058 GEN7_UCGCTL4, 1059 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1060 1061 /* WaInPlaceDecompressionHang:cfl */ 1062 wa_write_or(wal, 1063 GEN9_GAMT_ECO_REG_RW_IA, 1064 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1065 } 1066 1067 static void 1068 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1069 { 1070 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; 1071 unsigned int slice, subslice; 1072 u32 l3_en, mcr, mcr_mask; 1073 1074 GEM_BUG_ON(INTEL_GEN(i915) < 10); 1075 1076 /* 1077 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 1078 * L3Banks could be fused off in single slice scenario. If that is 1079 * the case, we might need to program MCR select to a valid L3Bank 1080 * by default, to make sure we correctly read certain registers 1081 * later on (in the range 0xB100 - 0xB3FF). 1082 * 1083 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 1084 * Before any MMIO read into slice/subslice specific registers, MCR 1085 * packet control register needs to be programmed to point to any 1086 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1087 * This means each subsequent MMIO read will be forwarded to an 1088 * specific s/ss combination, but this is OK since these registers 1089 * are consistent across s/ss in almost all cases. In the rare 1090 * occasions, such as INSTDONE, where this value is dependent 1091 * on s/ss combo, the read should be done with read_subslice_reg. 1092 * 1093 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 1094 * to which subslice, or to which L3 bank, the respective mmio reads 1095 * will go, we have to find a common index which works for both 1096 * accesses. 1097 * 1098 * Case where we cannot find a common index fortunately should not 1099 * happen in production hardware, so we only emit a warning instead of 1100 * implementing something more complex that requires checking the range 1101 * of every MMIO read. 1102 */ 1103 1104 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 1105 u32 l3_fuse = 1106 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 1107 GEN10_L3BANK_MASK; 1108 1109 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 1110 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 1111 } else { 1112 l3_en = ~0; 1113 } 1114 1115 slice = fls(sseu->slice_mask) - 1; 1116 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 1117 if (!subslice) { 1118 drm_warn(&i915->drm, 1119 "No common index found between subslice mask %x and L3 bank mask %x!\n", 1120 intel_sseu_get_subslices(sseu, slice), l3_en); 1121 subslice = fls(l3_en); 1122 drm_WARN_ON(&i915->drm, !subslice); 1123 } 1124 subslice--; 1125 1126 if (INTEL_GEN(i915) >= 11) { 1127 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1128 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1129 } else { 1130 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1131 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1132 } 1133 1134 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 1135 1136 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1137 } 1138 1139 static void 1140 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1141 { 1142 wa_init_mcr(i915, wal); 1143 1144 /* WaInPlaceDecompressionHang:cnl */ 1145 wa_write_or(wal, 1146 GEN9_GAMT_ECO_REG_RW_IA, 1147 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1148 } 1149 1150 static void 1151 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1152 { 1153 wa_init_mcr(i915, wal); 1154 1155 /* WaInPlaceDecompressionHang:icl */ 1156 wa_write_or(wal, 1157 GEN9_GAMT_ECO_REG_RW_IA, 1158 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1159 1160 /* WaModifyGamTlbPartitioning:icl */ 1161 wa_write_masked_or(wal, 1162 GEN11_GACB_PERF_CTRL, 1163 GEN11_HASH_CTRL_MASK, 1164 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1165 1166 /* Wa_1405766107:icl 1167 * Formerly known as WaCL2SFHalfMaxAlloc 1168 */ 1169 wa_write_or(wal, 1170 GEN11_LSN_UNSLCVC, 1171 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1172 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1173 1174 /* Wa_220166154:icl 1175 * Formerly known as WaDisCtxReload 1176 */ 1177 wa_write_or(wal, 1178 GEN8_GAMW_ECO_DEV_RW_IA, 1179 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1180 1181 /* Wa_1405779004:icl (pre-prod) */ 1182 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 1183 wa_write_or(wal, 1184 SLICE_UNIT_LEVEL_CLKGATE, 1185 MSCUNIT_CLKGATE_DIS); 1186 1187 /* Wa_1406838659:icl (pre-prod) */ 1188 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1189 wa_write_or(wal, 1190 INF_UNIT_LEVEL_CLKGATE, 1191 CGPSF_CLKGATE_DIS); 1192 1193 /* Wa_1406463099:icl 1194 * Formerly known as WaGamTlbPendError 1195 */ 1196 wa_write_or(wal, 1197 GAMT_CHKN_BIT_REG, 1198 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1199 1200 /* Wa_1607087056:icl,ehl,jsl */ 1201 if (IS_ICELAKE(i915) || 1202 IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 1203 wa_write_or(wal, 1204 SLICE_UNIT_LEVEL_CLKGATE, 1205 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1206 } 1207 } 1208 1209 static void 1210 gen12_gt_workarounds_init(struct drm_i915_private *i915, 1211 struct i915_wa_list *wal) 1212 { 1213 wa_init_mcr(i915, wal); 1214 } 1215 1216 static void 1217 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1218 { 1219 gen12_gt_workarounds_init(i915, wal); 1220 1221 /* Wa_1409420604:tgl */ 1222 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1223 wa_write_or(wal, 1224 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1225 CPSSUNIT_CLKGATE_DIS); 1226 1227 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1228 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1229 wa_write_or(wal, 1230 SLICE_UNIT_LEVEL_CLKGATE, 1231 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1232 } 1233 1234 static void 1235 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1236 { 1237 if (IS_TIGERLAKE(i915)) 1238 tgl_gt_workarounds_init(i915, wal); 1239 else if (IS_GEN(i915, 12)) 1240 gen12_gt_workarounds_init(i915, wal); 1241 else if (IS_GEN(i915, 11)) 1242 icl_gt_workarounds_init(i915, wal); 1243 else if (IS_CANNONLAKE(i915)) 1244 cnl_gt_workarounds_init(i915, wal); 1245 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1246 cfl_gt_workarounds_init(i915, wal); 1247 else if (IS_GEMINILAKE(i915)) 1248 glk_gt_workarounds_init(i915, wal); 1249 else if (IS_KABYLAKE(i915)) 1250 kbl_gt_workarounds_init(i915, wal); 1251 else if (IS_BROXTON(i915)) 1252 bxt_gt_workarounds_init(i915, wal); 1253 else if (IS_SKYLAKE(i915)) 1254 skl_gt_workarounds_init(i915, wal); 1255 else if (IS_HASWELL(i915)) 1256 hsw_gt_workarounds_init(i915, wal); 1257 else if (IS_VALLEYVIEW(i915)) 1258 vlv_gt_workarounds_init(i915, wal); 1259 else if (IS_IVYBRIDGE(i915)) 1260 ivb_gt_workarounds_init(i915, wal); 1261 else if (IS_GEN(i915, 6)) 1262 snb_gt_workarounds_init(i915, wal); 1263 else if (IS_GEN(i915, 5)) 1264 ilk_gt_workarounds_init(i915, wal); 1265 else if (IS_G4X(i915)) 1266 g4x_gt_workarounds_init(i915, wal); 1267 else if (IS_GEN(i915, 4)) 1268 gen4_gt_workarounds_init(i915, wal); 1269 else if (INTEL_GEN(i915) <= 8) 1270 return; 1271 else 1272 MISSING_CASE(INTEL_GEN(i915)); 1273 } 1274 1275 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1276 { 1277 struct i915_wa_list *wal = &i915->gt_wa_list; 1278 1279 wa_init_start(wal, "GT", "global"); 1280 gt_init_workarounds(i915, wal); 1281 wa_init_finish(wal); 1282 } 1283 1284 static enum forcewake_domains 1285 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1286 { 1287 enum forcewake_domains fw = 0; 1288 struct i915_wa *wa; 1289 unsigned int i; 1290 1291 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1292 fw |= intel_uncore_forcewake_for_reg(uncore, 1293 wa->reg, 1294 FW_REG_READ | 1295 FW_REG_WRITE); 1296 1297 return fw; 1298 } 1299 1300 static bool 1301 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1302 { 1303 if ((cur ^ wa->set) & wa->read) { 1304 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1305 name, from, i915_mmio_reg_offset(wa->reg), 1306 cur, cur & wa->read, wa->set); 1307 1308 return false; 1309 } 1310 1311 return true; 1312 } 1313 1314 static void 1315 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1316 { 1317 enum forcewake_domains fw; 1318 unsigned long flags; 1319 struct i915_wa *wa; 1320 unsigned int i; 1321 1322 if (!wal->count) 1323 return; 1324 1325 fw = wal_get_fw_for_rmw(uncore, wal); 1326 1327 spin_lock_irqsave(&uncore->lock, flags); 1328 intel_uncore_forcewake_get__locked(uncore, fw); 1329 1330 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1331 if (wa->clr) 1332 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1333 else 1334 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1335 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1336 wa_verify(wa, 1337 intel_uncore_read_fw(uncore, wa->reg), 1338 wal->name, "application"); 1339 } 1340 1341 intel_uncore_forcewake_put__locked(uncore, fw); 1342 spin_unlock_irqrestore(&uncore->lock, flags); 1343 } 1344 1345 void intel_gt_apply_workarounds(struct intel_gt *gt) 1346 { 1347 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1348 } 1349 1350 static bool wa_list_verify(struct intel_uncore *uncore, 1351 const struct i915_wa_list *wal, 1352 const char *from) 1353 { 1354 struct i915_wa *wa; 1355 unsigned int i; 1356 bool ok = true; 1357 1358 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1359 ok &= wa_verify(wa, 1360 intel_uncore_read(uncore, wa->reg), 1361 wal->name, from); 1362 1363 return ok; 1364 } 1365 1366 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1367 { 1368 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1369 } 1370 1371 static inline bool is_nonpriv_flags_valid(u32 flags) 1372 { 1373 /* Check only valid flag bits are set */ 1374 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1375 return false; 1376 1377 /* NB: Only 3 out of 4 enum values are valid for access field */ 1378 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1379 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1380 return false; 1381 1382 return true; 1383 } 1384 1385 static void 1386 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1387 { 1388 struct i915_wa wa = { 1389 .reg = reg 1390 }; 1391 1392 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1393 return; 1394 1395 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1396 return; 1397 1398 wa.reg.reg |= flags; 1399 _wa_add(wal, &wa); 1400 } 1401 1402 static void 1403 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1404 { 1405 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1406 } 1407 1408 static void gen9_whitelist_build(struct i915_wa_list *w) 1409 { 1410 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1411 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1412 1413 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1414 whitelist_reg(w, GEN8_CS_CHICKEN1); 1415 1416 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1417 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1418 1419 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1420 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1421 } 1422 1423 static void skl_whitelist_build(struct intel_engine_cs *engine) 1424 { 1425 struct i915_wa_list *w = &engine->whitelist; 1426 1427 if (engine->class != RENDER_CLASS) 1428 return; 1429 1430 gen9_whitelist_build(w); 1431 1432 /* WaDisableLSQCROPERFforOCL:skl */ 1433 whitelist_reg(w, GEN8_L3SQCREG4); 1434 } 1435 1436 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1437 { 1438 if (engine->class != RENDER_CLASS) 1439 return; 1440 1441 gen9_whitelist_build(&engine->whitelist); 1442 } 1443 1444 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1445 { 1446 struct i915_wa_list *w = &engine->whitelist; 1447 1448 if (engine->class != RENDER_CLASS) 1449 return; 1450 1451 gen9_whitelist_build(w); 1452 1453 /* WaDisableLSQCROPERFforOCL:kbl */ 1454 whitelist_reg(w, GEN8_L3SQCREG4); 1455 } 1456 1457 static void glk_whitelist_build(struct intel_engine_cs *engine) 1458 { 1459 struct i915_wa_list *w = &engine->whitelist; 1460 1461 if (engine->class != RENDER_CLASS) 1462 return; 1463 1464 gen9_whitelist_build(w); 1465 1466 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1467 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1468 } 1469 1470 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1471 { 1472 struct i915_wa_list *w = &engine->whitelist; 1473 1474 if (engine->class != RENDER_CLASS) 1475 return; 1476 1477 gen9_whitelist_build(w); 1478 1479 /* 1480 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1481 * 1482 * This covers 4 register which are next to one another : 1483 * - PS_INVOCATION_COUNT 1484 * - PS_INVOCATION_COUNT_UDW 1485 * - PS_DEPTH_COUNT 1486 * - PS_DEPTH_COUNT_UDW 1487 */ 1488 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1489 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1490 RING_FORCE_TO_NONPRIV_RANGE_4); 1491 } 1492 1493 static void cml_whitelist_build(struct intel_engine_cs *engine) 1494 { 1495 struct i915_wa_list *w = &engine->whitelist; 1496 1497 if (engine->class != RENDER_CLASS) 1498 whitelist_reg_ext(w, 1499 RING_CTX_TIMESTAMP(engine->mmio_base), 1500 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1501 1502 cfl_whitelist_build(engine); 1503 } 1504 1505 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1506 { 1507 struct i915_wa_list *w = &engine->whitelist; 1508 1509 if (engine->class != RENDER_CLASS) 1510 return; 1511 1512 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1513 whitelist_reg(w, GEN8_CS_CHICKEN1); 1514 } 1515 1516 static void icl_whitelist_build(struct intel_engine_cs *engine) 1517 { 1518 struct i915_wa_list *w = &engine->whitelist; 1519 1520 switch (engine->class) { 1521 case RENDER_CLASS: 1522 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1523 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1524 1525 /* WaAllowUMDToModifySamplerMode:icl */ 1526 whitelist_reg(w, GEN10_SAMPLER_MODE); 1527 1528 /* WaEnableStateCacheRedirectToCS:icl */ 1529 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1530 1531 /* 1532 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1533 * 1534 * This covers 4 register which are next to one another : 1535 * - PS_INVOCATION_COUNT 1536 * - PS_INVOCATION_COUNT_UDW 1537 * - PS_DEPTH_COUNT 1538 * - PS_DEPTH_COUNT_UDW 1539 */ 1540 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1541 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1542 RING_FORCE_TO_NONPRIV_RANGE_4); 1543 break; 1544 1545 case VIDEO_DECODE_CLASS: 1546 /* hucStatusRegOffset */ 1547 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1548 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1549 /* hucUKernelHdrInfoRegOffset */ 1550 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1551 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1552 /* hucStatus2RegOffset */ 1553 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1554 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1555 whitelist_reg_ext(w, 1556 RING_CTX_TIMESTAMP(engine->mmio_base), 1557 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1558 break; 1559 1560 default: 1561 whitelist_reg_ext(w, 1562 RING_CTX_TIMESTAMP(engine->mmio_base), 1563 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1564 break; 1565 } 1566 } 1567 1568 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1569 { 1570 struct i915_wa_list *w = &engine->whitelist; 1571 1572 switch (engine->class) { 1573 case RENDER_CLASS: 1574 /* 1575 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1576 * Wa_1408556865:tgl 1577 * 1578 * This covers 4 registers which are next to one another : 1579 * - PS_INVOCATION_COUNT 1580 * - PS_INVOCATION_COUNT_UDW 1581 * - PS_DEPTH_COUNT 1582 * - PS_DEPTH_COUNT_UDW 1583 */ 1584 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1585 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1586 RING_FORCE_TO_NONPRIV_RANGE_4); 1587 1588 /* Wa_1808121037:tgl */ 1589 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1590 1591 /* Wa_1806527549:tgl */ 1592 whitelist_reg(w, HIZ_CHICKEN); 1593 break; 1594 default: 1595 whitelist_reg_ext(w, 1596 RING_CTX_TIMESTAMP(engine->mmio_base), 1597 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1598 break; 1599 } 1600 } 1601 1602 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1603 { 1604 struct drm_i915_private *i915 = engine->i915; 1605 struct i915_wa_list *w = &engine->whitelist; 1606 1607 wa_init_start(w, "whitelist", engine->name); 1608 1609 if (IS_GEN(i915, 12)) 1610 tgl_whitelist_build(engine); 1611 else if (IS_GEN(i915, 11)) 1612 icl_whitelist_build(engine); 1613 else if (IS_CANNONLAKE(i915)) 1614 cnl_whitelist_build(engine); 1615 else if (IS_COMETLAKE(i915)) 1616 cml_whitelist_build(engine); 1617 else if (IS_COFFEELAKE(i915)) 1618 cfl_whitelist_build(engine); 1619 else if (IS_GEMINILAKE(i915)) 1620 glk_whitelist_build(engine); 1621 else if (IS_KABYLAKE(i915)) 1622 kbl_whitelist_build(engine); 1623 else if (IS_BROXTON(i915)) 1624 bxt_whitelist_build(engine); 1625 else if (IS_SKYLAKE(i915)) 1626 skl_whitelist_build(engine); 1627 else if (INTEL_GEN(i915) <= 8) 1628 return; 1629 else 1630 MISSING_CASE(INTEL_GEN(i915)); 1631 1632 wa_init_finish(w); 1633 } 1634 1635 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1636 { 1637 const struct i915_wa_list *wal = &engine->whitelist; 1638 struct intel_uncore *uncore = engine->uncore; 1639 const u32 base = engine->mmio_base; 1640 struct i915_wa *wa; 1641 unsigned int i; 1642 1643 if (!wal->count) 1644 return; 1645 1646 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1647 intel_uncore_write(uncore, 1648 RING_FORCE_TO_NONPRIV(base, i), 1649 i915_mmio_reg_offset(wa->reg)); 1650 1651 /* And clear the rest just in case of garbage */ 1652 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1653 intel_uncore_write(uncore, 1654 RING_FORCE_TO_NONPRIV(base, i), 1655 i915_mmio_reg_offset(RING_NOPID(base))); 1656 } 1657 1658 static void 1659 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1660 { 1661 struct drm_i915_private *i915 = engine->i915; 1662 1663 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1664 /* 1665 * Wa_1607138336:tgl 1666 * Wa_1607063988:tgl 1667 */ 1668 wa_write_or(wal, 1669 GEN9_CTX_PREEMPT_REG, 1670 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1671 1672 /* 1673 * Wa_1606679103:tgl 1674 * (see also Wa_1606682166:icl) 1675 */ 1676 wa_write_or(wal, 1677 GEN7_SARCHKMD, 1678 GEN7_DISABLE_SAMPLER_PREFETCH); 1679 1680 /* Wa_1408615072:tgl */ 1681 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1682 VSUNIT_CLKGATE_DIS_TGL); 1683 } 1684 1685 if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1686 /* Wa_1606931601:tgl,rkl */ 1687 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1688 1689 /* Wa_1409804808:tgl,rkl */ 1690 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1691 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1692 1693 /* 1694 * Wa_1409085225:tgl 1695 * Wa_14010229206:tgl,rkl 1696 */ 1697 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1698 1699 /* 1700 * Wa_1407928979:tgl A* 1701 * Wa_18011464164:tgl B0+ 1702 * Wa_22010931296:tgl B0+ 1703 * Wa_14010919138:rkl 1704 */ 1705 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1706 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1707 1708 /* 1709 * Wa_1607030317:tgl 1710 * Wa_1607186500:tgl 1711 * Wa_1607297627:tgl,rkl there are multiple entries for this 1712 * WA in the BSpec; some indicate this is an A0-only WA, 1713 * others indicate it applies to all steppings. 1714 */ 1715 wa_masked_en(wal, 1716 GEN6_RC_SLEEP_PSMI_CONTROL, 1717 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1718 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1719 } 1720 1721 if (IS_TIGERLAKE(i915)) { 1722 /* Wa_1606700617:tgl */ 1723 wa_masked_en(wal, 1724 GEN9_CS_DEBUG_MODE1, 1725 FF_DOP_CLOCK_GATE_DISABLE); 1726 } 1727 1728 if (IS_GEN(i915, 11)) { 1729 /* This is not an Wa. Enable for better image quality */ 1730 wa_masked_en(wal, 1731 _3D_CHICKEN3, 1732 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1733 1734 /* WaPipelineFlushCoherentLines:icl */ 1735 wa_write_or(wal, 1736 GEN8_L3SQCREG4, 1737 GEN8_LQSC_FLUSH_COHERENT_LINES); 1738 1739 /* 1740 * Wa_1405543622:icl 1741 * Formerly known as WaGAPZPriorityScheme 1742 */ 1743 wa_write_or(wal, 1744 GEN8_GARBCNTL, 1745 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1746 1747 /* 1748 * Wa_1604223664:icl 1749 * Formerly known as WaL3BankAddressHashing 1750 */ 1751 wa_write_masked_or(wal, 1752 GEN8_GARBCNTL, 1753 GEN11_HASH_CTRL_EXCL_MASK, 1754 GEN11_HASH_CTRL_EXCL_BIT0); 1755 wa_write_masked_or(wal, 1756 GEN11_GLBLINVL, 1757 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1758 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1759 1760 /* 1761 * Wa_1405733216:icl 1762 * Formerly known as WaDisableCleanEvicts 1763 */ 1764 wa_write_or(wal, 1765 GEN8_L3SQCREG4, 1766 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1767 1768 /* WaForwardProgressSoftReset:icl */ 1769 wa_write_or(wal, 1770 GEN10_SCRATCH_LNCF2, 1771 PMFLUSHDONE_LNICRSDROP | 1772 PMFLUSH_GAPL3UNBLOCK | 1773 PMFLUSHDONE_LNEBLK); 1774 1775 /* Wa_1406609255:icl (pre-prod) */ 1776 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1777 wa_write_or(wal, 1778 GEN7_SARCHKMD, 1779 GEN7_DISABLE_DEMAND_PREFETCH); 1780 1781 /* Wa_1606682166:icl */ 1782 wa_write_or(wal, 1783 GEN7_SARCHKMD, 1784 GEN7_DISABLE_SAMPLER_PREFETCH); 1785 1786 /* Wa_1409178092:icl */ 1787 wa_write_masked_or(wal, 1788 GEN11_SCRATCH2, 1789 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1790 0); 1791 1792 /* WaEnable32PlaneMode:icl */ 1793 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1794 GEN11_ENABLE_32_PLANE_MODE); 1795 1796 /* 1797 * Wa_1408615072:icl,ehl (vsunit) 1798 * Wa_1407596294:icl,ehl (hsunit) 1799 */ 1800 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1801 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1802 1803 /* Wa_1407352427:icl,ehl */ 1804 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1805 PSDUNIT_CLKGATE_DIS); 1806 1807 /* Wa_1406680159:icl,ehl */ 1808 wa_write_or(wal, 1809 SUBSLICE_UNIT_LEVEL_CLKGATE, 1810 GWUNIT_CLKGATE_DIS); 1811 1812 /* 1813 * Wa_1408767742:icl[a2..forever],ehl[all] 1814 * Wa_1605460711:icl[a0..c0] 1815 */ 1816 wa_write_or(wal, 1817 GEN7_FF_THREAD_MODE, 1818 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1819 1820 /* Wa_22010271021:ehl */ 1821 if (IS_ELKHARTLAKE(i915)) 1822 wa_masked_en(wal, 1823 GEN9_CS_DEBUG_MODE1, 1824 FF_DOP_CLOCK_GATE_DISABLE); 1825 } 1826 1827 if (IS_GEN_RANGE(i915, 9, 12)) { 1828 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1829 wa_masked_en(wal, 1830 GEN7_FF_SLICE_CS_CHICKEN1, 1831 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1832 } 1833 1834 if (IS_SKYLAKE(i915) || 1835 IS_KABYLAKE(i915) || 1836 IS_COFFEELAKE(i915) || 1837 IS_COMETLAKE(i915)) { 1838 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1839 wa_write_or(wal, 1840 GEN8_GARBCNTL, 1841 GEN9_GAPS_TSV_CREDIT_DISABLE); 1842 } 1843 1844 if (IS_BROXTON(i915)) { 1845 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1846 wa_masked_en(wal, 1847 FF_SLICE_CS_CHICKEN2, 1848 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1849 } 1850 1851 if (IS_GEN(i915, 9)) { 1852 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1853 wa_masked_en(wal, 1854 GEN9_CSFE_CHICKEN1_RCS, 1855 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1856 1857 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1858 wa_write_or(wal, 1859 BDW_SCRATCH1, 1860 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1861 1862 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1863 if (IS_GEN9_LP(i915)) 1864 wa_write_masked_or(wal, 1865 GEN8_L3SQCREG1, 1866 L3_PRIO_CREDITS_MASK, 1867 L3_GENERAL_PRIO_CREDITS(62) | 1868 L3_HIGH_PRIO_CREDITS(2)); 1869 1870 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1871 wa_write_or(wal, 1872 GEN8_L3SQCREG4, 1873 GEN8_LQSC_FLUSH_COHERENT_LINES); 1874 } 1875 1876 if (IS_GEN(i915, 7)) 1877 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1878 wa_masked_en(wal, 1879 GFX_MODE_GEN7, 1880 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1881 1882 if (IS_GEN_RANGE(i915, 6, 7)) 1883 /* 1884 * We need to disable the AsyncFlip performance optimisations in 1885 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1886 * already be programmed to '1' on all products. 1887 * 1888 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1889 */ 1890 wa_masked_en(wal, 1891 MI_MODE, 1892 ASYNC_FLIP_PERF_DISABLE); 1893 1894 if (IS_GEN(i915, 6)) { 1895 /* 1896 * Required for the hardware to program scanline values for 1897 * waiting 1898 * WaEnableFlushTlbInvalidationMode:snb 1899 */ 1900 wa_masked_en(wal, 1901 GFX_MODE, 1902 GFX_TLB_INVALIDATE_EXPLICIT); 1903 1904 /* 1905 * From the Sandybridge PRM, volume 1 part 3, page 24: 1906 * "If this bit is set, STCunit will have LRA as replacement 1907 * policy. [...] This bit must be reset. LRA replacement 1908 * policy is not supported." 1909 */ 1910 wa_masked_dis(wal, 1911 CACHE_MODE_0, 1912 CM0_STC_EVICT_DISABLE_LRA_SNB); 1913 } 1914 1915 if (IS_GEN_RANGE(i915, 4, 6)) 1916 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1917 wa_add(wal, MI_MODE, 1918 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1919 /* XXX bit doesn't stick on Broadwater */ 1920 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1921 1922 if (IS_GEN(i915, 4)) 1923 /* 1924 * Disable CONSTANT_BUFFER before it is loaded from the context 1925 * image. For as it is loaded, it is executed and the stored 1926 * address may no longer be valid, leading to a GPU hang. 1927 * 1928 * This imposes the requirement that userspace reload their 1929 * CONSTANT_BUFFER on every batch, fortunately a requirement 1930 * they are already accustomed to from before contexts were 1931 * enabled. 1932 */ 1933 wa_add(wal, ECOSKPD, 1934 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 1935 0 /* XXX bit doesn't stick on Broadwater */); 1936 } 1937 1938 static void 1939 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1940 { 1941 struct drm_i915_private *i915 = engine->i915; 1942 1943 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1944 if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1945 wa_write(wal, 1946 RING_SEMA_WAIT_POLL(engine->mmio_base), 1947 1); 1948 } 1949 } 1950 1951 static void 1952 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1953 { 1954 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1955 return; 1956 1957 if (engine->class == RENDER_CLASS) 1958 rcs_engine_wa_init(engine, wal); 1959 else 1960 xcs_engine_wa_init(engine, wal); 1961 } 1962 1963 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1964 { 1965 struct i915_wa_list *wal = &engine->wa_list; 1966 1967 if (INTEL_GEN(engine->i915) < 4) 1968 return; 1969 1970 wa_init_start(wal, "engine", engine->name); 1971 engine_init_workarounds(engine, wal); 1972 wa_init_finish(wal); 1973 } 1974 1975 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1976 { 1977 wa_list_apply(engine->uncore, &engine->wa_list); 1978 } 1979 1980 static struct i915_vma * 1981 create_scratch(struct i915_address_space *vm, int count) 1982 { 1983 struct drm_i915_gem_object *obj; 1984 struct i915_vma *vma; 1985 unsigned int size; 1986 int err; 1987 1988 size = round_up(count * sizeof(u32), PAGE_SIZE); 1989 obj = i915_gem_object_create_internal(vm->i915, size); 1990 if (IS_ERR(obj)) 1991 return ERR_CAST(obj); 1992 1993 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1994 1995 vma = i915_vma_instance(obj, vm, NULL); 1996 if (IS_ERR(vma)) { 1997 err = PTR_ERR(vma); 1998 goto err_obj; 1999 } 2000 2001 err = i915_vma_pin(vma, 0, 0, 2002 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2003 if (err) 2004 goto err_obj; 2005 2006 return vma; 2007 2008 err_obj: 2009 i915_gem_object_put(obj); 2010 return ERR_PTR(err); 2011 } 2012 2013 static const struct { 2014 u32 start; 2015 u32 end; 2016 } mcr_ranges_gen8[] = { 2017 { .start = 0x5500, .end = 0x55ff }, 2018 { .start = 0x7000, .end = 0x7fff }, 2019 { .start = 0x9400, .end = 0x97ff }, 2020 { .start = 0xb000, .end = 0xb3ff }, 2021 { .start = 0xe000, .end = 0xe7ff }, 2022 {}, 2023 }; 2024 2025 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2026 { 2027 int i; 2028 2029 if (INTEL_GEN(i915) < 8) 2030 return false; 2031 2032 /* 2033 * Registers in these ranges are affected by the MCR selector 2034 * which only controls CPU initiated MMIO. Routing does not 2035 * work for CS access so we cannot verify them on this path. 2036 */ 2037 for (i = 0; mcr_ranges_gen8[i].start; i++) 2038 if (offset >= mcr_ranges_gen8[i].start && 2039 offset <= mcr_ranges_gen8[i].end) 2040 return true; 2041 2042 return false; 2043 } 2044 2045 static int 2046 wa_list_srm(struct i915_request *rq, 2047 const struct i915_wa_list *wal, 2048 struct i915_vma *vma) 2049 { 2050 struct drm_i915_private *i915 = rq->engine->i915; 2051 unsigned int i, count = 0; 2052 const struct i915_wa *wa; 2053 u32 srm, *cs; 2054 2055 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2056 if (INTEL_GEN(i915) >= 8) 2057 srm++; 2058 2059 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2060 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2061 count++; 2062 } 2063 2064 cs = intel_ring_begin(rq, 4 * count); 2065 if (IS_ERR(cs)) 2066 return PTR_ERR(cs); 2067 2068 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2069 u32 offset = i915_mmio_reg_offset(wa->reg); 2070 2071 if (mcr_range(i915, offset)) 2072 continue; 2073 2074 *cs++ = srm; 2075 *cs++ = offset; 2076 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2077 *cs++ = 0; 2078 } 2079 intel_ring_advance(rq, cs); 2080 2081 return 0; 2082 } 2083 2084 static int engine_wa_list_verify(struct intel_context *ce, 2085 const struct i915_wa_list * const wal, 2086 const char *from) 2087 { 2088 const struct i915_wa *wa; 2089 struct i915_request *rq; 2090 struct i915_vma *vma; 2091 struct i915_gem_ww_ctx ww; 2092 unsigned int i; 2093 u32 *results; 2094 int err; 2095 2096 if (!wal->count) 2097 return 0; 2098 2099 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 2100 if (IS_ERR(vma)) 2101 return PTR_ERR(vma); 2102 2103 intel_engine_pm_get(ce->engine); 2104 i915_gem_ww_ctx_init(&ww, false); 2105 retry: 2106 err = i915_gem_object_lock(vma->obj, &ww); 2107 if (err == 0) 2108 err = intel_context_pin_ww(ce, &ww); 2109 if (err) 2110 goto err_pm; 2111 2112 rq = i915_request_create(ce); 2113 if (IS_ERR(rq)) { 2114 err = PTR_ERR(rq); 2115 goto err_unpin; 2116 } 2117 2118 err = i915_request_await_object(rq, vma->obj, true); 2119 if (err == 0) 2120 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2121 if (err == 0) 2122 err = wa_list_srm(rq, wal, vma); 2123 2124 i915_request_get(rq); 2125 if (err) 2126 i915_request_set_error_once(rq, err); 2127 i915_request_add(rq); 2128 2129 if (err) 2130 goto err_rq; 2131 2132 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2133 err = -ETIME; 2134 goto err_rq; 2135 } 2136 2137 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2138 if (IS_ERR(results)) { 2139 err = PTR_ERR(results); 2140 goto err_rq; 2141 } 2142 2143 err = 0; 2144 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2145 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2146 continue; 2147 2148 if (!wa_verify(wa, results[i], wal->name, from)) 2149 err = -ENXIO; 2150 } 2151 2152 i915_gem_object_unpin_map(vma->obj); 2153 2154 err_rq: 2155 i915_request_put(rq); 2156 err_unpin: 2157 intel_context_unpin(ce); 2158 err_pm: 2159 if (err == -EDEADLK) { 2160 err = i915_gem_ww_ctx_backoff(&ww); 2161 if (!err) 2162 goto retry; 2163 } 2164 i915_gem_ww_ctx_fini(&ww); 2165 intel_engine_pm_put(ce->engine); 2166 i915_vma_unpin(vma); 2167 i915_vma_put(vma); 2168 return err; 2169 } 2170 2171 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2172 const char *from) 2173 { 2174 return engine_wa_list_verify(engine->kernel_context, 2175 &engine->wa_list, 2176 from); 2177 } 2178 2179 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2180 #include "selftest_workarounds.c" 2181 #endif 2182