1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 /* 56 * KBL revision ID ordering is bizarre; higher revision ID's map to lower 57 * steppings in some cases. So rather than test against the revision ID 58 * directly, let's map that into our own range of increasing ID's that we 59 * can test against in a regular manner. 60 */ 61 62 const struct i915_rev_steppings kbl_revids[] = { 63 [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, 64 [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, 65 [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, 66 [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, 67 [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, 68 [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, 69 [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, 70 [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, 71 }; 72 73 const struct i915_rev_steppings tgl_uy_revids[] = { 74 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 }, 75 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 }, 76 [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 }, 77 [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 }, 78 }; 79 80 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 81 const struct i915_rev_steppings tgl_revids[] = { 82 [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 }, 83 [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 }, 84 }; 85 86 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 87 { 88 wal->name = name; 89 wal->engine_name = engine_name; 90 } 91 92 #define WA_LIST_CHUNK (1 << 4) 93 94 static void wa_init_finish(struct i915_wa_list *wal) 95 { 96 /* Trim unused entries. */ 97 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 98 struct i915_wa *list = kmemdup(wal->list, 99 wal->count * sizeof(*list), 100 GFP_KERNEL); 101 102 if (list) { 103 kfree(wal->list); 104 wal->list = list; 105 } 106 } 107 108 if (!wal->count) 109 return; 110 111 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 112 wal->wa_count, wal->name, wal->engine_name); 113 } 114 115 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 116 { 117 unsigned int addr = i915_mmio_reg_offset(wa->reg); 118 unsigned int start = 0, end = wal->count; 119 const unsigned int grow = WA_LIST_CHUNK; 120 struct i915_wa *wa_; 121 122 GEM_BUG_ON(!is_power_of_2(grow)); 123 124 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 125 struct i915_wa *list; 126 127 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 128 GFP_KERNEL); 129 if (!list) { 130 DRM_ERROR("No space for workaround init!\n"); 131 return; 132 } 133 134 if (wal->list) 135 memcpy(list, wal->list, sizeof(*wa) * wal->count); 136 137 wal->list = list; 138 } 139 140 while (start < end) { 141 unsigned int mid = start + (end - start) / 2; 142 143 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 144 start = mid + 1; 145 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 146 end = mid; 147 } else { 148 wa_ = &wal->list[mid]; 149 150 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 151 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 152 i915_mmio_reg_offset(wa_->reg), 153 wa_->clr, wa_->set); 154 155 wa_->set &= ~wa->clr; 156 } 157 158 wal->wa_count++; 159 wa_->set |= wa->set; 160 wa_->clr |= wa->clr; 161 wa_->read |= wa->read; 162 return; 163 } 164 } 165 166 wal->wa_count++; 167 wa_ = &wal->list[wal->count++]; 168 *wa_ = *wa; 169 170 while (wa_-- > wal->list) { 171 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 172 i915_mmio_reg_offset(wa_[1].reg)); 173 if (i915_mmio_reg_offset(wa_[1].reg) > 174 i915_mmio_reg_offset(wa_[0].reg)) 175 break; 176 177 swap(wa_[1], wa_[0]); 178 } 179 } 180 181 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 182 u32 clear, u32 set, u32 read_mask) 183 { 184 struct i915_wa wa = { 185 .reg = reg, 186 .clr = clear, 187 .set = set, 188 .read = read_mask, 189 }; 190 191 _wa_add(wal, &wa); 192 } 193 194 static void 195 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 196 { 197 wa_add(wal, reg, clear, set, clear); 198 } 199 200 static void 201 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 202 { 203 wa_write_masked_or(wal, reg, ~0, set); 204 } 205 206 static void 207 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 208 { 209 wa_write_masked_or(wal, reg, set, set); 210 } 211 212 static void 213 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 214 { 215 wa_write_masked_or(wal, reg, clr, 0); 216 } 217 218 static void 219 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 220 { 221 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 222 } 223 224 static void 225 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 226 { 227 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 228 } 229 230 #define WA_SET_BIT_MASKED(addr, mask) \ 231 wa_masked_en(wal, (addr), (mask)) 232 233 #define WA_CLR_BIT_MASKED(addr, mask) \ 234 wa_masked_dis(wal, (addr), (mask)) 235 236 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 237 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 238 239 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 240 struct i915_wa_list *wal) 241 { 242 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 243 } 244 245 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 246 struct i915_wa_list *wal) 247 { 248 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 249 } 250 251 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 252 struct i915_wa_list *wal) 253 { 254 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 255 256 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 257 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 258 259 /* WaDisablePartialInstShootdown:bdw,chv */ 260 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 261 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 262 263 /* Use Force Non-Coherent whenever executing a 3D context. This is a 264 * workaround for for a possible hang in the unlikely event a TLB 265 * invalidation occurs during a PSD flush. 266 */ 267 /* WaForceEnableNonCoherent:bdw,chv */ 268 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 269 WA_SET_BIT_MASKED(HDC_CHICKEN0, 270 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 271 HDC_FORCE_NON_COHERENT); 272 273 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 274 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 275 * polygons in the same 8x4 pixel/sample area to be processed without 276 * stalling waiting for the earlier ones to write to Hierarchical Z 277 * buffer." 278 * 279 * This optimization is off by default for BDW and CHV; turn it on. 280 */ 281 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 282 283 /* Wa4x4STCOptimizationDisable:bdw,chv */ 284 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 285 286 /* 287 * BSpec recommends 8x4 when MSAA is used, 288 * however in practice 16x4 seems fastest. 289 * 290 * Note that PS/WM thread counts depend on the WIZ hashing 291 * disable bit, which we don't touch here, but it's good 292 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 293 */ 294 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 295 GEN6_WIZ_HASHING_MASK, 296 GEN6_WIZ_HASHING_16x4); 297 } 298 299 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 300 struct i915_wa_list *wal) 301 { 302 struct drm_i915_private *i915 = engine->i915; 303 304 gen8_ctx_workarounds_init(engine, wal); 305 306 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 307 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 308 309 /* WaDisableDopClockGating:bdw 310 * 311 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 312 * to disable EUTC clock gating. 313 */ 314 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 315 DOP_CLOCK_GATING_DISABLE); 316 317 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 318 GEN8_SAMPLER_POWER_BYPASS_DIS); 319 320 WA_SET_BIT_MASKED(HDC_CHICKEN0, 321 /* WaForceContextSaveRestoreNonCoherent:bdw */ 322 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 323 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 324 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 325 } 326 327 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 328 struct i915_wa_list *wal) 329 { 330 gen8_ctx_workarounds_init(engine, wal); 331 332 /* WaDisableThreadStallDopClockGating:chv */ 333 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 334 335 /* Improve HiZ throughput on CHV. */ 336 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 337 } 338 339 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 340 struct i915_wa_list *wal) 341 { 342 struct drm_i915_private *i915 = engine->i915; 343 344 if (HAS_LLC(i915)) { 345 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 346 * 347 * Must match Display Engine. See 348 * WaCompressedResourceDisplayNewHashMode. 349 */ 350 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 351 GEN9_PBE_COMPRESSED_HASH_SELECTION); 352 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 353 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 354 } 355 356 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 357 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 358 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 359 FLOW_CONTROL_ENABLE | 360 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 361 362 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 363 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 364 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 365 GEN9_ENABLE_YV12_BUGFIX | 366 GEN9_ENABLE_GPGPU_PREEMPTION); 367 368 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 369 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 370 WA_SET_BIT_MASKED(CACHE_MODE_1, 371 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 372 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 373 374 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 375 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 376 GEN9_CCS_TLB_PREFETCH_ENABLE); 377 378 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 379 WA_SET_BIT_MASKED(HDC_CHICKEN0, 380 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 381 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 382 383 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 384 * both tied to WaForceContextSaveRestoreNonCoherent 385 * in some hsds for skl. We keep the tie for all gen9. The 386 * documentation is a bit hazy and so we want to get common behaviour, 387 * even though there is no clear evidence we would need both on kbl/bxt. 388 * This area has been source of system hangs so we play it safe 389 * and mimic the skl regardless of what bspec says. 390 * 391 * Use Force Non-Coherent whenever executing a 3D context. This 392 * is a workaround for a possible hang in the unlikely event 393 * a TLB invalidation occurs during a PSD flush. 394 */ 395 396 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 397 WA_SET_BIT_MASKED(HDC_CHICKEN0, 398 HDC_FORCE_NON_COHERENT); 399 400 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 401 if (IS_SKYLAKE(i915) || 402 IS_KABYLAKE(i915) || 403 IS_COFFEELAKE(i915) || 404 IS_COMETLAKE(i915)) 405 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 406 GEN8_SAMPLER_POWER_BYPASS_DIS); 407 408 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 409 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 410 411 /* 412 * Supporting preemption with fine-granularity requires changes in the 413 * batch buffer programming. Since we can't break old userspace, we 414 * need to set our default preemption level to safe value. Userspace is 415 * still able to use more fine-grained preemption levels, since in 416 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 417 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 418 * not real HW workarounds, but merely a way to start using preemption 419 * while maintaining old contract with userspace. 420 */ 421 422 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 423 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 424 425 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 426 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 427 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 428 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 429 430 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 431 if (IS_GEN9_LP(i915)) 432 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 433 } 434 435 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 436 struct i915_wa_list *wal) 437 { 438 struct intel_gt *gt = engine->gt; 439 u8 vals[3] = { 0, 0, 0 }; 440 unsigned int i; 441 442 for (i = 0; i < 3; i++) { 443 u8 ss; 444 445 /* 446 * Only consider slices where one, and only one, subslice has 7 447 * EUs 448 */ 449 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 450 continue; 451 452 /* 453 * subslice_7eu[i] != 0 (because of the check above) and 454 * ss_max == 4 (maximum number of subslices possible per slice) 455 * 456 * -> 0 <= ss <= 3; 457 */ 458 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 459 vals[i] = 3 - ss; 460 } 461 462 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 463 return; 464 465 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 466 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 467 GEN9_IZ_HASHING_MASK(2) | 468 GEN9_IZ_HASHING_MASK(1) | 469 GEN9_IZ_HASHING_MASK(0), 470 GEN9_IZ_HASHING(2, vals[2]) | 471 GEN9_IZ_HASHING(1, vals[1]) | 472 GEN9_IZ_HASHING(0, vals[0])); 473 } 474 475 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 476 struct i915_wa_list *wal) 477 { 478 gen9_ctx_workarounds_init(engine, wal); 479 skl_tune_iz_hashing(engine, wal); 480 } 481 482 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 483 struct i915_wa_list *wal) 484 { 485 gen9_ctx_workarounds_init(engine, wal); 486 487 /* WaDisableThreadStallDopClockGating:bxt */ 488 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 489 STALL_DOP_GATING_DISABLE); 490 491 /* WaToEnableHwFixForPushConstHWBug:bxt */ 492 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 493 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 494 } 495 496 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 497 struct i915_wa_list *wal) 498 { 499 struct drm_i915_private *i915 = engine->i915; 500 501 gen9_ctx_workarounds_init(engine, wal); 502 503 /* WaToEnableHwFixForPushConstHWBug:kbl */ 504 if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 505 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 506 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 507 508 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 509 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 510 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 511 } 512 513 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 514 struct i915_wa_list *wal) 515 { 516 gen9_ctx_workarounds_init(engine, wal); 517 518 /* WaToEnableHwFixForPushConstHWBug:glk */ 519 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 520 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 521 } 522 523 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 524 struct i915_wa_list *wal) 525 { 526 gen9_ctx_workarounds_init(engine, wal); 527 528 /* WaToEnableHwFixForPushConstHWBug:cfl */ 529 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 530 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 531 532 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 533 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 534 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 535 } 536 537 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 538 struct i915_wa_list *wal) 539 { 540 /* WaForceContextSaveRestoreNonCoherent:cnl */ 541 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 542 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 543 544 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 545 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 546 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 547 548 /* WaPushConstantDereferenceHoldDisable:cnl */ 549 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 550 551 /* FtrEnableFastAnisoL1BankingFix:cnl */ 552 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 553 554 /* WaDisable3DMidCmdPreemption:cnl */ 555 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 556 557 /* WaDisableGPGPUMidCmdPreemption:cnl */ 558 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 559 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 560 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 561 562 /* WaDisableEarlyEOT:cnl */ 563 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 564 } 565 566 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 567 struct i915_wa_list *wal) 568 { 569 struct drm_i915_private *i915 = engine->i915; 570 571 /* WaDisableBankHangMode:icl */ 572 wa_write(wal, 573 GEN8_L3CNTLREG, 574 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 575 GEN8_ERRDETBCTRL); 576 577 /* Wa_1604370585:icl (pre-prod) 578 * Formerly known as WaPushConstantDereferenceHoldDisable 579 */ 580 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 581 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 582 PUSH_CONSTANT_DEREF_DISABLE); 583 584 /* WaForceEnableNonCoherent:icl 585 * This is not the same workaround as in early Gen9 platforms, where 586 * lacking this could cause system hangs, but coherency performance 587 * overhead is high and only a few compute workloads really need it 588 * (the register is whitelisted in hardware now, so UMDs can opt in 589 * for coherency if they have a good reason). 590 */ 591 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 592 593 /* Wa_2006611047:icl (pre-prod) 594 * Formerly known as WaDisableImprovedTdlClkGating 595 */ 596 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 597 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 598 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 599 600 /* Wa_2006665173:icl (pre-prod) */ 601 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 602 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 603 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 604 605 /* WaEnableFloatBlendOptimization:icl */ 606 wa_write_masked_or(wal, 607 GEN10_CACHE_MODE_SS, 608 0, /* write-only, so skip validation */ 609 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 610 611 /* WaDisableGPGPUMidThreadPreemption:icl */ 612 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 613 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 614 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 615 616 /* allow headerless messages for preemptible GPGPU context */ 617 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 618 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 619 620 /* Wa_1604278689:icl,ehl */ 621 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 622 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 623 0, /* write-only register; skip validation */ 624 0xFFFFFFFF); 625 626 /* Wa_1406306137:icl,ehl */ 627 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 628 } 629 630 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 631 struct i915_wa_list *wal) 632 { 633 /* 634 * Wa_1409142259:tgl 635 * Wa_1409347922:tgl 636 * Wa_1409252684:tgl 637 * Wa_1409217633:tgl 638 * Wa_1409207793:tgl 639 * Wa_1409178076:tgl 640 * Wa_1408979724:tgl 641 * Wa_14010443199:rkl 642 * Wa_14010698770:rkl 643 */ 644 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 645 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 646 647 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 648 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 649 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 650 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 651 } 652 653 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 654 struct i915_wa_list *wal) 655 { 656 gen12_ctx_workarounds_init(engine, wal); 657 658 /* 659 * Wa_1604555607:tgl,rkl 660 * 661 * Note that the implementation of this workaround is further modified 662 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 663 * FF_MODE2 register will return the wrong value when read. The default 664 * value for this register is zero for all fields and there are no bit 665 * masks. So instead of doing a RMW we should just write the GS Timer 666 * and TDS timer values for Wa_1604555607 and Wa_16011163337. 667 */ 668 wa_add(wal, 669 FF_MODE2, 670 FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, 671 FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 672 0); 673 } 674 675 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 676 struct i915_wa_list *wal) 677 { 678 gen12_ctx_workarounds_init(engine, wal); 679 680 /* Wa_1409044764 */ 681 WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 682 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 683 684 /* Wa_22010493298 */ 685 WA_SET_BIT_MASKED(HIZ_CHICKEN, 686 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 687 } 688 689 static void 690 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 691 struct i915_wa_list *wal, 692 const char *name) 693 { 694 struct drm_i915_private *i915 = engine->i915; 695 696 if (engine->class != RENDER_CLASS) 697 return; 698 699 wa_init_start(wal, name, engine->name); 700 701 if (IS_DG1(i915)) 702 dg1_ctx_workarounds_init(engine, wal); 703 else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) 704 tgl_ctx_workarounds_init(engine, wal); 705 else if (IS_GEN(i915, 12)) 706 gen12_ctx_workarounds_init(engine, wal); 707 else if (IS_GEN(i915, 11)) 708 icl_ctx_workarounds_init(engine, wal); 709 else if (IS_CANNONLAKE(i915)) 710 cnl_ctx_workarounds_init(engine, wal); 711 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 712 cfl_ctx_workarounds_init(engine, wal); 713 else if (IS_GEMINILAKE(i915)) 714 glk_ctx_workarounds_init(engine, wal); 715 else if (IS_KABYLAKE(i915)) 716 kbl_ctx_workarounds_init(engine, wal); 717 else if (IS_BROXTON(i915)) 718 bxt_ctx_workarounds_init(engine, wal); 719 else if (IS_SKYLAKE(i915)) 720 skl_ctx_workarounds_init(engine, wal); 721 else if (IS_CHERRYVIEW(i915)) 722 chv_ctx_workarounds_init(engine, wal); 723 else if (IS_BROADWELL(i915)) 724 bdw_ctx_workarounds_init(engine, wal); 725 else if (IS_GEN(i915, 7)) 726 gen7_ctx_workarounds_init(engine, wal); 727 else if (IS_GEN(i915, 6)) 728 gen6_ctx_workarounds_init(engine, wal); 729 else if (INTEL_GEN(i915) < 8) 730 return; 731 else 732 MISSING_CASE(INTEL_GEN(i915)); 733 734 wa_init_finish(wal); 735 } 736 737 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 738 { 739 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 740 } 741 742 int intel_engine_emit_ctx_wa(struct i915_request *rq) 743 { 744 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 745 struct i915_wa *wa; 746 unsigned int i; 747 u32 *cs; 748 int ret; 749 750 if (wal->count == 0) 751 return 0; 752 753 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 754 if (ret) 755 return ret; 756 757 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 758 if (IS_ERR(cs)) 759 return PTR_ERR(cs); 760 761 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 762 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 763 *cs++ = i915_mmio_reg_offset(wa->reg); 764 *cs++ = wa->set; 765 } 766 *cs++ = MI_NOOP; 767 768 intel_ring_advance(rq, cs); 769 770 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 771 if (ret) 772 return ret; 773 774 return 0; 775 } 776 777 static void 778 gen4_gt_workarounds_init(struct drm_i915_private *i915, 779 struct i915_wa_list *wal) 780 { 781 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 782 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 783 } 784 785 static void 786 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 787 { 788 gen4_gt_workarounds_init(i915, wal); 789 790 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 791 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 792 } 793 794 static void 795 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 796 { 797 g4x_gt_workarounds_init(i915, wal); 798 799 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 800 } 801 802 static void 803 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 804 { 805 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 806 wa_masked_en(wal, 807 _3D_CHICKEN, 808 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 809 810 /* WaDisable_RenderCache_OperationalFlush:snb */ 811 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 812 813 /* 814 * BSpec recommends 8x4 when MSAA is used, 815 * however in practice 16x4 seems fastest. 816 * 817 * Note that PS/WM thread counts depend on the WIZ hashing 818 * disable bit, which we don't touch here, but it's good 819 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 820 */ 821 wa_add(wal, 822 GEN6_GT_MODE, 0, 823 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 824 GEN6_WIZ_HASHING_16x4); 825 826 wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); 827 828 wa_masked_en(wal, 829 _3D_CHICKEN3, 830 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 831 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 832 /* 833 * Bspec says: 834 * "This bit must be set if 3DSTATE_CLIP clip mode is set 835 * to normal and 3DSTATE_SF number of SF output attributes 836 * is more than 16." 837 */ 838 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 839 } 840 841 static void 842 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 843 { 844 /* WaDisableEarlyCull:ivb */ 845 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 846 847 /* WaDisablePSDDualDispatchEnable:ivb */ 848 if (IS_IVB_GT1(i915)) 849 wa_masked_en(wal, 850 GEN7_HALF_SLICE_CHICKEN1, 851 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 852 853 /* WaDisable_RenderCache_OperationalFlush:ivb */ 854 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 855 856 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 857 wa_masked_dis(wal, 858 GEN7_COMMON_SLICE_CHICKEN1, 859 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 860 861 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 862 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 863 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 864 865 /* WaForceL3Serialization:ivb */ 866 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 867 868 /* 869 * WaVSThreadDispatchOverride:ivb,vlv 870 * 871 * This actually overrides the dispatch 872 * mode for all thread types. 873 */ 874 wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, 875 GEN7_FF_SCHED_MASK, 876 GEN7_FF_TS_SCHED_HW | 877 GEN7_FF_VS_SCHED_HW | 878 GEN7_FF_DS_SCHED_HW); 879 880 if (0) { /* causes HiZ corruption on ivb:gt1 */ 881 /* enable HiZ Raw Stall Optimization */ 882 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 883 } 884 885 /* WaDisable4x2SubspanOptimization:ivb */ 886 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 887 888 /* 889 * BSpec recommends 8x4 when MSAA is used, 890 * however in practice 16x4 seems fastest. 891 * 892 * Note that PS/WM thread counts depend on the WIZ hashing 893 * disable bit, which we don't touch here, but it's good 894 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 895 */ 896 wa_add(wal, GEN7_GT_MODE, 0, 897 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 898 GEN6_WIZ_HASHING_16x4); 899 } 900 901 static void 902 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 903 { 904 /* WaDisableEarlyCull:vlv */ 905 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 906 907 /* WaPsdDispatchEnable:vlv */ 908 /* WaDisablePSDDualDispatchEnable:vlv */ 909 wa_masked_en(wal, 910 GEN7_HALF_SLICE_CHICKEN1, 911 GEN7_MAX_PS_THREAD_DEP | 912 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 913 914 /* WaDisable_RenderCache_OperationalFlush:vlv */ 915 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 916 917 /* WaForceL3Serialization:vlv */ 918 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 919 920 /* 921 * WaVSThreadDispatchOverride:ivb,vlv 922 * 923 * This actually overrides the dispatch 924 * mode for all thread types. 925 */ 926 wa_write_masked_or(wal, 927 GEN7_FF_THREAD_MODE, 928 GEN7_FF_SCHED_MASK, 929 GEN7_FF_TS_SCHED_HW | 930 GEN7_FF_VS_SCHED_HW | 931 GEN7_FF_DS_SCHED_HW); 932 933 /* 934 * BSpec says this must be set, even though 935 * WaDisable4x2SubspanOptimization isn't listed for VLV. 936 */ 937 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 938 939 /* 940 * BSpec recommends 8x4 when MSAA is used, 941 * however in practice 16x4 seems fastest. 942 * 943 * Note that PS/WM thread counts depend on the WIZ hashing 944 * disable bit, which we don't touch here, but it's good 945 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 946 */ 947 wa_add(wal, GEN7_GT_MODE, 0, 948 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 949 GEN6_WIZ_HASHING_16x4); 950 951 /* 952 * WaIncreaseL3CreditsForVLVB0:vlv 953 * This is the hardware default actually. 954 */ 955 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 956 } 957 958 static void 959 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 960 { 961 /* L3 caching of data atomics doesn't work -- disable it. */ 962 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 963 964 wa_add(wal, 965 HSW_ROW_CHICKEN3, 0, 966 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 967 0 /* XXX does this reg exist? */); 968 969 /* WaVSRefCountFullforceMissDisable:hsw */ 970 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 971 972 wa_masked_dis(wal, 973 CACHE_MODE_0_GEN7, 974 /* WaDisable_RenderCache_OperationalFlush:hsw */ 975 RC_OP_FLUSH_ENABLE | 976 /* enable HiZ Raw Stall Optimization */ 977 HIZ_RAW_STALL_OPT_DISABLE); 978 979 /* WaDisable4x2SubspanOptimization:hsw */ 980 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 981 982 /* 983 * BSpec recommends 8x4 when MSAA is used, 984 * however in practice 16x4 seems fastest. 985 * 986 * Note that PS/WM thread counts depend on the WIZ hashing 987 * disable bit, which we don't touch here, but it's good 988 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 989 */ 990 wa_add(wal, GEN7_GT_MODE, 0, 991 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 992 GEN6_WIZ_HASHING_16x4); 993 994 /* WaSampleCChickenBitEnable:hsw */ 995 wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 996 } 997 998 static void 999 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1000 { 1001 /* WaDisableKillLogic:bxt,skl,kbl */ 1002 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1003 wa_write_or(wal, 1004 GAM_ECOCHK, 1005 ECOCHK_DIS_TLB); 1006 1007 if (HAS_LLC(i915)) { 1008 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1009 * 1010 * Must match Display Engine. See 1011 * WaCompressedResourceDisplayNewHashMode. 1012 */ 1013 wa_write_or(wal, 1014 MMCD_MISC_CTRL, 1015 MMCD_PCLA | MMCD_HOTSPOT_EN); 1016 } 1017 1018 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1019 wa_write_or(wal, 1020 GAM_ECOCHK, 1021 BDW_DISABLE_HDC_INVALIDATION); 1022 } 1023 1024 static void 1025 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1026 { 1027 gen9_gt_workarounds_init(i915, wal); 1028 1029 /* WaDisableGafsUnitClkGating:skl */ 1030 wa_write_or(wal, 1031 GEN7_UCGCTL4, 1032 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1033 1034 /* WaInPlaceDecompressionHang:skl */ 1035 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 1036 wa_write_or(wal, 1037 GEN9_GAMT_ECO_REG_RW_IA, 1038 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1039 } 1040 1041 static void 1042 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1043 { 1044 gen9_gt_workarounds_init(i915, wal); 1045 1046 /* WaInPlaceDecompressionHang:bxt */ 1047 wa_write_or(wal, 1048 GEN9_GAMT_ECO_REG_RW_IA, 1049 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1050 } 1051 1052 static void 1053 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1054 { 1055 gen9_gt_workarounds_init(i915, wal); 1056 1057 /* WaDisableDynamicCreditSharing:kbl */ 1058 if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)) 1059 wa_write_or(wal, 1060 GAMT_CHKN_BIT_REG, 1061 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1062 1063 /* WaDisableGafsUnitClkGating:kbl */ 1064 wa_write_or(wal, 1065 GEN7_UCGCTL4, 1066 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1067 1068 /* WaInPlaceDecompressionHang:kbl */ 1069 wa_write_or(wal, 1070 GEN9_GAMT_ECO_REG_RW_IA, 1071 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1072 } 1073 1074 static void 1075 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1076 { 1077 gen9_gt_workarounds_init(i915, wal); 1078 } 1079 1080 static void 1081 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1082 { 1083 gen9_gt_workarounds_init(i915, wal); 1084 1085 /* WaDisableGafsUnitClkGating:cfl */ 1086 wa_write_or(wal, 1087 GEN7_UCGCTL4, 1088 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1089 1090 /* WaInPlaceDecompressionHang:cfl */ 1091 wa_write_or(wal, 1092 GEN9_GAMT_ECO_REG_RW_IA, 1093 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1094 } 1095 1096 static void 1097 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1098 { 1099 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; 1100 unsigned int slice, subslice; 1101 u32 l3_en, mcr, mcr_mask; 1102 1103 GEM_BUG_ON(INTEL_GEN(i915) < 10); 1104 1105 /* 1106 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 1107 * L3Banks could be fused off in single slice scenario. If that is 1108 * the case, we might need to program MCR select to a valid L3Bank 1109 * by default, to make sure we correctly read certain registers 1110 * later on (in the range 0xB100 - 0xB3FF). 1111 * 1112 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 1113 * Before any MMIO read into slice/subslice specific registers, MCR 1114 * packet control register needs to be programmed to point to any 1115 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1116 * This means each subsequent MMIO read will be forwarded to an 1117 * specific s/ss combination, but this is OK since these registers 1118 * are consistent across s/ss in almost all cases. In the rare 1119 * occasions, such as INSTDONE, where this value is dependent 1120 * on s/ss combo, the read should be done with read_subslice_reg. 1121 * 1122 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 1123 * to which subslice, or to which L3 bank, the respective mmio reads 1124 * will go, we have to find a common index which works for both 1125 * accesses. 1126 * 1127 * Case where we cannot find a common index fortunately should not 1128 * happen in production hardware, so we only emit a warning instead of 1129 * implementing something more complex that requires checking the range 1130 * of every MMIO read. 1131 */ 1132 1133 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 1134 u32 l3_fuse = 1135 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 1136 GEN10_L3BANK_MASK; 1137 1138 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 1139 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 1140 } else { 1141 l3_en = ~0; 1142 } 1143 1144 slice = fls(sseu->slice_mask) - 1; 1145 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 1146 if (!subslice) { 1147 drm_warn(&i915->drm, 1148 "No common index found between subslice mask %x and L3 bank mask %x!\n", 1149 intel_sseu_get_subslices(sseu, slice), l3_en); 1150 subslice = fls(l3_en); 1151 drm_WARN_ON(&i915->drm, !subslice); 1152 } 1153 subslice--; 1154 1155 if (INTEL_GEN(i915) >= 11) { 1156 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1157 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1158 } else { 1159 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1160 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1161 } 1162 1163 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 1164 1165 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1166 } 1167 1168 static void 1169 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1170 { 1171 wa_init_mcr(i915, wal); 1172 1173 /* WaInPlaceDecompressionHang:cnl */ 1174 wa_write_or(wal, 1175 GEN9_GAMT_ECO_REG_RW_IA, 1176 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1177 } 1178 1179 static void 1180 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1181 { 1182 wa_init_mcr(i915, wal); 1183 1184 /* WaInPlaceDecompressionHang:icl */ 1185 wa_write_or(wal, 1186 GEN9_GAMT_ECO_REG_RW_IA, 1187 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1188 1189 /* WaModifyGamTlbPartitioning:icl */ 1190 wa_write_masked_or(wal, 1191 GEN11_GACB_PERF_CTRL, 1192 GEN11_HASH_CTRL_MASK, 1193 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1194 1195 /* Wa_1405766107:icl 1196 * Formerly known as WaCL2SFHalfMaxAlloc 1197 */ 1198 wa_write_or(wal, 1199 GEN11_LSN_UNSLCVC, 1200 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1201 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1202 1203 /* Wa_220166154:icl 1204 * Formerly known as WaDisCtxReload 1205 */ 1206 wa_write_or(wal, 1207 GEN8_GAMW_ECO_DEV_RW_IA, 1208 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1209 1210 /* Wa_1405779004:icl (pre-prod) */ 1211 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 1212 wa_write_or(wal, 1213 SLICE_UNIT_LEVEL_CLKGATE, 1214 MSCUNIT_CLKGATE_DIS); 1215 1216 /* Wa_1406838659:icl (pre-prod) */ 1217 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1218 wa_write_or(wal, 1219 INF_UNIT_LEVEL_CLKGATE, 1220 CGPSF_CLKGATE_DIS); 1221 1222 /* Wa_1406463099:icl 1223 * Formerly known as WaGamTlbPendError 1224 */ 1225 wa_write_or(wal, 1226 GAMT_CHKN_BIT_REG, 1227 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1228 1229 /* Wa_1607087056:icl,ehl,jsl */ 1230 if (IS_ICELAKE(i915) || 1231 IS_JSL_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 1232 wa_write_or(wal, 1233 SLICE_UNIT_LEVEL_CLKGATE, 1234 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1235 } 1236 } 1237 1238 static void 1239 gen12_gt_workarounds_init(struct drm_i915_private *i915, 1240 struct i915_wa_list *wal) 1241 { 1242 wa_init_mcr(i915, wal); 1243 } 1244 1245 static void 1246 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1247 { 1248 gen12_gt_workarounds_init(i915, wal); 1249 1250 /* Wa_1409420604:tgl */ 1251 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1252 wa_write_or(wal, 1253 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1254 CPSSUNIT_CLKGATE_DIS); 1255 1256 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1257 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1258 wa_write_or(wal, 1259 SLICE_UNIT_LEVEL_CLKGATE, 1260 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1261 } 1262 1263 static void 1264 dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1265 { 1266 gen12_gt_workarounds_init(i915, wal); 1267 1268 /* Wa_1607087056:dg1 */ 1269 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)) 1270 wa_write_or(wal, 1271 SLICE_UNIT_LEVEL_CLKGATE, 1272 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1273 1274 /* Wa_1409420604:dg1 */ 1275 if (IS_DG1(i915)) 1276 wa_write_or(wal, 1277 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1278 CPSSUNIT_CLKGATE_DIS); 1279 1280 /* Wa_1408615072:dg1 */ 1281 /* Empirical testing shows this register is unaffected by engine reset. */ 1282 if (IS_DG1(i915)) 1283 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1284 VSUNIT_CLKGATE_DIS_TGL); 1285 } 1286 1287 static void 1288 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1289 { 1290 if (IS_DG1(i915)) 1291 dg1_gt_workarounds_init(i915, wal); 1292 else if (IS_TIGERLAKE(i915)) 1293 tgl_gt_workarounds_init(i915, wal); 1294 else if (IS_GEN(i915, 12)) 1295 gen12_gt_workarounds_init(i915, wal); 1296 else if (IS_GEN(i915, 11)) 1297 icl_gt_workarounds_init(i915, wal); 1298 else if (IS_CANNONLAKE(i915)) 1299 cnl_gt_workarounds_init(i915, wal); 1300 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1301 cfl_gt_workarounds_init(i915, wal); 1302 else if (IS_GEMINILAKE(i915)) 1303 glk_gt_workarounds_init(i915, wal); 1304 else if (IS_KABYLAKE(i915)) 1305 kbl_gt_workarounds_init(i915, wal); 1306 else if (IS_BROXTON(i915)) 1307 bxt_gt_workarounds_init(i915, wal); 1308 else if (IS_SKYLAKE(i915)) 1309 skl_gt_workarounds_init(i915, wal); 1310 else if (IS_HASWELL(i915)) 1311 hsw_gt_workarounds_init(i915, wal); 1312 else if (IS_VALLEYVIEW(i915)) 1313 vlv_gt_workarounds_init(i915, wal); 1314 else if (IS_IVYBRIDGE(i915)) 1315 ivb_gt_workarounds_init(i915, wal); 1316 else if (IS_GEN(i915, 6)) 1317 snb_gt_workarounds_init(i915, wal); 1318 else if (IS_GEN(i915, 5)) 1319 ilk_gt_workarounds_init(i915, wal); 1320 else if (IS_G4X(i915)) 1321 g4x_gt_workarounds_init(i915, wal); 1322 else if (IS_GEN(i915, 4)) 1323 gen4_gt_workarounds_init(i915, wal); 1324 else if (INTEL_GEN(i915) <= 8) 1325 return; 1326 else 1327 MISSING_CASE(INTEL_GEN(i915)); 1328 } 1329 1330 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1331 { 1332 struct i915_wa_list *wal = &i915->gt_wa_list; 1333 1334 wa_init_start(wal, "GT", "global"); 1335 gt_init_workarounds(i915, wal); 1336 wa_init_finish(wal); 1337 } 1338 1339 static enum forcewake_domains 1340 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1341 { 1342 enum forcewake_domains fw = 0; 1343 struct i915_wa *wa; 1344 unsigned int i; 1345 1346 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1347 fw |= intel_uncore_forcewake_for_reg(uncore, 1348 wa->reg, 1349 FW_REG_READ | 1350 FW_REG_WRITE); 1351 1352 return fw; 1353 } 1354 1355 static bool 1356 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1357 { 1358 if ((cur ^ wa->set) & wa->read) { 1359 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1360 name, from, i915_mmio_reg_offset(wa->reg), 1361 cur, cur & wa->read, wa->set); 1362 1363 return false; 1364 } 1365 1366 return true; 1367 } 1368 1369 static void 1370 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1371 { 1372 enum forcewake_domains fw; 1373 unsigned long flags; 1374 struct i915_wa *wa; 1375 unsigned int i; 1376 1377 if (!wal->count) 1378 return; 1379 1380 fw = wal_get_fw_for_rmw(uncore, wal); 1381 1382 spin_lock_irqsave(&uncore->lock, flags); 1383 intel_uncore_forcewake_get__locked(uncore, fw); 1384 1385 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1386 if (wa->clr) 1387 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1388 else 1389 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1390 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1391 wa_verify(wa, 1392 intel_uncore_read_fw(uncore, wa->reg), 1393 wal->name, "application"); 1394 } 1395 1396 intel_uncore_forcewake_put__locked(uncore, fw); 1397 spin_unlock_irqrestore(&uncore->lock, flags); 1398 } 1399 1400 void intel_gt_apply_workarounds(struct intel_gt *gt) 1401 { 1402 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1403 } 1404 1405 static bool wa_list_verify(struct intel_uncore *uncore, 1406 const struct i915_wa_list *wal, 1407 const char *from) 1408 { 1409 struct i915_wa *wa; 1410 unsigned int i; 1411 bool ok = true; 1412 1413 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1414 ok &= wa_verify(wa, 1415 intel_uncore_read(uncore, wa->reg), 1416 wal->name, from); 1417 1418 return ok; 1419 } 1420 1421 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1422 { 1423 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1424 } 1425 1426 static inline bool is_nonpriv_flags_valid(u32 flags) 1427 { 1428 /* Check only valid flag bits are set */ 1429 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1430 return false; 1431 1432 /* NB: Only 3 out of 4 enum values are valid for access field */ 1433 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1434 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1435 return false; 1436 1437 return true; 1438 } 1439 1440 static void 1441 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1442 { 1443 struct i915_wa wa = { 1444 .reg = reg 1445 }; 1446 1447 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1448 return; 1449 1450 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1451 return; 1452 1453 wa.reg.reg |= flags; 1454 _wa_add(wal, &wa); 1455 } 1456 1457 static void 1458 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1459 { 1460 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1461 } 1462 1463 static void gen9_whitelist_build(struct i915_wa_list *w) 1464 { 1465 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1466 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1467 1468 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1469 whitelist_reg(w, GEN8_CS_CHICKEN1); 1470 1471 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1472 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1473 1474 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1475 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1476 } 1477 1478 static void skl_whitelist_build(struct intel_engine_cs *engine) 1479 { 1480 struct i915_wa_list *w = &engine->whitelist; 1481 1482 if (engine->class != RENDER_CLASS) 1483 return; 1484 1485 gen9_whitelist_build(w); 1486 1487 /* WaDisableLSQCROPERFforOCL:skl */ 1488 whitelist_reg(w, GEN8_L3SQCREG4); 1489 } 1490 1491 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1492 { 1493 if (engine->class != RENDER_CLASS) 1494 return; 1495 1496 gen9_whitelist_build(&engine->whitelist); 1497 } 1498 1499 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1500 { 1501 struct i915_wa_list *w = &engine->whitelist; 1502 1503 if (engine->class != RENDER_CLASS) 1504 return; 1505 1506 gen9_whitelist_build(w); 1507 1508 /* WaDisableLSQCROPERFforOCL:kbl */ 1509 whitelist_reg(w, GEN8_L3SQCREG4); 1510 } 1511 1512 static void glk_whitelist_build(struct intel_engine_cs *engine) 1513 { 1514 struct i915_wa_list *w = &engine->whitelist; 1515 1516 if (engine->class != RENDER_CLASS) 1517 return; 1518 1519 gen9_whitelist_build(w); 1520 1521 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1522 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1523 } 1524 1525 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1526 { 1527 struct i915_wa_list *w = &engine->whitelist; 1528 1529 if (engine->class != RENDER_CLASS) 1530 return; 1531 1532 gen9_whitelist_build(w); 1533 1534 /* 1535 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1536 * 1537 * This covers 4 register which are next to one another : 1538 * - PS_INVOCATION_COUNT 1539 * - PS_INVOCATION_COUNT_UDW 1540 * - PS_DEPTH_COUNT 1541 * - PS_DEPTH_COUNT_UDW 1542 */ 1543 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1544 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1545 RING_FORCE_TO_NONPRIV_RANGE_4); 1546 } 1547 1548 static void cml_whitelist_build(struct intel_engine_cs *engine) 1549 { 1550 struct i915_wa_list *w = &engine->whitelist; 1551 1552 if (engine->class != RENDER_CLASS) 1553 whitelist_reg_ext(w, 1554 RING_CTX_TIMESTAMP(engine->mmio_base), 1555 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1556 1557 cfl_whitelist_build(engine); 1558 } 1559 1560 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1561 { 1562 struct i915_wa_list *w = &engine->whitelist; 1563 1564 if (engine->class != RENDER_CLASS) 1565 return; 1566 1567 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1568 whitelist_reg(w, GEN8_CS_CHICKEN1); 1569 } 1570 1571 static void icl_whitelist_build(struct intel_engine_cs *engine) 1572 { 1573 struct i915_wa_list *w = &engine->whitelist; 1574 1575 switch (engine->class) { 1576 case RENDER_CLASS: 1577 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1578 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1579 1580 /* WaAllowUMDToModifySamplerMode:icl */ 1581 whitelist_reg(w, GEN10_SAMPLER_MODE); 1582 1583 /* WaEnableStateCacheRedirectToCS:icl */ 1584 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1585 1586 /* 1587 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1588 * 1589 * This covers 4 register which are next to one another : 1590 * - PS_INVOCATION_COUNT 1591 * - PS_INVOCATION_COUNT_UDW 1592 * - PS_DEPTH_COUNT 1593 * - PS_DEPTH_COUNT_UDW 1594 */ 1595 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1596 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1597 RING_FORCE_TO_NONPRIV_RANGE_4); 1598 break; 1599 1600 case VIDEO_DECODE_CLASS: 1601 /* hucStatusRegOffset */ 1602 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1603 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1604 /* hucUKernelHdrInfoRegOffset */ 1605 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1606 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1607 /* hucStatus2RegOffset */ 1608 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1609 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1610 whitelist_reg_ext(w, 1611 RING_CTX_TIMESTAMP(engine->mmio_base), 1612 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1613 break; 1614 1615 default: 1616 whitelist_reg_ext(w, 1617 RING_CTX_TIMESTAMP(engine->mmio_base), 1618 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1619 break; 1620 } 1621 } 1622 1623 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1624 { 1625 struct i915_wa_list *w = &engine->whitelist; 1626 1627 switch (engine->class) { 1628 case RENDER_CLASS: 1629 /* 1630 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1631 * Wa_1408556865:tgl 1632 * 1633 * This covers 4 registers which are next to one another : 1634 * - PS_INVOCATION_COUNT 1635 * - PS_INVOCATION_COUNT_UDW 1636 * - PS_DEPTH_COUNT 1637 * - PS_DEPTH_COUNT_UDW 1638 */ 1639 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1640 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1641 RING_FORCE_TO_NONPRIV_RANGE_4); 1642 1643 /* Wa_1808121037:tgl */ 1644 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1645 1646 /* Wa_1806527549:tgl */ 1647 whitelist_reg(w, HIZ_CHICKEN); 1648 break; 1649 default: 1650 whitelist_reg_ext(w, 1651 RING_CTX_TIMESTAMP(engine->mmio_base), 1652 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1653 break; 1654 } 1655 } 1656 1657 static void dg1_whitelist_build(struct intel_engine_cs *engine) 1658 { 1659 struct i915_wa_list *w = &engine->whitelist; 1660 1661 tgl_whitelist_build(engine); 1662 1663 /* GEN:BUG:1409280441:dg1 */ 1664 if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) && 1665 (engine->class == RENDER_CLASS || 1666 engine->class == COPY_ENGINE_CLASS)) 1667 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 1668 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1669 } 1670 1671 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1672 { 1673 struct drm_i915_private *i915 = engine->i915; 1674 struct i915_wa_list *w = &engine->whitelist; 1675 1676 wa_init_start(w, "whitelist", engine->name); 1677 1678 if (IS_DG1(i915)) 1679 dg1_whitelist_build(engine); 1680 else if (IS_GEN(i915, 12)) 1681 tgl_whitelist_build(engine); 1682 else if (IS_GEN(i915, 11)) 1683 icl_whitelist_build(engine); 1684 else if (IS_CANNONLAKE(i915)) 1685 cnl_whitelist_build(engine); 1686 else if (IS_COMETLAKE(i915)) 1687 cml_whitelist_build(engine); 1688 else if (IS_COFFEELAKE(i915)) 1689 cfl_whitelist_build(engine); 1690 else if (IS_GEMINILAKE(i915)) 1691 glk_whitelist_build(engine); 1692 else if (IS_KABYLAKE(i915)) 1693 kbl_whitelist_build(engine); 1694 else if (IS_BROXTON(i915)) 1695 bxt_whitelist_build(engine); 1696 else if (IS_SKYLAKE(i915)) 1697 skl_whitelist_build(engine); 1698 else if (INTEL_GEN(i915) <= 8) 1699 return; 1700 else 1701 MISSING_CASE(INTEL_GEN(i915)); 1702 1703 wa_init_finish(w); 1704 } 1705 1706 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1707 { 1708 const struct i915_wa_list *wal = &engine->whitelist; 1709 struct intel_uncore *uncore = engine->uncore; 1710 const u32 base = engine->mmio_base; 1711 struct i915_wa *wa; 1712 unsigned int i; 1713 1714 if (!wal->count) 1715 return; 1716 1717 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1718 intel_uncore_write(uncore, 1719 RING_FORCE_TO_NONPRIV(base, i), 1720 i915_mmio_reg_offset(wa->reg)); 1721 1722 /* And clear the rest just in case of garbage */ 1723 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1724 intel_uncore_write(uncore, 1725 RING_FORCE_TO_NONPRIV(base, i), 1726 i915_mmio_reg_offset(RING_NOPID(base))); 1727 } 1728 1729 static void 1730 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1731 { 1732 struct drm_i915_private *i915 = engine->i915; 1733 1734 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || 1735 IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1736 /* 1737 * Wa_1607138336:tgl[a0],dg1[a0] 1738 * Wa_1607063988:tgl[a0],dg1[a0] 1739 */ 1740 wa_write_or(wal, 1741 GEN9_CTX_PREEMPT_REG, 1742 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1743 } 1744 1745 if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1746 /* 1747 * Wa_1606679103:tgl 1748 * (see also Wa_1606682166:icl) 1749 */ 1750 wa_write_or(wal, 1751 GEN7_SARCHKMD, 1752 GEN7_DISABLE_SAMPLER_PREFETCH); 1753 1754 /* Wa_1408615072:tgl */ 1755 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1756 VSUNIT_CLKGATE_DIS_TGL); 1757 } 1758 1759 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1760 /* Wa_1606931601:tgl,rkl,dg1 */ 1761 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1762 1763 /* 1764 * Wa_1407928979:tgl A* 1765 * Wa_18011464164:tgl[B0+],dg1[B0+] 1766 * Wa_22010931296:tgl[B0+],dg1[B0+] 1767 * Wa_14010919138:rkl, dg1 1768 */ 1769 wa_write_or(wal, GEN7_FF_THREAD_MODE, 1770 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1771 } 1772 1773 if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || 1774 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 1775 /* Wa_1409804808:tgl,rkl,dg1[a0] */ 1776 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1777 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1778 1779 /* 1780 * Wa_1409085225:tgl 1781 * Wa_14010229206:tgl,rkl,dg1[a0] 1782 */ 1783 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1784 1785 /* 1786 * Wa_1607030317:tgl 1787 * Wa_1607186500:tgl 1788 * Wa_1607297627:tgl,rkl,dg1[a0] 1789 * 1790 * On TGL and RKL there are multiple entries for this WA in the 1791 * BSpec; some indicate this is an A0-only WA, others indicate 1792 * it applies to all steppings so we trust the "all steppings." 1793 * For DG1 this only applies to A0. 1794 */ 1795 wa_masked_en(wal, 1796 GEN6_RC_SLEEP_PSMI_CONTROL, 1797 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1798 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1799 1800 /* 1801 * Wa_1606700617:tgl 1802 * Wa_22010271021:tgl,rkl 1803 */ 1804 wa_masked_en(wal, 1805 GEN9_CS_DEBUG_MODE1, 1806 FF_DOP_CLOCK_GATE_DISABLE); 1807 } 1808 1809 if (IS_GEN(i915, 12)) { 1810 /* Wa_1406941453:gen12 */ 1811 wa_masked_en(wal, 1812 GEN10_SAMPLER_MODE, 1813 ENABLE_SMALLPL); 1814 } 1815 1816 if (IS_GEN(i915, 11)) { 1817 /* This is not an Wa. Enable for better image quality */ 1818 wa_masked_en(wal, 1819 _3D_CHICKEN3, 1820 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1821 1822 /* WaPipelineFlushCoherentLines:icl */ 1823 wa_write_or(wal, 1824 GEN8_L3SQCREG4, 1825 GEN8_LQSC_FLUSH_COHERENT_LINES); 1826 1827 /* 1828 * Wa_1405543622:icl 1829 * Formerly known as WaGAPZPriorityScheme 1830 */ 1831 wa_write_or(wal, 1832 GEN8_GARBCNTL, 1833 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1834 1835 /* 1836 * Wa_1604223664:icl 1837 * Formerly known as WaL3BankAddressHashing 1838 */ 1839 wa_write_masked_or(wal, 1840 GEN8_GARBCNTL, 1841 GEN11_HASH_CTRL_EXCL_MASK, 1842 GEN11_HASH_CTRL_EXCL_BIT0); 1843 wa_write_masked_or(wal, 1844 GEN11_GLBLINVL, 1845 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1846 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1847 1848 /* 1849 * Wa_1405733216:icl 1850 * Formerly known as WaDisableCleanEvicts 1851 */ 1852 wa_write_or(wal, 1853 GEN8_L3SQCREG4, 1854 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1855 1856 /* WaForwardProgressSoftReset:icl */ 1857 wa_write_or(wal, 1858 GEN10_SCRATCH_LNCF2, 1859 PMFLUSHDONE_LNICRSDROP | 1860 PMFLUSH_GAPL3UNBLOCK | 1861 PMFLUSHDONE_LNEBLK); 1862 1863 /* Wa_1406609255:icl (pre-prod) */ 1864 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1865 wa_write_or(wal, 1866 GEN7_SARCHKMD, 1867 GEN7_DISABLE_DEMAND_PREFETCH); 1868 1869 /* Wa_1606682166:icl */ 1870 wa_write_or(wal, 1871 GEN7_SARCHKMD, 1872 GEN7_DISABLE_SAMPLER_PREFETCH); 1873 1874 /* Wa_1409178092:icl */ 1875 wa_write_masked_or(wal, 1876 GEN11_SCRATCH2, 1877 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1878 0); 1879 1880 /* WaEnable32PlaneMode:icl */ 1881 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1882 GEN11_ENABLE_32_PLANE_MODE); 1883 1884 /* 1885 * Wa_1408615072:icl,ehl (vsunit) 1886 * Wa_1407596294:icl,ehl (hsunit) 1887 */ 1888 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1889 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1890 1891 /* Wa_1407352427:icl,ehl */ 1892 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1893 PSDUNIT_CLKGATE_DIS); 1894 1895 /* Wa_1406680159:icl,ehl */ 1896 wa_write_or(wal, 1897 SUBSLICE_UNIT_LEVEL_CLKGATE, 1898 GWUNIT_CLKGATE_DIS); 1899 1900 /* 1901 * Wa_1408767742:icl[a2..forever],ehl[all] 1902 * Wa_1605460711:icl[a0..c0] 1903 */ 1904 wa_write_or(wal, 1905 GEN7_FF_THREAD_MODE, 1906 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1907 1908 /* Wa_22010271021:ehl */ 1909 if (IS_JSL_EHL(i915)) 1910 wa_masked_en(wal, 1911 GEN9_CS_DEBUG_MODE1, 1912 FF_DOP_CLOCK_GATE_DISABLE); 1913 } 1914 1915 if (IS_GEN_RANGE(i915, 9, 12)) { 1916 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1917 wa_masked_en(wal, 1918 GEN7_FF_SLICE_CS_CHICKEN1, 1919 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1920 } 1921 1922 if (IS_SKYLAKE(i915) || 1923 IS_KABYLAKE(i915) || 1924 IS_COFFEELAKE(i915) || 1925 IS_COMETLAKE(i915)) { 1926 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1927 wa_write_or(wal, 1928 GEN8_GARBCNTL, 1929 GEN9_GAPS_TSV_CREDIT_DISABLE); 1930 } 1931 1932 if (IS_BROXTON(i915)) { 1933 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1934 wa_masked_en(wal, 1935 FF_SLICE_CS_CHICKEN2, 1936 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1937 } 1938 1939 if (IS_GEN(i915, 9)) { 1940 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1941 wa_masked_en(wal, 1942 GEN9_CSFE_CHICKEN1_RCS, 1943 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1944 1945 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1946 wa_write_or(wal, 1947 BDW_SCRATCH1, 1948 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1949 1950 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1951 if (IS_GEN9_LP(i915)) 1952 wa_write_masked_or(wal, 1953 GEN8_L3SQCREG1, 1954 L3_PRIO_CREDITS_MASK, 1955 L3_GENERAL_PRIO_CREDITS(62) | 1956 L3_HIGH_PRIO_CREDITS(2)); 1957 1958 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1959 wa_write_or(wal, 1960 GEN8_L3SQCREG4, 1961 GEN8_LQSC_FLUSH_COHERENT_LINES); 1962 } 1963 1964 if (IS_GEN(i915, 7)) 1965 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1966 wa_masked_en(wal, 1967 GFX_MODE_GEN7, 1968 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1969 1970 if (IS_GEN_RANGE(i915, 6, 7)) 1971 /* 1972 * We need to disable the AsyncFlip performance optimisations in 1973 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1974 * already be programmed to '1' on all products. 1975 * 1976 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1977 */ 1978 wa_masked_en(wal, 1979 MI_MODE, 1980 ASYNC_FLIP_PERF_DISABLE); 1981 1982 if (IS_GEN(i915, 6)) { 1983 /* 1984 * Required for the hardware to program scanline values for 1985 * waiting 1986 * WaEnableFlushTlbInvalidationMode:snb 1987 */ 1988 wa_masked_en(wal, 1989 GFX_MODE, 1990 GFX_TLB_INVALIDATE_EXPLICIT); 1991 1992 /* 1993 * From the Sandybridge PRM, volume 1 part 3, page 24: 1994 * "If this bit is set, STCunit will have LRA as replacement 1995 * policy. [...] This bit must be reset. LRA replacement 1996 * policy is not supported." 1997 */ 1998 wa_masked_dis(wal, 1999 CACHE_MODE_0, 2000 CM0_STC_EVICT_DISABLE_LRA_SNB); 2001 } 2002 2003 if (IS_GEN_RANGE(i915, 4, 6)) 2004 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2005 wa_add(wal, MI_MODE, 2006 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2007 /* XXX bit doesn't stick on Broadwater */ 2008 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 2009 2010 if (IS_GEN(i915, 4)) 2011 /* 2012 * Disable CONSTANT_BUFFER before it is loaded from the context 2013 * image. For as it is loaded, it is executed and the stored 2014 * address may no longer be valid, leading to a GPU hang. 2015 * 2016 * This imposes the requirement that userspace reload their 2017 * CONSTANT_BUFFER on every batch, fortunately a requirement 2018 * they are already accustomed to from before contexts were 2019 * enabled. 2020 */ 2021 wa_add(wal, ECOSKPD, 2022 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2023 0 /* XXX bit doesn't stick on Broadwater */); 2024 } 2025 2026 static void 2027 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2028 { 2029 struct drm_i915_private *i915 = engine->i915; 2030 2031 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2032 if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 2033 wa_write(wal, 2034 RING_SEMA_WAIT_POLL(engine->mmio_base), 2035 1); 2036 } 2037 } 2038 2039 static void 2040 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2041 { 2042 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 2043 return; 2044 2045 if (engine->class == RENDER_CLASS) 2046 rcs_engine_wa_init(engine, wal); 2047 else 2048 xcs_engine_wa_init(engine, wal); 2049 } 2050 2051 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 2052 { 2053 struct i915_wa_list *wal = &engine->wa_list; 2054 2055 if (INTEL_GEN(engine->i915) < 4) 2056 return; 2057 2058 wa_init_start(wal, "engine", engine->name); 2059 engine_init_workarounds(engine, wal); 2060 wa_init_finish(wal); 2061 } 2062 2063 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 2064 { 2065 wa_list_apply(engine->uncore, &engine->wa_list); 2066 } 2067 2068 static struct i915_vma * 2069 create_scratch(struct i915_address_space *vm, int count) 2070 { 2071 struct drm_i915_gem_object *obj; 2072 struct i915_vma *vma; 2073 unsigned int size; 2074 int err; 2075 2076 size = round_up(count * sizeof(u32), PAGE_SIZE); 2077 obj = i915_gem_object_create_internal(vm->i915, size); 2078 if (IS_ERR(obj)) 2079 return ERR_CAST(obj); 2080 2081 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 2082 2083 vma = i915_vma_instance(obj, vm, NULL); 2084 if (IS_ERR(vma)) { 2085 err = PTR_ERR(vma); 2086 goto err_obj; 2087 } 2088 2089 err = i915_vma_pin(vma, 0, 0, 2090 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 2091 if (err) 2092 goto err_obj; 2093 2094 return vma; 2095 2096 err_obj: 2097 i915_gem_object_put(obj); 2098 return ERR_PTR(err); 2099 } 2100 2101 struct mcr_range { 2102 u32 start; 2103 u32 end; 2104 }; 2105 2106 static const struct mcr_range mcr_ranges_gen8[] = { 2107 { .start = 0x5500, .end = 0x55ff }, 2108 { .start = 0x7000, .end = 0x7fff }, 2109 { .start = 0x9400, .end = 0x97ff }, 2110 { .start = 0xb000, .end = 0xb3ff }, 2111 { .start = 0xe000, .end = 0xe7ff }, 2112 {}, 2113 }; 2114 2115 static const struct mcr_range mcr_ranges_gen12[] = { 2116 { .start = 0x8150, .end = 0x815f }, 2117 { .start = 0x9520, .end = 0x955f }, 2118 { .start = 0xb100, .end = 0xb3ff }, 2119 { .start = 0xde80, .end = 0xe8ff }, 2120 { .start = 0x24a00, .end = 0x24a7f }, 2121 {}, 2122 }; 2123 2124 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 2125 { 2126 const struct mcr_range *mcr_ranges; 2127 int i; 2128 2129 if (INTEL_GEN(i915) >= 12) 2130 mcr_ranges = mcr_ranges_gen12; 2131 else if (INTEL_GEN(i915) >= 8) 2132 mcr_ranges = mcr_ranges_gen8; 2133 else 2134 return false; 2135 2136 /* 2137 * Registers in these ranges are affected by the MCR selector 2138 * which only controls CPU initiated MMIO. Routing does not 2139 * work for CS access so we cannot verify them on this path. 2140 */ 2141 for (i = 0; mcr_ranges[i].start; i++) 2142 if (offset >= mcr_ranges[i].start && 2143 offset <= mcr_ranges[i].end) 2144 return true; 2145 2146 return false; 2147 } 2148 2149 static int 2150 wa_list_srm(struct i915_request *rq, 2151 const struct i915_wa_list *wal, 2152 struct i915_vma *vma) 2153 { 2154 struct drm_i915_private *i915 = rq->engine->i915; 2155 unsigned int i, count = 0; 2156 const struct i915_wa *wa; 2157 u32 srm, *cs; 2158 2159 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 2160 if (INTEL_GEN(i915) >= 8) 2161 srm++; 2162 2163 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2164 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 2165 count++; 2166 } 2167 2168 cs = intel_ring_begin(rq, 4 * count); 2169 if (IS_ERR(cs)) 2170 return PTR_ERR(cs); 2171 2172 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2173 u32 offset = i915_mmio_reg_offset(wa->reg); 2174 2175 if (mcr_range(i915, offset)) 2176 continue; 2177 2178 *cs++ = srm; 2179 *cs++ = offset; 2180 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 2181 *cs++ = 0; 2182 } 2183 intel_ring_advance(rq, cs); 2184 2185 return 0; 2186 } 2187 2188 static int engine_wa_list_verify(struct intel_context *ce, 2189 const struct i915_wa_list * const wal, 2190 const char *from) 2191 { 2192 const struct i915_wa *wa; 2193 struct i915_request *rq; 2194 struct i915_vma *vma; 2195 struct i915_gem_ww_ctx ww; 2196 unsigned int i; 2197 u32 *results; 2198 int err; 2199 2200 if (!wal->count) 2201 return 0; 2202 2203 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 2204 if (IS_ERR(vma)) 2205 return PTR_ERR(vma); 2206 2207 intel_engine_pm_get(ce->engine); 2208 i915_gem_ww_ctx_init(&ww, false); 2209 retry: 2210 err = i915_gem_object_lock(vma->obj, &ww); 2211 if (err == 0) 2212 err = intel_context_pin_ww(ce, &ww); 2213 if (err) 2214 goto err_pm; 2215 2216 rq = i915_request_create(ce); 2217 if (IS_ERR(rq)) { 2218 err = PTR_ERR(rq); 2219 goto err_unpin; 2220 } 2221 2222 err = i915_request_await_object(rq, vma->obj, true); 2223 if (err == 0) 2224 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 2225 if (err == 0) 2226 err = wa_list_srm(rq, wal, vma); 2227 2228 i915_request_get(rq); 2229 if (err) 2230 i915_request_set_error_once(rq, err); 2231 i915_request_add(rq); 2232 2233 if (err) 2234 goto err_rq; 2235 2236 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2237 err = -ETIME; 2238 goto err_rq; 2239 } 2240 2241 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2242 if (IS_ERR(results)) { 2243 err = PTR_ERR(results); 2244 goto err_rq; 2245 } 2246 2247 err = 0; 2248 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2249 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 2250 continue; 2251 2252 if (!wa_verify(wa, results[i], wal->name, from)) 2253 err = -ENXIO; 2254 } 2255 2256 i915_gem_object_unpin_map(vma->obj); 2257 2258 err_rq: 2259 i915_request_put(rq); 2260 err_unpin: 2261 intel_context_unpin(ce); 2262 err_pm: 2263 if (err == -EDEADLK) { 2264 err = i915_gem_ww_ctx_backoff(&ww); 2265 if (!err) 2266 goto retry; 2267 } 2268 i915_gem_ww_ctx_fini(&ww); 2269 intel_engine_pm_put(ce->engine); 2270 i915_vma_unpin(vma); 2271 i915_vma_put(vma); 2272 return err; 2273 } 2274 2275 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2276 const char *from) 2277 { 2278 return engine_wa_list_verify(engine->kernel_context, 2279 &engine->wa_list, 2280 from); 2281 } 2282 2283 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2284 #include "selftest_workarounds.c" 2285 #endif 2286