1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 106 wal->list = list; 107 } 108 109 while (start < end) { 110 unsigned int mid = start + (end - start) / 2; 111 112 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 113 start = mid + 1; 114 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 115 end = mid; 116 } else { 117 wa_ = &wal->list[mid]; 118 119 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 120 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 121 i915_mmio_reg_offset(wa_->reg), 122 wa_->clr, wa_->set); 123 124 wa_->set &= ~wa->clr; 125 } 126 127 wal->wa_count++; 128 wa_->set |= wa->set; 129 wa_->clr |= wa->clr; 130 wa_->read |= wa->read; 131 return; 132 } 133 } 134 135 wal->wa_count++; 136 wa_ = &wal->list[wal->count++]; 137 *wa_ = *wa; 138 139 while (wa_-- > wal->list) { 140 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 141 i915_mmio_reg_offset(wa_[1].reg)); 142 if (i915_mmio_reg_offset(wa_[1].reg) > 143 i915_mmio_reg_offset(wa_[0].reg)) 144 break; 145 146 swap(wa_[1], wa_[0]); 147 } 148 } 149 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 151 u32 clear, u32 set, u32 read_mask) 152 { 153 struct i915_wa wa = { 154 .reg = reg, 155 .clr = clear, 156 .set = set, 157 .read = read_mask, 158 }; 159 160 _wa_add(wal, &wa); 161 } 162 163 static void 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 165 { 166 wa_add(wal, reg, clear, set, clear); 167 } 168 169 static void 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 171 { 172 wa_write_masked_or(wal, reg, ~0, set); 173 } 174 175 static void 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 177 { 178 wa_write_masked_or(wal, reg, set, set); 179 } 180 181 static void 182 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 183 { 184 wa_write_masked_or(wal, reg, clr, 0); 185 } 186 187 static void 188 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 189 { 190 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 191 } 192 193 static void 194 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 195 { 196 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 197 } 198 199 #define WA_SET_BIT_MASKED(addr, mask) \ 200 wa_masked_en(wal, (addr), (mask)) 201 202 #define WA_CLR_BIT_MASKED(addr, mask) \ 203 wa_masked_dis(wal, (addr), (mask)) 204 205 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 206 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 207 208 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 209 struct i915_wa_list *wal) 210 { 211 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 212 213 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 214 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 215 216 /* WaDisablePartialInstShootdown:bdw,chv */ 217 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 218 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 219 220 /* Use Force Non-Coherent whenever executing a 3D context. This is a 221 * workaround for for a possible hang in the unlikely event a TLB 222 * invalidation occurs during a PSD flush. 223 */ 224 /* WaForceEnableNonCoherent:bdw,chv */ 225 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 226 WA_SET_BIT_MASKED(HDC_CHICKEN0, 227 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 228 HDC_FORCE_NON_COHERENT); 229 230 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 231 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 232 * polygons in the same 8x4 pixel/sample area to be processed without 233 * stalling waiting for the earlier ones to write to Hierarchical Z 234 * buffer." 235 * 236 * This optimization is off by default for BDW and CHV; turn it on. 237 */ 238 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 239 240 /* Wa4x4STCOptimizationDisable:bdw,chv */ 241 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 242 243 /* 244 * BSpec recommends 8x4 when MSAA is used, 245 * however in practice 16x4 seems fastest. 246 * 247 * Note that PS/WM thread counts depend on the WIZ hashing 248 * disable bit, which we don't touch here, but it's good 249 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 250 */ 251 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 252 GEN6_WIZ_HASHING_MASK, 253 GEN6_WIZ_HASHING_16x4); 254 } 255 256 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 257 struct i915_wa_list *wal) 258 { 259 struct drm_i915_private *i915 = engine->i915; 260 261 gen8_ctx_workarounds_init(engine, wal); 262 263 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 264 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 265 266 /* WaDisableDopClockGating:bdw 267 * 268 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 269 * to disable EUTC clock gating. 270 */ 271 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 272 DOP_CLOCK_GATING_DISABLE); 273 274 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 275 GEN8_SAMPLER_POWER_BYPASS_DIS); 276 277 WA_SET_BIT_MASKED(HDC_CHICKEN0, 278 /* WaForceContextSaveRestoreNonCoherent:bdw */ 279 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 280 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 281 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 282 } 283 284 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 285 struct i915_wa_list *wal) 286 { 287 gen8_ctx_workarounds_init(engine, wal); 288 289 /* WaDisableThreadStallDopClockGating:chv */ 290 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 291 292 /* Improve HiZ throughput on CHV. */ 293 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 294 } 295 296 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 297 struct i915_wa_list *wal) 298 { 299 struct drm_i915_private *i915 = engine->i915; 300 301 if (HAS_LLC(i915)) { 302 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 303 * 304 * Must match Display Engine. See 305 * WaCompressedResourceDisplayNewHashMode. 306 */ 307 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 308 GEN9_PBE_COMPRESSED_HASH_SELECTION); 309 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 310 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 311 } 312 313 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 314 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 315 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 316 FLOW_CONTROL_ENABLE | 317 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 318 319 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 320 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 321 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 322 GEN9_ENABLE_YV12_BUGFIX | 323 GEN9_ENABLE_GPGPU_PREEMPTION); 324 325 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 326 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 327 WA_SET_BIT_MASKED(CACHE_MODE_1, 328 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 329 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 330 331 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 332 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 333 GEN9_CCS_TLB_PREFETCH_ENABLE); 334 335 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 336 WA_SET_BIT_MASKED(HDC_CHICKEN0, 337 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 338 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 339 340 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 341 * both tied to WaForceContextSaveRestoreNonCoherent 342 * in some hsds for skl. We keep the tie for all gen9. The 343 * documentation is a bit hazy and so we want to get common behaviour, 344 * even though there is no clear evidence we would need both on kbl/bxt. 345 * This area has been source of system hangs so we play it safe 346 * and mimic the skl regardless of what bspec says. 347 * 348 * Use Force Non-Coherent whenever executing a 3D context. This 349 * is a workaround for a possible hang in the unlikely event 350 * a TLB invalidation occurs during a PSD flush. 351 */ 352 353 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 354 WA_SET_BIT_MASKED(HDC_CHICKEN0, 355 HDC_FORCE_NON_COHERENT); 356 357 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 358 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) 359 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 360 GEN8_SAMPLER_POWER_BYPASS_DIS); 361 362 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 363 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 364 365 /* 366 * Supporting preemption with fine-granularity requires changes in the 367 * batch buffer programming. Since we can't break old userspace, we 368 * need to set our default preemption level to safe value. Userspace is 369 * still able to use more fine-grained preemption levels, since in 370 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 371 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 372 * not real HW workarounds, but merely a way to start using preemption 373 * while maintaining old contract with userspace. 374 */ 375 376 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 377 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 378 379 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 380 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 381 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 382 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 383 384 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 385 if (IS_GEN9_LP(i915)) 386 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 387 } 388 389 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 390 struct i915_wa_list *wal) 391 { 392 struct drm_i915_private *i915 = engine->i915; 393 u8 vals[3] = { 0, 0, 0 }; 394 unsigned int i; 395 396 for (i = 0; i < 3; i++) { 397 u8 ss; 398 399 /* 400 * Only consider slices where one, and only one, subslice has 7 401 * EUs 402 */ 403 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) 404 continue; 405 406 /* 407 * subslice_7eu[i] != 0 (because of the check above) and 408 * ss_max == 4 (maximum number of subslices possible per slice) 409 * 410 * -> 0 <= ss <= 3; 411 */ 412 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; 413 vals[i] = 3 - ss; 414 } 415 416 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 417 return; 418 419 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 420 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 421 GEN9_IZ_HASHING_MASK(2) | 422 GEN9_IZ_HASHING_MASK(1) | 423 GEN9_IZ_HASHING_MASK(0), 424 GEN9_IZ_HASHING(2, vals[2]) | 425 GEN9_IZ_HASHING(1, vals[1]) | 426 GEN9_IZ_HASHING(0, vals[0])); 427 } 428 429 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 430 struct i915_wa_list *wal) 431 { 432 gen9_ctx_workarounds_init(engine, wal); 433 skl_tune_iz_hashing(engine, wal); 434 } 435 436 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 437 struct i915_wa_list *wal) 438 { 439 gen9_ctx_workarounds_init(engine, wal); 440 441 /* WaDisableThreadStallDopClockGating:bxt */ 442 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 443 STALL_DOP_GATING_DISABLE); 444 445 /* WaToEnableHwFixForPushConstHWBug:bxt */ 446 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 447 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 448 } 449 450 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 451 struct i915_wa_list *wal) 452 { 453 struct drm_i915_private *i915 = engine->i915; 454 455 gen9_ctx_workarounds_init(engine, wal); 456 457 /* WaToEnableHwFixForPushConstHWBug:kbl */ 458 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 459 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 460 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 461 462 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 463 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 464 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 465 } 466 467 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 468 struct i915_wa_list *wal) 469 { 470 gen9_ctx_workarounds_init(engine, wal); 471 472 /* WaToEnableHwFixForPushConstHWBug:glk */ 473 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 474 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 475 } 476 477 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 478 struct i915_wa_list *wal) 479 { 480 gen9_ctx_workarounds_init(engine, wal); 481 482 /* WaToEnableHwFixForPushConstHWBug:cfl */ 483 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 484 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 485 486 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 487 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 488 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 489 } 490 491 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 492 struct i915_wa_list *wal) 493 { 494 /* WaForceContextSaveRestoreNonCoherent:cnl */ 495 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 496 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 497 498 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 499 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 500 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 501 502 /* WaPushConstantDereferenceHoldDisable:cnl */ 503 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 504 505 /* FtrEnableFastAnisoL1BankingFix:cnl */ 506 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 507 508 /* WaDisable3DMidCmdPreemption:cnl */ 509 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 510 511 /* WaDisableGPGPUMidCmdPreemption:cnl */ 512 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 513 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 514 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 515 516 /* WaDisableEarlyEOT:cnl */ 517 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 518 } 519 520 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 521 struct i915_wa_list *wal) 522 { 523 struct drm_i915_private *i915 = engine->i915; 524 525 /* WaDisableBankHangMode:icl */ 526 wa_write(wal, 527 GEN8_L3CNTLREG, 528 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 529 GEN8_ERRDETBCTRL); 530 531 /* Wa_1604370585:icl (pre-prod) 532 * Formerly known as WaPushConstantDereferenceHoldDisable 533 */ 534 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 535 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 536 PUSH_CONSTANT_DEREF_DISABLE); 537 538 /* WaForceEnableNonCoherent:icl 539 * This is not the same workaround as in early Gen9 platforms, where 540 * lacking this could cause system hangs, but coherency performance 541 * overhead is high and only a few compute workloads really need it 542 * (the register is whitelisted in hardware now, so UMDs can opt in 543 * for coherency if they have a good reason). 544 */ 545 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 546 547 /* Wa_2006611047:icl (pre-prod) 548 * Formerly known as WaDisableImprovedTdlClkGating 549 */ 550 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 551 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 552 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 553 554 /* Wa_2006665173:icl (pre-prod) */ 555 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 556 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 557 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 558 559 /* WaEnableFloatBlendOptimization:icl */ 560 wa_write_masked_or(wal, 561 GEN10_CACHE_MODE_SS, 562 0, /* write-only, so skip validation */ 563 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 564 565 /* WaDisableGPGPUMidThreadPreemption:icl */ 566 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 567 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 568 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 569 570 /* allow headerless messages for preemptible GPGPU context */ 571 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 572 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 573 574 /* Wa_1604278689:icl,ehl */ 575 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 576 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 577 0, /* write-only register; skip validation */ 578 0xFFFFFFFF); 579 580 /* Wa_1406306137:icl,ehl */ 581 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 582 } 583 584 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 585 struct i915_wa_list *wal) 586 { 587 /* 588 * Wa_1409142259:tgl 589 * Wa_1409347922:tgl 590 * Wa_1409252684:tgl 591 * Wa_1409217633:tgl 592 * Wa_1409207793:tgl 593 * Wa_1409178076:tgl 594 * Wa_1408979724:tgl 595 */ 596 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 597 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 598 599 /* 600 * Wa_1604555607:gen12 and Wa_1608008084:gen12 601 * FF_MODE2 register will return the wrong value when read. The default 602 * value for this register is zero for all fields and there are no bit 603 * masks. So instead of doing a RMW we should just write the TDS timer 604 * value for Wa_1604555607. 605 */ 606 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, 607 FF_MODE2_TDS_TIMER_128, 0); 608 609 /* WaDisableGPGPUMidThreadPreemption:tgl */ 610 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 611 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 612 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 613 } 614 615 static void 616 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 617 struct i915_wa_list *wal, 618 const char *name) 619 { 620 struct drm_i915_private *i915 = engine->i915; 621 622 if (engine->class != RENDER_CLASS) 623 return; 624 625 wa_init_start(wal, name, engine->name); 626 627 if (IS_GEN(i915, 12)) 628 tgl_ctx_workarounds_init(engine, wal); 629 else if (IS_GEN(i915, 11)) 630 icl_ctx_workarounds_init(engine, wal); 631 else if (IS_CANNONLAKE(i915)) 632 cnl_ctx_workarounds_init(engine, wal); 633 else if (IS_COFFEELAKE(i915)) 634 cfl_ctx_workarounds_init(engine, wal); 635 else if (IS_GEMINILAKE(i915)) 636 glk_ctx_workarounds_init(engine, wal); 637 else if (IS_KABYLAKE(i915)) 638 kbl_ctx_workarounds_init(engine, wal); 639 else if (IS_BROXTON(i915)) 640 bxt_ctx_workarounds_init(engine, wal); 641 else if (IS_SKYLAKE(i915)) 642 skl_ctx_workarounds_init(engine, wal); 643 else if (IS_CHERRYVIEW(i915)) 644 chv_ctx_workarounds_init(engine, wal); 645 else if (IS_BROADWELL(i915)) 646 bdw_ctx_workarounds_init(engine, wal); 647 else if (INTEL_GEN(i915) < 8) 648 return; 649 else 650 MISSING_CASE(INTEL_GEN(i915)); 651 652 wa_init_finish(wal); 653 } 654 655 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 656 { 657 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 658 } 659 660 int intel_engine_emit_ctx_wa(struct i915_request *rq) 661 { 662 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 663 struct i915_wa *wa; 664 unsigned int i; 665 u32 *cs; 666 int ret; 667 668 if (wal->count == 0) 669 return 0; 670 671 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 672 if (ret) 673 return ret; 674 675 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 676 if (IS_ERR(cs)) 677 return PTR_ERR(cs); 678 679 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 680 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 681 *cs++ = i915_mmio_reg_offset(wa->reg); 682 *cs++ = wa->set; 683 } 684 *cs++ = MI_NOOP; 685 686 intel_ring_advance(rq, cs); 687 688 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 689 if (ret) 690 return ret; 691 692 return 0; 693 } 694 695 static void 696 gen4_gt_workarounds_init(struct drm_i915_private *i915, 697 struct i915_wa_list *wal) 698 { 699 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 700 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 701 } 702 703 static void 704 g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 705 { 706 gen4_gt_workarounds_init(i915, wal); 707 708 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 709 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 710 } 711 712 static void 713 ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 714 { 715 g4x_gt_workarounds_init(i915, wal); 716 717 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 718 } 719 720 static void 721 snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 722 { 723 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 724 wa_masked_en(wal, 725 _3D_CHICKEN, 726 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 727 728 /* WaDisable_RenderCache_OperationalFlush:snb */ 729 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 730 731 /* 732 * BSpec recommends 8x4 when MSAA is used, 733 * however in practice 16x4 seems fastest. 734 * 735 * Note that PS/WM thread counts depend on the WIZ hashing 736 * disable bit, which we don't touch here, but it's good 737 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 738 */ 739 wa_add(wal, 740 GEN6_GT_MODE, 0, 741 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 742 GEN6_WIZ_HASHING_16x4); 743 744 wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); 745 746 wa_masked_en(wal, 747 _3D_CHICKEN3, 748 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 749 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 750 /* 751 * Bspec says: 752 * "This bit must be set if 3DSTATE_CLIP clip mode is set 753 * to normal and 3DSTATE_SF number of SF output attributes 754 * is more than 16." 755 */ 756 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 757 } 758 759 static void 760 ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 761 { 762 /* WaDisableEarlyCull:ivb */ 763 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 764 765 /* WaDisablePSDDualDispatchEnable:ivb */ 766 if (IS_IVB_GT1(i915)) 767 wa_masked_en(wal, 768 GEN7_HALF_SLICE_CHICKEN1, 769 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 770 771 /* WaDisable_RenderCache_OperationalFlush:ivb */ 772 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 773 774 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 775 wa_masked_dis(wal, 776 GEN7_COMMON_SLICE_CHICKEN1, 777 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 778 779 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 780 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 781 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 782 783 /* WaForceL3Serialization:ivb */ 784 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 785 786 /* 787 * WaVSThreadDispatchOverride:ivb,vlv 788 * 789 * This actually overrides the dispatch 790 * mode for all thread types. 791 */ 792 wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, 793 GEN7_FF_SCHED_MASK, 794 GEN7_FF_TS_SCHED_HW | 795 GEN7_FF_VS_SCHED_HW | 796 GEN7_FF_DS_SCHED_HW); 797 798 if (0) { /* causes HiZ corruption on ivb:gt1 */ 799 /* enable HiZ Raw Stall Optimization */ 800 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 801 } 802 803 /* WaDisable4x2SubspanOptimization:ivb */ 804 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 805 806 /* 807 * BSpec recommends 8x4 when MSAA is used, 808 * however in practice 16x4 seems fastest. 809 * 810 * Note that PS/WM thread counts depend on the WIZ hashing 811 * disable bit, which we don't touch here, but it's good 812 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 813 */ 814 wa_add(wal, GEN7_GT_MODE, 0, 815 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 816 GEN6_WIZ_HASHING_16x4); 817 } 818 819 static void 820 vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 821 { 822 /* WaDisableEarlyCull:vlv */ 823 wa_masked_en(wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 824 825 /* WaPsdDispatchEnable:vlv */ 826 /* WaDisablePSDDualDispatchEnable:vlv */ 827 wa_masked_en(wal, 828 GEN7_HALF_SLICE_CHICKEN1, 829 GEN7_MAX_PS_THREAD_DEP | 830 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 831 832 /* WaDisable_RenderCache_OperationalFlush:vlv */ 833 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 834 835 /* WaForceL3Serialization:vlv */ 836 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 837 838 /* 839 * WaVSThreadDispatchOverride:ivb,vlv 840 * 841 * This actually overrides the dispatch 842 * mode for all thread types. 843 */ 844 wa_write_masked_or(wal, 845 GEN7_FF_THREAD_MODE, 846 GEN7_FF_SCHED_MASK, 847 GEN7_FF_TS_SCHED_HW | 848 GEN7_FF_VS_SCHED_HW | 849 GEN7_FF_DS_SCHED_HW); 850 851 /* 852 * BSpec says this must be set, even though 853 * WaDisable4x2SubspanOptimization isn't listed for VLV. 854 */ 855 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 856 857 /* 858 * BSpec recommends 8x4 when MSAA is used, 859 * however in practice 16x4 seems fastest. 860 * 861 * Note that PS/WM thread counts depend on the WIZ hashing 862 * disable bit, which we don't touch here, but it's good 863 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 864 */ 865 wa_add(wal, GEN7_GT_MODE, 0, 866 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 867 GEN6_WIZ_HASHING_16x4); 868 869 /* 870 * WaIncreaseL3CreditsForVLVB0:vlv 871 * This is the hardware default actually. 872 */ 873 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 874 } 875 876 static void 877 hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 878 { 879 /* L3 caching of data atomics doesn't work -- disable it. */ 880 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 881 882 wa_add(wal, 883 HSW_ROW_CHICKEN3, 0, 884 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 885 0 /* XXX does this reg exist? */); 886 887 /* WaVSRefCountFullforceMissDisable:hsw */ 888 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 889 890 wa_masked_dis(wal, 891 CACHE_MODE_0_GEN7, 892 /* WaDisable_RenderCache_OperationalFlush:hsw */ 893 RC_OP_FLUSH_ENABLE | 894 /* enable HiZ Raw Stall Optimization */ 895 HIZ_RAW_STALL_OPT_DISABLE); 896 897 /* WaDisable4x2SubspanOptimization:hsw */ 898 wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 899 900 /* 901 * BSpec recommends 8x4 when MSAA is used, 902 * however in practice 16x4 seems fastest. 903 * 904 * Note that PS/WM thread counts depend on the WIZ hashing 905 * disable bit, which we don't touch here, but it's good 906 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 907 */ 908 wa_add(wal, GEN7_GT_MODE, 0, 909 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), 910 GEN6_WIZ_HASHING_16x4); 911 912 /* WaSampleCChickenBitEnable:hsw */ 913 wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 914 } 915 916 static void 917 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 918 { 919 /* WaDisableKillLogic:bxt,skl,kbl */ 920 if (!IS_COFFEELAKE(i915)) 921 wa_write_or(wal, 922 GAM_ECOCHK, 923 ECOCHK_DIS_TLB); 924 925 if (HAS_LLC(i915)) { 926 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 927 * 928 * Must match Display Engine. See 929 * WaCompressedResourceDisplayNewHashMode. 930 */ 931 wa_write_or(wal, 932 MMCD_MISC_CTRL, 933 MMCD_PCLA | MMCD_HOTSPOT_EN); 934 } 935 936 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 937 wa_write_or(wal, 938 GAM_ECOCHK, 939 BDW_DISABLE_HDC_INVALIDATION); 940 } 941 942 static void 943 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 944 { 945 gen9_gt_workarounds_init(i915, wal); 946 947 /* WaDisableGafsUnitClkGating:skl */ 948 wa_write_or(wal, 949 GEN7_UCGCTL4, 950 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 951 952 /* WaInPlaceDecompressionHang:skl */ 953 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 954 wa_write_or(wal, 955 GEN9_GAMT_ECO_REG_RW_IA, 956 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 957 } 958 959 static void 960 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 961 { 962 gen9_gt_workarounds_init(i915, wal); 963 964 /* WaInPlaceDecompressionHang:bxt */ 965 wa_write_or(wal, 966 GEN9_GAMT_ECO_REG_RW_IA, 967 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 968 } 969 970 static void 971 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 972 { 973 gen9_gt_workarounds_init(i915, wal); 974 975 /* WaDisableDynamicCreditSharing:kbl */ 976 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0)) 977 wa_write_or(wal, 978 GAMT_CHKN_BIT_REG, 979 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 980 981 /* WaDisableGafsUnitClkGating:kbl */ 982 wa_write_or(wal, 983 GEN7_UCGCTL4, 984 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 985 986 /* WaInPlaceDecompressionHang:kbl */ 987 wa_write_or(wal, 988 GEN9_GAMT_ECO_REG_RW_IA, 989 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 990 } 991 992 static void 993 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 994 { 995 gen9_gt_workarounds_init(i915, wal); 996 } 997 998 static void 999 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1000 { 1001 gen9_gt_workarounds_init(i915, wal); 1002 1003 /* WaDisableGafsUnitClkGating:cfl */ 1004 wa_write_or(wal, 1005 GEN7_UCGCTL4, 1006 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1007 1008 /* WaInPlaceDecompressionHang:cfl */ 1009 wa_write_or(wal, 1010 GEN9_GAMT_ECO_REG_RW_IA, 1011 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1012 } 1013 1014 static void 1015 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1016 { 1017 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 1018 unsigned int slice, subslice; 1019 u32 l3_en, mcr, mcr_mask; 1020 1021 GEM_BUG_ON(INTEL_GEN(i915) < 10); 1022 1023 /* 1024 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 1025 * L3Banks could be fused off in single slice scenario. If that is 1026 * the case, we might need to program MCR select to a valid L3Bank 1027 * by default, to make sure we correctly read certain registers 1028 * later on (in the range 0xB100 - 0xB3FF). 1029 * 1030 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 1031 * Before any MMIO read into slice/subslice specific registers, MCR 1032 * packet control register needs to be programmed to point to any 1033 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1034 * This means each subsequent MMIO read will be forwarded to an 1035 * specific s/ss combination, but this is OK since these registers 1036 * are consistent across s/ss in almost all cases. In the rare 1037 * occasions, such as INSTDONE, where this value is dependent 1038 * on s/ss combo, the read should be done with read_subslice_reg. 1039 * 1040 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 1041 * to which subslice, or to which L3 bank, the respective mmio reads 1042 * will go, we have to find a common index which works for both 1043 * accesses. 1044 * 1045 * Case where we cannot find a common index fortunately should not 1046 * happen in production hardware, so we only emit a warning instead of 1047 * implementing something more complex that requires checking the range 1048 * of every MMIO read. 1049 */ 1050 1051 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 1052 u32 l3_fuse = 1053 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 1054 GEN10_L3BANK_MASK; 1055 1056 drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse); 1057 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 1058 } else { 1059 l3_en = ~0; 1060 } 1061 1062 slice = fls(sseu->slice_mask) - 1; 1063 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 1064 if (!subslice) { 1065 drm_warn(&i915->drm, 1066 "No common index found between subslice mask %x and L3 bank mask %x!\n", 1067 intel_sseu_get_subslices(sseu, slice), l3_en); 1068 subslice = fls(l3_en); 1069 drm_WARN_ON(&i915->drm, !subslice); 1070 } 1071 subslice--; 1072 1073 if (INTEL_GEN(i915) >= 11) { 1074 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1075 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1076 } else { 1077 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1078 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1079 } 1080 1081 drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr); 1082 1083 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1084 } 1085 1086 static void 1087 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1088 { 1089 wa_init_mcr(i915, wal); 1090 1091 /* WaInPlaceDecompressionHang:cnl */ 1092 wa_write_or(wal, 1093 GEN9_GAMT_ECO_REG_RW_IA, 1094 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1095 } 1096 1097 static void 1098 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1099 { 1100 wa_init_mcr(i915, wal); 1101 1102 /* WaInPlaceDecompressionHang:icl */ 1103 wa_write_or(wal, 1104 GEN9_GAMT_ECO_REG_RW_IA, 1105 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1106 1107 /* WaModifyGamTlbPartitioning:icl */ 1108 wa_write_masked_or(wal, 1109 GEN11_GACB_PERF_CTRL, 1110 GEN11_HASH_CTRL_MASK, 1111 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1112 1113 /* Wa_1405766107:icl 1114 * Formerly known as WaCL2SFHalfMaxAlloc 1115 */ 1116 wa_write_or(wal, 1117 GEN11_LSN_UNSLCVC, 1118 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1119 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1120 1121 /* Wa_220166154:icl 1122 * Formerly known as WaDisCtxReload 1123 */ 1124 wa_write_or(wal, 1125 GEN8_GAMW_ECO_DEV_RW_IA, 1126 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1127 1128 /* Wa_1405779004:icl (pre-prod) */ 1129 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 1130 wa_write_or(wal, 1131 SLICE_UNIT_LEVEL_CLKGATE, 1132 MSCUNIT_CLKGATE_DIS); 1133 1134 /* Wa_1406838659:icl (pre-prod) */ 1135 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1136 wa_write_or(wal, 1137 INF_UNIT_LEVEL_CLKGATE, 1138 CGPSF_CLKGATE_DIS); 1139 1140 /* Wa_1406463099:icl 1141 * Formerly known as WaGamTlbPendError 1142 */ 1143 wa_write_or(wal, 1144 GAMT_CHKN_BIT_REG, 1145 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1146 1147 /* Wa_1607087056:icl,ehl,jsl */ 1148 if (IS_ICELAKE(i915) || 1149 IS_EHL_REVID(i915, EHL_REVID_A0, EHL_REVID_A0)) { 1150 wa_write_or(wal, 1151 SLICE_UNIT_LEVEL_CLKGATE, 1152 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1153 } 1154 } 1155 1156 static void 1157 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 1158 { 1159 wa_init_mcr(i915, wal); 1160 1161 /* Wa_1409420604:tgl */ 1162 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1163 wa_write_or(wal, 1164 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1165 CPSSUNIT_CLKGATE_DIS); 1166 1167 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1168 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 1169 wa_write_or(wal, 1170 SLICE_UNIT_LEVEL_CLKGATE, 1171 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1172 } 1173 1174 static void 1175 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 1176 { 1177 if (IS_GEN(i915, 12)) 1178 tgl_gt_workarounds_init(i915, wal); 1179 else if (IS_GEN(i915, 11)) 1180 icl_gt_workarounds_init(i915, wal); 1181 else if (IS_CANNONLAKE(i915)) 1182 cnl_gt_workarounds_init(i915, wal); 1183 else if (IS_COFFEELAKE(i915)) 1184 cfl_gt_workarounds_init(i915, wal); 1185 else if (IS_GEMINILAKE(i915)) 1186 glk_gt_workarounds_init(i915, wal); 1187 else if (IS_KABYLAKE(i915)) 1188 kbl_gt_workarounds_init(i915, wal); 1189 else if (IS_BROXTON(i915)) 1190 bxt_gt_workarounds_init(i915, wal); 1191 else if (IS_SKYLAKE(i915)) 1192 skl_gt_workarounds_init(i915, wal); 1193 else if (IS_HASWELL(i915)) 1194 hsw_gt_workarounds_init(i915, wal); 1195 else if (IS_VALLEYVIEW(i915)) 1196 vlv_gt_workarounds_init(i915, wal); 1197 else if (IS_IVYBRIDGE(i915)) 1198 ivb_gt_workarounds_init(i915, wal); 1199 else if (IS_GEN(i915, 6)) 1200 snb_gt_workarounds_init(i915, wal); 1201 else if (IS_GEN(i915, 5)) 1202 ilk_gt_workarounds_init(i915, wal); 1203 else if (IS_G4X(i915)) 1204 g4x_gt_workarounds_init(i915, wal); 1205 else if (IS_GEN(i915, 4)) 1206 gen4_gt_workarounds_init(i915, wal); 1207 else if (INTEL_GEN(i915) <= 8) 1208 return; 1209 else 1210 MISSING_CASE(INTEL_GEN(i915)); 1211 } 1212 1213 void intel_gt_init_workarounds(struct drm_i915_private *i915) 1214 { 1215 struct i915_wa_list *wal = &i915->gt_wa_list; 1216 1217 wa_init_start(wal, "GT", "global"); 1218 gt_init_workarounds(i915, wal); 1219 wa_init_finish(wal); 1220 } 1221 1222 static enum forcewake_domains 1223 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1224 { 1225 enum forcewake_domains fw = 0; 1226 struct i915_wa *wa; 1227 unsigned int i; 1228 1229 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1230 fw |= intel_uncore_forcewake_for_reg(uncore, 1231 wa->reg, 1232 FW_REG_READ | 1233 FW_REG_WRITE); 1234 1235 return fw; 1236 } 1237 1238 static bool 1239 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1240 { 1241 if ((cur ^ wa->set) & wa->read) { 1242 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1243 name, from, i915_mmio_reg_offset(wa->reg), 1244 cur, cur & wa->read, wa->set); 1245 1246 return false; 1247 } 1248 1249 return true; 1250 } 1251 1252 static void 1253 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1254 { 1255 enum forcewake_domains fw; 1256 unsigned long flags; 1257 struct i915_wa *wa; 1258 unsigned int i; 1259 1260 if (!wal->count) 1261 return; 1262 1263 fw = wal_get_fw_for_rmw(uncore, wal); 1264 1265 spin_lock_irqsave(&uncore->lock, flags); 1266 intel_uncore_forcewake_get__locked(uncore, fw); 1267 1268 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1269 if (wa->clr) 1270 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1271 else 1272 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1273 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1274 wa_verify(wa, 1275 intel_uncore_read_fw(uncore, wa->reg), 1276 wal->name, "application"); 1277 } 1278 1279 intel_uncore_forcewake_put__locked(uncore, fw); 1280 spin_unlock_irqrestore(&uncore->lock, flags); 1281 } 1282 1283 void intel_gt_apply_workarounds(struct intel_gt *gt) 1284 { 1285 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1286 } 1287 1288 static bool wa_list_verify(struct intel_uncore *uncore, 1289 const struct i915_wa_list *wal, 1290 const char *from) 1291 { 1292 struct i915_wa *wa; 1293 unsigned int i; 1294 bool ok = true; 1295 1296 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1297 ok &= wa_verify(wa, 1298 intel_uncore_read(uncore, wa->reg), 1299 wal->name, from); 1300 1301 return ok; 1302 } 1303 1304 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1305 { 1306 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1307 } 1308 1309 static inline bool is_nonpriv_flags_valid(u32 flags) 1310 { 1311 /* Check only valid flag bits are set */ 1312 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1313 return false; 1314 1315 /* NB: Only 3 out of 4 enum values are valid for access field */ 1316 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1317 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1318 return false; 1319 1320 return true; 1321 } 1322 1323 static void 1324 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1325 { 1326 struct i915_wa wa = { 1327 .reg = reg 1328 }; 1329 1330 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1331 return; 1332 1333 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1334 return; 1335 1336 wa.reg.reg |= flags; 1337 _wa_add(wal, &wa); 1338 } 1339 1340 static void 1341 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1342 { 1343 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1344 } 1345 1346 static void gen9_whitelist_build(struct i915_wa_list *w) 1347 { 1348 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1349 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1350 1351 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1352 whitelist_reg(w, GEN8_CS_CHICKEN1); 1353 1354 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1355 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1356 1357 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1358 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1359 } 1360 1361 static void skl_whitelist_build(struct intel_engine_cs *engine) 1362 { 1363 struct i915_wa_list *w = &engine->whitelist; 1364 1365 if (engine->class != RENDER_CLASS) 1366 return; 1367 1368 gen9_whitelist_build(w); 1369 1370 /* WaDisableLSQCROPERFforOCL:skl */ 1371 whitelist_reg(w, GEN8_L3SQCREG4); 1372 } 1373 1374 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1375 { 1376 if (engine->class != RENDER_CLASS) 1377 return; 1378 1379 gen9_whitelist_build(&engine->whitelist); 1380 } 1381 1382 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1383 { 1384 struct i915_wa_list *w = &engine->whitelist; 1385 1386 if (engine->class != RENDER_CLASS) 1387 return; 1388 1389 gen9_whitelist_build(w); 1390 1391 /* WaDisableLSQCROPERFforOCL:kbl */ 1392 whitelist_reg(w, GEN8_L3SQCREG4); 1393 } 1394 1395 static void glk_whitelist_build(struct intel_engine_cs *engine) 1396 { 1397 struct i915_wa_list *w = &engine->whitelist; 1398 1399 if (engine->class != RENDER_CLASS) 1400 return; 1401 1402 gen9_whitelist_build(w); 1403 1404 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1405 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1406 } 1407 1408 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1409 { 1410 struct i915_wa_list *w = &engine->whitelist; 1411 1412 if (engine->class != RENDER_CLASS) 1413 return; 1414 1415 gen9_whitelist_build(w); 1416 1417 /* 1418 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1419 * 1420 * This covers 4 register which are next to one another : 1421 * - PS_INVOCATION_COUNT 1422 * - PS_INVOCATION_COUNT_UDW 1423 * - PS_DEPTH_COUNT 1424 * - PS_DEPTH_COUNT_UDW 1425 */ 1426 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1427 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1428 RING_FORCE_TO_NONPRIV_RANGE_4); 1429 } 1430 1431 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1432 { 1433 struct i915_wa_list *w = &engine->whitelist; 1434 1435 if (engine->class != RENDER_CLASS) 1436 return; 1437 1438 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1439 whitelist_reg(w, GEN8_CS_CHICKEN1); 1440 } 1441 1442 static void icl_whitelist_build(struct intel_engine_cs *engine) 1443 { 1444 struct i915_wa_list *w = &engine->whitelist; 1445 1446 switch (engine->class) { 1447 case RENDER_CLASS: 1448 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1449 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1450 1451 /* WaAllowUMDToModifySamplerMode:icl */ 1452 whitelist_reg(w, GEN10_SAMPLER_MODE); 1453 1454 /* WaEnableStateCacheRedirectToCS:icl */ 1455 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1456 1457 /* 1458 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1459 * 1460 * This covers 4 register which are next to one another : 1461 * - PS_INVOCATION_COUNT 1462 * - PS_INVOCATION_COUNT_UDW 1463 * - PS_DEPTH_COUNT 1464 * - PS_DEPTH_COUNT_UDW 1465 */ 1466 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1467 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1468 RING_FORCE_TO_NONPRIV_RANGE_4); 1469 break; 1470 1471 case VIDEO_DECODE_CLASS: 1472 /* hucStatusRegOffset */ 1473 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1474 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1475 /* hucUKernelHdrInfoRegOffset */ 1476 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1477 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1478 /* hucStatus2RegOffset */ 1479 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1480 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1481 break; 1482 1483 default: 1484 break; 1485 } 1486 } 1487 1488 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1489 { 1490 struct i915_wa_list *w = &engine->whitelist; 1491 1492 switch (engine->class) { 1493 case RENDER_CLASS: 1494 /* 1495 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1496 * Wa_1408556865:tgl 1497 * 1498 * This covers 4 registers which are next to one another : 1499 * - PS_INVOCATION_COUNT 1500 * - PS_INVOCATION_COUNT_UDW 1501 * - PS_DEPTH_COUNT 1502 * - PS_DEPTH_COUNT_UDW 1503 */ 1504 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1505 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1506 RING_FORCE_TO_NONPRIV_RANGE_4); 1507 1508 /* Wa_1808121037:tgl */ 1509 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1510 1511 /* Wa_1806527549:tgl */ 1512 whitelist_reg(w, HIZ_CHICKEN); 1513 break; 1514 default: 1515 break; 1516 } 1517 } 1518 1519 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1520 { 1521 struct drm_i915_private *i915 = engine->i915; 1522 struct i915_wa_list *w = &engine->whitelist; 1523 1524 wa_init_start(w, "whitelist", engine->name); 1525 1526 if (IS_GEN(i915, 12)) 1527 tgl_whitelist_build(engine); 1528 else if (IS_GEN(i915, 11)) 1529 icl_whitelist_build(engine); 1530 else if (IS_CANNONLAKE(i915)) 1531 cnl_whitelist_build(engine); 1532 else if (IS_COFFEELAKE(i915)) 1533 cfl_whitelist_build(engine); 1534 else if (IS_GEMINILAKE(i915)) 1535 glk_whitelist_build(engine); 1536 else if (IS_KABYLAKE(i915)) 1537 kbl_whitelist_build(engine); 1538 else if (IS_BROXTON(i915)) 1539 bxt_whitelist_build(engine); 1540 else if (IS_SKYLAKE(i915)) 1541 skl_whitelist_build(engine); 1542 else if (INTEL_GEN(i915) <= 8) 1543 return; 1544 else 1545 MISSING_CASE(INTEL_GEN(i915)); 1546 1547 wa_init_finish(w); 1548 } 1549 1550 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1551 { 1552 const struct i915_wa_list *wal = &engine->whitelist; 1553 struct intel_uncore *uncore = engine->uncore; 1554 const u32 base = engine->mmio_base; 1555 struct i915_wa *wa; 1556 unsigned int i; 1557 1558 if (!wal->count) 1559 return; 1560 1561 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1562 intel_uncore_write(uncore, 1563 RING_FORCE_TO_NONPRIV(base, i), 1564 i915_mmio_reg_offset(wa->reg)); 1565 1566 /* And clear the rest just in case of garbage */ 1567 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1568 intel_uncore_write(uncore, 1569 RING_FORCE_TO_NONPRIV(base, i), 1570 i915_mmio_reg_offset(RING_NOPID(base))); 1571 } 1572 1573 static void 1574 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1575 { 1576 struct drm_i915_private *i915 = engine->i915; 1577 1578 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1579 /* 1580 * Wa_1607138336:tgl 1581 * Wa_1607063988:tgl 1582 */ 1583 wa_write_or(wal, 1584 GEN9_CTX_PREEMPT_REG, 1585 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1586 1587 /* 1588 * Wa_1607030317:tgl 1589 * Wa_1607186500:tgl 1590 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 1591 * of then says it is fixed on B0 the other one says it is 1592 * permanent 1593 */ 1594 wa_masked_en(wal, 1595 GEN6_RC_SLEEP_PSMI_CONTROL, 1596 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1597 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1598 1599 /* 1600 * Wa_1606679103:tgl 1601 * (see also Wa_1606682166:icl) 1602 */ 1603 wa_write_or(wal, 1604 GEN7_SARCHKMD, 1605 GEN7_DISABLE_SAMPLER_PREFETCH); 1606 1607 /* Wa_1407928979:tgl */ 1608 wa_write_or(wal, 1609 GEN7_FF_THREAD_MODE, 1610 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1611 1612 /* Wa_1408615072:tgl */ 1613 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1614 VSUNIT_CLKGATE_DIS_TGL); 1615 } 1616 1617 if (IS_TIGERLAKE(i915)) { 1618 /* Wa_1606931601:tgl */ 1619 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1620 1621 /* Wa_1409804808:tgl */ 1622 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1623 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1624 1625 /* Wa_1606700617:tgl */ 1626 wa_masked_en(wal, 1627 GEN9_CS_DEBUG_MODE1, 1628 FF_DOP_CLOCK_GATE_DISABLE); 1629 1630 /* 1631 * Wa_1409085225:tgl 1632 * Wa_14010229206:tgl 1633 */ 1634 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1635 } 1636 1637 if (IS_GEN(i915, 11)) { 1638 /* This is not an Wa. Enable for better image quality */ 1639 wa_masked_en(wal, 1640 _3D_CHICKEN3, 1641 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1642 1643 /* WaPipelineFlushCoherentLines:icl */ 1644 wa_write_or(wal, 1645 GEN8_L3SQCREG4, 1646 GEN8_LQSC_FLUSH_COHERENT_LINES); 1647 1648 /* 1649 * Wa_1405543622:icl 1650 * Formerly known as WaGAPZPriorityScheme 1651 */ 1652 wa_write_or(wal, 1653 GEN8_GARBCNTL, 1654 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1655 1656 /* 1657 * Wa_1604223664:icl 1658 * Formerly known as WaL3BankAddressHashing 1659 */ 1660 wa_write_masked_or(wal, 1661 GEN8_GARBCNTL, 1662 GEN11_HASH_CTRL_EXCL_MASK, 1663 GEN11_HASH_CTRL_EXCL_BIT0); 1664 wa_write_masked_or(wal, 1665 GEN11_GLBLINVL, 1666 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1667 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1668 1669 /* 1670 * Wa_1405733216:icl 1671 * Formerly known as WaDisableCleanEvicts 1672 */ 1673 wa_write_or(wal, 1674 GEN8_L3SQCREG4, 1675 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1676 1677 /* WaForwardProgressSoftReset:icl */ 1678 wa_write_or(wal, 1679 GEN10_SCRATCH_LNCF2, 1680 PMFLUSHDONE_LNICRSDROP | 1681 PMFLUSH_GAPL3UNBLOCK | 1682 PMFLUSHDONE_LNEBLK); 1683 1684 /* Wa_1406609255:icl (pre-prod) */ 1685 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1686 wa_write_or(wal, 1687 GEN7_SARCHKMD, 1688 GEN7_DISABLE_DEMAND_PREFETCH); 1689 1690 /* Wa_1606682166:icl */ 1691 wa_write_or(wal, 1692 GEN7_SARCHKMD, 1693 GEN7_DISABLE_SAMPLER_PREFETCH); 1694 1695 /* Wa_1409178092:icl */ 1696 wa_write_masked_or(wal, 1697 GEN11_SCRATCH2, 1698 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1699 0); 1700 1701 /* WaEnable32PlaneMode:icl */ 1702 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1703 GEN11_ENABLE_32_PLANE_MODE); 1704 1705 /* 1706 * Wa_1408615072:icl,ehl (vsunit) 1707 * Wa_1407596294:icl,ehl (hsunit) 1708 */ 1709 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1710 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1711 1712 /* Wa_1407352427:icl,ehl */ 1713 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1714 PSDUNIT_CLKGATE_DIS); 1715 1716 /* Wa_1406680159:icl,ehl */ 1717 wa_write_or(wal, 1718 SUBSLICE_UNIT_LEVEL_CLKGATE, 1719 GWUNIT_CLKGATE_DIS); 1720 1721 /* 1722 * Wa_1408767742:icl[a2..forever],ehl[all] 1723 * Wa_1605460711:icl[a0..c0] 1724 */ 1725 wa_write_or(wal, 1726 GEN7_FF_THREAD_MODE, 1727 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1728 } 1729 1730 if (IS_GEN_RANGE(i915, 9, 12)) { 1731 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1732 wa_masked_en(wal, 1733 GEN7_FF_SLICE_CS_CHICKEN1, 1734 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1735 } 1736 1737 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { 1738 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1739 wa_write_or(wal, 1740 GEN8_GARBCNTL, 1741 GEN9_GAPS_TSV_CREDIT_DISABLE); 1742 } 1743 1744 if (IS_BROXTON(i915)) { 1745 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1746 wa_masked_en(wal, 1747 FF_SLICE_CS_CHICKEN2, 1748 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1749 } 1750 1751 if (IS_GEN(i915, 9)) { 1752 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1753 wa_masked_en(wal, 1754 GEN9_CSFE_CHICKEN1_RCS, 1755 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1756 1757 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1758 wa_write_or(wal, 1759 BDW_SCRATCH1, 1760 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1761 1762 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1763 if (IS_GEN9_LP(i915)) 1764 wa_write_masked_or(wal, 1765 GEN8_L3SQCREG1, 1766 L3_PRIO_CREDITS_MASK, 1767 L3_GENERAL_PRIO_CREDITS(62) | 1768 L3_HIGH_PRIO_CREDITS(2)); 1769 1770 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1771 wa_write_or(wal, 1772 GEN8_L3SQCREG4, 1773 GEN8_LQSC_FLUSH_COHERENT_LINES); 1774 } 1775 1776 if (IS_GEN(i915, 7)) 1777 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1778 wa_masked_en(wal, 1779 GFX_MODE_GEN7, 1780 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1781 1782 if (IS_GEN_RANGE(i915, 6, 7)) 1783 /* 1784 * We need to disable the AsyncFlip performance optimisations in 1785 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1786 * already be programmed to '1' on all products. 1787 * 1788 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1789 */ 1790 wa_masked_en(wal, 1791 MI_MODE, 1792 ASYNC_FLIP_PERF_DISABLE); 1793 1794 if (IS_GEN(i915, 6)) { 1795 /* 1796 * Required for the hardware to program scanline values for 1797 * waiting 1798 * WaEnableFlushTlbInvalidationMode:snb 1799 */ 1800 wa_masked_en(wal, 1801 GFX_MODE, 1802 GFX_TLB_INVALIDATE_EXPLICIT); 1803 1804 /* 1805 * From the Sandybridge PRM, volume 1 part 3, page 24: 1806 * "If this bit is set, STCunit will have LRA as replacement 1807 * policy. [...] This bit must be reset. LRA replacement 1808 * policy is not supported." 1809 */ 1810 wa_masked_dis(wal, 1811 CACHE_MODE_0, 1812 CM0_STC_EVICT_DISABLE_LRA_SNB); 1813 } 1814 1815 if (IS_GEN_RANGE(i915, 4, 6)) 1816 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1817 wa_add(wal, MI_MODE, 1818 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1819 /* XXX bit doesn't stick on Broadwater */ 1820 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1821 } 1822 1823 static void 1824 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1825 { 1826 struct drm_i915_private *i915 = engine->i915; 1827 1828 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1829 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1830 wa_write(wal, 1831 RING_SEMA_WAIT_POLL(engine->mmio_base), 1832 1); 1833 } 1834 } 1835 1836 static void 1837 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1838 { 1839 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1840 return; 1841 1842 if (engine->class == RENDER_CLASS) 1843 rcs_engine_wa_init(engine, wal); 1844 else 1845 xcs_engine_wa_init(engine, wal); 1846 } 1847 1848 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1849 { 1850 struct i915_wa_list *wal = &engine->wa_list; 1851 1852 if (INTEL_GEN(engine->i915) < 4) 1853 return; 1854 1855 wa_init_start(wal, "engine", engine->name); 1856 engine_init_workarounds(engine, wal); 1857 wa_init_finish(wal); 1858 } 1859 1860 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1861 { 1862 wa_list_apply(engine->uncore, &engine->wa_list); 1863 } 1864 1865 static struct i915_vma * 1866 create_scratch(struct i915_address_space *vm, int count) 1867 { 1868 struct drm_i915_gem_object *obj; 1869 struct i915_vma *vma; 1870 unsigned int size; 1871 int err; 1872 1873 size = round_up(count * sizeof(u32), PAGE_SIZE); 1874 obj = i915_gem_object_create_internal(vm->i915, size); 1875 if (IS_ERR(obj)) 1876 return ERR_CAST(obj); 1877 1878 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1879 1880 vma = i915_vma_instance(obj, vm, NULL); 1881 if (IS_ERR(vma)) { 1882 err = PTR_ERR(vma); 1883 goto err_obj; 1884 } 1885 1886 err = i915_vma_pin(vma, 0, 0, 1887 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 1888 if (err) 1889 goto err_obj; 1890 1891 return vma; 1892 1893 err_obj: 1894 i915_gem_object_put(obj); 1895 return ERR_PTR(err); 1896 } 1897 1898 static const struct { 1899 u32 start; 1900 u32 end; 1901 } mcr_ranges_gen8[] = { 1902 { .start = 0x5500, .end = 0x55ff }, 1903 { .start = 0x7000, .end = 0x7fff }, 1904 { .start = 0x9400, .end = 0x97ff }, 1905 { .start = 0xb000, .end = 0xb3ff }, 1906 { .start = 0xe000, .end = 0xe7ff }, 1907 {}, 1908 }; 1909 1910 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1911 { 1912 int i; 1913 1914 if (INTEL_GEN(i915) < 8) 1915 return false; 1916 1917 /* 1918 * Registers in these ranges are affected by the MCR selector 1919 * which only controls CPU initiated MMIO. Routing does not 1920 * work for CS access so we cannot verify them on this path. 1921 */ 1922 for (i = 0; mcr_ranges_gen8[i].start; i++) 1923 if (offset >= mcr_ranges_gen8[i].start && 1924 offset <= mcr_ranges_gen8[i].end) 1925 return true; 1926 1927 return false; 1928 } 1929 1930 static int 1931 wa_list_srm(struct i915_request *rq, 1932 const struct i915_wa_list *wal, 1933 struct i915_vma *vma) 1934 { 1935 struct drm_i915_private *i915 = rq->i915; 1936 unsigned int i, count = 0; 1937 const struct i915_wa *wa; 1938 u32 srm, *cs; 1939 1940 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 1941 if (INTEL_GEN(i915) >= 8) 1942 srm++; 1943 1944 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1945 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 1946 count++; 1947 } 1948 1949 cs = intel_ring_begin(rq, 4 * count); 1950 if (IS_ERR(cs)) 1951 return PTR_ERR(cs); 1952 1953 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1954 u32 offset = i915_mmio_reg_offset(wa->reg); 1955 1956 if (mcr_range(i915, offset)) 1957 continue; 1958 1959 *cs++ = srm; 1960 *cs++ = offset; 1961 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 1962 *cs++ = 0; 1963 } 1964 intel_ring_advance(rq, cs); 1965 1966 return 0; 1967 } 1968 1969 static int engine_wa_list_verify(struct intel_context *ce, 1970 const struct i915_wa_list * const wal, 1971 const char *from) 1972 { 1973 const struct i915_wa *wa; 1974 struct i915_request *rq; 1975 struct i915_vma *vma; 1976 unsigned int i; 1977 u32 *results; 1978 int err; 1979 1980 if (!wal->count) 1981 return 0; 1982 1983 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 1984 if (IS_ERR(vma)) 1985 return PTR_ERR(vma); 1986 1987 intel_engine_pm_get(ce->engine); 1988 rq = intel_context_create_request(ce); 1989 intel_engine_pm_put(ce->engine); 1990 if (IS_ERR(rq)) { 1991 err = PTR_ERR(rq); 1992 goto err_vma; 1993 } 1994 1995 i915_vma_lock(vma); 1996 err = i915_request_await_object(rq, vma->obj, true); 1997 if (err == 0) 1998 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 1999 i915_vma_unlock(vma); 2000 if (err) { 2001 i915_request_add(rq); 2002 goto err_vma; 2003 } 2004 2005 err = wa_list_srm(rq, wal, vma); 2006 if (err) 2007 goto err_vma; 2008 2009 i915_request_get(rq); 2010 i915_request_add(rq); 2011 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 2012 err = -ETIME; 2013 goto err_rq; 2014 } 2015 2016 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 2017 if (IS_ERR(results)) { 2018 err = PTR_ERR(results); 2019 goto err_rq; 2020 } 2021 2022 err = 0; 2023 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 2024 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 2025 continue; 2026 2027 if (!wa_verify(wa, results[i], wal->name, from)) 2028 err = -ENXIO; 2029 } 2030 2031 i915_gem_object_unpin_map(vma->obj); 2032 2033 err_rq: 2034 i915_request_put(rq); 2035 err_vma: 2036 i915_vma_unpin(vma); 2037 i915_vma_put(vma); 2038 return err; 2039 } 2040 2041 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 2042 const char *from) 2043 { 2044 return engine_wa_list_verify(engine->kernel_context, 2045 &engine->wa_list, 2046 from); 2047 } 2048 2049 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2050 #include "selftest_workarounds.c" 2051 #endif 2052