1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2014-2018 Intel Corporation 5 */ 6 7 #include "i915_drv.h" 8 #include "intel_context.h" 9 #include "intel_engine_pm.h" 10 #include "intel_gt.h" 11 #include "intel_ring.h" 12 #include "intel_workarounds.h" 13 14 /** 15 * DOC: Hardware workarounds 16 * 17 * This file is intended as a central place to implement most [1]_ of the 18 * required workarounds for hardware to work as originally intended. They fall 19 * in five basic categories depending on how/when they are applied: 20 * 21 * - Workarounds that touch registers that are saved/restored to/from the HW 22 * context image. The list is emitted (via Load Register Immediate commands) 23 * everytime a new context is created. 24 * - GT workarounds. The list of these WAs is applied whenever these registers 25 * revert to default values (on GPU reset, suspend/resume [2]_, etc..). 26 * - Display workarounds. The list is applied during display clock-gating 27 * initialization. 28 * - Workarounds that whitelist a privileged register, so that UMDs can manage 29 * them directly. This is just a special case of a MMMIO workaround (as we 30 * write the list of these to/be-whitelisted registers to some special HW 31 * registers). 32 * - Workaround batchbuffers, that get executed automatically by the hardware 33 * on every HW context restore. 34 * 35 * .. [1] Please notice that there are other WAs that, due to their nature, 36 * cannot be applied from a central place. Those are peppered around the rest 37 * of the code, as needed. 38 * 39 * .. [2] Technically, some registers are powercontext saved & restored, so they 40 * survive a suspend/resume. In practice, writing them again is not too 41 * costly and simplifies things. We can revisit this in the future. 42 * 43 * Layout 44 * ~~~~~~ 45 * 46 * Keep things in this file ordered by WA type, as per the above (context, GT, 47 * display, register whitelist, batchbuffer). Then, inside each type, keep the 48 * following order: 49 * 50 * - Infrastructure functions and macros 51 * - WAs per platform in standard gen/chrono order 52 * - Public functions to init or apply the given workaround type. 53 */ 54 55 static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) 56 { 57 wal->name = name; 58 wal->engine_name = engine_name; 59 } 60 61 #define WA_LIST_CHUNK (1 << 4) 62 63 static void wa_init_finish(struct i915_wa_list *wal) 64 { 65 /* Trim unused entries. */ 66 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 67 struct i915_wa *list = kmemdup(wal->list, 68 wal->count * sizeof(*list), 69 GFP_KERNEL); 70 71 if (list) { 72 kfree(wal->list); 73 wal->list = list; 74 } 75 } 76 77 if (!wal->count) 78 return; 79 80 DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n", 81 wal->wa_count, wal->name, wal->engine_name); 82 } 83 84 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 85 { 86 unsigned int addr = i915_mmio_reg_offset(wa->reg); 87 unsigned int start = 0, end = wal->count; 88 const unsigned int grow = WA_LIST_CHUNK; 89 struct i915_wa *wa_; 90 91 GEM_BUG_ON(!is_power_of_2(grow)); 92 93 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 94 struct i915_wa *list; 95 96 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 97 GFP_KERNEL); 98 if (!list) { 99 DRM_ERROR("No space for workaround init!\n"); 100 return; 101 } 102 103 if (wal->list) 104 memcpy(list, wal->list, sizeof(*wa) * wal->count); 105 106 wal->list = list; 107 } 108 109 while (start < end) { 110 unsigned int mid = start + (end - start) / 2; 111 112 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 113 start = mid + 1; 114 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 115 end = mid; 116 } else { 117 wa_ = &wal->list[mid]; 118 119 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 120 DRM_ERROR("Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 121 i915_mmio_reg_offset(wa_->reg), 122 wa_->clr, wa_->set); 123 124 wa_->set &= ~wa->clr; 125 } 126 127 wal->wa_count++; 128 wa_->set |= wa->set; 129 wa_->clr |= wa->clr; 130 wa_->read |= wa->read; 131 return; 132 } 133 } 134 135 wal->wa_count++; 136 wa_ = &wal->list[wal->count++]; 137 *wa_ = *wa; 138 139 while (wa_-- > wal->list) { 140 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 141 i915_mmio_reg_offset(wa_[1].reg)); 142 if (i915_mmio_reg_offset(wa_[1].reg) > 143 i915_mmio_reg_offset(wa_[0].reg)) 144 break; 145 146 swap(wa_[1], wa_[0]); 147 } 148 } 149 150 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 151 u32 clear, u32 set, u32 read_mask) 152 { 153 struct i915_wa wa = { 154 .reg = reg, 155 .clr = clear, 156 .set = set, 157 .read = read_mask, 158 }; 159 160 _wa_add(wal, &wa); 161 } 162 163 static void 164 wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 165 { 166 wa_add(wal, reg, clear, set, clear); 167 } 168 169 static void 170 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 171 { 172 wa_write_masked_or(wal, reg, ~0, set); 173 } 174 175 static void 176 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 177 { 178 wa_write_masked_or(wal, reg, set, set); 179 } 180 181 static void 182 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 183 { 184 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val); 185 } 186 187 static void 188 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 189 { 190 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val); 191 } 192 193 #define WA_SET_BIT_MASKED(addr, mask) \ 194 wa_masked_en(wal, (addr), (mask)) 195 196 #define WA_CLR_BIT_MASKED(addr, mask) \ 197 wa_masked_dis(wal, (addr), (mask)) 198 199 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 200 wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) 201 202 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 203 struct i915_wa_list *wal) 204 { 205 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 206 207 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 208 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 209 210 /* WaDisablePartialInstShootdown:bdw,chv */ 211 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 212 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 213 214 /* Use Force Non-Coherent whenever executing a 3D context. This is a 215 * workaround for for a possible hang in the unlikely event a TLB 216 * invalidation occurs during a PSD flush. 217 */ 218 /* WaForceEnableNonCoherent:bdw,chv */ 219 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 220 WA_SET_BIT_MASKED(HDC_CHICKEN0, 221 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 222 HDC_FORCE_NON_COHERENT); 223 224 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 225 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 226 * polygons in the same 8x4 pixel/sample area to be processed without 227 * stalling waiting for the earlier ones to write to Hierarchical Z 228 * buffer." 229 * 230 * This optimization is off by default for BDW and CHV; turn it on. 231 */ 232 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 233 234 /* Wa4x4STCOptimizationDisable:bdw,chv */ 235 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 236 237 /* 238 * BSpec recommends 8x4 when MSAA is used, 239 * however in practice 16x4 seems fastest. 240 * 241 * Note that PS/WM thread counts depend on the WIZ hashing 242 * disable bit, which we don't touch here, but it's good 243 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 244 */ 245 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 246 GEN6_WIZ_HASHING_MASK, 247 GEN6_WIZ_HASHING_16x4); 248 } 249 250 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 251 struct i915_wa_list *wal) 252 { 253 struct drm_i915_private *i915 = engine->i915; 254 255 gen8_ctx_workarounds_init(engine, wal); 256 257 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 258 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 259 260 /* WaDisableDopClockGating:bdw 261 * 262 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 263 * to disable EUTC clock gating. 264 */ 265 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 266 DOP_CLOCK_GATING_DISABLE); 267 268 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 269 GEN8_SAMPLER_POWER_BYPASS_DIS); 270 271 WA_SET_BIT_MASKED(HDC_CHICKEN0, 272 /* WaForceContextSaveRestoreNonCoherent:bdw */ 273 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 274 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 275 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 276 } 277 278 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 279 struct i915_wa_list *wal) 280 { 281 gen8_ctx_workarounds_init(engine, wal); 282 283 /* WaDisableThreadStallDopClockGating:chv */ 284 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 285 286 /* Improve HiZ throughput on CHV. */ 287 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 288 } 289 290 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 291 struct i915_wa_list *wal) 292 { 293 struct drm_i915_private *i915 = engine->i915; 294 295 if (HAS_LLC(i915)) { 296 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 297 * 298 * Must match Display Engine. See 299 * WaCompressedResourceDisplayNewHashMode. 300 */ 301 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 302 GEN9_PBE_COMPRESSED_HASH_SELECTION); 303 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 304 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 305 } 306 307 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 308 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 309 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 310 FLOW_CONTROL_ENABLE | 311 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 312 313 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 314 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 315 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 316 GEN9_ENABLE_YV12_BUGFIX | 317 GEN9_ENABLE_GPGPU_PREEMPTION); 318 319 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 320 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 321 WA_SET_BIT_MASKED(CACHE_MODE_1, 322 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 323 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 324 325 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 326 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 327 GEN9_CCS_TLB_PREFETCH_ENABLE); 328 329 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 330 WA_SET_BIT_MASKED(HDC_CHICKEN0, 331 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 332 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 333 334 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 335 * both tied to WaForceContextSaveRestoreNonCoherent 336 * in some hsds for skl. We keep the tie for all gen9. The 337 * documentation is a bit hazy and so we want to get common behaviour, 338 * even though there is no clear evidence we would need both on kbl/bxt. 339 * This area has been source of system hangs so we play it safe 340 * and mimic the skl regardless of what bspec says. 341 * 342 * Use Force Non-Coherent whenever executing a 3D context. This 343 * is a workaround for a possible hang in the unlikely event 344 * a TLB invalidation occurs during a PSD flush. 345 */ 346 347 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 348 WA_SET_BIT_MASKED(HDC_CHICKEN0, 349 HDC_FORCE_NON_COHERENT); 350 351 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 352 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) 353 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 354 GEN8_SAMPLER_POWER_BYPASS_DIS); 355 356 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 357 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 358 359 /* 360 * Supporting preemption with fine-granularity requires changes in the 361 * batch buffer programming. Since we can't break old userspace, we 362 * need to set our default preemption level to safe value. Userspace is 363 * still able to use more fine-grained preemption levels, since in 364 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 365 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 366 * not real HW workarounds, but merely a way to start using preemption 367 * while maintaining old contract with userspace. 368 */ 369 370 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 371 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 372 373 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 374 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 375 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 376 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 377 378 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 379 if (IS_GEN9_LP(i915)) 380 WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 381 } 382 383 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 384 struct i915_wa_list *wal) 385 { 386 struct drm_i915_private *i915 = engine->i915; 387 u8 vals[3] = { 0, 0, 0 }; 388 unsigned int i; 389 390 for (i = 0; i < 3; i++) { 391 u8 ss; 392 393 /* 394 * Only consider slices where one, and only one, subslice has 7 395 * EUs 396 */ 397 if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) 398 continue; 399 400 /* 401 * subslice_7eu[i] != 0 (because of the check above) and 402 * ss_max == 4 (maximum number of subslices possible per slice) 403 * 404 * -> 0 <= ss <= 3; 405 */ 406 ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; 407 vals[i] = 3 - ss; 408 } 409 410 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 411 return; 412 413 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 414 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 415 GEN9_IZ_HASHING_MASK(2) | 416 GEN9_IZ_HASHING_MASK(1) | 417 GEN9_IZ_HASHING_MASK(0), 418 GEN9_IZ_HASHING(2, vals[2]) | 419 GEN9_IZ_HASHING(1, vals[1]) | 420 GEN9_IZ_HASHING(0, vals[0])); 421 } 422 423 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 424 struct i915_wa_list *wal) 425 { 426 gen9_ctx_workarounds_init(engine, wal); 427 skl_tune_iz_hashing(engine, wal); 428 } 429 430 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 431 struct i915_wa_list *wal) 432 { 433 gen9_ctx_workarounds_init(engine, wal); 434 435 /* WaDisableThreadStallDopClockGating:bxt */ 436 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 437 STALL_DOP_GATING_DISABLE); 438 439 /* WaToEnableHwFixForPushConstHWBug:bxt */ 440 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 441 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 442 } 443 444 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 445 struct i915_wa_list *wal) 446 { 447 struct drm_i915_private *i915 = engine->i915; 448 449 gen9_ctx_workarounds_init(engine, wal); 450 451 /* WaToEnableHwFixForPushConstHWBug:kbl */ 452 if (IS_KBL_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) 453 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 454 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 455 456 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 457 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 458 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 459 } 460 461 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 462 struct i915_wa_list *wal) 463 { 464 gen9_ctx_workarounds_init(engine, wal); 465 466 /* WaToEnableHwFixForPushConstHWBug:glk */ 467 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 468 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 469 } 470 471 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 472 struct i915_wa_list *wal) 473 { 474 gen9_ctx_workarounds_init(engine, wal); 475 476 /* WaToEnableHwFixForPushConstHWBug:cfl */ 477 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 478 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 479 480 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 481 WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, 482 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 483 } 484 485 static void cnl_ctx_workarounds_init(struct intel_engine_cs *engine, 486 struct i915_wa_list *wal) 487 { 488 struct drm_i915_private *i915 = engine->i915; 489 490 /* WaForceContextSaveRestoreNonCoherent:cnl */ 491 WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0, 492 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); 493 494 /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */ 495 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0)) 496 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, THROTTLE_12_5); 497 498 /* WaDisableReplayBufferBankArbitrationOptimization:cnl */ 499 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 500 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 501 502 /* WaDisableEnhancedSBEVertexCaching:cnl (pre-prod) */ 503 if (IS_CNL_REVID(i915, 0, CNL_REVID_B0)) 504 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 505 GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE); 506 507 /* WaPushConstantDereferenceHoldDisable:cnl */ 508 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); 509 510 /* FtrEnableFastAnisoL1BankingFix:cnl */ 511 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); 512 513 /* WaDisable3DMidCmdPreemption:cnl */ 514 WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 515 516 /* WaDisableGPGPUMidCmdPreemption:cnl */ 517 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 518 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 519 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 520 521 /* WaDisableEarlyEOT:cnl */ 522 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, DISABLE_EARLY_EOT); 523 } 524 525 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 526 struct i915_wa_list *wal) 527 { 528 struct drm_i915_private *i915 = engine->i915; 529 530 /* WaDisableBankHangMode:icl */ 531 wa_write(wal, 532 GEN8_L3CNTLREG, 533 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 534 GEN8_ERRDETBCTRL); 535 536 /* Wa_1604370585:icl (pre-prod) 537 * Formerly known as WaPushConstantDereferenceHoldDisable 538 */ 539 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 540 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 541 PUSH_CONSTANT_DEREF_DISABLE); 542 543 /* WaForceEnableNonCoherent:icl 544 * This is not the same workaround as in early Gen9 platforms, where 545 * lacking this could cause system hangs, but coherency performance 546 * overhead is high and only a few compute workloads really need it 547 * (the register is whitelisted in hardware now, so UMDs can opt in 548 * for coherency if they have a good reason). 549 */ 550 WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 551 552 /* Wa_2006611047:icl (pre-prod) 553 * Formerly known as WaDisableImprovedTdlClkGating 554 */ 555 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 556 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 557 GEN11_TDL_CLOCK_GATING_FIX_DISABLE); 558 559 /* Wa_2006665173:icl (pre-prod) */ 560 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 561 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 562 GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC); 563 564 /* WaEnableFloatBlendOptimization:icl */ 565 wa_write_masked_or(wal, 566 GEN10_CACHE_MODE_SS, 567 0, /* write-only, so skip validation */ 568 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE)); 569 570 /* WaDisableGPGPUMidThreadPreemption:icl */ 571 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 572 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 573 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 574 575 /* allow headerless messages for preemptible GPGPU context */ 576 WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, 577 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 578 579 /* Wa_1604278689:icl,ehl */ 580 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 581 wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER, 582 0, /* write-only register; skip validation */ 583 0xFFFFFFFF); 584 585 /* Wa_1406306137:icl,ehl */ 586 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 587 } 588 589 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 590 struct i915_wa_list *wal) 591 { 592 /* 593 * Wa_1409142259:tgl 594 * Wa_1409347922:tgl 595 * Wa_1409252684:tgl 596 * Wa_1409217633:tgl 597 * Wa_1409207793:tgl 598 * Wa_1409178076:tgl 599 * Wa_1408979724:tgl 600 */ 601 WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, 602 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 603 604 /* 605 * Wa_1604555607:gen12 and Wa_1608008084:gen12 606 * FF_MODE2 register will return the wrong value when read. The default 607 * value for this register is zero for all fields and there are no bit 608 * masks. So instead of doing a RMW we should just write the TDS timer 609 * value for Wa_1604555607. 610 */ 611 wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, 612 FF_MODE2_TDS_TIMER_128, 0); 613 614 /* WaDisableGPGPUMidThreadPreemption:tgl */ 615 WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, 616 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 617 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 618 } 619 620 static void 621 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 622 struct i915_wa_list *wal, 623 const char *name) 624 { 625 struct drm_i915_private *i915 = engine->i915; 626 627 if (engine->class != RENDER_CLASS) 628 return; 629 630 wa_init_start(wal, name, engine->name); 631 632 if (IS_GEN(i915, 12)) 633 tgl_ctx_workarounds_init(engine, wal); 634 else if (IS_GEN(i915, 11)) 635 icl_ctx_workarounds_init(engine, wal); 636 else if (IS_CANNONLAKE(i915)) 637 cnl_ctx_workarounds_init(engine, wal); 638 else if (IS_COFFEELAKE(i915)) 639 cfl_ctx_workarounds_init(engine, wal); 640 else if (IS_GEMINILAKE(i915)) 641 glk_ctx_workarounds_init(engine, wal); 642 else if (IS_KABYLAKE(i915)) 643 kbl_ctx_workarounds_init(engine, wal); 644 else if (IS_BROXTON(i915)) 645 bxt_ctx_workarounds_init(engine, wal); 646 else if (IS_SKYLAKE(i915)) 647 skl_ctx_workarounds_init(engine, wal); 648 else if (IS_CHERRYVIEW(i915)) 649 chv_ctx_workarounds_init(engine, wal); 650 else if (IS_BROADWELL(i915)) 651 bdw_ctx_workarounds_init(engine, wal); 652 else if (INTEL_GEN(i915) < 8) 653 return; 654 else 655 MISSING_CASE(INTEL_GEN(i915)); 656 657 wa_init_finish(wal); 658 } 659 660 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 661 { 662 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 663 } 664 665 int intel_engine_emit_ctx_wa(struct i915_request *rq) 666 { 667 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 668 struct i915_wa *wa; 669 unsigned int i; 670 u32 *cs; 671 int ret; 672 673 if (wal->count == 0) 674 return 0; 675 676 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 677 if (ret) 678 return ret; 679 680 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 681 if (IS_ERR(cs)) 682 return PTR_ERR(cs); 683 684 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 685 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 686 *cs++ = i915_mmio_reg_offset(wa->reg); 687 *cs++ = wa->set; 688 } 689 *cs++ = MI_NOOP; 690 691 intel_ring_advance(rq, cs); 692 693 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 694 if (ret) 695 return ret; 696 697 return 0; 698 } 699 700 static void 701 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 702 { 703 /* WaDisableKillLogic:bxt,skl,kbl */ 704 if (!IS_COFFEELAKE(i915)) 705 wa_write_or(wal, 706 GAM_ECOCHK, 707 ECOCHK_DIS_TLB); 708 709 if (HAS_LLC(i915)) { 710 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 711 * 712 * Must match Display Engine. See 713 * WaCompressedResourceDisplayNewHashMode. 714 */ 715 wa_write_or(wal, 716 MMCD_MISC_CTRL, 717 MMCD_PCLA | MMCD_HOTSPOT_EN); 718 } 719 720 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 721 wa_write_or(wal, 722 GAM_ECOCHK, 723 BDW_DISABLE_HDC_INVALIDATION); 724 } 725 726 static void 727 skl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 728 { 729 gen9_gt_workarounds_init(i915, wal); 730 731 /* WaDisableGafsUnitClkGating:skl */ 732 wa_write_or(wal, 733 GEN7_UCGCTL4, 734 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 735 736 /* WaInPlaceDecompressionHang:skl */ 737 if (IS_SKL_REVID(i915, SKL_REVID_H0, REVID_FOREVER)) 738 wa_write_or(wal, 739 GEN9_GAMT_ECO_REG_RW_IA, 740 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 741 } 742 743 static void 744 bxt_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 745 { 746 gen9_gt_workarounds_init(i915, wal); 747 748 /* WaInPlaceDecompressionHang:bxt */ 749 wa_write_or(wal, 750 GEN9_GAMT_ECO_REG_RW_IA, 751 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 752 } 753 754 static void 755 kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 756 { 757 gen9_gt_workarounds_init(i915, wal); 758 759 /* WaDisableDynamicCreditSharing:kbl */ 760 if (IS_KBL_REVID(i915, 0, KBL_REVID_B0)) 761 wa_write_or(wal, 762 GAMT_CHKN_BIT_REG, 763 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 764 765 /* WaDisableGafsUnitClkGating:kbl */ 766 wa_write_or(wal, 767 GEN7_UCGCTL4, 768 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 769 770 /* WaInPlaceDecompressionHang:kbl */ 771 wa_write_or(wal, 772 GEN9_GAMT_ECO_REG_RW_IA, 773 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 774 } 775 776 static void 777 glk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 778 { 779 gen9_gt_workarounds_init(i915, wal); 780 } 781 782 static void 783 cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 784 { 785 gen9_gt_workarounds_init(i915, wal); 786 787 /* WaDisableGafsUnitClkGating:cfl */ 788 wa_write_or(wal, 789 GEN7_UCGCTL4, 790 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 791 792 /* WaInPlaceDecompressionHang:cfl */ 793 wa_write_or(wal, 794 GEN9_GAMT_ECO_REG_RW_IA, 795 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 796 } 797 798 static void 799 wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 800 { 801 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 802 unsigned int slice, subslice; 803 u32 l3_en, mcr, mcr_mask; 804 805 GEM_BUG_ON(INTEL_GEN(i915) < 10); 806 807 /* 808 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl 809 * L3Banks could be fused off in single slice scenario. If that is 810 * the case, we might need to program MCR select to a valid L3Bank 811 * by default, to make sure we correctly read certain registers 812 * later on (in the range 0xB100 - 0xB3FF). 813 * 814 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl 815 * Before any MMIO read into slice/subslice specific registers, MCR 816 * packet control register needs to be programmed to point to any 817 * enabled s/ss pair. Otherwise, incorrect values will be returned. 818 * This means each subsequent MMIO read will be forwarded to an 819 * specific s/ss combination, but this is OK since these registers 820 * are consistent across s/ss in almost all cases. In the rare 821 * occasions, such as INSTDONE, where this value is dependent 822 * on s/ss combo, the read should be done with read_subslice_reg. 823 * 824 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both 825 * to which subslice, or to which L3 bank, the respective mmio reads 826 * will go, we have to find a common index which works for both 827 * accesses. 828 * 829 * Case where we cannot find a common index fortunately should not 830 * happen in production hardware, so we only emit a warning instead of 831 * implementing something more complex that requires checking the range 832 * of every MMIO read. 833 */ 834 835 if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) { 836 u32 l3_fuse = 837 intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) & 838 GEN10_L3BANK_MASK; 839 840 DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse); 841 l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse); 842 } else { 843 l3_en = ~0; 844 } 845 846 slice = fls(sseu->slice_mask) - 1; 847 subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice)); 848 if (!subslice) { 849 DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n", 850 intel_sseu_get_subslices(sseu, slice), l3_en); 851 subslice = fls(l3_en); 852 drm_WARN_ON(&i915->drm, !subslice); 853 } 854 subslice--; 855 856 if (INTEL_GEN(i915) >= 11) { 857 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 858 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 859 } else { 860 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 861 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 862 } 863 864 DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr); 865 866 wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 867 } 868 869 static void 870 cnl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 871 { 872 wa_init_mcr(i915, wal); 873 874 /* WaDisableI2mCycleOnWRPort:cnl (pre-prod) */ 875 if (IS_CNL_REVID(i915, CNL_REVID_B0, CNL_REVID_B0)) 876 wa_write_or(wal, 877 GAMT_CHKN_BIT_REG, 878 GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT); 879 880 /* WaInPlaceDecompressionHang:cnl */ 881 wa_write_or(wal, 882 GEN9_GAMT_ECO_REG_RW_IA, 883 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 884 } 885 886 static void 887 icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 888 { 889 wa_init_mcr(i915, wal); 890 891 /* WaInPlaceDecompressionHang:icl */ 892 wa_write_or(wal, 893 GEN9_GAMT_ECO_REG_RW_IA, 894 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 895 896 /* WaModifyGamTlbPartitioning:icl */ 897 wa_write_masked_or(wal, 898 GEN11_GACB_PERF_CTRL, 899 GEN11_HASH_CTRL_MASK, 900 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 901 902 /* Wa_1405766107:icl 903 * Formerly known as WaCL2SFHalfMaxAlloc 904 */ 905 wa_write_or(wal, 906 GEN11_LSN_UNSLCVC, 907 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 908 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 909 910 /* Wa_220166154:icl 911 * Formerly known as WaDisCtxReload 912 */ 913 wa_write_or(wal, 914 GEN8_GAMW_ECO_DEV_RW_IA, 915 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 916 917 /* Wa_1405779004:icl (pre-prod) */ 918 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0)) 919 wa_write_or(wal, 920 SLICE_UNIT_LEVEL_CLKGATE, 921 MSCUNIT_CLKGATE_DIS); 922 923 /* Wa_1406838659:icl (pre-prod) */ 924 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 925 wa_write_or(wal, 926 INF_UNIT_LEVEL_CLKGATE, 927 CGPSF_CLKGATE_DIS); 928 929 /* Wa_1406463099:icl 930 * Formerly known as WaGamTlbPendError 931 */ 932 wa_write_or(wal, 933 GAMT_CHKN_BIT_REG, 934 GAMT_CHKN_DISABLE_L3_COH_PIPE); 935 936 /* Wa_1607087056:icl */ 937 wa_write_or(wal, 938 SLICE_UNIT_LEVEL_CLKGATE, 939 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 940 } 941 942 static void 943 tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 944 { 945 /* Wa_1409420604:tgl */ 946 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 947 wa_write_or(wal, 948 SUBSLICE_UNIT_LEVEL_CLKGATE2, 949 CPSSUNIT_CLKGATE_DIS); 950 951 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 952 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) 953 wa_write_or(wal, 954 SLICE_UNIT_LEVEL_CLKGATE, 955 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 956 } 957 958 static void 959 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) 960 { 961 if (IS_GEN(i915, 12)) 962 tgl_gt_workarounds_init(i915, wal); 963 else if (IS_GEN(i915, 11)) 964 icl_gt_workarounds_init(i915, wal); 965 else if (IS_CANNONLAKE(i915)) 966 cnl_gt_workarounds_init(i915, wal); 967 else if (IS_COFFEELAKE(i915)) 968 cfl_gt_workarounds_init(i915, wal); 969 else if (IS_GEMINILAKE(i915)) 970 glk_gt_workarounds_init(i915, wal); 971 else if (IS_KABYLAKE(i915)) 972 kbl_gt_workarounds_init(i915, wal); 973 else if (IS_BROXTON(i915)) 974 bxt_gt_workarounds_init(i915, wal); 975 else if (IS_SKYLAKE(i915)) 976 skl_gt_workarounds_init(i915, wal); 977 else if (INTEL_GEN(i915) <= 8) 978 return; 979 else 980 MISSING_CASE(INTEL_GEN(i915)); 981 } 982 983 void intel_gt_init_workarounds(struct drm_i915_private *i915) 984 { 985 struct i915_wa_list *wal = &i915->gt_wa_list; 986 987 wa_init_start(wal, "GT", "global"); 988 gt_init_workarounds(i915, wal); 989 wa_init_finish(wal); 990 } 991 992 static enum forcewake_domains 993 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 994 { 995 enum forcewake_domains fw = 0; 996 struct i915_wa *wa; 997 unsigned int i; 998 999 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1000 fw |= intel_uncore_forcewake_for_reg(uncore, 1001 wa->reg, 1002 FW_REG_READ | 1003 FW_REG_WRITE); 1004 1005 return fw; 1006 } 1007 1008 static bool 1009 wa_verify(const struct i915_wa *wa, u32 cur, const char *name, const char *from) 1010 { 1011 if ((cur ^ wa->set) & wa->read) { 1012 DRM_ERROR("%s workaround lost on %s! (%x=%x/%x, expected %x)\n", 1013 name, from, i915_mmio_reg_offset(wa->reg), 1014 cur, cur & wa->read, wa->set); 1015 1016 return false; 1017 } 1018 1019 return true; 1020 } 1021 1022 static void 1023 wa_list_apply(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1024 { 1025 enum forcewake_domains fw; 1026 unsigned long flags; 1027 struct i915_wa *wa; 1028 unsigned int i; 1029 1030 if (!wal->count) 1031 return; 1032 1033 fw = wal_get_fw_for_rmw(uncore, wal); 1034 1035 spin_lock_irqsave(&uncore->lock, flags); 1036 intel_uncore_forcewake_get__locked(uncore, fw); 1037 1038 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1039 if (wa->clr) 1040 intel_uncore_rmw_fw(uncore, wa->reg, wa->clr, wa->set); 1041 else 1042 intel_uncore_write_fw(uncore, wa->reg, wa->set); 1043 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 1044 wa_verify(wa, 1045 intel_uncore_read_fw(uncore, wa->reg), 1046 wal->name, "application"); 1047 } 1048 1049 intel_uncore_forcewake_put__locked(uncore, fw); 1050 spin_unlock_irqrestore(&uncore->lock, flags); 1051 } 1052 1053 void intel_gt_apply_workarounds(struct intel_gt *gt) 1054 { 1055 wa_list_apply(gt->uncore, >->i915->gt_wa_list); 1056 } 1057 1058 static bool wa_list_verify(struct intel_uncore *uncore, 1059 const struct i915_wa_list *wal, 1060 const char *from) 1061 { 1062 struct i915_wa *wa; 1063 unsigned int i; 1064 bool ok = true; 1065 1066 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1067 ok &= wa_verify(wa, 1068 intel_uncore_read(uncore, wa->reg), 1069 wal->name, from); 1070 1071 return ok; 1072 } 1073 1074 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1075 { 1076 return wa_list_verify(gt->uncore, >->i915->gt_wa_list, from); 1077 } 1078 1079 static inline bool is_nonpriv_flags_valid(u32 flags) 1080 { 1081 /* Check only valid flag bits are set */ 1082 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1083 return false; 1084 1085 /* NB: Only 3 out of 4 enum values are valid for access field */ 1086 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1087 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1088 return false; 1089 1090 return true; 1091 } 1092 1093 static void 1094 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1095 { 1096 struct i915_wa wa = { 1097 .reg = reg 1098 }; 1099 1100 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1101 return; 1102 1103 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1104 return; 1105 1106 wa.reg.reg |= flags; 1107 _wa_add(wal, &wa); 1108 } 1109 1110 static void 1111 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1112 { 1113 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1114 } 1115 1116 static void gen9_whitelist_build(struct i915_wa_list *w) 1117 { 1118 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1119 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1120 1121 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1122 whitelist_reg(w, GEN8_CS_CHICKEN1); 1123 1124 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1125 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1126 1127 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1128 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1129 } 1130 1131 static void skl_whitelist_build(struct intel_engine_cs *engine) 1132 { 1133 struct i915_wa_list *w = &engine->whitelist; 1134 1135 if (engine->class != RENDER_CLASS) 1136 return; 1137 1138 gen9_whitelist_build(w); 1139 1140 /* WaDisableLSQCROPERFforOCL:skl */ 1141 whitelist_reg(w, GEN8_L3SQCREG4); 1142 } 1143 1144 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1145 { 1146 if (engine->class != RENDER_CLASS) 1147 return; 1148 1149 gen9_whitelist_build(&engine->whitelist); 1150 } 1151 1152 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1153 { 1154 struct i915_wa_list *w = &engine->whitelist; 1155 1156 if (engine->class != RENDER_CLASS) 1157 return; 1158 1159 gen9_whitelist_build(w); 1160 1161 /* WaDisableLSQCROPERFforOCL:kbl */ 1162 whitelist_reg(w, GEN8_L3SQCREG4); 1163 } 1164 1165 static void glk_whitelist_build(struct intel_engine_cs *engine) 1166 { 1167 struct i915_wa_list *w = &engine->whitelist; 1168 1169 if (engine->class != RENDER_CLASS) 1170 return; 1171 1172 gen9_whitelist_build(w); 1173 1174 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1175 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1176 } 1177 1178 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1179 { 1180 struct i915_wa_list *w = &engine->whitelist; 1181 1182 if (engine->class != RENDER_CLASS) 1183 return; 1184 1185 gen9_whitelist_build(w); 1186 1187 /* 1188 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1189 * 1190 * This covers 4 register which are next to one another : 1191 * - PS_INVOCATION_COUNT 1192 * - PS_INVOCATION_COUNT_UDW 1193 * - PS_DEPTH_COUNT 1194 * - PS_DEPTH_COUNT_UDW 1195 */ 1196 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1197 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1198 RING_FORCE_TO_NONPRIV_RANGE_4); 1199 } 1200 1201 static void cnl_whitelist_build(struct intel_engine_cs *engine) 1202 { 1203 struct i915_wa_list *w = &engine->whitelist; 1204 1205 if (engine->class != RENDER_CLASS) 1206 return; 1207 1208 /* WaEnablePreemptionGranularityControlByUMD:cnl */ 1209 whitelist_reg(w, GEN8_CS_CHICKEN1); 1210 } 1211 1212 static void icl_whitelist_build(struct intel_engine_cs *engine) 1213 { 1214 struct i915_wa_list *w = &engine->whitelist; 1215 1216 switch (engine->class) { 1217 case RENDER_CLASS: 1218 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 1219 whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7); 1220 1221 /* WaAllowUMDToModifySamplerMode:icl */ 1222 whitelist_reg(w, GEN10_SAMPLER_MODE); 1223 1224 /* WaEnableStateCacheRedirectToCS:icl */ 1225 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1226 1227 /* 1228 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 1229 * 1230 * This covers 4 register which are next to one another : 1231 * - PS_INVOCATION_COUNT 1232 * - PS_INVOCATION_COUNT_UDW 1233 * - PS_DEPTH_COUNT 1234 * - PS_DEPTH_COUNT_UDW 1235 */ 1236 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1237 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1238 RING_FORCE_TO_NONPRIV_RANGE_4); 1239 break; 1240 1241 case VIDEO_DECODE_CLASS: 1242 /* hucStatusRegOffset */ 1243 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 1244 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1245 /* hucUKernelHdrInfoRegOffset */ 1246 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 1247 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1248 /* hucStatus2RegOffset */ 1249 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 1250 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1251 break; 1252 1253 default: 1254 break; 1255 } 1256 } 1257 1258 static void tgl_whitelist_build(struct intel_engine_cs *engine) 1259 { 1260 struct i915_wa_list *w = &engine->whitelist; 1261 1262 switch (engine->class) { 1263 case RENDER_CLASS: 1264 /* 1265 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 1266 * Wa_1408556865:tgl 1267 * 1268 * This covers 4 registers which are next to one another : 1269 * - PS_INVOCATION_COUNT 1270 * - PS_INVOCATION_COUNT_UDW 1271 * - PS_DEPTH_COUNT 1272 * - PS_DEPTH_COUNT_UDW 1273 */ 1274 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1275 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1276 RING_FORCE_TO_NONPRIV_RANGE_4); 1277 1278 /* Wa_1808121037:tgl */ 1279 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 1280 1281 /* Wa_1806527549:tgl */ 1282 whitelist_reg(w, HIZ_CHICKEN); 1283 break; 1284 default: 1285 break; 1286 } 1287 } 1288 1289 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 1290 { 1291 struct drm_i915_private *i915 = engine->i915; 1292 struct i915_wa_list *w = &engine->whitelist; 1293 1294 wa_init_start(w, "whitelist", engine->name); 1295 1296 if (IS_GEN(i915, 12)) 1297 tgl_whitelist_build(engine); 1298 else if (IS_GEN(i915, 11)) 1299 icl_whitelist_build(engine); 1300 else if (IS_CANNONLAKE(i915)) 1301 cnl_whitelist_build(engine); 1302 else if (IS_COFFEELAKE(i915)) 1303 cfl_whitelist_build(engine); 1304 else if (IS_GEMINILAKE(i915)) 1305 glk_whitelist_build(engine); 1306 else if (IS_KABYLAKE(i915)) 1307 kbl_whitelist_build(engine); 1308 else if (IS_BROXTON(i915)) 1309 bxt_whitelist_build(engine); 1310 else if (IS_SKYLAKE(i915)) 1311 skl_whitelist_build(engine); 1312 else if (INTEL_GEN(i915) <= 8) 1313 return; 1314 else 1315 MISSING_CASE(INTEL_GEN(i915)); 1316 1317 wa_init_finish(w); 1318 } 1319 1320 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 1321 { 1322 const struct i915_wa_list *wal = &engine->whitelist; 1323 struct intel_uncore *uncore = engine->uncore; 1324 const u32 base = engine->mmio_base; 1325 struct i915_wa *wa; 1326 unsigned int i; 1327 1328 if (!wal->count) 1329 return; 1330 1331 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1332 intel_uncore_write(uncore, 1333 RING_FORCE_TO_NONPRIV(base, i), 1334 i915_mmio_reg_offset(wa->reg)); 1335 1336 /* And clear the rest just in case of garbage */ 1337 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 1338 intel_uncore_write(uncore, 1339 RING_FORCE_TO_NONPRIV(base, i), 1340 i915_mmio_reg_offset(RING_NOPID(base))); 1341 } 1342 1343 static void 1344 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1345 { 1346 struct drm_i915_private *i915 = engine->i915; 1347 1348 if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { 1349 /* 1350 * Wa_1607138336:tgl 1351 * Wa_1607063988:tgl 1352 */ 1353 wa_write_or(wal, 1354 GEN9_CTX_PREEMPT_REG, 1355 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 1356 1357 /* 1358 * Wa_1607030317:tgl 1359 * Wa_1607186500:tgl 1360 * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 1361 * of then says it is fixed on B0 the other one says it is 1362 * permanent 1363 */ 1364 wa_masked_en(wal, 1365 GEN6_RC_SLEEP_PSMI_CONTROL, 1366 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 1367 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 1368 1369 /* 1370 * Wa_1606679103:tgl 1371 * (see also Wa_1606682166:icl) 1372 */ 1373 wa_write_or(wal, 1374 GEN7_SARCHKMD, 1375 GEN7_DISABLE_SAMPLER_PREFETCH); 1376 1377 /* Wa_1407928979:tgl */ 1378 wa_write_or(wal, 1379 GEN7_FF_THREAD_MODE, 1380 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1381 1382 /* 1383 * Wa_1409085225:tgl 1384 * Wa_14010229206:tgl 1385 */ 1386 wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 1387 1388 /* Wa_1408615072:tgl */ 1389 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1390 VSUNIT_CLKGATE_DIS_TGL); 1391 } 1392 1393 if (IS_TIGERLAKE(i915)) { 1394 /* Wa_1606931601:tgl */ 1395 wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 1396 1397 /* Wa_1409804808:tgl */ 1398 wa_masked_en(wal, GEN7_ROW_CHICKEN2, 1399 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 1400 1401 /* Wa_1606700617:tgl */ 1402 wa_masked_en(wal, 1403 GEN9_CS_DEBUG_MODE1, 1404 FF_DOP_CLOCK_GATE_DISABLE); 1405 } 1406 1407 if (IS_GEN(i915, 11)) { 1408 /* This is not an Wa. Enable for better image quality */ 1409 wa_masked_en(wal, 1410 _3D_CHICKEN3, 1411 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 1412 1413 /* WaPipelineFlushCoherentLines:icl */ 1414 wa_write_or(wal, 1415 GEN8_L3SQCREG4, 1416 GEN8_LQSC_FLUSH_COHERENT_LINES); 1417 1418 /* 1419 * Wa_1405543622:icl 1420 * Formerly known as WaGAPZPriorityScheme 1421 */ 1422 wa_write_or(wal, 1423 GEN8_GARBCNTL, 1424 GEN11_ARBITRATION_PRIO_ORDER_MASK); 1425 1426 /* 1427 * Wa_1604223664:icl 1428 * Formerly known as WaL3BankAddressHashing 1429 */ 1430 wa_write_masked_or(wal, 1431 GEN8_GARBCNTL, 1432 GEN11_HASH_CTRL_EXCL_MASK, 1433 GEN11_HASH_CTRL_EXCL_BIT0); 1434 wa_write_masked_or(wal, 1435 GEN11_GLBLINVL, 1436 GEN11_BANK_HASH_ADDR_EXCL_MASK, 1437 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 1438 1439 /* 1440 * Wa_1405733216:icl 1441 * Formerly known as WaDisableCleanEvicts 1442 */ 1443 wa_write_or(wal, 1444 GEN8_L3SQCREG4, 1445 GEN11_LQSC_CLEAN_EVICT_DISABLE); 1446 1447 /* WaForwardProgressSoftReset:icl */ 1448 wa_write_or(wal, 1449 GEN10_SCRATCH_LNCF2, 1450 PMFLUSHDONE_LNICRSDROP | 1451 PMFLUSH_GAPL3UNBLOCK | 1452 PMFLUSHDONE_LNEBLK); 1453 1454 /* Wa_1406609255:icl (pre-prod) */ 1455 if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) 1456 wa_write_or(wal, 1457 GEN7_SARCHKMD, 1458 GEN7_DISABLE_DEMAND_PREFETCH); 1459 1460 /* Wa_1606682166:icl */ 1461 wa_write_or(wal, 1462 GEN7_SARCHKMD, 1463 GEN7_DISABLE_SAMPLER_PREFETCH); 1464 1465 /* Wa_1409178092:icl */ 1466 wa_write_masked_or(wal, 1467 GEN11_SCRATCH2, 1468 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 1469 0); 1470 1471 /* WaEnable32PlaneMode:icl */ 1472 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 1473 GEN11_ENABLE_32_PLANE_MODE); 1474 1475 /* 1476 * Wa_1408615072:icl,ehl (vsunit) 1477 * Wa_1407596294:icl,ehl (hsunit) 1478 */ 1479 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1480 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 1481 1482 /* Wa_1407352427:icl,ehl */ 1483 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1484 PSDUNIT_CLKGATE_DIS); 1485 1486 /* Wa_1406680159:icl,ehl */ 1487 wa_write_or(wal, 1488 SUBSLICE_UNIT_LEVEL_CLKGATE, 1489 GWUNIT_CLKGATE_DIS); 1490 1491 /* 1492 * Wa_1408767742:icl[a2..forever],ehl[all] 1493 * Wa_1605460711:icl[a0..c0] 1494 */ 1495 wa_write_or(wal, 1496 GEN7_FF_THREAD_MODE, 1497 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 1498 } 1499 1500 if (IS_GEN_RANGE(i915, 9, 12)) { 1501 /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */ 1502 wa_masked_en(wal, 1503 GEN7_FF_SLICE_CS_CHICKEN1, 1504 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 1505 } 1506 1507 if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { 1508 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 1509 wa_write_or(wal, 1510 GEN8_GARBCNTL, 1511 GEN9_GAPS_TSV_CREDIT_DISABLE); 1512 } 1513 1514 if (IS_BROXTON(i915)) { 1515 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1516 wa_masked_en(wal, 1517 FF_SLICE_CS_CHICKEN2, 1518 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1519 } 1520 1521 if (IS_GEN(i915, 9)) { 1522 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 1523 wa_masked_en(wal, 1524 GEN9_CSFE_CHICKEN1_RCS, 1525 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 1526 1527 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 1528 wa_write_or(wal, 1529 BDW_SCRATCH1, 1530 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 1531 1532 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 1533 if (IS_GEN9_LP(i915)) 1534 wa_write_masked_or(wal, 1535 GEN8_L3SQCREG1, 1536 L3_PRIO_CREDITS_MASK, 1537 L3_GENERAL_PRIO_CREDITS(62) | 1538 L3_HIGH_PRIO_CREDITS(2)); 1539 1540 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 1541 wa_write_or(wal, 1542 GEN8_L3SQCREG4, 1543 GEN8_LQSC_FLUSH_COHERENT_LINES); 1544 } 1545 1546 if (IS_GEN(i915, 7)) 1547 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1548 wa_masked_en(wal, 1549 GFX_MODE_GEN7, 1550 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 1551 1552 if (IS_GEN_RANGE(i915, 6, 7)) 1553 /* 1554 * We need to disable the AsyncFlip performance optimisations in 1555 * order to use MI_WAIT_FOR_EVENT within the CS. It should 1556 * already be programmed to '1' on all products. 1557 * 1558 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1559 */ 1560 wa_masked_en(wal, 1561 MI_MODE, 1562 ASYNC_FLIP_PERF_DISABLE); 1563 1564 if (IS_GEN(i915, 6)) { 1565 /* 1566 * Required for the hardware to program scanline values for 1567 * waiting 1568 * WaEnableFlushTlbInvalidationMode:snb 1569 */ 1570 wa_masked_en(wal, 1571 GFX_MODE, 1572 GFX_TLB_INVALIDATE_EXPLICIT); 1573 1574 /* 1575 * From the Sandybridge PRM, volume 1 part 3, page 24: 1576 * "If this bit is set, STCunit will have LRA as replacement 1577 * policy. [...] This bit must be reset. LRA replacement 1578 * policy is not supported." 1579 */ 1580 wa_masked_dis(wal, 1581 CACHE_MODE_0, 1582 CM0_STC_EVICT_DISABLE_LRA_SNB); 1583 } 1584 1585 if (IS_GEN_RANGE(i915, 4, 6)) 1586 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1587 wa_add(wal, MI_MODE, 1588 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 1589 /* XXX bit doesn't stick on Broadwater */ 1590 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); 1591 } 1592 1593 static void 1594 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1595 { 1596 struct drm_i915_private *i915 = engine->i915; 1597 1598 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 1599 if (IS_KBL_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { 1600 wa_write(wal, 1601 RING_SEMA_WAIT_POLL(engine->mmio_base), 1602 1); 1603 } 1604 } 1605 1606 static void 1607 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 1608 { 1609 if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4)) 1610 return; 1611 1612 if (engine->class == RENDER_CLASS) 1613 rcs_engine_wa_init(engine, wal); 1614 else 1615 xcs_engine_wa_init(engine, wal); 1616 } 1617 1618 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 1619 { 1620 struct i915_wa_list *wal = &engine->wa_list; 1621 1622 if (INTEL_GEN(engine->i915) < 4) 1623 return; 1624 1625 wa_init_start(wal, "engine", engine->name); 1626 engine_init_workarounds(engine, wal); 1627 wa_init_finish(wal); 1628 } 1629 1630 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 1631 { 1632 wa_list_apply(engine->uncore, &engine->wa_list); 1633 } 1634 1635 static struct i915_vma * 1636 create_scratch(struct i915_address_space *vm, int count) 1637 { 1638 struct drm_i915_gem_object *obj; 1639 struct i915_vma *vma; 1640 unsigned int size; 1641 int err; 1642 1643 size = round_up(count * sizeof(u32), PAGE_SIZE); 1644 obj = i915_gem_object_create_internal(vm->i915, size); 1645 if (IS_ERR(obj)) 1646 return ERR_CAST(obj); 1647 1648 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 1649 1650 vma = i915_vma_instance(obj, vm, NULL); 1651 if (IS_ERR(vma)) { 1652 err = PTR_ERR(vma); 1653 goto err_obj; 1654 } 1655 1656 err = i915_vma_pin(vma, 0, 0, 1657 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 1658 if (err) 1659 goto err_obj; 1660 1661 return vma; 1662 1663 err_obj: 1664 i915_gem_object_put(obj); 1665 return ERR_PTR(err); 1666 } 1667 1668 static const struct { 1669 u32 start; 1670 u32 end; 1671 } mcr_ranges_gen8[] = { 1672 { .start = 0x5500, .end = 0x55ff }, 1673 { .start = 0x7000, .end = 0x7fff }, 1674 { .start = 0x9400, .end = 0x97ff }, 1675 { .start = 0xb000, .end = 0xb3ff }, 1676 { .start = 0xe000, .end = 0xe7ff }, 1677 {}, 1678 }; 1679 1680 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 1681 { 1682 int i; 1683 1684 if (INTEL_GEN(i915) < 8) 1685 return false; 1686 1687 /* 1688 * Registers in these ranges are affected by the MCR selector 1689 * which only controls CPU initiated MMIO. Routing does not 1690 * work for CS access so we cannot verify them on this path. 1691 */ 1692 for (i = 0; mcr_ranges_gen8[i].start; i++) 1693 if (offset >= mcr_ranges_gen8[i].start && 1694 offset <= mcr_ranges_gen8[i].end) 1695 return true; 1696 1697 return false; 1698 } 1699 1700 static int 1701 wa_list_srm(struct i915_request *rq, 1702 const struct i915_wa_list *wal, 1703 struct i915_vma *vma) 1704 { 1705 struct drm_i915_private *i915 = rq->i915; 1706 unsigned int i, count = 0; 1707 const struct i915_wa *wa; 1708 u32 srm, *cs; 1709 1710 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 1711 if (INTEL_GEN(i915) >= 8) 1712 srm++; 1713 1714 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1715 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 1716 count++; 1717 } 1718 1719 cs = intel_ring_begin(rq, 4 * count); 1720 if (IS_ERR(cs)) 1721 return PTR_ERR(cs); 1722 1723 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1724 u32 offset = i915_mmio_reg_offset(wa->reg); 1725 1726 if (mcr_range(i915, offset)) 1727 continue; 1728 1729 *cs++ = srm; 1730 *cs++ = offset; 1731 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 1732 *cs++ = 0; 1733 } 1734 intel_ring_advance(rq, cs); 1735 1736 return 0; 1737 } 1738 1739 static int engine_wa_list_verify(struct intel_context *ce, 1740 const struct i915_wa_list * const wal, 1741 const char *from) 1742 { 1743 const struct i915_wa *wa; 1744 struct i915_request *rq; 1745 struct i915_vma *vma; 1746 unsigned int i; 1747 u32 *results; 1748 int err; 1749 1750 if (!wal->count) 1751 return 0; 1752 1753 vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count); 1754 if (IS_ERR(vma)) 1755 return PTR_ERR(vma); 1756 1757 intel_engine_pm_get(ce->engine); 1758 rq = intel_context_create_request(ce); 1759 intel_engine_pm_put(ce->engine); 1760 if (IS_ERR(rq)) { 1761 err = PTR_ERR(rq); 1762 goto err_vma; 1763 } 1764 1765 i915_vma_lock(vma); 1766 err = i915_request_await_object(rq, vma->obj, true); 1767 if (err == 0) 1768 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 1769 i915_vma_unlock(vma); 1770 if (err) { 1771 i915_request_add(rq); 1772 goto err_vma; 1773 } 1774 1775 err = wa_list_srm(rq, wal, vma); 1776 if (err) 1777 goto err_vma; 1778 1779 i915_request_get(rq); 1780 i915_request_add(rq); 1781 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 1782 err = -ETIME; 1783 goto err_rq; 1784 } 1785 1786 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 1787 if (IS_ERR(results)) { 1788 err = PTR_ERR(results); 1789 goto err_rq; 1790 } 1791 1792 err = 0; 1793 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1794 if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) 1795 continue; 1796 1797 if (!wa_verify(wa, results[i], wal->name, from)) 1798 err = -ENXIO; 1799 } 1800 1801 i915_gem_object_unpin_map(vma->obj); 1802 1803 err_rq: 1804 i915_request_put(rq); 1805 err_vma: 1806 i915_vma_unpin(vma); 1807 i915_vma_put(vma); 1808 return err; 1809 } 1810 1811 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 1812 const char *from) 1813 { 1814 return engine_wa_list_verify(engine->kernel_context, 1815 &engine->wa_list, 1816 from); 1817 } 1818 1819 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 1820 #include "selftest_workarounds.c" 1821 #endif 1822