1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2014-2018 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "intel_context.h" 8 #include "intel_engine_pm.h" 9 #include "intel_engine_regs.h" 10 #include "intel_gpu_commands.h" 11 #include "intel_gt.h" 12 #include "intel_gt_mcr.h" 13 #include "intel_gt_regs.h" 14 #include "intel_ring.h" 15 #include "intel_workarounds.h" 16 17 /** 18 * DOC: Hardware workarounds 19 * 20 * Hardware workarounds are register programming documented to be executed in 21 * the driver that fall outside of the normal programming sequences for a 22 * platform. There are some basic categories of workarounds, depending on 23 * how/when they are applied: 24 * 25 * - Context workarounds: workarounds that touch registers that are 26 * saved/restored to/from the HW context image. The list is emitted (via Load 27 * Register Immediate commands) once when initializing the device and saved in 28 * the default context. That default context is then used on every context 29 * creation to have a "primed golden context", i.e. a context image that 30 * already contains the changes needed to all the registers. 31 * 32 * - Engine workarounds: the list of these WAs is applied whenever the specific 33 * engine is reset. It's also possible that a set of engine classes share a 34 * common power domain and they are reset together. This happens on some 35 * platforms with render and compute engines. In this case (at least) one of 36 * them need to keeep the workaround programming: the approach taken in the 37 * driver is to tie those workarounds to the first compute/render engine that 38 * is registered. When executing with GuC submission, engine resets are 39 * outside of kernel driver control, hence the list of registers involved in 40 * written once, on engine initialization, and then passed to GuC, that 41 * saves/restores their values before/after the reset takes place. See 42 * ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference. 43 * 44 * - GT workarounds: the list of these WAs is applied whenever these registers 45 * revert to their default values: on GPU reset, suspend/resume [1]_, etc. 46 * 47 * - Register whitelist: some workarounds need to be implemented in userspace, 48 * but need to touch privileged registers. The whitelist in the kernel 49 * instructs the hardware to allow the access to happen. From the kernel side, 50 * this is just a special case of a MMIO workaround (as we write the list of 51 * these to/be-whitelisted registers to some special HW registers). 52 * 53 * - Workaround batchbuffers: buffers that get executed automatically by the 54 * hardware on every HW context restore. These buffers are created and 55 * programmed in the default context so the hardware always go through those 56 * programming sequences when switching contexts. The support for workaround 57 * batchbuffers is enabled these hardware mechanisms: 58 * 59 * #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default 60 * context, pointing the hardware to jump to that location when that offset 61 * is reached in the context restore. Workaround batchbuffer in the driver 62 * currently uses this mechanism for all platforms. 63 * 64 * #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context, 65 * pointing the hardware to a buffer to continue executing after the 66 * engine registers are restored in a context restore sequence. This is 67 * currently not used in the driver. 68 * 69 * - Other: There are WAs that, due to their nature, cannot be applied from a 70 * central place. Those are peppered around the rest of the code, as needed. 71 * Workarounds related to the display IP are the main example. 72 * 73 * .. [1] Technically, some registers are powercontext saved & restored, so they 74 * survive a suspend/resume. In practice, writing them again is not too 75 * costly and simplifies things, so it's the approach taken in the driver. 76 */ 77 78 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, 79 const char *name, const char *engine_name) 80 { 81 wal->gt = gt; 82 wal->name = name; 83 wal->engine_name = engine_name; 84 } 85 86 #define WA_LIST_CHUNK (1 << 4) 87 88 static void wa_init_finish(struct i915_wa_list *wal) 89 { 90 /* Trim unused entries. */ 91 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { 92 struct i915_wa *list = kmemdup(wal->list, 93 wal->count * sizeof(*list), 94 GFP_KERNEL); 95 96 if (list) { 97 kfree(wal->list); 98 wal->list = list; 99 } 100 } 101 102 if (!wal->count) 103 return; 104 105 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", 106 wal->wa_count, wal->name, wal->engine_name); 107 } 108 109 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) 110 { 111 unsigned int addr = i915_mmio_reg_offset(wa->reg); 112 struct drm_i915_private *i915 = wal->gt->i915; 113 unsigned int start = 0, end = wal->count; 114 const unsigned int grow = WA_LIST_CHUNK; 115 struct i915_wa *wa_; 116 117 GEM_BUG_ON(!is_power_of_2(grow)); 118 119 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ 120 struct i915_wa *list; 121 122 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), 123 GFP_KERNEL); 124 if (!list) { 125 drm_err(&i915->drm, "No space for workaround init!\n"); 126 return; 127 } 128 129 if (wal->list) { 130 memcpy(list, wal->list, sizeof(*wa) * wal->count); 131 kfree(wal->list); 132 } 133 134 wal->list = list; 135 } 136 137 while (start < end) { 138 unsigned int mid = start + (end - start) / 2; 139 140 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { 141 start = mid + 1; 142 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { 143 end = mid; 144 } else { 145 wa_ = &wal->list[mid]; 146 147 if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) { 148 drm_err(&i915->drm, 149 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n", 150 i915_mmio_reg_offset(wa_->reg), 151 wa_->clr, wa_->set); 152 153 wa_->set &= ~wa->clr; 154 } 155 156 wal->wa_count++; 157 wa_->set |= wa->set; 158 wa_->clr |= wa->clr; 159 wa_->read |= wa->read; 160 return; 161 } 162 } 163 164 wal->wa_count++; 165 wa_ = &wal->list[wal->count++]; 166 *wa_ = *wa; 167 168 while (wa_-- > wal->list) { 169 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == 170 i915_mmio_reg_offset(wa_[1].reg)); 171 if (i915_mmio_reg_offset(wa_[1].reg) > 172 i915_mmio_reg_offset(wa_[0].reg)) 173 break; 174 175 swap(wa_[1], wa_[0]); 176 } 177 } 178 179 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, 180 u32 clear, u32 set, u32 read_mask, bool masked_reg) 181 { 182 struct i915_wa wa = { 183 .reg = reg, 184 .clr = clear, 185 .set = set, 186 .read = read_mask, 187 .masked_reg = masked_reg, 188 }; 189 190 _wa_add(wal, &wa); 191 } 192 193 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, 194 u32 clear, u32 set, u32 read_mask, bool masked_reg) 195 { 196 struct i915_wa wa = { 197 .mcr_reg = reg, 198 .clr = clear, 199 .set = set, 200 .read = read_mask, 201 .masked_reg = masked_reg, 202 .is_mcr = 1, 203 }; 204 205 _wa_add(wal, &wa); 206 } 207 208 static void 209 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) 210 { 211 wa_add(wal, reg, clear, set, clear, false); 212 } 213 214 static void 215 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) 216 { 217 wa_mcr_add(wal, reg, clear, set, clear, false); 218 } 219 220 static void 221 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 222 { 223 wa_write_clr_set(wal, reg, ~0, set); 224 } 225 226 static void 227 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) 228 { 229 wa_write_clr_set(wal, reg, set, set); 230 } 231 232 static void 233 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) 234 { 235 wa_mcr_write_clr_set(wal, reg, set, set); 236 } 237 238 static void 239 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) 240 { 241 wa_write_clr_set(wal, reg, clr, 0); 242 } 243 244 static void 245 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) 246 { 247 wa_mcr_write_clr_set(wal, reg, clr, 0); 248 } 249 250 /* 251 * WA operations on "masked register". A masked register has the upper 16 bits 252 * documented as "masked" in b-spec. Its purpose is to allow writing to just a 253 * portion of the register without a rmw: you simply write in the upper 16 bits 254 * the mask of bits you are going to modify. 255 * 256 * The wa_masked_* family of functions already does the necessary operations to 257 * calculate the mask based on the parameters passed, so user only has to 258 * provide the lower 16 bits of that register. 259 */ 260 261 static void 262 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 263 { 264 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 265 } 266 267 static void 268 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 269 { 270 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); 271 } 272 273 static void 274 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) 275 { 276 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 277 } 278 279 static void 280 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) 281 { 282 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); 283 } 284 285 static void 286 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, 287 u32 mask, u32 val) 288 { 289 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 290 } 291 292 static void 293 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, 294 u32 mask, u32 val) 295 { 296 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); 297 } 298 299 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 300 struct i915_wa_list *wal) 301 { 302 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 303 } 304 305 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, 306 struct i915_wa_list *wal) 307 { 308 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 309 } 310 311 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, 312 struct i915_wa_list *wal) 313 { 314 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); 315 316 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 317 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); 318 319 /* WaDisablePartialInstShootdown:bdw,chv */ 320 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 321 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 322 323 /* Use Force Non-Coherent whenever executing a 3D context. This is a 324 * workaround for a possible hang in the unlikely event a TLB 325 * invalidation occurs during a PSD flush. 326 */ 327 /* WaForceEnableNonCoherent:bdw,chv */ 328 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 329 wa_masked_en(wal, HDC_CHICKEN0, 330 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 331 HDC_FORCE_NON_COHERENT); 332 333 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 334 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 335 * polygons in the same 8x4 pixel/sample area to be processed without 336 * stalling waiting for the earlier ones to write to Hierarchical Z 337 * buffer." 338 * 339 * This optimization is off by default for BDW and CHV; turn it on. 340 */ 341 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 342 343 /* Wa4x4STCOptimizationDisable:bdw,chv */ 344 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 345 346 /* 347 * BSpec recommends 8x4 when MSAA is used, 348 * however in practice 16x4 seems fastest. 349 * 350 * Note that PS/WM thread counts depend on the WIZ hashing 351 * disable bit, which we don't touch here, but it's good 352 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 353 */ 354 wa_masked_field_set(wal, GEN7_GT_MODE, 355 GEN6_WIZ_HASHING_MASK, 356 GEN6_WIZ_HASHING_16x4); 357 } 358 359 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine, 360 struct i915_wa_list *wal) 361 { 362 struct drm_i915_private *i915 = engine->i915; 363 364 gen8_ctx_workarounds_init(engine, wal); 365 366 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 367 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 368 369 /* WaDisableDopClockGating:bdw 370 * 371 * Also see the related UCGTCL1 write in bdw_init_clock_gating() 372 * to disable EUTC clock gating. 373 */ 374 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 375 DOP_CLOCK_GATING_DISABLE); 376 377 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 378 GEN8_SAMPLER_POWER_BYPASS_DIS); 379 380 wa_masked_en(wal, HDC_CHICKEN0, 381 /* WaForceContextSaveRestoreNonCoherent:bdw */ 382 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 383 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 384 (IS_BDW_GT3(i915) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 385 } 386 387 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine, 388 struct i915_wa_list *wal) 389 { 390 gen8_ctx_workarounds_init(engine, wal); 391 392 /* WaDisableThreadStallDopClockGating:chv */ 393 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 394 395 /* Improve HiZ throughput on CHV. */ 396 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 397 } 398 399 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, 400 struct i915_wa_list *wal) 401 { 402 struct drm_i915_private *i915 = engine->i915; 403 404 if (HAS_LLC(i915)) { 405 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 406 * 407 * Must match Display Engine. See 408 * WaCompressedResourceDisplayNewHashMode. 409 */ 410 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 411 GEN9_PBE_COMPRESSED_HASH_SELECTION); 412 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 413 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); 414 } 415 416 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ 417 /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */ 418 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 419 FLOW_CONTROL_ENABLE | 420 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 421 422 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */ 423 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */ 424 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 425 GEN9_ENABLE_YV12_BUGFIX | 426 GEN9_ENABLE_GPGPU_PREEMPTION); 427 428 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */ 429 /* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */ 430 wa_masked_en(wal, CACHE_MODE_1, 431 GEN8_4x4_STC_OPTIMIZATION_DISABLE | 432 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); 433 434 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */ 435 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, 436 GEN9_CCS_TLB_PREFETCH_ENABLE); 437 438 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */ 439 wa_masked_en(wal, HDC_CHICKEN0, 440 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 441 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 442 443 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 444 * both tied to WaForceContextSaveRestoreNonCoherent 445 * in some hsds for skl. We keep the tie for all gen9. The 446 * documentation is a bit hazy and so we want to get common behaviour, 447 * even though there is no clear evidence we would need both on kbl/bxt. 448 * This area has been source of system hangs so we play it safe 449 * and mimic the skl regardless of what bspec says. 450 * 451 * Use Force Non-Coherent whenever executing a 3D context. This 452 * is a workaround for a possible hang in the unlikely event 453 * a TLB invalidation occurs during a PSD flush. 454 */ 455 456 /* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */ 457 wa_masked_en(wal, HDC_CHICKEN0, 458 HDC_FORCE_NON_COHERENT); 459 460 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ 461 if (IS_SKYLAKE(i915) || 462 IS_KABYLAKE(i915) || 463 IS_COFFEELAKE(i915) || 464 IS_COMETLAKE(i915)) 465 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, 466 GEN8_SAMPLER_POWER_BYPASS_DIS); 467 468 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */ 469 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 470 471 /* 472 * Supporting preemption with fine-granularity requires changes in the 473 * batch buffer programming. Since we can't break old userspace, we 474 * need to set our default preemption level to safe value. Userspace is 475 * still able to use more fine-grained preemption levels, since in 476 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the 477 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are 478 * not real HW workarounds, but merely a way to start using preemption 479 * while maintaining old contract with userspace. 480 */ 481 482 /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */ 483 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); 484 485 /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */ 486 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 487 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 488 GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); 489 490 /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ 491 if (IS_GEN9_LP(i915)) 492 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); 493 } 494 495 static void skl_tune_iz_hashing(struct intel_engine_cs *engine, 496 struct i915_wa_list *wal) 497 { 498 struct intel_gt *gt = engine->gt; 499 u8 vals[3] = { 0, 0, 0 }; 500 unsigned int i; 501 502 for (i = 0; i < 3; i++) { 503 u8 ss; 504 505 /* 506 * Only consider slices where one, and only one, subslice has 7 507 * EUs 508 */ 509 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) 510 continue; 511 512 /* 513 * subslice_7eu[i] != 0 (because of the check above) and 514 * ss_max == 4 (maximum number of subslices possible per slice) 515 * 516 * -> 0 <= ss <= 3; 517 */ 518 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; 519 vals[i] = 3 - ss; 520 } 521 522 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 523 return; 524 525 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 526 wa_masked_field_set(wal, GEN7_GT_MODE, 527 GEN9_IZ_HASHING_MASK(2) | 528 GEN9_IZ_HASHING_MASK(1) | 529 GEN9_IZ_HASHING_MASK(0), 530 GEN9_IZ_HASHING(2, vals[2]) | 531 GEN9_IZ_HASHING(1, vals[1]) | 532 GEN9_IZ_HASHING(0, vals[0])); 533 } 534 535 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine, 536 struct i915_wa_list *wal) 537 { 538 gen9_ctx_workarounds_init(engine, wal); 539 skl_tune_iz_hashing(engine, wal); 540 } 541 542 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine, 543 struct i915_wa_list *wal) 544 { 545 gen9_ctx_workarounds_init(engine, wal); 546 547 /* WaDisableThreadStallDopClockGating:bxt */ 548 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 549 STALL_DOP_GATING_DISABLE); 550 551 /* WaToEnableHwFixForPushConstHWBug:bxt */ 552 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 553 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 554 } 555 556 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, 557 struct i915_wa_list *wal) 558 { 559 struct drm_i915_private *i915 = engine->i915; 560 561 gen9_ctx_workarounds_init(engine, wal); 562 563 /* WaToEnableHwFixForPushConstHWBug:kbl */ 564 if (IS_KBL_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) 565 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 566 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 567 568 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 569 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 570 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 571 } 572 573 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine, 574 struct i915_wa_list *wal) 575 { 576 gen9_ctx_workarounds_init(engine, wal); 577 578 /* WaToEnableHwFixForPushConstHWBug:glk */ 579 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 580 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 581 } 582 583 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine, 584 struct i915_wa_list *wal) 585 { 586 gen9_ctx_workarounds_init(engine, wal); 587 588 /* WaToEnableHwFixForPushConstHWBug:cfl */ 589 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, 590 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 591 592 /* WaDisableSbeCacheDispatchPortSharing:cfl */ 593 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 594 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 595 } 596 597 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 598 struct i915_wa_list *wal) 599 { 600 /* Wa_1406697149 (WaDisableBankHangMode:icl) */ 601 wa_write(wal, 602 GEN8_L3CNTLREG, 603 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | 604 GEN8_ERRDETBCTRL); 605 606 /* WaForceEnableNonCoherent:icl 607 * This is not the same workaround as in early Gen9 platforms, where 608 * lacking this could cause system hangs, but coherency performance 609 * overhead is high and only a few compute workloads really need it 610 * (the register is whitelisted in hardware now, so UMDs can opt in 611 * for coherency if they have a good reason). 612 */ 613 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); 614 615 /* WaEnableFloatBlendOptimization:icl */ 616 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 617 _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE), 618 0 /* write-only, so skip validation */, 619 true); 620 621 /* WaDisableGPGPUMidThreadPreemption:icl */ 622 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 623 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 624 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 625 626 /* allow headerless messages for preemptible GPGPU context */ 627 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 628 GEN11_SAMPLER_ENABLE_HEADLESS_MSG); 629 630 /* Wa_1604278689:icl,ehl */ 631 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); 632 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, 633 0, /* write-only register; skip validation */ 634 0xFFFFFFFF); 635 636 /* Wa_1406306137:icl,ehl */ 637 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); 638 } 639 640 /* 641 * These settings aren't actually workarounds, but general tuning settings that 642 * need to be programmed on dg2 platform. 643 */ 644 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine, 645 struct i915_wa_list *wal) 646 { 647 wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); 648 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, 649 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); 650 wa_mcr_add(wal, 651 XEHP_FF_MODE2, 652 FF_MODE2_TDS_TIMER_MASK, 653 FF_MODE2_TDS_TIMER_128, 654 0, false); 655 } 656 657 /* 658 * These settings aren't actually workarounds, but general tuning settings that 659 * need to be programmed on several platforms. 660 */ 661 static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine, 662 struct i915_wa_list *wal) 663 { 664 /* 665 * Although some platforms refer to it as Wa_1604555607, we need to 666 * program it even on those that don't explicitly list that 667 * workaround. 668 * 669 * Note that the programming of this register is further modified 670 * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. 671 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong 672 * value when read. The default value for this register is zero for all 673 * fields and there are no bit masks. So instead of doing a RMW we 674 * should just write TDS timer value. For the same reason read 675 * verification is ignored. 676 */ 677 wa_add(wal, 678 GEN12_FF_MODE2, 679 FF_MODE2_TDS_TIMER_MASK, 680 FF_MODE2_TDS_TIMER_128, 681 0, false); 682 } 683 684 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 685 struct i915_wa_list *wal) 686 { 687 struct drm_i915_private *i915 = engine->i915; 688 689 gen12_ctx_gt_tuning_init(engine, wal); 690 691 /* 692 * Wa_1409142259:tgl,dg1,adl-p 693 * Wa_1409347922:tgl,dg1,adl-p 694 * Wa_1409252684:tgl,dg1,adl-p 695 * Wa_1409217633:tgl,dg1,adl-p 696 * Wa_1409207793:tgl,dg1,adl-p 697 * Wa_1409178076:tgl,dg1,adl-p 698 * Wa_1408979724:tgl,dg1,adl-p 699 * Wa_14010443199:tgl,rkl,dg1,adl-p 700 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p 701 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p 702 */ 703 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, 704 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 705 706 /* WaDisableGPGPUMidThreadPreemption:gen12 */ 707 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, 708 GEN9_PREEMPT_GPGPU_LEVEL_MASK, 709 GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); 710 711 /* 712 * Wa_16011163337 713 * 714 * Like in gen12_ctx_gt_tuning_init(), read verification is ignored due 715 * to Wa_1608008084. 716 */ 717 wa_add(wal, 718 GEN12_FF_MODE2, 719 FF_MODE2_GS_TIMER_MASK, 720 FF_MODE2_GS_TIMER_224, 721 0, false); 722 723 if (!IS_DG1(i915)) 724 /* Wa_1806527549 */ 725 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); 726 } 727 728 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, 729 struct i915_wa_list *wal) 730 { 731 gen12_ctx_workarounds_init(engine, wal); 732 733 /* Wa_1409044764 */ 734 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, 735 DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); 736 737 /* Wa_22010493298 */ 738 wa_masked_en(wal, HIZ_CHICKEN, 739 DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); 740 } 741 742 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 743 struct i915_wa_list *wal) 744 { 745 dg2_ctx_gt_tuning_init(engine, wal); 746 747 /* Wa_16011186671:dg2_g11 */ 748 if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 749 wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH); 750 wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE); 751 } 752 753 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 754 /* Wa_14010469329:dg2_g10 */ 755 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 756 XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE); 757 758 /* 759 * Wa_22010465075:dg2_g10 760 * Wa_22010613112:dg2_g10 761 * Wa_14010698770:dg2_g10 762 */ 763 wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3, 764 GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); 765 } 766 767 /* Wa_16013271637:dg2 */ 768 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, 769 MSC_MSAA_REODER_BUF_BYPASS_DISABLE); 770 771 /* Wa_14014947963:dg2 */ 772 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || 773 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 774 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); 775 776 /* Wa_18018764978:dg2 */ 777 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) || 778 IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) 779 wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); 780 781 /* Wa_15010599737:dg2 */ 782 wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); 783 784 /* Wa_18019271663:dg2 */ 785 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); 786 } 787 788 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, 789 struct i915_wa_list *wal) 790 { 791 /* 792 * This is a "fake" workaround defined by software to ensure we 793 * maintain reliable, backward-compatible behavior for userspace with 794 * regards to how nested MI_BATCH_BUFFER_START commands are handled. 795 * 796 * The per-context setting of MI_MODE[12] determines whether the bits 797 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted 798 * in the traditional manner or whether they should instead use a new 799 * tgl+ meaning that breaks backward compatibility, but allows nesting 800 * into 3rd-level batchbuffers. When this new capability was first 801 * added in TGL, it remained off by default unless a context 802 * intentionally opted in to the new behavior. However Xe_HPG now 803 * flips this on by default and requires that we explicitly opt out if 804 * we don't want the new behavior. 805 * 806 * From a SW perspective, we want to maintain the backward-compatible 807 * behavior for userspace, so we'll apply a fake workaround to set it 808 * back to the legacy behavior on platforms where the hardware default 809 * is to break compatibility. At the moment there is no Linux 810 * userspace that utilizes third-level batchbuffers, so this will avoid 811 * userspace from needing to make any changes. using the legacy 812 * meaning is the correct thing to do. If/when we have userspace 813 * consumers that want to utilize third-level batch nesting, we can 814 * provide a context parameter to allow them to opt-in. 815 */ 816 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); 817 } 818 819 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine, 820 struct i915_wa_list *wal) 821 { 822 u8 mocs; 823 824 /* 825 * Some blitter commands do not have a field for MOCS, those 826 * commands will use MOCS index pointed by BLIT_CCTL. 827 * BLIT_CCTL registers are needed to be programmed to un-cached. 828 */ 829 if (engine->class == COPY_ENGINE_CLASS) { 830 mocs = engine->gt->mocs.uc_index; 831 wa_write_clr_set(wal, 832 BLIT_CCTL(engine->mmio_base), 833 BLIT_CCTL_MASK, 834 BLIT_CCTL_MOCS(mocs, mocs)); 835 } 836 } 837 838 /* 839 * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround 840 * defined by the hardware team, but it programming general context registers. 841 * Adding those context register programming in context workaround 842 * allow us to use the wa framework for proper application and validation. 843 */ 844 static void 845 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine, 846 struct i915_wa_list *wal) 847 { 848 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) 849 fakewa_disable_nestedbb_mode(engine, wal); 850 851 gen12_ctx_gt_mocs_init(engine, wal); 852 } 853 854 static void 855 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 856 struct i915_wa_list *wal, 857 const char *name) 858 { 859 struct drm_i915_private *i915 = engine->i915; 860 861 wa_init_start(wal, engine->gt, name, engine->name); 862 863 /* Applies to all engines */ 864 /* 865 * Fake workarounds are not the actual workaround but 866 * programming of context registers using workaround framework. 867 */ 868 if (GRAPHICS_VER(i915) >= 12) 869 gen12_ctx_gt_fake_wa_init(engine, wal); 870 871 if (engine->class != RENDER_CLASS) 872 goto done; 873 874 if (IS_PONTEVECCHIO(i915)) 875 ; /* noop; none at this time */ 876 else if (IS_DG2(i915)) 877 dg2_ctx_workarounds_init(engine, wal); 878 else if (IS_XEHPSDV(i915)) 879 ; /* noop; none at this time */ 880 else if (IS_DG1(i915)) 881 dg1_ctx_workarounds_init(engine, wal); 882 else if (GRAPHICS_VER(i915) == 12) 883 gen12_ctx_workarounds_init(engine, wal); 884 else if (GRAPHICS_VER(i915) == 11) 885 icl_ctx_workarounds_init(engine, wal); 886 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 887 cfl_ctx_workarounds_init(engine, wal); 888 else if (IS_GEMINILAKE(i915)) 889 glk_ctx_workarounds_init(engine, wal); 890 else if (IS_KABYLAKE(i915)) 891 kbl_ctx_workarounds_init(engine, wal); 892 else if (IS_BROXTON(i915)) 893 bxt_ctx_workarounds_init(engine, wal); 894 else if (IS_SKYLAKE(i915)) 895 skl_ctx_workarounds_init(engine, wal); 896 else if (IS_CHERRYVIEW(i915)) 897 chv_ctx_workarounds_init(engine, wal); 898 else if (IS_BROADWELL(i915)) 899 bdw_ctx_workarounds_init(engine, wal); 900 else if (GRAPHICS_VER(i915) == 7) 901 gen7_ctx_workarounds_init(engine, wal); 902 else if (GRAPHICS_VER(i915) == 6) 903 gen6_ctx_workarounds_init(engine, wal); 904 else if (GRAPHICS_VER(i915) < 8) 905 ; 906 else 907 MISSING_CASE(GRAPHICS_VER(i915)); 908 909 done: 910 wa_init_finish(wal); 911 } 912 913 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine) 914 { 915 __intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context"); 916 } 917 918 int intel_engine_emit_ctx_wa(struct i915_request *rq) 919 { 920 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; 921 struct i915_wa *wa; 922 unsigned int i; 923 u32 *cs; 924 int ret; 925 926 if (wal->count == 0) 927 return 0; 928 929 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 930 if (ret) 931 return ret; 932 933 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); 934 if (IS_ERR(cs)) 935 return PTR_ERR(cs); 936 937 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); 938 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 939 *cs++ = i915_mmio_reg_offset(wa->reg); 940 *cs++ = wa->set; 941 } 942 *cs++ = MI_NOOP; 943 944 intel_ring_advance(rq, cs); 945 946 ret = rq->engine->emit_flush(rq, EMIT_BARRIER); 947 if (ret) 948 return ret; 949 950 return 0; 951 } 952 953 static void 954 gen4_gt_workarounds_init(struct intel_gt *gt, 955 struct i915_wa_list *wal) 956 { 957 /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ 958 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 959 } 960 961 static void 962 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 963 { 964 gen4_gt_workarounds_init(gt, wal); 965 966 /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ 967 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); 968 } 969 970 static void 971 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 972 { 973 g4x_gt_workarounds_init(gt, wal); 974 975 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); 976 } 977 978 static void 979 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 980 { 981 } 982 983 static void 984 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 985 { 986 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 987 wa_masked_dis(wal, 988 GEN7_COMMON_SLICE_CHICKEN1, 989 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 990 991 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 992 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); 993 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 994 995 /* WaForceL3Serialization:ivb */ 996 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 997 } 998 999 static void 1000 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1001 { 1002 /* WaForceL3Serialization:vlv */ 1003 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); 1004 1005 /* 1006 * WaIncreaseL3CreditsForVLVB0:vlv 1007 * This is the hardware default actually. 1008 */ 1009 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 1010 } 1011 1012 static void 1013 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1014 { 1015 /* L3 caching of data atomics doesn't work -- disable it. */ 1016 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 1017 1018 wa_add(wal, 1019 HSW_ROW_CHICKEN3, 0, 1020 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 1021 0 /* XXX does this reg exist? */, true); 1022 1023 /* WaVSRefCountFullforceMissDisable:hsw */ 1024 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); 1025 } 1026 1027 static void 1028 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) 1029 { 1030 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 1031 unsigned int slice, subslice; 1032 u32 mcr, mcr_mask; 1033 1034 GEM_BUG_ON(GRAPHICS_VER(i915) != 9); 1035 1036 /* 1037 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml 1038 * Before any MMIO read into slice/subslice specific registers, MCR 1039 * packet control register needs to be programmed to point to any 1040 * enabled s/ss pair. Otherwise, incorrect values will be returned. 1041 * This means each subsequent MMIO read will be forwarded to an 1042 * specific s/ss combination, but this is OK since these registers 1043 * are consistent across s/ss in almost all cases. In the rare 1044 * occasions, such as INSTDONE, where this value is dependent 1045 * on s/ss combo, the read should be done with read_subslice_reg. 1046 */ 1047 slice = ffs(sseu->slice_mask) - 1; 1048 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); 1049 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); 1050 GEM_BUG_ON(!subslice); 1051 subslice--; 1052 1053 /* 1054 * We use GEN8_MCR..() macros to calculate the |mcr| value for 1055 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads 1056 */ 1057 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 1058 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 1059 1060 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); 1061 1062 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); 1063 } 1064 1065 static void 1066 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1067 { 1068 struct drm_i915_private *i915 = gt->i915; 1069 1070 /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ 1071 gen9_wa_init_mcr(i915, wal); 1072 1073 /* WaDisableKillLogic:bxt,skl,kbl */ 1074 if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) 1075 wa_write_or(wal, 1076 GAM_ECOCHK, 1077 ECOCHK_DIS_TLB); 1078 1079 if (HAS_LLC(i915)) { 1080 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl 1081 * 1082 * Must match Display Engine. See 1083 * WaCompressedResourceDisplayNewHashMode. 1084 */ 1085 wa_write_or(wal, 1086 MMCD_MISC_CTRL, 1087 MMCD_PCLA | MMCD_HOTSPOT_EN); 1088 } 1089 1090 /* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */ 1091 wa_write_or(wal, 1092 GAM_ECOCHK, 1093 BDW_DISABLE_HDC_INVALIDATION); 1094 } 1095 1096 static void 1097 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1098 { 1099 gen9_gt_workarounds_init(gt, wal); 1100 1101 /* WaDisableGafsUnitClkGating:skl */ 1102 wa_write_or(wal, 1103 GEN7_UCGCTL4, 1104 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1105 1106 /* WaInPlaceDecompressionHang:skl */ 1107 if (IS_SKL_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0)) 1108 wa_write_or(wal, 1109 GEN9_GAMT_ECO_REG_RW_IA, 1110 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1111 } 1112 1113 static void 1114 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1115 { 1116 gen9_gt_workarounds_init(gt, wal); 1117 1118 /* WaDisableDynamicCreditSharing:kbl */ 1119 if (IS_KBL_GRAPHICS_STEP(gt->i915, 0, STEP_C0)) 1120 wa_write_or(wal, 1121 GAMT_CHKN_BIT_REG, 1122 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1123 1124 /* WaDisableGafsUnitClkGating:kbl */ 1125 wa_write_or(wal, 1126 GEN7_UCGCTL4, 1127 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1128 1129 /* WaInPlaceDecompressionHang:kbl */ 1130 wa_write_or(wal, 1131 GEN9_GAMT_ECO_REG_RW_IA, 1132 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1133 } 1134 1135 static void 1136 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1137 { 1138 gen9_gt_workarounds_init(gt, wal); 1139 } 1140 1141 static void 1142 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1143 { 1144 gen9_gt_workarounds_init(gt, wal); 1145 1146 /* WaDisableGafsUnitClkGating:cfl */ 1147 wa_write_or(wal, 1148 GEN7_UCGCTL4, 1149 GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1150 1151 /* WaInPlaceDecompressionHang:cfl */ 1152 wa_write_or(wal, 1153 GEN9_GAMT_ECO_REG_RW_IA, 1154 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1155 } 1156 1157 static void __set_mcr_steering(struct i915_wa_list *wal, 1158 i915_reg_t steering_reg, 1159 unsigned int slice, unsigned int subslice) 1160 { 1161 u32 mcr, mcr_mask; 1162 1163 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 1164 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 1165 1166 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); 1167 } 1168 1169 static void debug_dump_steering(struct intel_gt *gt) 1170 { 1171 struct drm_printer p = drm_debug_printer("MCR Steering:"); 1172 1173 if (drm_debug_enabled(DRM_UT_DRIVER)) 1174 intel_gt_mcr_report_steering(&p, gt, false); 1175 } 1176 1177 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, 1178 unsigned int slice, unsigned int subslice) 1179 { 1180 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); 1181 1182 gt->default_steering.groupid = slice; 1183 gt->default_steering.instanceid = subslice; 1184 1185 debug_dump_steering(gt); 1186 } 1187 1188 static void 1189 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1190 { 1191 const struct sseu_dev_info *sseu = >->info.sseu; 1192 unsigned int subslice; 1193 1194 GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11); 1195 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); 1196 1197 /* 1198 * Although a platform may have subslices, we need to always steer 1199 * reads to the lowest instance that isn't fused off. When Render 1200 * Power Gating is enabled, grabbing forcewake will only power up a 1201 * single subslice (the "minconfig") if there isn't a real workload 1202 * that needs to be run; this means that if we steer register reads to 1203 * one of the higher subslices, we run the risk of reading back 0's or 1204 * random garbage. 1205 */ 1206 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); 1207 1208 /* 1209 * If the subslice we picked above also steers us to a valid L3 bank, 1210 * then we can just rely on the default steering and won't need to 1211 * worry about explicitly re-steering L3BANK reads later. 1212 */ 1213 if (gt->info.l3bank_mask & BIT(subslice)) 1214 gt->steering_table[L3BANK] = NULL; 1215 1216 __add_mcr_wa(gt, wal, 0, subslice); 1217 } 1218 1219 static void 1220 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1221 { 1222 const struct sseu_dev_info *sseu = >->info.sseu; 1223 unsigned long slice, subslice = 0, slice_mask = 0; 1224 u32 lncf_mask = 0; 1225 int i; 1226 1227 /* 1228 * On Xe_HP the steering increases in complexity. There are now several 1229 * more units that require steering and we're not guaranteed to be able 1230 * to find a common setting for all of them. These are: 1231 * - GSLICE (fusable) 1232 * - DSS (sub-unit within gslice; fusable) 1233 * - L3 Bank (fusable) 1234 * - MSLICE (fusable) 1235 * - LNCF (sub-unit within mslice; always present if mslice is present) 1236 * 1237 * We'll do our default/implicit steering based on GSLICE (in the 1238 * sliceid field) and DSS (in the subsliceid field). If we can 1239 * find overlap between the valid MSLICE and/or LNCF values with 1240 * a suitable GSLICE, then we can just re-use the default value and 1241 * skip and explicit steering at runtime. 1242 * 1243 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find 1244 * a valid sliceid value. DSS steering is the only type of steering 1245 * that utilizes the 'subsliceid' bits. 1246 * 1247 * Also note that, even though the steering domain is called "GSlice" 1248 * and it is encoded in the register using the gslice format, the spec 1249 * says that the combined (geometry | compute) fuse should be used to 1250 * select the steering. 1251 */ 1252 1253 /* Find the potential gslice candidates */ 1254 slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask, 1255 GEN_DSS_PER_GSLICE); 1256 1257 /* 1258 * Find the potential LNCF candidates. Either LNCF within a valid 1259 * mslice is fine. 1260 */ 1261 for_each_set_bit(i, >->info.mslice_mask, GEN12_MAX_MSLICES) 1262 lncf_mask |= (0x3 << (i * 2)); 1263 1264 /* 1265 * Are there any sliceid values that work for both GSLICE and LNCF 1266 * steering? 1267 */ 1268 if (slice_mask & lncf_mask) { 1269 slice_mask &= lncf_mask; 1270 gt->steering_table[LNCF] = NULL; 1271 } 1272 1273 /* How about sliceid values that also work for MSLICE steering? */ 1274 if (slice_mask & gt->info.mslice_mask) { 1275 slice_mask &= gt->info.mslice_mask; 1276 gt->steering_table[MSLICE] = NULL; 1277 } 1278 1279 if (IS_XEHPSDV(gt->i915) && slice_mask & BIT(0)) 1280 gt->steering_table[GAM] = NULL; 1281 1282 slice = __ffs(slice_mask); 1283 subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) % 1284 GEN_DSS_PER_GSLICE; 1285 1286 __add_mcr_wa(gt, wal, slice, subslice); 1287 1288 /* 1289 * SQIDI ranges are special because they use different steering 1290 * registers than everything else we work with. On XeHP SDV and 1291 * DG2-G10, any value in the steering registers will work fine since 1292 * all instances are present, but DG2-G11 only has SQIDI instances at 1293 * ID's 2 and 3, so we need to steer to one of those. For simplicity 1294 * we'll just steer to a hardcoded "2" since that value will work 1295 * everywhere. 1296 */ 1297 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); 1298 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); 1299 1300 /* 1301 * On DG2, GAM registers have a dedicated steering control register 1302 * and must always be programmed to a hardcoded groupid of "1." 1303 */ 1304 if (IS_DG2(gt->i915)) 1305 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); 1306 } 1307 1308 static void 1309 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) 1310 { 1311 unsigned int dss; 1312 1313 /* 1314 * Setup implicit steering for COMPUTE and DSS ranges to the first 1315 * non-fused-off DSS. All other types of MCR registers will be 1316 * explicitly steered. 1317 */ 1318 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); 1319 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); 1320 } 1321 1322 static void 1323 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1324 { 1325 struct drm_i915_private *i915 = gt->i915; 1326 1327 icl_wa_init_mcr(gt, wal); 1328 1329 /* WaModifyGamTlbPartitioning:icl */ 1330 wa_write_clr_set(wal, 1331 GEN11_GACB_PERF_CTRL, 1332 GEN11_HASH_CTRL_MASK, 1333 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); 1334 1335 /* Wa_1405766107:icl 1336 * Formerly known as WaCL2SFHalfMaxAlloc 1337 */ 1338 wa_write_or(wal, 1339 GEN11_LSN_UNSLCVC, 1340 GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | 1341 GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); 1342 1343 /* Wa_220166154:icl 1344 * Formerly known as WaDisCtxReload 1345 */ 1346 wa_write_or(wal, 1347 GEN8_GAMW_ECO_DEV_RW_IA, 1348 GAMW_ECO_DEV_CTX_RELOAD_DISABLE); 1349 1350 /* Wa_1406463099:icl 1351 * Formerly known as WaGamTlbPendError 1352 */ 1353 wa_write_or(wal, 1354 GAMT_CHKN_BIT_REG, 1355 GAMT_CHKN_DISABLE_L3_COH_PIPE); 1356 1357 /* Wa_1407352427:icl,ehl */ 1358 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1359 PSDUNIT_CLKGATE_DIS); 1360 1361 /* Wa_1406680159:icl,ehl */ 1362 wa_mcr_write_or(wal, 1363 GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1364 GWUNIT_CLKGATE_DIS); 1365 1366 /* Wa_1607087056:icl,ehl,jsl */ 1367 if (IS_ICELAKE(i915) || 1368 IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1369 wa_write_or(wal, 1370 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1371 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1372 1373 /* 1374 * This is not a documented workaround, but rather an optimization 1375 * to reduce sampler power. 1376 */ 1377 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1378 } 1379 1380 /* 1381 * Though there are per-engine instances of these registers, 1382 * they retain their value through engine resets and should 1383 * only be provided on the GT workaround list rather than 1384 * the engine-specific workaround list. 1385 */ 1386 static void 1387 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) 1388 { 1389 struct intel_engine_cs *engine; 1390 int id; 1391 1392 for_each_engine(engine, gt, id) { 1393 if (engine->class != VIDEO_DECODE_CLASS || 1394 (engine->instance % 2)) 1395 continue; 1396 1397 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), 1398 IECPUNIT_CLKGATE_DIS); 1399 } 1400 } 1401 1402 static void 1403 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1404 { 1405 icl_wa_init_mcr(gt, wal); 1406 1407 /* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */ 1408 wa_14011060649(gt, wal); 1409 1410 /* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */ 1411 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); 1412 } 1413 1414 static void 1415 tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1416 { 1417 struct drm_i915_private *i915 = gt->i915; 1418 1419 gen12_gt_workarounds_init(gt, wal); 1420 1421 /* Wa_1409420604:tgl */ 1422 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1423 wa_mcr_write_or(wal, 1424 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1425 CPSSUNIT_CLKGATE_DIS); 1426 1427 /* Wa_1607087056:tgl also know as BUG:1409180338 */ 1428 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1429 wa_write_or(wal, 1430 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1431 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1432 1433 /* Wa_1408615072:tgl[a0] */ 1434 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1435 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1436 VSUNIT_CLKGATE_DIS_TGL); 1437 } 1438 1439 static void 1440 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1441 { 1442 struct drm_i915_private *i915 = gt->i915; 1443 1444 gen12_gt_workarounds_init(gt, wal); 1445 1446 /* Wa_1607087056:dg1 */ 1447 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1448 wa_write_or(wal, 1449 GEN11_SLICE_UNIT_LEVEL_CLKGATE, 1450 L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); 1451 1452 /* Wa_1409420604:dg1 */ 1453 if (IS_DG1(i915)) 1454 wa_mcr_write_or(wal, 1455 SUBSLICE_UNIT_LEVEL_CLKGATE2, 1456 CPSSUNIT_CLKGATE_DIS); 1457 1458 /* Wa_1408615072:dg1 */ 1459 /* Empirical testing shows this register is unaffected by engine reset. */ 1460 if (IS_DG1(i915)) 1461 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, 1462 VSUNIT_CLKGATE_DIS_TGL); 1463 } 1464 1465 static void 1466 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1467 { 1468 struct drm_i915_private *i915 = gt->i915; 1469 1470 xehp_init_mcr(gt, wal); 1471 1472 /* Wa_1409757795:xehpsdv */ 1473 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); 1474 1475 /* Wa_16011155590:xehpsdv */ 1476 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) 1477 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1478 TSGUNIT_CLKGATE_DIS); 1479 1480 /* Wa_14011780169:xehpsdv */ 1481 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_B0, STEP_FOREVER)) { 1482 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1483 GAMTLBVDBOX7_CLKGATE_DIS | 1484 GAMTLBVDBOX6_CLKGATE_DIS | 1485 GAMTLBVDBOX5_CLKGATE_DIS | 1486 GAMTLBVDBOX4_CLKGATE_DIS | 1487 GAMTLBVDBOX3_CLKGATE_DIS | 1488 GAMTLBVDBOX2_CLKGATE_DIS | 1489 GAMTLBVDBOX1_CLKGATE_DIS | 1490 GAMTLBVDBOX0_CLKGATE_DIS | 1491 GAMTLBKCR_CLKGATE_DIS | 1492 GAMTLBGUC_CLKGATE_DIS | 1493 GAMTLBBLT_CLKGATE_DIS); 1494 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1495 GAMTLBGFXA1_CLKGATE_DIS | 1496 GAMTLBCOMPA0_CLKGATE_DIS | 1497 GAMTLBCOMPA1_CLKGATE_DIS | 1498 GAMTLBCOMPB0_CLKGATE_DIS | 1499 GAMTLBCOMPB1_CLKGATE_DIS | 1500 GAMTLBCOMPC0_CLKGATE_DIS | 1501 GAMTLBCOMPC1_CLKGATE_DIS | 1502 GAMTLBCOMPD0_CLKGATE_DIS | 1503 GAMTLBCOMPD1_CLKGATE_DIS | 1504 GAMTLBMERT_CLKGATE_DIS | 1505 GAMTLBVEBOX3_CLKGATE_DIS | 1506 GAMTLBVEBOX2_CLKGATE_DIS | 1507 GAMTLBVEBOX1_CLKGATE_DIS | 1508 GAMTLBVEBOX0_CLKGATE_DIS); 1509 } 1510 1511 /* Wa_16012725990:xehpsdv */ 1512 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER)) 1513 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); 1514 1515 /* Wa_14011060649:xehpsdv */ 1516 wa_14011060649(gt, wal); 1517 } 1518 1519 static void 1520 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1521 { 1522 struct intel_engine_cs *engine; 1523 int id; 1524 1525 xehp_init_mcr(gt, wal); 1526 1527 /* Wa_14011060649:dg2 */ 1528 wa_14011060649(gt, wal); 1529 1530 /* 1531 * Although there are per-engine instances of these registers, 1532 * they technically exist outside the engine itself and are not 1533 * impacted by engine resets. Furthermore, they're part of the 1534 * GuC blacklist so trying to treat them as engine workarounds 1535 * will result in GuC initialization failure and a wedged GPU. 1536 */ 1537 for_each_engine(engine, gt, id) { 1538 if (engine->class != VIDEO_DECODE_CLASS) 1539 continue; 1540 1541 /* Wa_16010515920:dg2_g10 */ 1542 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) 1543 wa_write_or(wal, VDBOX_CGCTL3F18(engine->mmio_base), 1544 ALNUNIT_CLKGATE_DIS); 1545 } 1546 1547 if (IS_DG2_G10(gt->i915)) { 1548 /* Wa_22010523718:dg2 */ 1549 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1550 CG3DDISCFEG_CLKGATE_DIS); 1551 1552 /* Wa_14011006942:dg2 */ 1553 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, 1554 DSS_ROUTER_CLKGATE_DIS); 1555 } 1556 1557 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) { 1558 /* Wa_14010948348:dg2_g10 */ 1559 wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS); 1560 1561 /* Wa_14011037102:dg2_g10 */ 1562 wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS); 1563 1564 /* Wa_14011371254:dg2_g10 */ 1565 wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS); 1566 1567 /* Wa_14011431319:dg2_g10 */ 1568 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | 1569 GAMTLBVDBOX7_CLKGATE_DIS | 1570 GAMTLBVDBOX6_CLKGATE_DIS | 1571 GAMTLBVDBOX5_CLKGATE_DIS | 1572 GAMTLBVDBOX4_CLKGATE_DIS | 1573 GAMTLBVDBOX3_CLKGATE_DIS | 1574 GAMTLBVDBOX2_CLKGATE_DIS | 1575 GAMTLBVDBOX1_CLKGATE_DIS | 1576 GAMTLBVDBOX0_CLKGATE_DIS | 1577 GAMTLBKCR_CLKGATE_DIS | 1578 GAMTLBGUC_CLKGATE_DIS | 1579 GAMTLBBLT_CLKGATE_DIS); 1580 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | 1581 GAMTLBGFXA1_CLKGATE_DIS | 1582 GAMTLBCOMPA0_CLKGATE_DIS | 1583 GAMTLBCOMPA1_CLKGATE_DIS | 1584 GAMTLBCOMPB0_CLKGATE_DIS | 1585 GAMTLBCOMPB1_CLKGATE_DIS | 1586 GAMTLBCOMPC0_CLKGATE_DIS | 1587 GAMTLBCOMPC1_CLKGATE_DIS | 1588 GAMTLBCOMPD0_CLKGATE_DIS | 1589 GAMTLBCOMPD1_CLKGATE_DIS | 1590 GAMTLBMERT_CLKGATE_DIS | 1591 GAMTLBVEBOX3_CLKGATE_DIS | 1592 GAMTLBVEBOX2_CLKGATE_DIS | 1593 GAMTLBVEBOX1_CLKGATE_DIS | 1594 GAMTLBVEBOX0_CLKGATE_DIS); 1595 1596 /* Wa_14010569222:dg2_g10 */ 1597 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 1598 GAMEDIA_CLKGATE_DIS); 1599 1600 /* Wa_14011028019:dg2_g10 */ 1601 wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS); 1602 } 1603 1604 /* Wa_14014830051:dg2 */ 1605 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); 1606 1607 /* 1608 * The following are not actually "workarounds" but rather 1609 * recommended tuning settings documented in the bspec's 1610 * performance guide section. 1611 */ 1612 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); 1613 1614 /* Wa_14015795083 */ 1615 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1616 } 1617 1618 static void 1619 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1620 { 1621 pvc_init_mcr(gt, wal); 1622 1623 /* Wa_14015795083 */ 1624 wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); 1625 } 1626 1627 static void 1628 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1629 { 1630 /* FIXME: Actual workarounds will be added in future patch(es) */ 1631 1632 /* 1633 * Unlike older platforms, we no longer setup implicit steering here; 1634 * all MCR accesses are explicitly steered. 1635 */ 1636 debug_dump_steering(gt); 1637 } 1638 1639 static void 1640 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 1641 { 1642 /* FIXME: Actual workarounds will be added in future patch(es) */ 1643 1644 debug_dump_steering(gt); 1645 } 1646 1647 static void 1648 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 1649 { 1650 struct drm_i915_private *i915 = gt->i915; 1651 1652 if (gt->type == GT_MEDIA) { 1653 if (MEDIA_VER(i915) >= 13) 1654 xelpmp_gt_workarounds_init(gt, wal); 1655 else 1656 MISSING_CASE(MEDIA_VER(i915)); 1657 1658 return; 1659 } 1660 1661 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 1662 xelpg_gt_workarounds_init(gt, wal); 1663 else if (IS_PONTEVECCHIO(i915)) 1664 pvc_gt_workarounds_init(gt, wal); 1665 else if (IS_DG2(i915)) 1666 dg2_gt_workarounds_init(gt, wal); 1667 else if (IS_XEHPSDV(i915)) 1668 xehpsdv_gt_workarounds_init(gt, wal); 1669 else if (IS_DG1(i915)) 1670 dg1_gt_workarounds_init(gt, wal); 1671 else if (IS_TIGERLAKE(i915)) 1672 tgl_gt_workarounds_init(gt, wal); 1673 else if (GRAPHICS_VER(i915) == 12) 1674 gen12_gt_workarounds_init(gt, wal); 1675 else if (GRAPHICS_VER(i915) == 11) 1676 icl_gt_workarounds_init(gt, wal); 1677 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 1678 cfl_gt_workarounds_init(gt, wal); 1679 else if (IS_GEMINILAKE(i915)) 1680 glk_gt_workarounds_init(gt, wal); 1681 else if (IS_KABYLAKE(i915)) 1682 kbl_gt_workarounds_init(gt, wal); 1683 else if (IS_BROXTON(i915)) 1684 gen9_gt_workarounds_init(gt, wal); 1685 else if (IS_SKYLAKE(i915)) 1686 skl_gt_workarounds_init(gt, wal); 1687 else if (IS_HASWELL(i915)) 1688 hsw_gt_workarounds_init(gt, wal); 1689 else if (IS_VALLEYVIEW(i915)) 1690 vlv_gt_workarounds_init(gt, wal); 1691 else if (IS_IVYBRIDGE(i915)) 1692 ivb_gt_workarounds_init(gt, wal); 1693 else if (GRAPHICS_VER(i915) == 6) 1694 snb_gt_workarounds_init(gt, wal); 1695 else if (GRAPHICS_VER(i915) == 5) 1696 ilk_gt_workarounds_init(gt, wal); 1697 else if (IS_G4X(i915)) 1698 g4x_gt_workarounds_init(gt, wal); 1699 else if (GRAPHICS_VER(i915) == 4) 1700 gen4_gt_workarounds_init(gt, wal); 1701 else if (GRAPHICS_VER(i915) <= 8) 1702 ; 1703 else 1704 MISSING_CASE(GRAPHICS_VER(i915)); 1705 } 1706 1707 void intel_gt_init_workarounds(struct intel_gt *gt) 1708 { 1709 struct i915_wa_list *wal = >->wa_list; 1710 1711 wa_init_start(wal, gt, "GT", "global"); 1712 gt_init_workarounds(gt, wal); 1713 wa_init_finish(wal); 1714 } 1715 1716 static enum forcewake_domains 1717 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) 1718 { 1719 enum forcewake_domains fw = 0; 1720 struct i915_wa *wa; 1721 unsigned int i; 1722 1723 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1724 fw |= intel_uncore_forcewake_for_reg(uncore, 1725 wa->reg, 1726 FW_REG_READ | 1727 FW_REG_WRITE); 1728 1729 return fw; 1730 } 1731 1732 static bool 1733 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur, 1734 const char *name, const char *from) 1735 { 1736 if ((cur ^ wa->set) & wa->read) { 1737 drm_err(>->i915->drm, 1738 "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n", 1739 name, from, i915_mmio_reg_offset(wa->reg), 1740 cur, cur & wa->read, wa->set & wa->read); 1741 1742 return false; 1743 } 1744 1745 return true; 1746 } 1747 1748 static void wa_list_apply(const struct i915_wa_list *wal) 1749 { 1750 struct intel_gt *gt = wal->gt; 1751 struct intel_uncore *uncore = gt->uncore; 1752 enum forcewake_domains fw; 1753 unsigned long flags; 1754 struct i915_wa *wa; 1755 unsigned int i; 1756 1757 if (!wal->count) 1758 return; 1759 1760 fw = wal_get_fw_for_rmw(uncore, wal); 1761 1762 intel_gt_mcr_lock(gt, &flags); 1763 spin_lock(&uncore->lock); 1764 intel_uncore_forcewake_get__locked(uncore, fw); 1765 1766 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 1767 u32 val, old = 0; 1768 1769 /* open-coded rmw due to steering */ 1770 if (wa->clr) 1771 old = wa->is_mcr ? 1772 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1773 intel_uncore_read_fw(uncore, wa->reg); 1774 val = (old & ~wa->clr) | wa->set; 1775 if (val != old || !wa->clr) { 1776 if (wa->is_mcr) 1777 intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val); 1778 else 1779 intel_uncore_write_fw(uncore, wa->reg, val); 1780 } 1781 1782 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { 1783 u32 val = wa->is_mcr ? 1784 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1785 intel_uncore_read_fw(uncore, wa->reg); 1786 1787 wa_verify(gt, wa, val, wal->name, "application"); 1788 } 1789 } 1790 1791 intel_uncore_forcewake_put__locked(uncore, fw); 1792 spin_unlock(&uncore->lock); 1793 intel_gt_mcr_unlock(gt, flags); 1794 } 1795 1796 void intel_gt_apply_workarounds(struct intel_gt *gt) 1797 { 1798 wa_list_apply(>->wa_list); 1799 } 1800 1801 static bool wa_list_verify(struct intel_gt *gt, 1802 const struct i915_wa_list *wal, 1803 const char *from) 1804 { 1805 struct intel_uncore *uncore = gt->uncore; 1806 struct i915_wa *wa; 1807 enum forcewake_domains fw; 1808 unsigned long flags; 1809 unsigned int i; 1810 bool ok = true; 1811 1812 fw = wal_get_fw_for_rmw(uncore, wal); 1813 1814 intel_gt_mcr_lock(gt, &flags); 1815 spin_lock(&uncore->lock); 1816 intel_uncore_forcewake_get__locked(uncore, fw); 1817 1818 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 1819 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? 1820 intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) : 1821 intel_uncore_read_fw(uncore, wa->reg), 1822 wal->name, from); 1823 1824 intel_uncore_forcewake_put__locked(uncore, fw); 1825 spin_unlock(&uncore->lock); 1826 intel_gt_mcr_unlock(gt, flags); 1827 1828 return ok; 1829 } 1830 1831 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from) 1832 { 1833 return wa_list_verify(gt, >->wa_list, from); 1834 } 1835 1836 __maybe_unused 1837 static bool is_nonpriv_flags_valid(u32 flags) 1838 { 1839 /* Check only valid flag bits are set */ 1840 if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID) 1841 return false; 1842 1843 /* NB: Only 3 out of 4 enum values are valid for access field */ 1844 if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == 1845 RING_FORCE_TO_NONPRIV_ACCESS_INVALID) 1846 return false; 1847 1848 return true; 1849 } 1850 1851 static void 1852 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) 1853 { 1854 struct i915_wa wa = { 1855 .reg = reg 1856 }; 1857 1858 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1859 return; 1860 1861 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1862 return; 1863 1864 wa.reg.reg |= flags; 1865 _wa_add(wal, &wa); 1866 } 1867 1868 static void 1869 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) 1870 { 1871 struct i915_wa wa = { 1872 .mcr_reg = reg, 1873 .is_mcr = 1, 1874 }; 1875 1876 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) 1877 return; 1878 1879 if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags))) 1880 return; 1881 1882 wa.mcr_reg.reg |= flags; 1883 _wa_add(wal, &wa); 1884 } 1885 1886 static void 1887 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) 1888 { 1889 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1890 } 1891 1892 static void 1893 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) 1894 { 1895 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); 1896 } 1897 1898 static void gen9_whitelist_build(struct i915_wa_list *w) 1899 { 1900 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */ 1901 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 1902 1903 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */ 1904 whitelist_reg(w, GEN8_CS_CHICKEN1); 1905 1906 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */ 1907 whitelist_reg(w, GEN8_HDC_CHICKEN1); 1908 1909 /* WaSendPushConstantsFromMMIO:skl,bxt */ 1910 whitelist_reg(w, COMMON_SLICE_CHICKEN2); 1911 } 1912 1913 static void skl_whitelist_build(struct intel_engine_cs *engine) 1914 { 1915 struct i915_wa_list *w = &engine->whitelist; 1916 1917 if (engine->class != RENDER_CLASS) 1918 return; 1919 1920 gen9_whitelist_build(w); 1921 1922 /* WaDisableLSQCROPERFforOCL:skl */ 1923 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1924 } 1925 1926 static void bxt_whitelist_build(struct intel_engine_cs *engine) 1927 { 1928 if (engine->class != RENDER_CLASS) 1929 return; 1930 1931 gen9_whitelist_build(&engine->whitelist); 1932 } 1933 1934 static void kbl_whitelist_build(struct intel_engine_cs *engine) 1935 { 1936 struct i915_wa_list *w = &engine->whitelist; 1937 1938 if (engine->class != RENDER_CLASS) 1939 return; 1940 1941 gen9_whitelist_build(w); 1942 1943 /* WaDisableLSQCROPERFforOCL:kbl */ 1944 whitelist_mcr_reg(w, GEN8_L3SQCREG4); 1945 } 1946 1947 static void glk_whitelist_build(struct intel_engine_cs *engine) 1948 { 1949 struct i915_wa_list *w = &engine->whitelist; 1950 1951 if (engine->class != RENDER_CLASS) 1952 return; 1953 1954 gen9_whitelist_build(w); 1955 1956 /* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */ 1957 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 1958 } 1959 1960 static void cfl_whitelist_build(struct intel_engine_cs *engine) 1961 { 1962 struct i915_wa_list *w = &engine->whitelist; 1963 1964 if (engine->class != RENDER_CLASS) 1965 return; 1966 1967 gen9_whitelist_build(w); 1968 1969 /* 1970 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml 1971 * 1972 * This covers 4 register which are next to one another : 1973 * - PS_INVOCATION_COUNT 1974 * - PS_INVOCATION_COUNT_UDW 1975 * - PS_DEPTH_COUNT 1976 * - PS_DEPTH_COUNT_UDW 1977 */ 1978 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 1979 RING_FORCE_TO_NONPRIV_ACCESS_RD | 1980 RING_FORCE_TO_NONPRIV_RANGE_4); 1981 } 1982 1983 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine) 1984 { 1985 struct i915_wa_list *w = &engine->whitelist; 1986 1987 if (engine->class != RENDER_CLASS) 1988 whitelist_reg_ext(w, 1989 RING_CTX_TIMESTAMP(engine->mmio_base), 1990 RING_FORCE_TO_NONPRIV_ACCESS_RD); 1991 } 1992 1993 static void cml_whitelist_build(struct intel_engine_cs *engine) 1994 { 1995 allow_read_ctx_timestamp(engine); 1996 1997 cfl_whitelist_build(engine); 1998 } 1999 2000 static void icl_whitelist_build(struct intel_engine_cs *engine) 2001 { 2002 struct i915_wa_list *w = &engine->whitelist; 2003 2004 allow_read_ctx_timestamp(engine); 2005 2006 switch (engine->class) { 2007 case RENDER_CLASS: 2008 /* WaAllowUMDToModifyHalfSliceChicken7:icl */ 2009 whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7); 2010 2011 /* WaAllowUMDToModifySamplerMode:icl */ 2012 whitelist_mcr_reg(w, GEN10_SAMPLER_MODE); 2013 2014 /* WaEnableStateCacheRedirectToCS:icl */ 2015 whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); 2016 2017 /* 2018 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl 2019 * 2020 * This covers 4 register which are next to one another : 2021 * - PS_INVOCATION_COUNT 2022 * - PS_INVOCATION_COUNT_UDW 2023 * - PS_DEPTH_COUNT 2024 * - PS_DEPTH_COUNT_UDW 2025 */ 2026 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2027 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2028 RING_FORCE_TO_NONPRIV_RANGE_4); 2029 break; 2030 2031 case VIDEO_DECODE_CLASS: 2032 /* hucStatusRegOffset */ 2033 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base), 2034 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2035 /* hucUKernelHdrInfoRegOffset */ 2036 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base), 2037 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2038 /* hucStatus2RegOffset */ 2039 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), 2040 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2041 break; 2042 2043 default: 2044 break; 2045 } 2046 } 2047 2048 static void tgl_whitelist_build(struct intel_engine_cs *engine) 2049 { 2050 struct i915_wa_list *w = &engine->whitelist; 2051 2052 allow_read_ctx_timestamp(engine); 2053 2054 switch (engine->class) { 2055 case RENDER_CLASS: 2056 /* 2057 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl 2058 * Wa_1408556865:tgl 2059 * 2060 * This covers 4 registers which are next to one another : 2061 * - PS_INVOCATION_COUNT 2062 * - PS_INVOCATION_COUNT_UDW 2063 * - PS_DEPTH_COUNT 2064 * - PS_DEPTH_COUNT_UDW 2065 */ 2066 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2067 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2068 RING_FORCE_TO_NONPRIV_RANGE_4); 2069 2070 /* 2071 * Wa_1808121037:tgl 2072 * Wa_14012131227:dg1 2073 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p 2074 */ 2075 whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); 2076 2077 /* Wa_1806527549:tgl */ 2078 whitelist_reg(w, HIZ_CHICKEN); 2079 break; 2080 default: 2081 break; 2082 } 2083 } 2084 2085 static void dg1_whitelist_build(struct intel_engine_cs *engine) 2086 { 2087 struct i915_wa_list *w = &engine->whitelist; 2088 2089 tgl_whitelist_build(engine); 2090 2091 /* GEN:BUG:1409280441:dg1 */ 2092 if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) && 2093 (engine->class == RENDER_CLASS || 2094 engine->class == COPY_ENGINE_CLASS)) 2095 whitelist_reg_ext(w, RING_ID(engine->mmio_base), 2096 RING_FORCE_TO_NONPRIV_ACCESS_RD); 2097 } 2098 2099 static void xehpsdv_whitelist_build(struct intel_engine_cs *engine) 2100 { 2101 allow_read_ctx_timestamp(engine); 2102 } 2103 2104 static void dg2_whitelist_build(struct intel_engine_cs *engine) 2105 { 2106 struct i915_wa_list *w = &engine->whitelist; 2107 2108 allow_read_ctx_timestamp(engine); 2109 2110 switch (engine->class) { 2111 case RENDER_CLASS: 2112 /* 2113 * Wa_1507100340:dg2_g10 2114 * 2115 * This covers 4 registers which are next to one another : 2116 * - PS_INVOCATION_COUNT 2117 * - PS_INVOCATION_COUNT_UDW 2118 * - PS_DEPTH_COUNT 2119 * - PS_DEPTH_COUNT_UDW 2120 */ 2121 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2122 whitelist_reg_ext(w, PS_INVOCATION_COUNT, 2123 RING_FORCE_TO_NONPRIV_ACCESS_RD | 2124 RING_FORCE_TO_NONPRIV_RANGE_4); 2125 2126 break; 2127 case COMPUTE_CLASS: 2128 /* Wa_16011157294:dg2_g10 */ 2129 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) 2130 whitelist_reg(w, GEN9_CTX_PREEMPT_REG); 2131 break; 2132 default: 2133 break; 2134 } 2135 } 2136 2137 static void blacklist_trtt(struct intel_engine_cs *engine) 2138 { 2139 struct i915_wa_list *w = &engine->whitelist; 2140 2141 /* 2142 * Prevent read/write access to [0x4400, 0x4600) which covers 2143 * the TRTT range across all engines. Note that normally userspace 2144 * cannot access the other engines' trtt control, but for simplicity 2145 * we cover the entire range on each engine. 2146 */ 2147 whitelist_reg_ext(w, _MMIO(0x4400), 2148 RING_FORCE_TO_NONPRIV_DENY | 2149 RING_FORCE_TO_NONPRIV_RANGE_64); 2150 whitelist_reg_ext(w, _MMIO(0x4500), 2151 RING_FORCE_TO_NONPRIV_DENY | 2152 RING_FORCE_TO_NONPRIV_RANGE_64); 2153 } 2154 2155 static void pvc_whitelist_build(struct intel_engine_cs *engine) 2156 { 2157 allow_read_ctx_timestamp(engine); 2158 2159 /* Wa_16014440446:pvc */ 2160 blacklist_trtt(engine); 2161 } 2162 2163 void intel_engine_init_whitelist(struct intel_engine_cs *engine) 2164 { 2165 struct drm_i915_private *i915 = engine->i915; 2166 struct i915_wa_list *w = &engine->whitelist; 2167 2168 wa_init_start(w, engine->gt, "whitelist", engine->name); 2169 2170 if (IS_PONTEVECCHIO(i915)) 2171 pvc_whitelist_build(engine); 2172 else if (IS_DG2(i915)) 2173 dg2_whitelist_build(engine); 2174 else if (IS_XEHPSDV(i915)) 2175 xehpsdv_whitelist_build(engine); 2176 else if (IS_DG1(i915)) 2177 dg1_whitelist_build(engine); 2178 else if (GRAPHICS_VER(i915) == 12) 2179 tgl_whitelist_build(engine); 2180 else if (GRAPHICS_VER(i915) == 11) 2181 icl_whitelist_build(engine); 2182 else if (IS_COMETLAKE(i915)) 2183 cml_whitelist_build(engine); 2184 else if (IS_COFFEELAKE(i915)) 2185 cfl_whitelist_build(engine); 2186 else if (IS_GEMINILAKE(i915)) 2187 glk_whitelist_build(engine); 2188 else if (IS_KABYLAKE(i915)) 2189 kbl_whitelist_build(engine); 2190 else if (IS_BROXTON(i915)) 2191 bxt_whitelist_build(engine); 2192 else if (IS_SKYLAKE(i915)) 2193 skl_whitelist_build(engine); 2194 else if (GRAPHICS_VER(i915) <= 8) 2195 ; 2196 else 2197 MISSING_CASE(GRAPHICS_VER(i915)); 2198 2199 wa_init_finish(w); 2200 } 2201 2202 void intel_engine_apply_whitelist(struct intel_engine_cs *engine) 2203 { 2204 const struct i915_wa_list *wal = &engine->whitelist; 2205 struct intel_uncore *uncore = engine->uncore; 2206 const u32 base = engine->mmio_base; 2207 struct i915_wa *wa; 2208 unsigned int i; 2209 2210 if (!wal->count) 2211 return; 2212 2213 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) 2214 intel_uncore_write(uncore, 2215 RING_FORCE_TO_NONPRIV(base, i), 2216 i915_mmio_reg_offset(wa->reg)); 2217 2218 /* And clear the rest just in case of garbage */ 2219 for (; i < RING_MAX_NONPRIV_SLOTS; i++) 2220 intel_uncore_write(uncore, 2221 RING_FORCE_TO_NONPRIV(base, i), 2222 i915_mmio_reg_offset(RING_NOPID(base))); 2223 } 2224 2225 /* 2226 * engine_fake_wa_init(), a place holder to program the registers 2227 * which are not part of an official workaround defined by the 2228 * hardware team. 2229 * Adding programming of those register inside workaround will 2230 * allow utilizing wa framework to proper application and verification. 2231 */ 2232 static void 2233 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2234 { 2235 u8 mocs_w, mocs_r; 2236 2237 /* 2238 * RING_CMD_CCTL specifies the default MOCS entry that will be used 2239 * by the command streamer when executing commands that don't have 2240 * a way to explicitly specify a MOCS setting. The default should 2241 * usually reference whichever MOCS entry corresponds to uncached 2242 * behavior, although use of a WB cached entry is recommended by the 2243 * spec in certain circumstances on specific platforms. 2244 */ 2245 if (GRAPHICS_VER(engine->i915) >= 12) { 2246 mocs_r = engine->gt->mocs.uc_index; 2247 mocs_w = engine->gt->mocs.uc_index; 2248 2249 if (HAS_L3_CCS_READ(engine->i915) && 2250 engine->class == COMPUTE_CLASS) { 2251 mocs_r = engine->gt->mocs.wb_index; 2252 2253 /* 2254 * Even on the few platforms where MOCS 0 is a 2255 * legitimate table entry, it's never the correct 2256 * setting to use here; we can assume the MOCS init 2257 * just forgot to initialize wb_index. 2258 */ 2259 drm_WARN_ON(&engine->i915->drm, mocs_r == 0); 2260 } 2261 2262 wa_masked_field_set(wal, 2263 RING_CMD_CCTL(engine->mmio_base), 2264 CMD_CCTL_MOCS_MASK, 2265 CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r)); 2266 } 2267 } 2268 2269 static bool needs_wa_1308578152(struct intel_engine_cs *engine) 2270 { 2271 return intel_sseu_find_first_xehp_dss(&engine->gt->info.sseu, 0, 0) >= 2272 GEN_DSS_PER_GSLICE; 2273 } 2274 2275 static void 2276 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2277 { 2278 struct drm_i915_private *i915 = engine->i915; 2279 2280 if (IS_DG2(i915)) { 2281 /* Wa_1509235366:dg2 */ 2282 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2283 GLOBAL_INVALIDATION_MODE); 2284 } 2285 2286 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2287 /* Wa_14013392000:dg2_g11 */ 2288 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE); 2289 } 2290 2291 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2292 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2293 /* Wa_1509727124:dg2 */ 2294 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2295 SC_DISABLE_POWER_OPTIMIZATION_EBB); 2296 } 2297 2298 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || 2299 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { 2300 /* Wa_14012419201:dg2 */ 2301 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, 2302 GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX); 2303 } 2304 2305 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2306 IS_DG2_G11(i915)) { 2307 /* 2308 * Wa_22012826095:dg2 2309 * Wa_22013059131:dg2 2310 */ 2311 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2312 MAXREQS_PER_BANK, 2313 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2314 2315 /* Wa_22013059131:dg2 */ 2316 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2317 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2318 } 2319 2320 /* Wa_1308578152:dg2_g10 when first gslice is fused off */ 2321 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) && 2322 needs_wa_1308578152(engine)) { 2323 wa_masked_dis(wal, GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON, 2324 GEN12_REPLAY_MODE_GRANULARITY); 2325 } 2326 2327 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || 2328 IS_DG2_G11(i915) || IS_DG2_G12(i915)) { 2329 /* Wa_22013037850:dg2 */ 2330 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2331 DISABLE_128B_EVICTION_COMMAND_UDW); 2332 2333 /* Wa_22012856258:dg2 */ 2334 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2335 GEN12_DISABLE_READ_SUPPRESSION); 2336 2337 /* 2338 * Wa_22010960976:dg2 2339 * Wa_14013347512:dg2 2340 */ 2341 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, 2342 LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK); 2343 } 2344 2345 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2346 /* 2347 * Wa_1608949956:dg2_g10 2348 * Wa_14010198302:dg2_g10 2349 */ 2350 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, 2351 MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE); 2352 2353 /* 2354 * Wa_14010918519:dg2_g10 2355 * 2356 * LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping, 2357 * so ignoring verification. 2358 */ 2359 wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0, 2360 FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE, 2361 0, false); 2362 } 2363 2364 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) { 2365 /* Wa_22010430635:dg2 */ 2366 wa_mcr_masked_en(wal, 2367 GEN9_ROW_CHICKEN4, 2368 GEN12_DISABLE_GRF_CLEAR); 2369 2370 /* Wa_14010648519:dg2 */ 2371 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2372 } 2373 2374 /* Wa_14013202645:dg2 */ 2375 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) || 2376 IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) 2377 wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY); 2378 2379 /* Wa_22012532006:dg2 */ 2380 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) || 2381 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) 2382 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, 2383 DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); 2384 2385 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) { 2386 /* Wa_14010680813:dg2_g10 */ 2387 wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS | 2388 EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS); 2389 } 2390 2391 if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) || 2392 IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) { 2393 /* Wa_14012362059:dg2 */ 2394 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2395 } 2396 2397 if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) || 2398 IS_DG2_G10(i915)) { 2399 /* Wa_22014600077:dg2 */ 2400 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2401 _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH), 2402 0 /* Wa_14012342262 write-only reg, so skip verification */, 2403 true); 2404 } 2405 2406 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2407 IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2408 /* 2409 * Wa_1607138336:tgl[a0],dg1[a0] 2410 * Wa_1607063988:tgl[a0],dg1[a0] 2411 */ 2412 wa_write_or(wal, 2413 GEN9_CTX_PREEMPT_REG, 2414 GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); 2415 } 2416 2417 if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) { 2418 /* 2419 * Wa_1606679103:tgl 2420 * (see also Wa_1606682166:icl) 2421 */ 2422 wa_write_or(wal, 2423 GEN7_SARCHKMD, 2424 GEN7_DISABLE_SAMPLER_PREFETCH); 2425 } 2426 2427 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) || 2428 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2429 /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */ 2430 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); 2431 2432 /* 2433 * Wa_1407928979:tgl A* 2434 * Wa_18011464164:tgl[B0+],dg1[B0+] 2435 * Wa_22010931296:tgl[B0+],dg1[B0+] 2436 * Wa_14010919138:rkl,dg1,adl-s,adl-p 2437 */ 2438 wa_write_or(wal, GEN7_FF_THREAD_MODE, 2439 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2440 } 2441 2442 if (IS_ALDERLAKE_P(i915) || IS_DG2(i915) || IS_ALDERLAKE_S(i915) || 2443 IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2444 /* 2445 * Wa_1606700617:tgl,dg1,adl-p 2446 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p 2447 * Wa_14010826681:tgl,dg1,rkl,adl-p 2448 * Wa_18019627453:dg2 2449 */ 2450 wa_masked_en(wal, 2451 GEN9_CS_DEBUG_MODE1, 2452 FF_DOP_CLOCK_GATE_DISABLE); 2453 } 2454 2455 if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || 2456 IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2457 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { 2458 /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */ 2459 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, 2460 GEN12_PUSH_CONST_DEREF_HOLD_DIS); 2461 2462 /* 2463 * Wa_1409085225:tgl 2464 * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p 2465 */ 2466 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); 2467 } 2468 2469 if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) || 2470 IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) { 2471 /* 2472 * Wa_1607030317:tgl 2473 * Wa_1607186500:tgl 2474 * Wa_1607297627:tgl,rkl,dg1[a0],adlp 2475 * 2476 * On TGL and RKL there are multiple entries for this WA in the 2477 * BSpec; some indicate this is an A0-only WA, others indicate 2478 * it applies to all steppings so we trust the "all steppings." 2479 * For DG1 this only applies to A0. 2480 */ 2481 wa_masked_en(wal, 2482 RING_PSMI_CTL(RENDER_RING_BASE), 2483 GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | 2484 GEN8_RC_SEMA_IDLE_MSG_DISABLE); 2485 } 2486 2487 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || 2488 IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) { 2489 /* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */ 2490 wa_mcr_masked_en(wal, 2491 GEN10_SAMPLER_MODE, 2492 ENABLE_SMALLPL); 2493 } 2494 2495 if (GRAPHICS_VER(i915) == 11) { 2496 /* This is not an Wa. Enable for better image quality */ 2497 wa_masked_en(wal, 2498 _3D_CHICKEN3, 2499 _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE); 2500 2501 /* 2502 * Wa_1405543622:icl 2503 * Formerly known as WaGAPZPriorityScheme 2504 */ 2505 wa_write_or(wal, 2506 GEN8_GARBCNTL, 2507 GEN11_ARBITRATION_PRIO_ORDER_MASK); 2508 2509 /* 2510 * Wa_1604223664:icl 2511 * Formerly known as WaL3BankAddressHashing 2512 */ 2513 wa_write_clr_set(wal, 2514 GEN8_GARBCNTL, 2515 GEN11_HASH_CTRL_EXCL_MASK, 2516 GEN11_HASH_CTRL_EXCL_BIT0); 2517 wa_write_clr_set(wal, 2518 GEN11_GLBLINVL, 2519 GEN11_BANK_HASH_ADDR_EXCL_MASK, 2520 GEN11_BANK_HASH_ADDR_EXCL_BIT0); 2521 2522 /* 2523 * Wa_1405733216:icl 2524 * Formerly known as WaDisableCleanEvicts 2525 */ 2526 wa_mcr_write_or(wal, 2527 GEN8_L3SQCREG4, 2528 GEN11_LQSC_CLEAN_EVICT_DISABLE); 2529 2530 /* Wa_1606682166:icl */ 2531 wa_write_or(wal, 2532 GEN7_SARCHKMD, 2533 GEN7_DISABLE_SAMPLER_PREFETCH); 2534 2535 /* Wa_1409178092:icl */ 2536 wa_mcr_write_clr_set(wal, 2537 GEN11_SCRATCH2, 2538 GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 2539 0); 2540 2541 /* WaEnable32PlaneMode:icl */ 2542 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, 2543 GEN11_ENABLE_32_PLANE_MODE); 2544 2545 /* 2546 * Wa_1408615072:icl,ehl (vsunit) 2547 * Wa_1407596294:icl,ehl (hsunit) 2548 */ 2549 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, 2550 VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 2551 2552 /* 2553 * Wa_1408767742:icl[a2..forever],ehl[all] 2554 * Wa_1605460711:icl[a0..c0] 2555 */ 2556 wa_write_or(wal, 2557 GEN7_FF_THREAD_MODE, 2558 GEN12_FF_TESSELATION_DOP_GATE_DISABLE); 2559 2560 /* Wa_22010271021 */ 2561 wa_masked_en(wal, 2562 GEN9_CS_DEBUG_MODE1, 2563 FF_DOP_CLOCK_GATE_DISABLE); 2564 } 2565 2566 /* 2567 * Intel platforms that support fine-grained preemption (i.e., gen9 and 2568 * beyond) allow the kernel-mode driver to choose between two different 2569 * options for controlling preemption granularity and behavior. 2570 * 2571 * Option 1 (hardware default): 2572 * Preemption settings are controlled in a global manner via 2573 * kernel-only register CS_DEBUG_MODE1 (0x20EC). Any granularity 2574 * and settings chosen by the kernel-mode driver will apply to all 2575 * userspace clients. 2576 * 2577 * Option 2: 2578 * Preemption settings are controlled on a per-context basis via 2579 * register CS_CHICKEN1 (0x2580). CS_CHICKEN1 is saved/restored on 2580 * context switch and is writable by userspace (e.g., via 2581 * MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer) 2582 * which allows different userspace drivers/clients to select 2583 * different settings, or to change those settings on the fly in 2584 * response to runtime needs. This option was known by name 2585 * "FtrPerCtxtPreemptionGranularityControl" at one time, although 2586 * that name is somewhat misleading as other non-granularity 2587 * preemption settings are also impacted by this decision. 2588 * 2589 * On Linux, our policy has always been to let userspace drivers 2590 * control preemption granularity/settings (Option 2). This was 2591 * originally mandatory on gen9 to prevent ABI breakage (old gen9 2592 * userspace developed before object-level preemption was enabled would 2593 * not behave well if i915 were to go with Option 1 and enable that 2594 * preemption in a global manner). On gen9 each context would have 2595 * object-level preemption disabled by default (see 2596 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but 2597 * userspace drivers could opt-in to object-level preemption as they 2598 * saw fit. For post-gen9 platforms, we continue to utilize Option 2; 2599 * even though it is no longer necessary for ABI compatibility when 2600 * enabling a new platform, it does ensure that userspace will be able 2601 * to implement any workarounds that show up requiring temporary 2602 * adjustments to preemption behavior at runtime. 2603 * 2604 * Notes/Workarounds: 2605 * - Wa_14015141709: On DG2 and early steppings of MTL, 2606 * CS_CHICKEN1[0] does not disable object-level preemption as 2607 * it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been 2608 * using Option 1). Effectively this means userspace is unable 2609 * to disable object-level preemption on these platforms/steppings 2610 * despite the setting here. 2611 * 2612 * - Wa_16013994831: May require that userspace program 2613 * CS_CHICKEN1[10] when certain runtime conditions are true. 2614 * Userspace requires Option 2 to be in effect for their update of 2615 * CS_CHICKEN1[10] to be effective. 2616 * 2617 * Other workarounds may appear in the future that will also require 2618 * Option 2 behavior to allow proper userspace implementation. 2619 */ 2620 if (GRAPHICS_VER(i915) >= 9) 2621 wa_masked_en(wal, 2622 GEN7_FF_SLICE_CS_CHICKEN1, 2623 GEN9_FFSC_PERCTX_PREEMPT_CTRL); 2624 2625 if (IS_SKYLAKE(i915) || 2626 IS_KABYLAKE(i915) || 2627 IS_COFFEELAKE(i915) || 2628 IS_COMETLAKE(i915)) { 2629 /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ 2630 wa_write_or(wal, 2631 GEN8_GARBCNTL, 2632 GEN9_GAPS_TSV_CREDIT_DISABLE); 2633 } 2634 2635 if (IS_BROXTON(i915)) { 2636 /* WaDisablePooledEuLoadBalancingFix:bxt */ 2637 wa_masked_en(wal, 2638 FF_SLICE_CS_CHICKEN2, 2639 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 2640 } 2641 2642 if (GRAPHICS_VER(i915) == 9) { 2643 /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */ 2644 wa_masked_en(wal, 2645 GEN9_CSFE_CHICKEN1_RCS, 2646 GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE); 2647 2648 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */ 2649 wa_mcr_write_or(wal, 2650 BDW_SCRATCH1, 2651 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 2652 2653 /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ 2654 if (IS_GEN9_LP(i915)) 2655 wa_mcr_write_clr_set(wal, 2656 GEN8_L3SQCREG1, 2657 L3_PRIO_CREDITS_MASK, 2658 L3_GENERAL_PRIO_CREDITS(62) | 2659 L3_HIGH_PRIO_CREDITS(2)); 2660 2661 /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */ 2662 wa_mcr_write_or(wal, 2663 GEN8_L3SQCREG4, 2664 GEN8_LQSC_FLUSH_COHERENT_LINES); 2665 2666 /* Disable atomics in L3 to prevent unrecoverable hangs */ 2667 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, 2668 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2669 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, 2670 GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0); 2671 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, 2672 EVICTION_PERF_FIX_ENABLE, 0); 2673 } 2674 2675 if (IS_HASWELL(i915)) { 2676 /* WaSampleCChickenBitEnable:hsw */ 2677 wa_masked_en(wal, 2678 HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); 2679 2680 wa_masked_dis(wal, 2681 CACHE_MODE_0_GEN7, 2682 /* enable HiZ Raw Stall Optimization */ 2683 HIZ_RAW_STALL_OPT_DISABLE); 2684 } 2685 2686 if (IS_VALLEYVIEW(i915)) { 2687 /* WaDisableEarlyCull:vlv */ 2688 wa_masked_en(wal, 2689 _3D_CHICKEN3, 2690 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2691 2692 /* 2693 * WaVSThreadDispatchOverride:ivb,vlv 2694 * 2695 * This actually overrides the dispatch 2696 * mode for all thread types. 2697 */ 2698 wa_write_clr_set(wal, 2699 GEN7_FF_THREAD_MODE, 2700 GEN7_FF_SCHED_MASK, 2701 GEN7_FF_TS_SCHED_HW | 2702 GEN7_FF_VS_SCHED_HW | 2703 GEN7_FF_DS_SCHED_HW); 2704 2705 /* WaPsdDispatchEnable:vlv */ 2706 /* WaDisablePSDDualDispatchEnable:vlv */ 2707 wa_masked_en(wal, 2708 GEN7_HALF_SLICE_CHICKEN1, 2709 GEN7_MAX_PS_THREAD_DEP | 2710 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2711 } 2712 2713 if (IS_IVYBRIDGE(i915)) { 2714 /* WaDisableEarlyCull:ivb */ 2715 wa_masked_en(wal, 2716 _3D_CHICKEN3, 2717 _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); 2718 2719 if (0) { /* causes HiZ corruption on ivb:gt1 */ 2720 /* enable HiZ Raw Stall Optimization */ 2721 wa_masked_dis(wal, 2722 CACHE_MODE_0_GEN7, 2723 HIZ_RAW_STALL_OPT_DISABLE); 2724 } 2725 2726 /* 2727 * WaVSThreadDispatchOverride:ivb,vlv 2728 * 2729 * This actually overrides the dispatch 2730 * mode for all thread types. 2731 */ 2732 wa_write_clr_set(wal, 2733 GEN7_FF_THREAD_MODE, 2734 GEN7_FF_SCHED_MASK, 2735 GEN7_FF_TS_SCHED_HW | 2736 GEN7_FF_VS_SCHED_HW | 2737 GEN7_FF_DS_SCHED_HW); 2738 2739 /* WaDisablePSDDualDispatchEnable:ivb */ 2740 if (IS_IVB_GT1(i915)) 2741 wa_masked_en(wal, 2742 GEN7_HALF_SLICE_CHICKEN1, 2743 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2744 } 2745 2746 if (GRAPHICS_VER(i915) == 7) { 2747 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 2748 wa_masked_en(wal, 2749 RING_MODE_GEN7(RENDER_RING_BASE), 2750 GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE); 2751 2752 /* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */ 2753 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); 2754 2755 /* 2756 * BSpec says this must be set, even though 2757 * WaDisable4x2SubspanOptimization:ivb,hsw 2758 * WaDisable4x2SubspanOptimization isn't listed for VLV. 2759 */ 2760 wa_masked_en(wal, 2761 CACHE_MODE_1, 2762 PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); 2763 2764 /* 2765 * BSpec recommends 8x4 when MSAA is used, 2766 * however in practice 16x4 seems fastest. 2767 * 2768 * Note that PS/WM thread counts depend on the WIZ hashing 2769 * disable bit, which we don't touch here, but it's good 2770 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2771 */ 2772 wa_masked_field_set(wal, 2773 GEN7_GT_MODE, 2774 GEN6_WIZ_HASHING_MASK, 2775 GEN6_WIZ_HASHING_16x4); 2776 } 2777 2778 if (IS_GRAPHICS_VER(i915, 6, 7)) 2779 /* 2780 * We need to disable the AsyncFlip performance optimisations in 2781 * order to use MI_WAIT_FOR_EVENT within the CS. It should 2782 * already be programmed to '1' on all products. 2783 * 2784 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 2785 */ 2786 wa_masked_en(wal, 2787 RING_MI_MODE(RENDER_RING_BASE), 2788 ASYNC_FLIP_PERF_DISABLE); 2789 2790 if (GRAPHICS_VER(i915) == 6) { 2791 /* 2792 * Required for the hardware to program scanline values for 2793 * waiting 2794 * WaEnableFlushTlbInvalidationMode:snb 2795 */ 2796 wa_masked_en(wal, 2797 GFX_MODE, 2798 GFX_TLB_INVALIDATE_EXPLICIT); 2799 2800 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 2801 wa_masked_en(wal, 2802 _3D_CHICKEN, 2803 _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); 2804 2805 wa_masked_en(wal, 2806 _3D_CHICKEN3, 2807 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 2808 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | 2809 /* 2810 * Bspec says: 2811 * "This bit must be set if 3DSTATE_CLIP clip mode is set 2812 * to normal and 3DSTATE_SF number of SF output attributes 2813 * is more than 16." 2814 */ 2815 _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); 2816 2817 /* 2818 * BSpec recommends 8x4 when MSAA is used, 2819 * however in practice 16x4 seems fastest. 2820 * 2821 * Note that PS/WM thread counts depend on the WIZ hashing 2822 * disable bit, which we don't touch here, but it's good 2823 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 2824 */ 2825 wa_masked_field_set(wal, 2826 GEN6_GT_MODE, 2827 GEN6_WIZ_HASHING_MASK, 2828 GEN6_WIZ_HASHING_16x4); 2829 2830 /* WaDisable_RenderCache_OperationalFlush:snb */ 2831 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); 2832 2833 /* 2834 * From the Sandybridge PRM, volume 1 part 3, page 24: 2835 * "If this bit is set, STCunit will have LRA as replacement 2836 * policy. [...] This bit must be reset. LRA replacement 2837 * policy is not supported." 2838 */ 2839 wa_masked_dis(wal, 2840 CACHE_MODE_0, 2841 CM0_STC_EVICT_DISABLE_LRA_SNB); 2842 } 2843 2844 if (IS_GRAPHICS_VER(i915, 4, 6)) 2845 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 2846 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), 2847 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), 2848 /* XXX bit doesn't stick on Broadwater */ 2849 IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true); 2850 2851 if (GRAPHICS_VER(i915) == 4) 2852 /* 2853 * Disable CONSTANT_BUFFER before it is loaded from the context 2854 * image. For as it is loaded, it is executed and the stored 2855 * address may no longer be valid, leading to a GPU hang. 2856 * 2857 * This imposes the requirement that userspace reload their 2858 * CONSTANT_BUFFER on every batch, fortunately a requirement 2859 * they are already accustomed to from before contexts were 2860 * enabled. 2861 */ 2862 wa_add(wal, ECOSKPD(RENDER_RING_BASE), 2863 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), 2864 0 /* XXX bit doesn't stick on Broadwater */, 2865 true); 2866 } 2867 2868 static void 2869 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2870 { 2871 struct drm_i915_private *i915 = engine->i915; 2872 2873 /* WaKBLVECSSemaphoreWaitPoll:kbl */ 2874 if (IS_KBL_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) { 2875 wa_write(wal, 2876 RING_SEMA_WAIT_POLL(engine->mmio_base), 2877 1); 2878 } 2879 } 2880 2881 static void 2882 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2883 { 2884 if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) { 2885 /* Wa_14014999345:pvc */ 2886 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); 2887 } 2888 } 2889 2890 /* 2891 * The bspec performance guide has recommended MMIO tuning settings. These 2892 * aren't truly "workarounds" but we want to program them with the same 2893 * workaround infrastructure to ensure that they're automatically added to 2894 * the GuC save/restore lists, re-applied at the right times, and checked for 2895 * any conflicting programming requested by real workarounds. 2896 * 2897 * Programming settings should be added here only if their registers are not 2898 * part of an engine's register state context. If a register is part of a 2899 * context, then any tuning settings should be programmed in an appropriate 2900 * function invoked by __intel_engine_init_ctx_wa(). 2901 */ 2902 static void 2903 add_render_compute_tuning_settings(struct drm_i915_private *i915, 2904 struct i915_wa_list *wal) 2905 { 2906 if (IS_PONTEVECCHIO(i915)) { 2907 wa_write(wal, XEHPC_L3SCRUB, 2908 SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); 2909 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); 2910 } 2911 2912 if (IS_DG2(i915)) { 2913 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); 2914 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); 2915 } 2916 2917 /* 2918 * This tuning setting proves beneficial only on ATS-M designs; the 2919 * default "age based" setting is optimal on regular DG2 and other 2920 * platforms. 2921 */ 2922 if (INTEL_INFO(i915)->tuning_thread_rr_after_dep) 2923 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, 2924 THREAD_EX_ARB_MODE_RR_AFTER_DEP); 2925 2926 if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) 2927 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); 2928 } 2929 2930 /* 2931 * The workarounds in this function apply to shared registers in 2932 * the general render reset domain that aren't tied to a 2933 * specific engine. Since all render+compute engines get reset 2934 * together, and the contents of these registers are lost during 2935 * the shared render domain reset, we'll define such workarounds 2936 * here and then add them to just a single RCS or CCS engine's 2937 * workaround list (whichever engine has the XXXX flag). 2938 */ 2939 static void 2940 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2941 { 2942 struct drm_i915_private *i915 = engine->i915; 2943 2944 add_render_compute_tuning_settings(i915, wal); 2945 2946 if (IS_PONTEVECCHIO(i915)) { 2947 /* Wa_16016694945 */ 2948 wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); 2949 } 2950 2951 if (IS_XEHPSDV(i915)) { 2952 /* Wa_1409954639 */ 2953 wa_mcr_masked_en(wal, 2954 GEN8_ROW_CHICKEN, 2955 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2956 2957 /* Wa_1607196519 */ 2958 wa_mcr_masked_en(wal, 2959 GEN9_ROW_CHICKEN4, 2960 GEN12_DISABLE_GRF_CLEAR); 2961 2962 /* Wa_14010670810:xehpsdv */ 2963 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); 2964 2965 /* Wa_14010449647:xehpsdv */ 2966 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2967 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2968 2969 /* Wa_18011725039:xehpsdv */ 2970 if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { 2971 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); 2972 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); 2973 } 2974 2975 /* Wa_14012362059:xehpsdv */ 2976 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); 2977 2978 /* Wa_14014368820:xehpsdv */ 2979 wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | 2980 GLOBAL_INVALIDATION_MODE); 2981 } 2982 2983 if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { 2984 /* Wa_14015227452:dg2,pvc */ 2985 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2986 2987 /* Wa_22014226127:dg2,pvc */ 2988 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2989 2990 /* Wa_16015675438:dg2,pvc */ 2991 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2992 2993 /* Wa_18018781329:dg2,pvc */ 2994 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); 2995 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); 2996 wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB); 2997 wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB); 2998 } 2999 3000 if (IS_DG2(i915)) { 3001 /* 3002 * Wa_16011620976:dg2_g11 3003 * Wa_22015475538:dg2 3004 */ 3005 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 3006 3007 /* Wa_18017747507:dg2 */ 3008 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 3009 } 3010 3011 if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) || IS_DG2_G11(i915)) 3012 /* 3013 * Wa_22012654132 3014 * 3015 * Note that register 0xE420 is write-only and cannot be read 3016 * back for verification on DG2 (due to Wa_14012342262), so 3017 * we need to explicitly skip the readback. 3018 */ 3019 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 3020 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 3021 0 /* write-only, so skip validation */, 3022 true); 3023 } 3024 3025 static void 3026 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) 3027 { 3028 if (GRAPHICS_VER(engine->i915) < 4) 3029 return; 3030 3031 engine_fake_wa_init(engine, wal); 3032 3033 /* 3034 * These are common workarounds that just need to applied 3035 * to a single RCS/CCS engine's workaround list since 3036 * they're reset as part of the general render domain reset. 3037 */ 3038 if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) 3039 general_render_compute_wa_init(engine, wal); 3040 3041 if (engine->class == COMPUTE_CLASS) 3042 ccs_engine_wa_init(engine, wal); 3043 else if (engine->class == RENDER_CLASS) 3044 rcs_engine_wa_init(engine, wal); 3045 else 3046 xcs_engine_wa_init(engine, wal); 3047 } 3048 3049 void intel_engine_init_workarounds(struct intel_engine_cs *engine) 3050 { 3051 struct i915_wa_list *wal = &engine->wa_list; 3052 3053 wa_init_start(wal, engine->gt, "engine", engine->name); 3054 engine_init_workarounds(engine, wal); 3055 wa_init_finish(wal); 3056 } 3057 3058 void intel_engine_apply_workarounds(struct intel_engine_cs *engine) 3059 { 3060 wa_list_apply(&engine->wa_list); 3061 } 3062 3063 static const struct i915_range mcr_ranges_gen8[] = { 3064 { .start = 0x5500, .end = 0x55ff }, 3065 { .start = 0x7000, .end = 0x7fff }, 3066 { .start = 0x9400, .end = 0x97ff }, 3067 { .start = 0xb000, .end = 0xb3ff }, 3068 { .start = 0xe000, .end = 0xe7ff }, 3069 {}, 3070 }; 3071 3072 static const struct i915_range mcr_ranges_gen12[] = { 3073 { .start = 0x8150, .end = 0x815f }, 3074 { .start = 0x9520, .end = 0x955f }, 3075 { .start = 0xb100, .end = 0xb3ff }, 3076 { .start = 0xde80, .end = 0xe8ff }, 3077 { .start = 0x24a00, .end = 0x24a7f }, 3078 {}, 3079 }; 3080 3081 static const struct i915_range mcr_ranges_xehp[] = { 3082 { .start = 0x4000, .end = 0x4aff }, 3083 { .start = 0x5200, .end = 0x52ff }, 3084 { .start = 0x5400, .end = 0x7fff }, 3085 { .start = 0x8140, .end = 0x815f }, 3086 { .start = 0x8c80, .end = 0x8dff }, 3087 { .start = 0x94d0, .end = 0x955f }, 3088 { .start = 0x9680, .end = 0x96ff }, 3089 { .start = 0xb000, .end = 0xb3ff }, 3090 { .start = 0xc800, .end = 0xcfff }, 3091 { .start = 0xd800, .end = 0xd8ff }, 3092 { .start = 0xdc00, .end = 0xffff }, 3093 { .start = 0x17000, .end = 0x17fff }, 3094 { .start = 0x24a00, .end = 0x24a7f }, 3095 {}, 3096 }; 3097 3098 static bool mcr_range(struct drm_i915_private *i915, u32 offset) 3099 { 3100 const struct i915_range *mcr_ranges; 3101 int i; 3102 3103 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 3104 mcr_ranges = mcr_ranges_xehp; 3105 else if (GRAPHICS_VER(i915) >= 12) 3106 mcr_ranges = mcr_ranges_gen12; 3107 else if (GRAPHICS_VER(i915) >= 8) 3108 mcr_ranges = mcr_ranges_gen8; 3109 else 3110 return false; 3111 3112 /* 3113 * Registers in these ranges are affected by the MCR selector 3114 * which only controls CPU initiated MMIO. Routing does not 3115 * work for CS access so we cannot verify them on this path. 3116 */ 3117 for (i = 0; mcr_ranges[i].start; i++) 3118 if (offset >= mcr_ranges[i].start && 3119 offset <= mcr_ranges[i].end) 3120 return true; 3121 3122 return false; 3123 } 3124 3125 static int 3126 wa_list_srm(struct i915_request *rq, 3127 const struct i915_wa_list *wal, 3128 struct i915_vma *vma) 3129 { 3130 struct drm_i915_private *i915 = rq->engine->i915; 3131 unsigned int i, count = 0; 3132 const struct i915_wa *wa; 3133 u32 srm, *cs; 3134 3135 srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; 3136 if (GRAPHICS_VER(i915) >= 8) 3137 srm++; 3138 3139 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3140 if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg))) 3141 count++; 3142 } 3143 3144 cs = intel_ring_begin(rq, 4 * count); 3145 if (IS_ERR(cs)) 3146 return PTR_ERR(cs); 3147 3148 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3149 u32 offset = i915_mmio_reg_offset(wa->reg); 3150 3151 if (mcr_range(i915, offset)) 3152 continue; 3153 3154 *cs++ = srm; 3155 *cs++ = offset; 3156 *cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i; 3157 *cs++ = 0; 3158 } 3159 intel_ring_advance(rq, cs); 3160 3161 return 0; 3162 } 3163 3164 static int engine_wa_list_verify(struct intel_context *ce, 3165 const struct i915_wa_list * const wal, 3166 const char *from) 3167 { 3168 const struct i915_wa *wa; 3169 struct i915_request *rq; 3170 struct i915_vma *vma; 3171 struct i915_gem_ww_ctx ww; 3172 unsigned int i; 3173 u32 *results; 3174 int err; 3175 3176 if (!wal->count) 3177 return 0; 3178 3179 vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm, 3180 wal->count * sizeof(u32)); 3181 if (IS_ERR(vma)) 3182 return PTR_ERR(vma); 3183 3184 intel_engine_pm_get(ce->engine); 3185 i915_gem_ww_ctx_init(&ww, false); 3186 retry: 3187 err = i915_gem_object_lock(vma->obj, &ww); 3188 if (err == 0) 3189 err = intel_context_pin_ww(ce, &ww); 3190 if (err) 3191 goto err_pm; 3192 3193 err = i915_vma_pin_ww(vma, &ww, 0, 0, 3194 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 3195 if (err) 3196 goto err_unpin; 3197 3198 rq = i915_request_create(ce); 3199 if (IS_ERR(rq)) { 3200 err = PTR_ERR(rq); 3201 goto err_vma; 3202 } 3203 3204 err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); 3205 if (err == 0) 3206 err = wa_list_srm(rq, wal, vma); 3207 3208 i915_request_get(rq); 3209 if (err) 3210 i915_request_set_error_once(rq, err); 3211 i915_request_add(rq); 3212 3213 if (err) 3214 goto err_rq; 3215 3216 if (i915_request_wait(rq, 0, HZ / 5) < 0) { 3217 err = -ETIME; 3218 goto err_rq; 3219 } 3220 3221 results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); 3222 if (IS_ERR(results)) { 3223 err = PTR_ERR(results); 3224 goto err_rq; 3225 } 3226 3227 err = 0; 3228 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { 3229 if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) 3230 continue; 3231 3232 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) 3233 err = -ENXIO; 3234 } 3235 3236 i915_gem_object_unpin_map(vma->obj); 3237 3238 err_rq: 3239 i915_request_put(rq); 3240 err_vma: 3241 i915_vma_unpin(vma); 3242 err_unpin: 3243 intel_context_unpin(ce); 3244 err_pm: 3245 if (err == -EDEADLK) { 3246 err = i915_gem_ww_ctx_backoff(&ww); 3247 if (!err) 3248 goto retry; 3249 } 3250 i915_gem_ww_ctx_fini(&ww); 3251 intel_engine_pm_put(ce->engine); 3252 i915_vma_put(vma); 3253 return err; 3254 } 3255 3256 int intel_engine_verify_workarounds(struct intel_engine_cs *engine, 3257 const char *from) 3258 { 3259 return engine_wa_list_verify(engine->kernel_context, 3260 &engine->wa_list, 3261 from); 3262 } 3263 3264 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 3265 #include "selftest_workarounds.c" 3266 #endif 3267