1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_SSEU_H__ 7 #define __INTEL_SSEU_H__ 8 9 #include <linux/types.h> 10 #include <linux/kernel.h> 11 12 #include "i915_gem.h" 13 14 struct drm_i915_private; 15 struct intel_gt; 16 struct drm_printer; 17 18 /* 19 * Maximum number of slices on older platforms. Slices no longer exist 20 * starting on Xe_HP ("gslices," "cslices," etc. are a different concept and 21 * are not expressed through fusing). 22 */ 23 #define GEN_MAX_HSW_SLICES 3 24 25 /* 26 * Maximum number of subslices that can exist within a HSW-style slice. This 27 * is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the 28 * GEN_MAX_DSS value below). 29 */ 30 #define GEN_MAX_SS_PER_HSW_SLICE 6 31 32 /* Maximum number of DSS on newer platforms (Xe_HP and beyond). */ 33 #define GEN_MAX_DSS 32 34 35 /* Maximum number of EUs that can exist within a subslice or DSS. */ 36 #define GEN_MAX_EUS_PER_SS 16 37 38 #define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b)) 39 40 /* The maximum number of bits needed to express each subslice/DSS independently */ 41 #define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \ 42 GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE) 43 44 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) 45 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE) 46 #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS) 47 48 #define GEN_DSS_PER_GSLICE 4 49 #define GEN_DSS_PER_CSLICE 8 50 #define GEN_DSS_PER_MSLICE 8 51 52 #define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE) 53 #define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE) 54 55 struct sseu_dev_info { 56 u8 slice_mask; 57 u8 subslice_mask[GEN_SS_MASK_SIZE]; 58 u8 geometry_subslice_mask[GEN_SS_MASK_SIZE]; 59 u8 compute_subslice_mask[GEN_SS_MASK_SIZE]; 60 u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE]; 61 u16 eu_total; 62 u8 eu_per_subslice; 63 u8 min_eu_in_pool; 64 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 65 u8 subslice_7eu[3]; 66 u8 has_slice_pg:1; 67 u8 has_subslice_pg:1; 68 u8 has_eu_pg:1; 69 70 /* Topology fields */ 71 u8 max_slices; 72 u8 max_subslices; 73 u8 max_eus_per_subslice; 74 75 u8 ss_stride; 76 u8 eu_stride; 77 }; 78 79 /* 80 * Powergating configuration for a particular (context,engine). 81 */ 82 struct intel_sseu { 83 u8 slice_mask; 84 u8 subslice_mask; 85 u8 min_eus_per_subslice; 86 u8 max_eus_per_subslice; 87 }; 88 89 static inline struct intel_sseu 90 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 91 { 92 struct intel_sseu value = { 93 .slice_mask = sseu->slice_mask, 94 .subslice_mask = sseu->subslice_mask[0], 95 .min_eus_per_subslice = sseu->max_eus_per_subslice, 96 .max_eus_per_subslice = sseu->max_eus_per_subslice, 97 }; 98 99 return value; 100 } 101 102 static inline bool 103 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, 104 int subslice) 105 { 106 u8 mask; 107 int ss_idx = subslice / BITS_PER_BYTE; 108 109 if (slice >= sseu->max_slices || 110 subslice >= sseu->max_subslices) 111 return false; 112 113 GEM_BUG_ON(ss_idx >= sseu->ss_stride); 114 115 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; 116 117 return mask & BIT(subslice % BITS_PER_BYTE); 118 } 119 120 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 121 u8 max_subslices, u8 max_eus_per_subslice); 122 123 unsigned int 124 intel_sseu_subslice_total(const struct sseu_dev_info *sseu); 125 126 unsigned int 127 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); 128 129 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); 130 131 u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu); 132 133 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, 134 u8 *subslice_mask, u32 ss_mask); 135 136 void intel_sseu_info_init(struct intel_gt *gt); 137 138 u32 intel_sseu_make_rpcs(struct intel_gt *gt, 139 const struct intel_sseu *req_sseu); 140 141 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); 142 void intel_sseu_print_topology(struct drm_i915_private *i915, 143 const struct sseu_dev_info *sseu, 144 struct drm_printer *p); 145 146 u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice); 147 148 #endif /* __INTEL_SSEU_H__ */ 149