1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #ifndef __INTEL_SSEU_H__ 8 #define __INTEL_SSEU_H__ 9 10 #include <linux/types.h> 11 #include <linux/kernel.h> 12 13 #include "i915_gem.h" 14 15 struct drm_i915_private; 16 17 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 18 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 19 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) 20 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) 21 #define GEN_MAX_EUS (16) /* TGL upper bound */ 22 #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS) 23 24 struct sseu_dev_info { 25 u8 slice_mask; 26 u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; 27 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE]; 28 u16 eu_total; 29 u8 eu_per_subslice; 30 u8 min_eu_in_pool; 31 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 32 u8 subslice_7eu[3]; 33 u8 has_slice_pg:1; 34 u8 has_subslice_pg:1; 35 u8 has_eu_pg:1; 36 37 /* Topology fields */ 38 u8 max_slices; 39 u8 max_subslices; 40 u8 max_eus_per_subslice; 41 42 u8 ss_stride; 43 u8 eu_stride; 44 }; 45 46 /* 47 * Powergating configuration for a particular (context,engine). 48 */ 49 struct intel_sseu { 50 u8 slice_mask; 51 u8 subslice_mask; 52 u8 min_eus_per_subslice; 53 u8 max_eus_per_subslice; 54 }; 55 56 static inline struct intel_sseu 57 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 58 { 59 struct intel_sseu value = { 60 .slice_mask = sseu->slice_mask, 61 .subslice_mask = sseu->subslice_mask[0], 62 .min_eus_per_subslice = sseu->max_eus_per_subslice, 63 .max_eus_per_subslice = sseu->max_eus_per_subslice, 64 }; 65 66 return value; 67 } 68 69 static inline bool 70 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, 71 int subslice) 72 { 73 u8 mask; 74 int ss_idx = subslice / BITS_PER_BYTE; 75 76 GEM_BUG_ON(ss_idx >= sseu->ss_stride); 77 78 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; 79 80 return mask & BIT(subslice % BITS_PER_BYTE); 81 } 82 83 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 84 u8 max_subslices, u8 max_eus_per_subslice); 85 86 unsigned int 87 intel_sseu_subslice_total(const struct sseu_dev_info *sseu); 88 89 unsigned int 90 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); 91 92 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); 93 94 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, 95 u32 ss_mask); 96 97 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, 98 const struct intel_sseu *req_sseu); 99 100 #endif /* __INTEL_SSEU_H__ */ 101