1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright © 2019 Intel Corporation 5 */ 6 7 #ifndef __INTEL_SSEU_H__ 8 #define __INTEL_SSEU_H__ 9 10 #include <linux/types.h> 11 12 struct drm_i915_private; 13 14 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 15 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 16 17 struct sseu_dev_info { 18 u8 slice_mask; 19 u8 subslice_mask[GEN_MAX_SLICES]; 20 u16 eu_total; 21 u8 eu_per_subslice; 22 u8 min_eu_in_pool; 23 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 24 u8 subslice_7eu[3]; 25 u8 has_slice_pg:1; 26 u8 has_subslice_pg:1; 27 u8 has_eu_pg:1; 28 29 /* Topology fields */ 30 u8 max_slices; 31 u8 max_subslices; 32 u8 max_eus_per_subslice; 33 34 /* We don't have more than 8 eus per subslice at the moment and as we 35 * store eus enabled using bits, no need to multiply by eus per 36 * subslice. 37 */ 38 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; 39 }; 40 41 /* 42 * Powergating configuration for a particular (context,engine). 43 */ 44 struct intel_sseu { 45 u8 slice_mask; 46 u8 subslice_mask; 47 u8 min_eus_per_subslice; 48 u8 max_eus_per_subslice; 49 }; 50 51 static inline struct intel_sseu 52 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 53 { 54 struct intel_sseu value = { 55 .slice_mask = sseu->slice_mask, 56 .subslice_mask = sseu->subslice_mask[0], 57 .min_eus_per_subslice = sseu->max_eus_per_subslice, 58 .max_eus_per_subslice = sseu->max_eus_per_subslice, 59 }; 60 61 return value; 62 } 63 64 u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, 65 const struct intel_sseu *req_sseu); 66 67 #endif /* __INTEL_SSEU_H__ */ 68