1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_SSEU_H__ 7 #define __INTEL_SSEU_H__ 8 9 #include <linux/types.h> 10 #include <linux/kernel.h> 11 12 #include "i915_gem.h" 13 14 struct drm_i915_private; 15 struct intel_gt; 16 struct drm_printer; 17 18 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 19 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ 20 #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE) 21 #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES) 22 #define GEN_MAX_EUS (16) /* TGL upper bound */ 23 #define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS) 24 25 struct sseu_dev_info { 26 u8 slice_mask; 27 u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE]; 28 u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES * GEN_MAX_EU_STRIDE]; 29 u16 eu_total; 30 u8 eu_per_subslice; 31 u8 min_eu_in_pool; 32 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ 33 u8 subslice_7eu[3]; 34 u8 has_slice_pg:1; 35 u8 has_subslice_pg:1; 36 u8 has_eu_pg:1; 37 38 /* Topology fields */ 39 u8 max_slices; 40 u8 max_subslices; 41 u8 max_eus_per_subslice; 42 43 u8 ss_stride; 44 u8 eu_stride; 45 }; 46 47 /* 48 * Powergating configuration for a particular (context,engine). 49 */ 50 struct intel_sseu { 51 u8 slice_mask; 52 u8 subslice_mask; 53 u8 min_eus_per_subslice; 54 u8 max_eus_per_subslice; 55 }; 56 57 static inline struct intel_sseu 58 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) 59 { 60 struct intel_sseu value = { 61 .slice_mask = sseu->slice_mask, 62 .subslice_mask = sseu->subslice_mask[0], 63 .min_eus_per_subslice = sseu->max_eus_per_subslice, 64 .max_eus_per_subslice = sseu->max_eus_per_subslice, 65 }; 66 67 return value; 68 } 69 70 static inline bool 71 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, 72 int subslice) 73 { 74 u8 mask; 75 int ss_idx = subslice / BITS_PER_BYTE; 76 77 GEM_BUG_ON(ss_idx >= sseu->ss_stride); 78 79 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; 80 81 return mask & BIT(subslice % BITS_PER_BYTE); 82 } 83 84 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 85 u8 max_subslices, u8 max_eus_per_subslice); 86 87 unsigned int 88 intel_sseu_subslice_total(const struct sseu_dev_info *sseu); 89 90 unsigned int 91 intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice); 92 93 u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); 94 95 void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, 96 u32 ss_mask); 97 98 void intel_sseu_info_init(struct intel_gt *gt); 99 100 u32 intel_sseu_make_rpcs(struct intel_gt *gt, 101 const struct intel_sseu *req_sseu); 102 103 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); 104 void intel_sseu_print_topology(const struct sseu_dev_info *sseu, 105 struct drm_printer *p); 106 107 #endif /* __INTEL_SSEU_H__ */ 108